JP3955150B2 - Phase interpolator, timing signal generation circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generation circuit is applied - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase interpolator, a timing signal generation circuit, and a semiconductor integrated circuit device and a semiconductor integrated circuit system to which the timing signal generation circuit is applied. In particular, the present invention relates to signal transmission between LSI chips or in one chip. The present invention relates to a timing signal generation circuit for speeding up signal transmission between a plurality of elements and circuit blocks.
[0002]
In recent years, signal transmission between LSI (Large Scale Integration Circuit) chips, for example, signal transmission between DRAM (Dynamic Random Access Memory) and a processor (logic circuit), or in one LSI chip (semiconductor integrated circuit device) It has become necessary to perform signal transmission between a plurality of elements and circuit blocks at high speed. There is a demand for providing a timing signal generation circuit capable of generating a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and high accuracy.
[0003]
[Prior art]
In recent years, the performance of components constituting computers and other information processing equipment has greatly improved, and in particular, the performance of DRAMs and processors has greatly improved over time. That is, while the processor has been greatly improved in performance in terms of high speed, the DRAM has been greatly improved in performance mainly in terms of increased capacity. However, the increase in operation speed in DRAM is not as great as the increase in capacity. As a result, the speed gap between the DRAM and the processor becomes large, and in recent years, this speed gap has become an obstacle to improving the performance of computers. is there. In addition to the signal transmission between these chips, the signal transmission speed between the elements and component circuits (circuit blocks) in one LSI chip (semiconductor integrated circuit device) as the size of the chip increases. It has become a major factor limiting performance.
[0004]
For example, in order to increase the speed of signal transmission between LSI chips, it is necessary for a circuit that receives a signal to operate at an accurate timing with respect to the signal. Conventionally, a DLL (Delay Locked Loop) is required. And a method such as PLL (Phase Locked Loop) is known.
FIG. 1 is a block diagram showing an example of a conventional timing signal generation circuit, and shows an example of a timing signal generation circuit using a DLL circuit. In FIG. 1, reference numeral 100 is a DLL circuit, 111 is a variable delay line, 112 is a phase comparison circuit, 113 is a control signal generation circuit, 114 is a drive circuit (clock driver), 102 is a delay circuit, and 103 is a reception circuit. Is shown.
[0005]
The DLL circuit 100 includes a variable delay line 111, a phase comparison circuit 112, and a control signal generation circuit 113. The phase comparison circuit 112 receives the reference clock CKr and the output of the clock driver 114 (internal clock CKin), and the delay amount (delay unit) of the variable delay line 111 so that the phase difference between the clocks CKr and CKin is as small as possible. D stage number) is controlled. That is, the phase comparison circuit 112 supplies the up signal UP or the down signal DN to the control signal generation circuit 113 according to the phase difference between the reference clock CKr and the internal clock CKin, and the control signal generation circuit 113 Alternatively, the delay amount of the variable delay line 111 is controlled by a control signal CS (signal for selecting the number of stages of the delay unit D) corresponding to the down signal DN. As a result, an internal clock CKin phase-synchronized with the reference clock CKr is generated.
[0006]
The output of the clock driver 114 is supplied as the internal clock CKin of the LSI chip (semiconductor integrated circuit device). For example, it is used as the timing signal TS of the receiving circuit 103 via the delay circuit (appropriate delay stage) 102. . That is, for example, the receiving circuit 103 takes in (latches) a signal SS given in accordance with the internal clock CKin supplied via the delay circuit 102. Here, the delay circuit 102 is provided to generate the timing signal TS by adjusting the timing of the internal clock CKin delayed according to, for example, the drive capability of the clock driver 114 and the load capacity of the signal line.
[0007]
[Problems to be solved by the invention]
The timing signal generating circuit using the conventional DLL circuit shown in FIG. 1 or the timing signal generating circuit having a similar configuration in which the DLL circuit is replaced with a PLL circuit is an internal clock having the same phase as the reference clock CKr. Although CKin can be generated, there is a problem to be solved when the internal clock CKin is used for high-speed signal transmission between LSI chips, for example.
[0008]
First, in signal transmission between LSI chips (or between electronic devices), multi-bit transmission using a plurality of signal lines is often applied in order to obtain a necessary signal transmission band. The optimum reception timing for each bit differs due to variations in delay characteristics of the signal lines. Therefore, for example, a plurality of DLL circuits are provided in order to adjust the timing of each bit, but in that case, there is a problem that the circuit scale becomes too large.
[0009]
Even in the case of 1-bit width transmission, the optimum reception timing of the receiving circuit is usually different from the rising or falling edge of the reference clock CKr. For this reason, the reference clock CKr is passed through the delay stage. A reception clock is generated. However, even if an internal clock CKin that does not depend on variations in element characteristics is generated using a DLL circuit or a PLL circuit, a delay that is unrelated to the cycle of the reference clock CKr occurs in the delay stage. When a change occurs in the clock frequency, there is a problem that reception at an optimal timing becomes impossible.
[0010]
In view of the problems of the above-described conventional timing signal generation circuit, the present invention provides a timing capable of generating a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and high accuracy. An object is to provide a signal generation circuit.
[0011]
[Means for Solving the Problems]
  The present inventionThe first form ofAccording to the present invention, a parent circuit that generates an internal signal having the same cycle or phase as the input reference signal by feedback control, and an internal signal and a control signal from the parent circuit are received, and the reference signal A child circuit for generating a timing signal having a predetermined timing;The parent circuit includes a comparison circuit that compares the period or phase of the reference signal and the internal signal, a control signal generation circuit that changes the control signal according to the output of the comparison circuit, and the control signal And a delay delay line for a master circuit that controls the delay amount of the reference signal and outputs the internal signal, and the child circuit is configured to receive the internal signal by a control signal from the parent circuit. Variable delay line for a child circuit that delays a signal and outputs the timing signalA timing signal generating circuit is provided.
[0012]
  The present inventionThe second form ofAccording toA parent circuit that generates an internal signal having the same cycle or phase as the input reference signal by feedback control, and receives the internal signal and the control signal from the parent circuit, and has a predetermined timing with respect to the reference signal. A sub-circuit that generates a timing signal having a comparison circuit that compares the period or phase of the reference signal and the internal signal, and changes the control signal according to the output of the comparison circuit A DLL circuit comprising: a control signal generation circuit; and a variable delay line for a parent circuit that outputs the internal signal by controlling a delay amount of the reference signal by the control signal, and the child circuit includes the child circuit, Receiving a plurality of input signals of different phases related to the internal signal and outputting the timing signal in an intermediate phase of the input signals of the plurality of phases according to the control signal; Timing signal generating circuit, characterized by comprising Taporeta is provided.
According to the third aspect of the present invention, a parent circuit that generates an internal signal having the same period or phase as the input reference signal by feedback control, and receives a control signal from the parent circuit, and receives the reference signal. A sub-circuit that generates a timing signal having a predetermined timing with respect to the signal, and the parent circuit compares the cycle or phase of the reference signal and the internal signal, and outputs the comparison circuit A PLL circuit comprising: a control signal generation circuit that changes the control signal according to the control signal; and a voltage control oscillator for a parent circuit that generates an internal signal corresponding to the reference signal according to the control signal; and A child circuit includes a child circuit voltage-controlled oscillator that outputs the timing signal in response to a control signal from the parent circuit. It is.
[0013]
Thereby, a plurality of timing signals having a predetermined phase difference in synchronization with the reference signal can be generated with a simple configuration and with high accuracy.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
First, the principle configuration of the timing signal generation circuit according to the present invention will be described with reference to FIG.
FIG. 2 is a block diagram showing the principle configuration of the timing signal generating circuit according to the present invention. In FIG. 2, reference numeral 1 is a parent circuit, 2 is a child circuit, 10 is a DLL circuit, 11 is a variable delay line, 12 is a phase comparison circuit, 13 is a control signal generation circuit, and 14 is a drive circuit (clock driver). Is shown.
[0015]
As shown in FIG. 2, the timing signal generation circuit of the present invention includes a parent circuit 1 and a plurality of child circuits 2. The parent circuit 1 has the same configuration as that of the conventional timing signal generation circuit 111 shown in FIG. 1, and includes a DLL circuit 10 and a clock driver 14. Note that the parent circuit 1 is not limited to the one using a DLL circuit, and may be one using a PLL circuit, for example.
[0016]
The DLL circuit 10 includes a variable delay line 11, a phase comparison circuit 12, and a control signal generation circuit 13. The phase comparison circuit 12 receives the reference clock CKr and the output of the clock driver 14 (internal clock CKin), and compares the phases of these clocks CKr and CKin. Further, the control signal generation circuit 13 generates a control signal (for example, an analog value voltage or current) CS based on the result of the phase comparison. The delay amount of the variable delay line 11 is controlled by the control signal CS from the control signal generation circuit 13, and finally the phase difference between the reference clock CKr and the internal clock CKin is minimized. Here, the output (CKin) of the clock driver 14 is not only fed back to the phase comparison circuit 12 but also supplied to each child circuit 2, and the control signal CS from the control signal generation circuit 13 is also supplied to each child circuit 2. Has been supplied to.
[0017]
As shown in FIG. 2, in the timing signal generation circuit according to the present invention, a plurality of child circuits 2 are also controlled by a control signal (output signal of the control signal generation circuit 13) CS used in the parent circuit 1. It has become. That is, in each child circuit 2, the control signal CS used for controlling the delay amount of the variable delay line 11 in the DLL circuit 10 of the parent circuit 1 is used as it is, and the delay element ( The delay element essentially the same as the delay unit D) can be used to provide a delay proportional to the period of the reference clock CKr.
[0018]
Therefore, the child circuit 2 can also generate a timing signal (TS) having a delay amount based on the period of the reference clock CKr (that is, having a constant phase difference relationship with respect to the reference clock). Further, by using the control signal CS generated in the parent circuit 1 also in the child circuit 2, the response frequency characteristic of the child circuit 2 can be controlled according to the frequency of the reference clock CKr. Specifically, for example, the characteristic frequency (for example, cutoff frequency) of the filter circuit used in the child circuit 2 can be made proportional to the frequency of the reference clock CKr. By utilizing this fact, it becomes possible to generate a sinusoidal wave having a constant amplitude in the child circuit 2 by passing a rectangular wave clock having a CMOS amplitude through a filter, for example.
[0019]
Thus, according to the timing signal generation circuit of the present invention, the timing signal synchronized with the reference clock CKr can be generated by the child circuit 2 having a much simpler configuration than the parent circuit 1. Further, by changing the response speed of the child circuit 2 in accordance with the frequency of the reference clock CKr, it is possible to generate a highly accurate timing signal TS over a wide frequency range.
[0020]
Hereinafter, embodiments of a phase interpolator, a timing signal generation circuit, a semiconductor integrated circuit device to which the timing signal generation circuit is applied, and a semiconductor integrated circuit system according to the present invention will be described with reference to the accompanying drawings.
FIG. 3 is a block diagram showing the configuration of the timing signal generating circuit as the first embodiment of the present invention.
[0021]
As shown in FIG. 3, the variable delay line 11 is composed of a plurality of delay units D, and a delay amount in the variable delay line 11 is selected by selecting a predetermined number of delay units D of the variable delay line 11 by the control signal CS. Is to control. The control signal generation circuit 13 includes a charge pump circuit 131 and a buffer amplifier 132, and an up signal UP or a down signal DN from the phase comparison circuit 12 output according to the phase difference between the reference clock CKr and the internal clock CKin. A control signal CS corresponding to the above is generated.
[0022]
Further, as shown in FIG. 3, the child circuit 2 has a variable delay line 21 configured to include a plurality of delay units D that are the same as the delay units that configure the variable delay line 11 of the parent circuit 1, An internal clock CKin that is an output of the clock driver 14 of the parent circuit 1 is input to the variable delay line 21 of the child circuit 2. The child circuit 2 is used, for example, to generate a timing signal (TS) having a predetermined delay with respect to the clock cycle.
[0023]
The delay amount of the variable delay line 21 of the child circuit 2 (the number of stages of the delay unit D) is controlled by a control signal CS that is an output of the control signal generation circuit 13 (buffer amplifier 132) of the parent circuit 1. . Thus, the same delay unit D as the variable delay line 11 of the parent circuit 1 is used for the child circuit 2, and a plurality of timing signals (TS1, TS2, TS2, TS2, TS2) having a delay amount proportional to the period of the reference clock CKr. ...) can be generated. Each of these timing signals TS1, TS2,... Has a predetermined delay amount with respect to the reference clock CKr, for example, a signal having a timing delayed by 1 / m, 2 / m,. It has become. A plurality of child circuits 2 can be provided for one parent circuit 1, and the variable delay line 21 of each child circuit 2 has a smaller circuit scale than the variable delay line 11 of the parent circuit 1, for example. That is, it can be configured such that the number of stages of the delay unit D is reduced.
[0024]
In the above, the parent circuit 1 and the plurality of child circuits 2 can be provided in one semiconductor integrated circuit device (LSI chip), but the parent circuit 1 and each child circuit 2 are provided in different semiconductor integrated circuit devices. You may comprise. That is, the timing signal generation circuit can be applied to a semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices.
[0025]
FIG. 4 is a circuit diagram showing an example of the delay unit D in the variable delay line of the timing signal generation circuit of FIG. Here, the circuit example of the delay unit D shown in FIG. 4 is common to the delay unit in the variable delay line 11 of the parent circuit 1 and the delay unit in the variable delay line 21 of the child circuit 2.
As shown in FIG. 4, each delay unit D includes a p-channel MOS (pMOS) transistor and an n-channel MOS (nMOS) provided between a high potential power line (Vcc) and a low potential power line (Vss). ) A CMOS inverter DI composed of transistors, an nMOS transistor DT and a capacitor DC provided between the output of the CMOS inverter DI and the low-potential power line (Vss). The variable delay line 11 (21) is configured by connecting a plurality of delay units D in cascade. Note that the delay unit D shown in FIG. 4 is configured to supply the control voltage Vcs (control signal CS) to the gate of the transistor DT, but the present invention is not limited to this, and various configurations are used. be able to. For example, transistors operating in a constant current mode are inserted on the source sides of transistors (pMOS and nMOS) of a CMOS inverter DI as shown in FIG. 8 to be described later, and the delay is controlled by control voltages Vcn and Vcp to these transistors. It is also possible to do. In order to avoid logic inversion, the two delay units D may be configured as one unit (one stage).
[0026]
FIG. 5 is a block circuit diagram showing an example of the phase comparison circuit 12 in the timing signal generation circuit of FIG. 3, and FIG. 6 is a timing diagram for explaining the operation of the phase comparison circuit of FIG.
As shown in FIG. 5, the phase comparison circuit 12 compares the phases of the reference clock CKr and the internal clock CKin, and outputs an up signal (/ UP) or a down signal (/ DN) according to the phase difference between these signals. The frequency of the reference clock CKr and the internal clock CKin is divided by two, and the logic of the reference clock CKr ′ and the internal clock CKin ′ having a double cycle is taken and a negative logic up signal (/ UP) And a down signal (/ DN) is generated.
[0027]
That is, as shown in FIG. 6, the timing at which the internal clock CKin ′ divided by two changes from the low level “L” to the high level “H” is the same as the reference clock CKr ′ divided by two is the low level “L”. If it is earlier than the timing at which the signal changes from high to “H”, the low level “L” up signal / UP is output, while the reference clock CKr ′ divided by two is supplied from the low level “L” to the high level “H”. If it is later than the timing of changing to "", a low level "L" down signal / DN is output.
[0028]
FIG. 7 is a circuit diagram showing an example of the charge pump circuit 131 in the timing signal generation circuit of FIG.
As shown in FIG. 7, the charge pump circuit 131 is provided between the high potential power supply line (Vcc) and the low potential power supply line (Vss), and an up signal (inverted logic up signal) / UP is supplied to the gate. The pMOS transistor and the nMOS transistor to which the down signal DN is supplied to the gate. That is, when the low level “L” up signal / UP is output, the potential of the output level Vco is high, while the high level “H” down signal DN (/ DN is low level “L”). Is output, the potential of the output level Vco is lowered.
[0029]
The output Vco of the charge pump circuit 131 becomes a control voltage Vcs (control signal CS) via the buffer amplifier 132, and is applied to the gate of the transistor DT of each delay unit D in FIG. When the potential of the control voltage Vcs increases, the load capacity at the output of each CMOS inverter DI increases, the delay amount of the variable delay line 11 (21) increases, and the phase of the internal clock CKin is delayed. Conversely, if the potential of the control voltage Vcs is lowered, the load capacity at the output of each CMOS inverter DI is reduced, the delay amount of the variable delay line 11 (21) is reduced, and the phase of the internal clock CKin advances. Become.
[0030]
FIG. 8 is a circuit diagram showing another example of the delay unit D in the variable delay line of the timing signal generation circuit of FIG.
As shown in FIG. 8, the delay unit D inserts a transistor that operates in a constant current mode on the source side of the transistors (pMOS and nMOS) of the CMOS inverter DI, and delays with the control voltages Vcn and Vcp to the transistor. It comes to control. That is, the pMOS transistor DTp is provided between the high potential power supply line (Vcc) and the source of the pMOS transistor of the CMOS inverter DI, and between the low potential power supply line (Vss) and the source of the nMOS transistor of the CMOS inverter DI. An nMOS transistor DTn is provided. A control voltage Vcp is applied to the gate of the transistor DTp, and a control voltage Vcn is applied to the gate of the transistor DTn. The delay unit D shown in FIG. 8 has an advantage that the variable range of the delay amount by one delay unit is wide. In order to avoid logic inversion, the two delay units D may be configured as one unit (one stage) as described above.
[0031]
FIG. 9 is a block circuit diagram showing the configuration of the control signal generation circuit 13 in the timing signal generation circuit as the second embodiment of the present invention, and FIG. 10 shows the current − for converting the output of the control signal generation circuit 13 of FIG. 3 is a circuit diagram illustrating an example of a voltage conversion circuit 133. FIG.
As shown in FIG. 9, the control signal generation circuit 13 includes a charge pump circuit 131 and a plurality of pMOS transistors 1321 and 1322 that are current mirror connected. The sources of the pMOS transistors 1321 and 1322 are connected to the high potential power supply line (Vcc), and the output of the charge pump circuit 131 is supplied to the gates. A control signal CS supplied from the drains of the pMOS transistors 1321 and 1322 to the parent circuit 1 and the child circuit 2 is output. That is, in the second embodiment, a current signal is used for delivery of the control signal CS to the parent circuit 1 and the child circuit 2. Here, a plurality of pMOS transistors 1322 for the child circuit can be provided corresponding to the number of child circuits 2, for example.
[0032]
As shown in FIG. 10, in the parent circuit 1 and each child circuit 2, the control signal (current signal) CS from the control signal generation circuit 13 (pMOS transistors 1321 and 1322) is sent by the current-voltage conversion circuit 133. The control voltages Vcn and Vcp are converted. The control voltages Vcn and Vcp are applied to the gates of the transistors DTp and DTn of the delay unit shown in FIG. 8, for example. In order to control the delay unit shown in FIG. 4, the control voltage Vcn is used as the control voltage Vcs. Here, the current-voltage conversion circuit 133 is configured by nMOS transistors 1331 and 1333 and a pMOS transistor 1332, but is not limited thereto.
In the second embodiment, the control signal CS is distributed by a current signal, so that, for example, the threshold value of the transistor caused by the distance between the parent circuit 1 and the child circuit 2 in the chip is reduced. There is an advantage that the transmission of the control signal CS is not hindered.
[0033]
FIG. 11 is a block diagram showing the configuration of the main part of a timing signal generating circuit according to a third embodiment of the present invention, and FIG. 12 performs digital-analog conversion (D / A conversion) on the output of the up / down counter of FIG. It is a block circuit diagram showing an example of a D / A converter.
As apparent from the comparison between FIG. 11 and FIG. 3, in the third embodiment, an up / down counter 134 is used instead of the charge pump circuit 131 in the first embodiment. That is, the up / down counter 134 counts the up signal UP and the down signal DN from the phase comparison circuit 12, and supplies, for example, 6-bit count signals b0 to b5 to the D / A converter 135 shown in FIG. It has become.
[0034]
The D / A converter 135 is a current matrix cell type D / A converter. For example, the 6-bit count signals b0 to b5 that are the output of the up / down counter 134 are converted into analog signals and the control signal CS is output. It has become.
FIG. 13 is a circuit diagram showing a configuration example of one current matrix cell (U) in the D / A converter 135 shown in FIG.
[0035]
As shown in FIG. 13, one current matrix cell U includes an AND gate UA, an OR gate UO, and two nMOS transistors UT1 and UT2, and the cells U are arranged in a matrix to form a current matrix. The unit 1350 is configured, and the count signals (b2, b3; b4, b5) are supplied to each current matrix cell U through the decoders 1351, 1352. The high-order count signals b0 and b1 are transmitted from one transistor (1353) of two nMOS transistors (1353, 1354; 1355, 1356) provided in series between the output terminal and the low potential power supply line (Vss). , 1355). The control voltage Vc is applied to the gate of the other transistor (1354, 1356). The control voltage Vc is also applied to the gate of the transistor UT2 in each current matrix cell U.
[0036]
In the third embodiment shown in FIGS. 11 to 13, by using the combination of the up / down counter 134 and the D / A converter 135, the loop filter can be easily designed and the phase of the loop using the DLL circuit can be compared. Even when the operation is completely stopped, the delay amount can be kept constant, and there is an advantage that power consumption can be reduced.
[0037]
FIG. 14 is a block diagram showing a configuration of a timing signal generating circuit applied to a child circuit as a fourth embodiment of the present invention, and FIG. 15 is a circuit diagram showing an example of the phase interpolator 136 of FIG.
As shown in FIG. 14, in the fourth embodiment, an input clock (in2) and a signal (in1) delayed by one delay stage are passed through a phase interpolator (phase interpolator) 136. The timing signal TS in the child circuit 2 is generated.
[0038]
As shown in FIG. 15, the phase interpolator 136 changes the bias current (Tail Current) of the input transistor pair of the two sets of differential amplification stages 1361 and 1362, thereby changing the two inputs (in 1 and in 2). Further, the signals S1 and S2 from the two sets of differential amplifier stages 1361 and 1362 are passed through the comparator 1363, so that the phase output (timing between the two signals S1 and S2 is intermediate). Signal TS). Here, the weights of the inputs in1 and in2 in each of the differential amplifier stages 1361 and 1362 are, for example, the control codes (C01, C02, and C2) for the gate of one transistor (1364) of two nMOS transistors connected in series. .., C0n; C11, C12,..., C1n), and a control voltage (Vcs) is applied to the gate of the other transistor (1365). The advantage of using such a phase interpolator 136 is that the timing of the output signal (timing signal TS) can be adjusted with finer resolution than the delay unit for one stage, and high-precision timing adjustment is possible.
[0039]
FIG. 16 is a circuit diagram showing another example of the phase interpolator 136 as the fifth embodiment of the present invention.
The phase interpolator 136 shown in FIG. 16 includes two voltage-current conversion circuits 136a and 136b, and each voltage-current conversion circuit includes pMOS transistors 61 and 63 and nMOS transistors 62 and 64, respectively. The voltage-current conversion circuits 136a and 136b are configured to perform voltage-current conversion on the voltage inputs in1 and in2, respectively, and output them. Here, the number of output transistors (65, 66) of the voltage-current conversion circuit is controlled by the switch means 67 by an external signal, and as a result, the conversion coefficient of the voltage-current conversion changes. The converted current is summed, and the result is input to a comparator to obtain a timing signal (TS).
[0040]
FIG. 17 is a circuit diagram showing the configuration of the timing signal generation circuit (phase interpolator 136) used for the simulation of the fifth embodiment of the present invention, and FIG. 18 shows the simulation of the timing signal generation circuit of FIG. It is a figure which shows a result (SPICE simulation result).
As shown in FIG. 17, the phase interpolator 136 includes voltage-current conversion circuits 136a and 136b that perform voltage-current conversion on input signals (voltage signals) in1 and in2, respectively. A delay unit D (the same delay unit used for the variable delay line 11: see FIG. 4 or FIG. 8) is inserted at the input of each voltage-current conversion circuit 136a and 136b, and the input signals in1 and in2 Signals in1 * and in2 * with a moderate change are supplied to voltage-current conversion circuits 136a and 136b, respectively. In addition, reference symbol W in FIG.₀~ W₇(/ W₀~ / W₇) Is an external signal for controlling the switching of the transfer gate (switch means) 67, and these external signals W₀~ W₇(/ W₀~ / W₇) To open and close the transfer gate 67 to control the number of output transistors (65, 66) of the voltage-current conversion circuit 136a (136b). Thereby, as shown in FIG. 18, the timing of output (Out) can be changed. That is, the operation of the phase interpolator 136 is realized by changing the weights of the two input signals in1 and in2 by changing the conversion coefficients of the current-voltage conversion circuits 136a and 136b. The phase interpolator according to the fifth embodiment does not use a current mirror differential amplification stage as in the fourth embodiment shown in FIG.
[0041]
FIG. 19 is a block diagram showing a configuration of a timing signal generating circuit as a sixth embodiment of the present invention.
As shown in FIG. 19, in the sixth embodiment, a DLL circuit is constituted by a parent circuit 1 and a child circuit 2, and a coarse delay control unit that performs coarse delay control on the parent circuit 1 and a fine delay circuit. A fine delay control unit that performs delay control is provided, and a circuit corresponding to the fine delay control unit of the parent circuit 1 is provided for the child circuit 2.
[0042]
The coarse delay control unit in the parent circuit 1 includes a delay line 11, a phase comparison circuit 12a, an up / down counter 134a, a D / A converter 135, and a selector 15. The fine delay control unit in the parent circuit 1 includes The phase interpolator 136 and, for example, two delay units D that delay the output of the coarse delay control unit (selector 15) by one stage and two stages and supply it to the phase interpolator 136 are configured. Yes. Here, the reference clock CKr and the output of the final stage of the delay line 11 composed of, for example, m stages of delay units D are input to the phase comparison circuit 12a, and further the output of the D / A converter 135 ( Current control signal) is supplied to the delay line 11, and a signal having a timing at which the phase is equally divided according to the number of stages of the delay unit D is output from the delay line 11 to the selector 15. The selector 15 and the phase interpolator 136 are supplied with control signals generated by the phase comparison circuit 12b and the up / down counter 134b. That is, the coarse delay control unit takes out taps from the delay line 11 having a plurality of delay units, selects the output of each tap by the selector (selection means) 15, and supplies the output signal to each fine delay control unit. It is like that.
[0043]
As shown in FIG. 19, each child circuit 2 receives the output of the phase interpolator 236 and the coarse delay control unit (selector 15) of the parent circuit 1 in the same manner as the fine delay control unit of the parent circuit 1. A fine delay control unit including two delay units D that are supplied to the phase interpolator 236 after being delayed by one stage and two stages is provided. The configuration of the delay unit D in the fine delay control unit can be changed variously.
[0044]
As shown in FIG. 19, the sixth embodiment connects the coarse delay control unit of the parent circuit 1 and the fine delay control unit (the fine delay control unit of the parent circuit 1 or each child circuit 2) in series. The coarse delay control unit itself constitutes a DLL loop. Further, the fine delay control unit using the phase interpolator (136, 236) obtains a delay with a resolution higher than that of the delay stage (one delay unit D) of the parent circuit 1. Here, the delay unit used for the phase interpolator (136, 236) of the fine delay control unit is the same as the delay unit D in the delay line 11 of the coarse delay control unit. The output (current control signal) of the D / A converter 135 is also supplied to each child circuit 2.
[0045]
Thus, according to the sixth embodiment, a delay with a resolution higher than the resolution of the delay line 11 can be set by the digital signal, and a highly accurate DLL signal can be obtained. Furthermore, it is possible to realize a digitally controlled DLL circuit capable of stopping the phase comparison operation for a long time or returning from the sleep mode in a short time. In addition, by arranging a plurality of fine delay control units (phase interpolators 236) as the child circuit 2, there is also an advantage that a plurality of timing signals having a resolution higher than the resolution of the delay line 11 can be generated. .
[0046]
FIG. 20 is a block diagram showing a configuration of a timing signal generating circuit as a seventh embodiment of the present invention.
In the seventh embodiment, not only the control signal CS (the output of the control signal generation circuit 13) but also the three-phase internal clocks CK1 to CK3 (the delay outputs of the delay line 11) are transmitted from the parent circuit 1 to the child circuit 2. ) Is also output. In the child circuit 2, a timing signal (output clock) having an arbitrary phase is generated by the phase interpolator 236 based on the three-phase clocks CK1 to CK3 supplied from the parent circuit 1.
[0047]
That is, as illustrated in FIG. 20, in the child circuit 2, for example, the three-phase clocks CK <b> 1 to CK <b> 3 are supplied to the switch unit 238 via the delay unit D for gradual signal change. The switch unit 238 selects a predetermined combination of the three-phase clocks and supplies the selected combination to the respective inputs of the operational amplifiers 237a and 237b. The outputs of the operational amplifiers 237a and 237b are received and phase-divided to output a predetermined timing signal. The seventh embodiment has an advantage that the slave circuit 2 can generate a timing signal (output clock) having an arbitrary phase within 360 degrees.
[0048]
FIG. 21 is a circuit diagram showing a configuration of a sine wave generating circuit as an eighth embodiment of the present invention.
In recent years, attention has been paid to the use of a sine wave as a clock waveform in order to reduce power consumption of a clock driver and to reduce clock noise by eliminating harmonic components. Note that the power consumption of the clock driver can be reduced when a sine wave clock is used because the output waveform does not need to rise and fall sharply (it can be gradual). This is because it can be configured with a small size (a transistor with low power consumption) with low driving capability. FIG. 21 shows an example of a sine wave clock generation circuit applied to the child circuit 2, for example.
[0049]
As shown in FIG. 21, for example, the voltage (control voltage) Vcn and Vcp obtained by the current-voltage conversion circuit 133 as shown in FIG. 10 is passed through the delay unit D as shown in FIG. A CMOS clock (rectangular wave) having an amplitude is converted into a triangular wave, and the triangular wave is further converted into a sine wave (pseudo sine wave) through a constant current driver CD having nonlinear input / output characteristics. Here, a delay unit D that operates in response to a control signal (CS) from the parent circuit 1 is used for a portion that generates a triangular wave. The delay of the delay unit D is in the period of the reference clock (CKr). Since it is proportional, the amplitude of the triangular wave is kept constant even if the frequency of the reference clock changes. Therefore, the eighth embodiment has an advantage that a sine wave can be generated over a wide frequency range.
[0050]
FIG. 22 is a diagram showing simulation results (SPICE simulation results) of the sine wave generation circuit of FIG. 21, FIG. 22 (a) shows a case where the input signal (clock) is 40 MHz, and FIG. 22 (b) shows the input signal. Is 100 MHz, and FIG. 22C shows the case where the input signal is 400 MHz. For example, a resistor R having a resistance value that is half the characteristic impedance of the transmission line is provided at the output of the sine wave generation circuit for simulation.
[0051]
As is apparent from FIGS. 22A to 22C, the sine wave generation circuit of FIG. 21 converts an input rectangular wave into a substantially sine wave for each frequency (40 MHz, 100 MHz, 400 MHz). Output.
FIG. 23 is a block diagram showing a configuration of a timing signal generation circuit as a ninth embodiment of the present invention, and shows an example of a timing signal generation circuit to which a PLL circuit is applied.
[0052]
In FIG. 23, reference numeral 12 denotes a phase comparison circuit, 134 denotes an up / down counter, 135 denotes a D / A converter, and 21 denotes a variable voltage oscillator (VCO). Here, the variable voltage oscillator 21 is constituted by, for example, a ring oscillator in which the same circuit as the delay unit D shown in FIG. 8 is connected in cascade in three stages, and a control transistor (DTp, DTn) at each stage has a control circuit. Control voltages Vcp and Vcn, which are outputs of the signal generation circuit (current-voltage conversion circuit 133), are applied, and thereby the oscillation frequency is controlled. Each child circuit 2 includes a current-voltage conversion circuit 133 and a variable voltage oscillator 21.
[0053]
As described above, in the ninth embodiment, since the master circuit 1 uses a PLL circuit instead of a DLL circuit, an output signal (timing signal) is output even when a completely periodic clock signal cannot be obtained. Can be generated. That is, for example, even when jitter is included in the input reference clock CKr, the jitter component can be removed by the variable voltage oscillator (ring oscillator) 21 or the like, so that the clock component is recovered from the received data. It is preferable.
[0054]
FIG. 24 is a block diagram showing a configuration of a timing signal generating circuit as a tenth embodiment of the present invention.
In the tenth embodiment, the parent circuit 1 is a circuit to which a DLL circuit that outputs an internal clock (CKin) locked to the reference clock (CKr) is applied, and the child circuits 2a to 2z are multi-bit receiving circuits 3a to 3c. It is provided according to each bit of 3z. Here, the parent circuit 1 is not limited to that shown in FIG. 19, and various circuits can be applied.
[0055]
As shown in FIG. 24, each of the child circuits 2a to 2z (2a) corresponds to the selector (15), the delay line (11), the delay unit (D), and the phase interpolator (136) in FIG. Selector 211, delay line 215, two delay units D, and phase interpolator 236, and supply timing signals TSa to TSz to the corresponding receiving circuits 3a to 3z, respectively. The circuits 3a to 3z control the timing for taking in the signals SSa to SSz.
[0056]
In the tenth embodiment, in each of the child circuits 2a to 2z, the levels of the signals SSa to SSz in the corresponding receiving circuits 3a to 3z are sequentially detected, and the delay amount is controlled so that the capture timing is optimized. To do. That is, the switch means 210 sequentially switches the signal (SSa) from the receiving circuit (for example, 3a) and supplies it to the A / D converter 220 that performs analog-digital conversion (A / D conversion), and the level becomes maximum. As described above (so as to increase the S / N ratio), the selection by the selector 215 (the delay amount by the delay line 211) is controlled via the control circuit 230. Here, in each receiving circuit (3a), for example, when the signal SSa is taken in at the optimum timing TSa, the level of the signal SSa is maximized. The timing of the signal TSa is defined.
[0057]
That is, in the tenth embodiment, the delay amount by the delay line 211 is controlled by, for example, a 6-bit digital signal, and this digital signal is controlled so that the signal strength in each of the receiving circuits 3a to 3z is maximized. . The signal strength optimization operation is performed while a special signal (for example, a sequence such as “1010...”) Is being sent. According to the tenth embodiment, even in the case of multi-bit parallel signal transmission, there is an advantage that the operation timing of the receiving circuit can be optimized including the signal line delay between each bit.
[0058]
FIG. 25 is a block diagram showing a main part configuration of a timing signal generating circuit as an eleventh embodiment of the present invention.
In the eleventh embodiment, similarly to the tenth embodiment described above, the multi-bit reception timing is optimized by each bit, and the parent circuit 1 is a signal locked to the reference clock CKr (internal clock CKin). Is supposed to occur. Here, the child circuit 2 (2a to 2z) is provided for each bit of the multi-bit receiving circuit 3 (3a to 3z) as in the tenth embodiment, and as shown in FIG. Each child circuit 2 is provided with a fine delay control unit using a phase interpolator 236 to control the input sampling timing (CL1, CL2) with a 6-bit digital signal, as will be described later. Yes.
[0059]
In FIG. 25, reference numeral 212 indicates a combinational logic circuit, 234 indicates an up / down counter, and 241 and 242 indicate reception latch circuits. The phase interpolator 236 is supplied with the outputs (φ1, / φ1, φ2, / φ2) of the four-phase PLL circuit (250) of the parent circuit 1, and outputs control clocks CL1 and CL2 to each latch circuit. The sampling timings 241 and 242 are controlled. Here, each of the latch circuits 241 and 242 is configured by two D-type flip-flops (D-FF), and sampling of the two flip-flops in the latch circuit 241 is controlled by the control clock CL1, and the latch circuit 242 Sampling of the two flip-flops is controlled by control clocks CL1 and CL2.
[0060]
That is, in each child circuit 2 (2a to 2z) of the eleventh embodiment, two reception latch circuits 241 and 242 are provided for one bit, and one latch circuit 241 The input is sampled at the center of the reception window (also called a bit cell), and the other latch circuit 242 samples the boundary between two adjacent bit cells. Therefore, these two latch circuits 241 and 242 are controlled by control clocks CL1 and CL2 that are 180 degrees out of phase, respectively, and the input signal is sampled at a sampling rate twice that of a normal sampling rate. By using such two latch circuits 241, 242, when a data transition from “0” to “1” or “1” to “0” occurs between adjacent bit cells, the sampling timing (control clock) It is possible to know whether the timing of CL1 and CL2 was earlier or later than the data.
[0061]
Specifically, first, when a data transition occurs in which the Nth data is “1” and the N + 1th data is “0”, the output of the bit cell center sampling latch circuit 241 is D (N), and When the output of the bit cell boundary sampling latch circuit 242 is B (N), the series of “D (N), B (N), D (N + 1)” is “1, 0, 0” or “1, 1, 0 ”. Here, the series “1, 0, 0” indicates that the timing of the sampling control clock (CL1, CL2) is later than the data, and the series “1, 1, 0” has the timing of the control clock. It was faster than the data.
[0062]
Next, when a data transition occurs in which the Nth data is “0” and the N + 1th data is “1”, “D (N), B (N), D (N + 1)” is a sequence “0”. , 0, 1 ”indicates that the timing of the sampling control clocks (CL1, CL2) is earlier than the data, and the sequence“ 0, 1, 1 ”is later than the data. It shows that.
[0063]
Then, by passing the outputs of the two latch circuits 241 and 242 through the combinational logic circuit 212, determination signals (up signal UP, down signal DN) as to whether the control clocks CL1 and CL2 should be delayed or accelerated are obtained. be able to. This determination signal (UP, DN) is counted by the up / down counter 234, and the content is converted into a 6-bit signal (C00, C01, C02; C10, C11, C12) and supplied to the phase interpolator 236. By controlling the timing of the control clocks CL1 and CL2, the signal reception timing can be optimized and the S / N ratio can be increased.
[0064]
Here, the processing for optimizing the timing of signal reception in the eleventh embodiment is performed, for example, while a signal dedicated to this timing optimization (a special signal, for example, a sequence “101010...”) Is being sent. You just have to do it. Thus, according to the eleventh embodiment, as in the tenth embodiment described above, the A / D converter 220 for evaluating the signal reception intensity as an analog quantity can be eliminated, and the switch There is an advantage that the timing optimization processing can be performed in parallel with multiple bits without sequentially selecting by means 210. Therefore, in each bit, when a transition from “0” to “1” or “1” to “0” is guaranteed at a certain frequency (for example, data is coded in a system such as 10B / 8B). Case), the optimization process of the reception timing in each bit can be performed in parallel with the data transmission / reception.
[0065]
FIG. 26 is a circuit diagram showing an example of a phase interpolator (phase adjuster) 236 in the timing signal generation circuit of FIG.
As shown in FIGS. 25 and 26, the phase interpolator 236 is provided with the 6-bit signals (C00, C01, C02; C10, C11, C12) from the up / down counter 234 and the parent circuit 1. The output (φ1, / φ1, φ2, / φ2) of the four-phase PLL circuit (250) is supplied. These 6-bit signals weight the differential inputs in the differential amplifier stages 2361 and 2362. Here, the outputs (φ1, / φ1, φ2, / φ2) of the four-phase PLL circuit are supplied to the respective inputs of the differential amplifier stages 2361 and 2362 through the switch means 2360 controlled by the control signals Sns and / Sns. It is switched and supplied. Similarly to FIG. 15 described above, the control clocks CL1 and CL2 are generated by passing the signals from the two differential amplification stages 2361 and 2362 through the output stage (comparator) 2363.
[0066]
FIG. 27 is a circuit diagram showing an example of a four-phase PLL circuit 250 that can be used in the timing signal generation circuit of FIG.
As shown in FIG. 27, the four-phase PLL circuit 250 includes four stages of differential amplification units 2511 to 2514, four signal conversion units 2521 to 2524, and inverters 2531 to 2534. That is, four stages of differential amplifying units 2511 to 2514 are connected in cascade, a predetermined signal is supplied to each of the signal converting units 2521 to 2524, level inversion and waveform shaping are performed by inverters 2531 to 2534, and a 4-phase output signal φ1 , / Φ1, φ2, / φ2 are obtained.
[0067]
28 is a circuit diagram showing an example of the signal conversion unit 252 (2521 to 2524) in the four-phase PLL circuit of FIG. 27, and FIG. 29 is a differential amplification unit 251 (2511 to 2514) in the four-phase PLL circuit of FIG. It is a circuit diagram which shows an example.
As shown in FIGS. 27 and 28, two input signals (A, B) are supplied to the signal conversion unit 252 (2521 to 2524), and one output signal (Z) is output. . That is, each signal conversion unit 252 (2521 to 2524) includes two each of the second-stage differential amplification unit 2512 or the fourth-stage differential amplification unit 2514 in the four-stage differential amplification unit connected in cascade. An output signal is provided as inputs A and B, and these two inputs A and B are processed to produce one output Z. This output Z is subjected to level inversion and waveform shaping through an inverter 253 (2531 to 2534), and output from the four-phase PLL circuit 250 as outputs φ1, φ2, / φ1, and / φ2, respectively. Here, when the signal INH is at the high level “H”, the signal conversion unit 252 always outputs the high level “H” signal (Z), the signal INH is at the low level “L”, and the control signal CTL. When the signal is at the high level “H”, the signal (Z) corresponding to the input signals A and B is output.
[0068]
As shown in FIG. 27 and FIG. 29, the differential amplifiers 251 (2511 to 2514) are connected in cascade, and the output signals (OUT1, OUT2) of the differential amplifiers 2511, 5122, and 2513 in the previous stage are the differentials in the subsequent stage. The amplifiers 2512, 2513, and 2514 are supplied as input signals IN1 and IN2. Note that the output signal of the differential amplifier 2514 at the final stage (fourth stage) is supplied to the differential amplifier 2511 at the first stage. Here, the differential amplifier 251 is activated when the control signal CTL is at a high level “H”.
[0069]
FIG. 30 is a diagram showing output signals of the 4-phase PLL circuit of FIG.
A four-phase PLL circuit 250 configured by applying the signal conversion unit 252 and the differential amplification unit 251 shown in FIG. 28 and FIG. 29 uses four-phase output signals φ1 and φ2 having phases different by 90 degrees as shown in FIG. , / Φ1, / φ2 are obtained. These signals φ1, φ2, / φ1, / φ2, for example, are supplied to the phase interpolator 236 in the child circuit 2 as shown in FIG.
[0070]
Note that the configurations of the four-phase PLL circuit 250, the signal conversion unit 252 and the differential amplification unit 251 are not limited to those described above, and various circuit configurations can be used. .
As described above, according to the timing signal generation circuit according to each embodiment of the present invention, the timing signal synchronized with the reference clock can be generated by the child circuit having a much simpler configuration than the parent circuit. Further, by changing the response speed of the child circuit in accordance with the frequency of the reference clock, it becomes possible to generate a highly accurate timing signal over a wide frequency range. That is, a timing pulse having a constant phase difference in synchronization with the reference clock signal can be generated by a large number of simple structure child circuits, and a high-accuracy timing signal required for transmission and reception of high-speed signals is small. It can be generated by a circuit with an occupied area.
[0071]
Although the parent circuit and the plurality of child circuits can be provided in one semiconductor integrated circuit device (LSI chip), the parent circuit and each child circuit may be provided in different semiconductor integrated circuit devices. Good. That is, the timing signal generation circuit according to each embodiment of the present invention can be applied to a semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices, a multichip module (MCM), or the like.
[0072]
Next, an embodiment of a phase interpolator according to the present invention will be described with reference to the accompanying drawings.
FIG. 31 is a block diagram showing the principle configuration of the phase interpolator according to the present invention, and FIG. 32 is a waveform diagram for explaining the operation of the phase interpolator of FIG.
[0073]
In FIG. 31, reference numerals 41 and 42 denote analog periodic waveform generation units, 43 denotes a weighting control unit, 44 denotes an addition waveform generation unit, and 45 denotes an analog / digital conversion unit.
As shown in FIG. 31, the analog periodic waveform generator 41 receives the first digital periodic signal DIS1 and generates a first analog periodic waveform (f1: see FIG. 32) having an analog value. In addition, the analog periodic waveform generator 42 receives the second digital periodic signal DIS2 and generates a second analog periodic waveform (f2: see FIG. 32) having an analog value. Here, the first digital periodic signal DIS1 and the second digital periodic signal DIS2 are signals with different time axes (signals having different phases). The phase interpolator, for example, generates a digital signal having an arbitrary intermediate phase from the digital signals DIS1 and DIS2 having such different phases.
[0074]
The first analog periodic waveform f1 and the second analog periodic waveform f2 are weighted by the weighting control unit 43 and added by the addition waveform generation unit 44 to obtain a third analog periodic waveform (f3: see FIG. 32). Is generated. That is, when x is 0 ≦ x ≦ 1, a third analog periodic waveform f3 that satisfies f3 = (1−x) f1 + xf2 is obtained as an output of the added waveform generation unit 44.
[0075]
Then, the analog / digital conversion unit 45 converts the third analog periodic waveform f3 into a third digital periodic signal DO having a predetermined phase and outputs it. Here, the analog / digital conversion unit 45 is, for example. Comparing the third analog periodic waveform f3 with the reference voltage Vr, the comparator is configured to output “0” or “1”.
[0076]
The phase interpolator according to the present invention can be applied as, for example, the phase interpolators 136 and 236 (FIGS. 14, 19, and 20) in the timing signal generation circuit described above. Needless to say, it can be widely applied to various circuits.
FIG. 33 is a circuit diagram showing a configuration example of a phase interpolator as a twelfth embodiment of the present invention, and FIG. 34 is a circuit diagram showing a configuration example of a weighting control unit in the phase interpolator of FIG. 33, reference numerals 41a, 41b and 42a, 42b are sine wave generating circuits, 430 is a weighting control circuit (weighting control unit), 440 is an operational amplifier circuit (added waveform generating circuit), and 450 is a comparison circuit (analog). / Digital conversion circuit).
[0077]
As described above with reference to FIG. 21, the phase interpolator of the twelfth embodiment shown in FIG. 33 is configured to pass the digital signals (rectangular waves) DIS1 and DIS2 through the delay circuits 41a and 42a. The rectangular wave is converted into a triangular wave, and further passed through driver circuits (non-linear amplifier circuits) 41b and 42b, thereby converting the triangular wave into a sine wave (pseudo sine wave). Further, these sine waves (f1 and f2) are supplied to the weighting control circuit 430, and after predetermined weighting is performed by the weighting control units (4301 and 4302), they are added by the operational amplifier circuit 440, and the comparator 450.
[0078]
As shown in FIG. 34, the weighting control unit 4301 (4302) includes a plurality (n) of transfer gates provided in parallel between the input and the output. These n (for example, 16) transfer gates are connected and controlled by control signals C41 to C4n, respectively, and a sine wave f1 (f2) depending on the number of transfer gates that conduct between the input and the output. ) Is weighted. That is, in the circuit example of FIG. 34, by setting an arbitrary number of the control signals C41 to C4n to the high level “H”, the corresponding number of transfer gates are turned on, and the conductance (input side of the operational amplifier circuit 440 is set). (Conductance) is changed.
[0079]
In FIG. 34, the nMOS and pMOS transistors constituting each transfer gate are all configured to have the same size. However, the sizes of the nMOS and pMOS transistors in each transfer gate are changed (for example, the gate width of the minimum transistor is reduced). 1 by setting the gate widths of the other transistors to 1.1, 1.2, 1.3,..., Respectively, and turning any transfer gate on, or combining any plurality of transfer gates to turn on, In other words, the sine wave f1 (f2) can be weighted by conducting at least one transfer gate.
[0080]
FIG. 35 is a circuit diagram showing a configuration example of a phase interpolator as a thirteenth embodiment of the present invention. 35, reference numeral 4101 denotes a selector circuit, 4111 to 411n denote CMOS inverters, 4103 denotes a capacitive load, and 4104 denotes a comparison circuit (comparator).
The selector circuit 4101 selectively controls k CMOS inverters 4111 to 411k to which the first digital cycle signal DIS1 is input and nk CMOS inverters 411k to 411n to which the second digital cycle signal DIS2 is input. To do. That is, the selector circuit 4101 controls the number of CMOS inverters (k) that receive the digital signal DIS1 and the number of CMOS inverters (n−k) that receive the digital periodic signal DIS2. ing. Here, for example, 16 CMOS inverters 4111 to 411n are provided. The outputs of the CMOS inverters 4111 to 411n are commonly connected and supplied to a terminal to which the capacitive load 4103 is connected (an input terminal of the comparator 4104). Then, the comparator 4104 outputs a digital period signal DO of “0” or “1” compared with the reference voltage Vr (1/2 · Vcc).
[0081]
Each of the CMOS inverters 4111 to 411n directly receives a digital signal DIS1 or DIS2 which is a rectangular wave, but the output of each of the CMOS inverters 4111 to 411n has an analog periodic waveform having an analog value by the capacitive load 4103. . In the phase interpolator according to the thirteenth embodiment, the number of CMOS inverters connected to the first and second digital periodic signals DIS1 and DIS2 is controlled to thereby make analog signals of the digital signals (DIS1, DIS2). Both waveform control and weighting control are performed. The phase interpolator according to the thirteenth embodiment has an advantage that the sine wave generation circuit is unnecessary and the linearity of the weight control is high.
[0082]
FIG. 36 is a circuit diagram showing a configuration example of a phase interpolator as a fourteenth embodiment of the present invention.
In the phase interpolator of the fourteenth embodiment, the digital signals DIS1 and DIS2 are received by two inverters 4211, 4212 and 4221, 4222, respectively, and the outputs of these inverters 4211, 4212, 4221, 4222 The pMOS and nMOS transistors of the output stages 4231 to 423n and 4241 to 424n are driven. Here, the outputs of the output stages 4231 to 423n (4241 to 424n) are taken out via transfer gates controlled in connection by control signals C411 to C41n (C421 to C42n), connected in common, and input to the comparator 4250. Has been supplied to.
[0083]
That is, the phase interpolator of the fourteenth embodiment uses a plurality of CMOS inverters for weighting control as in the thirteenth embodiment described above, but the number of connections by the control signal is controlled by the output stage. The input circuit (inverters 4211, 4212 and 4221, 4222) is common. Here, the nMOS and pMOS transistors constituting each output stage (and each transfer gate) 4231 to 423n and 4241 to 424n are configured to have the same size, and the number of output stages to be connected is, for example, 16 or There are 32.
[0084]
In the phase interpolator of the fourteenth embodiment, the input capacitance of the circuit is constant regardless of the weight value, so that the phase shift of the input digital signals DIS1, DIS2 due to the loading effect does not occur, and more accurate timing ( There is an advantage that a digital signal DO having a phase difference) can be generated.
FIG. 37 is a circuit diagram showing a configuration example of a phase interpolator as a fifteenth embodiment of the present invention, and FIG. 38 is a circuit diagram showing an example of a transconductor in the phase interpolator of FIG.
[0085]
As shown in FIG. 37, the phase interpolator of the fifteenth embodiment converts each digital input signal DIS1 and DIS2 into a triangular wave by an integrating circuit comprising inverters 4301 and 4302 and capacitive loads 4303 and 4304, respectively. This is supplied to transconductors (variable transconductors) 4305 and 4306. Here, the integration circuit is obtained by switching a constant current with a digital signal, but various other integration circuits can also be used, and a filter that simply attenuates the high-frequency component of the digital signal instead of the integration circuit. It may be a circuit.
[0086]
As shown in FIG. 38A and FIG. 38B, the transconductor 4305 (4306) extracts a current output corresponding to the input voltage.
First, the transconductor 4305 in FIG. 38A includes pMOS transistors 4351 and 4354, an nMOS transistor 4352, and a resistor 4353, and a current corresponding to the input voltage (IN) applied to the gate of the transistor 4352 is converted into a transistor. The current flowing through the transistor 4351 and flowing through the transistor 4354 connected to the transistor 4351 as a current mirror is taken out as a current output.
[0087]
Also, the transconductor 4305 in FIG. 38B includes pMOS transistors 4361, 4364, and 4366 and nMOS transistors 4362, 4363, and 4365, and is applied to one input of the differential circuit (the gate of the transistor 4362). Current flowing through the transistor 4364 according to the input voltage (IN) and the reference voltage (1/2 · Vcc) applied to the other input is taken out from the transistor 4366 connected to the transistor 4364 as a current output. It is like that.
[0088]
As the transconductor 4305 (4306), various transconductor circuits known in the field of continuous time analog processing can be applied in addition to the one shown in FIG.
As shown in FIG. 37, a triangular wave is converted into a current signal by transconductors 4305 and 4306 and then output to a resistance load 4307, thereby realizing a weighted sum. Then, the comparator 4308 generates a digital signal DO having a predetermined phase as compared with the reference voltage (1/2 · Vcc).
[0089]
The phase interpolator according to the fifteenth embodiment has an advantage that a circuit with high accuracy can be designed because a circuit for converting to a triangular wave and a circuit for generating a sum can be separately optimized.
FIG. 39 is a circuit diagram showing a configuration example of a phase interpolator as a sixteenth embodiment of the present invention. In FIG. 39, reference symbol V1 + corresponds to the first digital cycle signal DIS1, V1- corresponds to the inverted signal (/ DIS1) of the first digital cycle signal DIS1, and V2 + corresponds to the second digital cycle signal DIS2. V2- corresponds to the inverted signal (/ DIS2) of the second digital period signal DIS2.
[0090]
As shown in FIG. 39, in the phase interpolator of the sixteenth embodiment, the analog periodic waveform generation unit and the addition waveform generation unit use the constant current sources with switches (4401, 4403 and 4402, 4404) as capacitive loads. (4405 and 4406). That is, when the first input digital signal DIS1 (V1 +) is at the high level “H”, the nMOS transistor 4414 in the constant current source 4401 with the switch is turned on, the pMOS transistor 4411 is turned off, and the constant with the switch is set. In the current source 4402, the nMOS transistor 4424 is turned off and the pMOS transistor 4421 is turned on, so that a current flows to the capacitive load 4405 via the nMOS transistors 4413 and 4414, and the pMOS transistors 4421 and 4422 flow to the capacitive load 4406. Current flows through. Conversely, when the first input digital signal DIS1 is at the low level “L”, a current flows through the capacitive load 4405 via the pMOS transistors 4411 and 4412, and the capacitive load 4406 via the nMOS transistors 4423 and 4424. Current flows. The same applies to the second input digital signal DIS2 (V2 +) having different phases. The other end of the capacitive load 4405 whose one end is connected to the positive logic input of the comparator 4407 is set to the intermediate potential (1/2 · Vcc). Similarly, the capacitive load whose one end is connected to the negative logic input of the comparator 4407. The other end of 4406 is also at an intermediate potential (1/2 · Vcc).
[0091]
Then, an analog addition waveform (waveform at one end of the capacitive load 4405) by the positive logic digital cycle signals DIS1, DIS2 (V1 +, V2 +) and a negative logic digital cycle signal / DIS1, / DIS2 (V1-, V2-). The analog addition waveform (waveform at one end of the capacitive load 4406) is compared by the comparator 4407, and the digital periodic signal DO corresponding to the comparison result is output.
[0092]
In the phase interpolator according to the sixteenth embodiment, the weighting control is performed by changing the voltage level of the bias signals (Vcp1, Vcn1; Vcp2, Vcn2). Regarding the circuit that generates the bias signal. Will be described later with reference to FIGS. 40 and 41.
As described above, the phase interpolator according to the sixteenth embodiment uses the constant current sources (4412, 4413 and 413) as the analog periodic waveform generation and addition waveform generation unit by the first digital periodic signal DIS1 (V1 +, V1-). 4422, 4423), a current polarity switching means (4411, 4414 and 4421, 4424) for switching the polarity of the current flowing from the common capacitive load (4405, 4406), and a current value control means for controlling the current value of the current source ( 4412, 4413 and 4422, 4423). The second digital periodic signal DIS2 is configured in the same manner.
[0093]
The switch-equipped constant current source 4401 (4402 to 4404) has a structure in which a pMOS transistor 4412 and an nMOS transistor 4413 biased in a constant current mode are inserted on each drain side of the pMOS transistor 4411 and the nMOS transistor 4414 constituting the CMOS inverter. ing. Note that not the drain side of the transistor constituting the CMOS inverter but the source side (between the source of the pMOS transistor 4411 and the high-potential power line Vcc and between the source of the nMOS transistor 4414 and the low-potential power line Vss). A pMOS transistor and an nMOS transistor biased in the constant current mode may be inserted.
[0094]
The phase interpolator according to the sixteenth embodiment has a function for converting a digital input signal into an analog signal (function of an analog periodic waveform generation unit) and a function for generating a sum (function of an addition waveform generation unit). This can be realized on the terminal, and the power consumption can be reduced by simplifying the circuit configuration.
40 is a circuit diagram showing an example of a circuit for generating a bias signal in the phase interpolator of FIG. 39, and FIG. 41 is a circuit showing another example of a circuit for generating a bias signal in the phase interpolator of FIG. FIG.
[0095]
As described above, in the phase interpolator shown in FIG. 39, the control of the weighting of each digital periodic signal DIS1, DIS2; FIG. 40 and FIG. 41 show examples of the bias signal generation circuit (4408) for generating this bias signal.
[0096]
As shown in FIG. 40, as an example of the bias signal generation circuit 4408, a plurality of sets of two pMOS transistors 4481 and 4482 connected in series are provided in parallel, and a reference voltage is applied to the gate of each transistor 4481. (Vr) is applied, and control signals (digital signals) C431 to C43n are supplied to the gates of the other transistors 4482 for switching control.
[0097]
Here, the two transistor sets (4481, 4482) are all connected in common to one end of the nMOS transistor 4483, and the current flowing through the set of transistors (conducted) selected by the control signals C431 to C43n. Is summed to flow through the nMOS transistor 4483. Further, the current flowing through the transistor 4383 flows through the nMOS transistor 4484 connected in a current mirror and the pMOS transistor 4485 connected in series with the transistor 4484. Then, bias signals Vcp1 (Vcp2) and Vcn1 (Vcn2) are obtained through transistors 4485 and 4484 (4483). Note that the phase interpolator of FIG. 39 requires two bias signal generation circuits, a circuit that generates the bias signals Vcp1 and Vcn1, and a circuit that generates the bias signals Vcp2 and Vcn2. When the positive logic control signals C431 to C43n are supplied to the bias signal generation circuit that generates Vcp1 and Vcn1, the inverted logic control signal (for the bias signal generation circuit that generates the bias signals Vcp2 and Vcn2) / C431 to / C43n is supplied to control weighting.
[0098]
As described above, the bias signal generation circuit 4408 shown in FIG. 40 is configured as a current output type D / A converter, and the current received from the D / A converter is mirrored by the current mirror circuit in the controlled current source. Thus, a variable constant current is obtained, and bias signals Vcp1 (Vcp2) and Vcn1 (Vcn2) having predetermined voltage levels according to the control signals C431 to C43n are generated. This bias signal generating circuit has an advantage that it can be realized with a small amount of circuit since the controlled current source has a simple configuration.
[0099]
FIG. 41 is a circuit diagram showing another example of a circuit for generating a bias signal in the phase interpolator of FIG.
As shown in FIG. 41, as another example of the bias signal generation circuit 4408, control signals (digital signals) C441 to C44n are respectively applied to the drains of a plurality of pMOS transistors 4486 to which a reference voltage (Vr) is applied. One end (source) of the pMOS transistors 4487 and 4488 whose switching is controlled by this is connected. Here, the corresponding control signals C441 to C44n are supplied to the gates of the respective transistors 4487, and the control signals (/ C441 to / C44n) inverted by the inverter 4489 are respectively supplied to the gates of the respective transistors 4488. ) Is supplied. Accordingly, in each group, one of the transistors 4487 and 4488 is turned on and the other is turned off.
[0100]
The other ends (drains) of the transistors 4487 in each set are connected in common so that the sum of the currents flowing through the transistors 4487 in the on state flows to the nMOS transistor 44831. Similarly, the other ends of the transistors 4488 in the sets Are connected in common, and the sum of currents flowing through the transistor 4488 in the on state flows to the nMOS transistor 44832. In the same manner as described with reference to FIG. 40, the currents flowing through the transistors 44831 and 44832 are the current mirror-connected nMOS transistors 44841 and 44842, and the pMOS transistors connected in series with the transistors 44841 and 44842. The current flows to 44851 and 44852, and the bias signals Vcp1, Vcn1, and Vcp2, Vcn2 are obtained, respectively.
[0101]
As described above, the bias signal generation circuit 4408 shown in FIG. 41 is connected so that the output of the current control type D / A converter for controlling the output value of the current source is switched to the complementary output node. It has become. Here, since the output current itself of the D / A converter is always kept constant, the voltage of the output transistor of the D / A converter is kept constant, and a spike-like transient as seen when the current is interrupted. There is an advantage of no response. Further, the current consumption of the current output type D / A converter can be reduced (about half).
[0102]
42 is a circuit diagram showing a configuration example of a variable current source (4500) as a modification of the sixteenth embodiment of FIG. 39. Each constant current source (4401-4404) in the phase interpolator of FIG. ). In the current source 4500 shown in FIG. 42, the bias signals (bias voltages) Vcp and Vcn are signals having a constant voltage level, and weighting control is performed by the control signals C451 to C45n.
[0103]
As shown in FIG. 42, the variable current source 4500 of the present modification includes transistors 4501 and 4503 (4412 and 4413) to which the bias signals Vcp (Vcp1) and Vcn (Vcn1) are supplied in the constant current source 4401 of FIG. A plurality of sets), and a pMOS transistor 4506 and an nMOS transistor 4508 are provided between the transistors 4501 and 4503, respectively. Here, positive logic control signals C451 to C45n are supplied to the gates of the respective transistors 4508, and inverted control signals (/ C451 to / C451 to the gates of the respective transistors 4506 are respectively supplied to the gates of the respective transistors 4506. / C45n). Then, connection nodes 4506 and 4508 of each set are connected in common, and an output (output terminal) out is taken out. As shown in FIG. 39, the output terminal out is connected to, for example, one end of a capacitive load (4405 or 4406) and one input terminal of a comparator (4407).
[0104]
In this way, the variable current source of this modification shown in FIG. 42 controls the number of output transistors (4506, 4508) of the current mirror in order to obtain a variable current source, and the current mirror operation transistor (4502). , 4503) is always kept constant, and the stability of the current can be increased. Furthermore, since the variable current source of this modification is current control by the number of transistors, there is an advantage that the linearity is also good.
[0105]
FIG. 43 is a circuit diagram showing a configuration example of a part of a phase interpolator as a seventeenth embodiment of the present invention. A clamp circuit 4600 is provided between two input terminals of the comparator 4407 in the phase interpolator of FIG. It is provided.
As shown in FIG. 43, for example, by providing a clamp circuit 4600 between two input terminals (a node generated by adding analog waveforms) of the comparator 4407 in the phase interpolator of FIG. Even when the values are unbalanced, the clamp circuit 4600 keeps the common mode potential of these nodes constant, so that the comparison operation by the comparator 4407 in the next stage can always be performed in a constant state. The accuracy can be improved.
[0106]
The clamp circuit 4600 shown in FIG. 43 applies 1/2 · Vcc (reference voltage) to the gates of two nMOS transistors 4601 and 4602 connected in series, and to the connection point between the transistors 4601 and 4602. Also, 1/2 · Vcc is applied to clamp the potential between the two input terminals of the comparator 4407. As the clamp circuit 4600, various configurations other than the one shown in FIG. 43 can be applied.
[0107]
FIG. 44 is a diagram for explaining a configuration example of a phase interpolator as an eighteenth embodiment of the present invention. In FIG. 44, the horizontal axis indicates the number of transistors selected (connected) by the D / A input code, that is, the control signal, and the vertical axis indicates the total output current flowing through these selected transistors. Show.
As described above, the phase interpolator of the present invention selects, for example, a plurality of transistors of the same size by a control signal (digital signal) in order to realize weighting control for controlling weighting of each analog periodic waveform. The current output is adjusted by controlling the number of transistors to be connected.
[0108]
A characteristic curve LL1 in FIG. 44 shows the relationship between the number of connected transistors and the output current when transistors of the same size are selected by a control signal, and is a non-linear curve.
Therefore, in the eighteenth embodiment, as shown by the characteristic curve LL2 in FIG. 44, each relationship is such that the relationship between the number of transistors controlled by the control signal and the output current is a linear curve (straight line). The transistor size is adjusted.
[0109]
For example, in the bias signal generation circuit shown in FIG. 40, the number of transistors 4482 that are conductive (connected) is controlled in accordance with the control signals C431 to C43n, and the sum of the currents that flow through all the transistors 4482 that are conductive is the transistor. In such a case, by applying the eighteenth embodiment, the number of transistors 4482 that are turned on in response to the control signals C431 to C43n and the current (output current) that flows through the transistor 4483 are obtained. The size of each transistor 4482 (4481) is adjusted so as to maintain a linear relationship. Note that this transistor size adjustment is not limited to the transistors in the current D / A converter described above, but transistors related to the current mirror circuit or the like (for example, the transistor 4383, 4484, 4485, etc.) can also be adjusted.
[0110]
Thus, by applying the eighteenth embodiment, the timing accuracy of the signal output from the phase interpolator can be further improved.
[0111]
【The invention's effect】
As described above in detail, according to the present invention, a plurality of timing signals having a predetermined phase difference in synchronization with the reference clock can be generated with a simple configuration and high accuracy. That is, according to the present invention, it is possible to generate timing pulses having a constant phase difference in synchronism with the reference clock signal in a large number of simple structure child circuits. Therefore, it is possible to generate a highly accurate timing signal necessary for transmitting and receiving a high-speed signal with a small circuit area.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional timing signal generating circuit.
FIG. 2 is a block diagram showing a principle configuration of a timing signal generating circuit according to the present invention.
FIG. 3 is a block diagram showing a configuration example of a timing signal generation circuit as a first embodiment of the present invention.
4 is a circuit diagram showing an example of a delay unit in a variable delay line of the timing signal generation circuit of FIG. 3;
5 is a block circuit diagram showing an example of a phase comparison circuit in the timing signal generation circuit of FIG. 3. FIG.
6 is a timing diagram for explaining the operation of the phase comparison circuit of FIG. 5;
7 is a circuit diagram showing an example of a charge pump circuit in the timing signal generation circuit of FIG. 3. FIG.
8 is a circuit diagram showing another example of a delay unit in the variable delay line of the timing signal generation circuit of FIG. 3;
FIG. 9 is a block circuit diagram showing a configuration example of a control signal generation circuit in a timing signal generation circuit according to a second embodiment of the present invention.
10 is a circuit diagram showing an example of a current-voltage conversion circuit that converts the output of the control signal generation circuit of FIG. 9;
FIG. 11 is a block diagram showing an example of a main configuration of a timing signal generation circuit according to a third embodiment of the present invention.
12 is a block circuit diagram showing an example of a D / A converter that D / A converts the output of the up / down counter of FIG. 11; FIG.
13 is a circuit diagram showing a configuration example of one current matrix cell in the D / A converter shown in FIG. 12;
FIG. 14 is a block diagram showing a configuration example of a timing signal generating circuit applied to a child circuit as a fourth embodiment of the present invention.
15 is a circuit diagram showing an example of the phase interpolator of FIG. 14;
FIG. 16 is a circuit diagram showing a configuration example of a phase interpolator as a fifth embodiment of the present invention;
FIG. 17 is a circuit diagram showing a configuration example of a timing signal generating circuit used for performing a simulation of the fifth embodiment of the present invention.
FIG. 18 is a diagram showing a simulation result of the timing signal generation circuit of FIG. 17;
FIG. 19 is a block diagram illustrating a configuration example of a timing signal generation circuit according to a sixth embodiment of the present invention.
FIG. 20 is a block diagram showing a configuration example of a timing signal generation circuit according to a seventh embodiment of the present invention.
FIG. 21 is a circuit diagram showing a configuration example of a sine wave generating circuit according to an eighth embodiment of the present invention.
22 is a diagram showing a simulation result of the sine wave generation circuit of FIG. 21. FIG.
FIG. 23 is a block diagram showing a configuration example of a timing signal generating circuit as a ninth embodiment of the present invention.
FIG. 24 is a block diagram showing a configuration example of a timing signal generation circuit according to a tenth embodiment of the present invention.
FIG. 25 is a block diagram showing an example of a main configuration of a timing signal generation circuit according to an eleventh embodiment of the present invention.
26 is a circuit diagram showing an example of a phase interpolator (phase adjuster) in the timing signal generation circuit of FIG. 25. FIG.
FIG. 27 is a circuit diagram showing an example of a four-phase PLL circuit that can be used in the timing signal generation circuit of FIG. 25;
28 is a circuit diagram showing an example of a differential amplifier in the four-phase PLL circuit of FIG. 27. FIG.
29 is a circuit diagram showing an example of a signal conversion unit in the four-phase PLL circuit of FIG. 27. FIG.
30 is a diagram showing an output signal of the 4-phase PLL circuit of FIG. 27. FIG.
FIG. 31 is a block diagram showing a principle configuration of a phase interpolator according to the present invention.
32 is a waveform diagram for explaining the operation of the phase interpolator of FIG. 31. FIG.
FIG. 33 is a circuit diagram showing a configuration example of a phase interpolator as a twelfth embodiment of the present invention.
34 is a circuit diagram showing a configuration example of a weighting control unit in the phase interpolator of FIG. 33. FIG.
FIG. 35 is a circuit diagram showing a configuration example of a phase interpolator as a thirteenth embodiment of the present invention.
FIG. 36 is a circuit diagram showing a configuration example of a phase interpolator as a fourteenth embodiment of the present invention.
FIG. 37 is a circuit diagram showing a configuration example of a phase interpolator as a fifteenth embodiment of the present invention.
38 is a circuit diagram showing an example of a transconductor in the phase interpolator of FIG. 37. FIG.
FIG. 39 is a circuit diagram showing a configuration example of a phase interpolator as a sixteenth embodiment of the present invention.
40 is a circuit diagram showing an example of a circuit for generating a bias signal in the phase interpolator of FIG. 39. FIG.
41 is a circuit diagram showing another example of a circuit for generating a bias signal in the phase interpolator of FIG. 39. FIG.
42 is a circuit diagram showing a configuration example of a variable current source as a modification of the sixteenth embodiment of FIG. 39;
FIG. 43 is a circuit diagram showing a configuration example of a part of a phase interpolator as a seventeenth embodiment of the present invention.
FIG. 44 is a diagram for explaining a configuration example of a phase interpolator as an eighteenth embodiment of the present invention.
[Explanation of symbols]
1 ... Parent circuit
2 ... Child circuit
10 ... DLL circuit
11 ... Variable delay line
12, 12a, 12b ... Phase comparison circuit
13. Control signal generation circuit
14 ... Drive circuit (clock driver)
15 ... Selector
21 ... Voltage controlled oscillator (VCO)
131 ... Charge pump circuit
132 ... Buffer amplifier
133 ... Current-voltage conversion circuit
134, 134a, 134b, 234 ... up / down counter
135 ... D / A converter
136, 236 ... Phase interpolator
212 ... Combinational logic circuit
210: Selection means
220 ... A / D converter
230 ... Control circuit
241,242 ... Latch circuit
250 ... 4 phase PLL circuit
CKr ... Reference clock
CKin ... Internal clock
CS ... Control signal
D ... Delay unit (delay stage)
41, 42 ... Analog periodic waveform generator
43 ... Weighting control unit
44 ... Addition waveform generator
45. Analog / digital converter
DIS1... First digital periodic signal
DIS2 ... Second digital periodic signal
DO ... Digital output signal

Claims (30)

A parent circuit that generates an internal signal having the same period or phase as the input reference signal by feedback control;
A child circuit that receives an internal signal and a control signal from the parent circuit and generates a timing signal having a predetermined timing with respect to the reference signal , and
The parent circuit includes a comparison circuit that compares the cycle or phase of the reference signal and the internal signal, a control signal generation circuit that changes the control signal according to an output of the comparison circuit, and the reference signal based on the control signal. A variable delay line for a master circuit that outputs the internal signal by controlling a delay amount of
Child circuit, a timing signal generating circuit, characterized in that it comprises a sub-circuit for the variable delay line for outputting the timing signal by delaying the internal signal by a control signal from said parent circuit. A parent circuit that generates an internal signal having the same period or phase as the input reference signal by feedback control;
A child circuit that receives an internal signal and a control signal from the parent circuit and generates a timing signal having a predetermined timing with respect to the reference signal, and
The parent circuit includes a comparison circuit that compares the cycle or phase of the reference signal and the internal signal, a control signal generation circuit that changes the control signal according to an output of the comparison circuit, and the reference signal based on the control signal. A variable delay line for a master circuit that outputs the internal signal by controlling a delay amount of
Child circuit receives an input signal of a different phase associated to said internal signal, that you include a phase interpolator for outputting the timing signal of an intermediate phase of the input signal of the plurality of phase in accordance with said control signal A characteristic timing signal generation circuit. A parent circuit that generates an internal signal having the same period or phase as the input reference signal by feedback control;
A child circuit that receives a control signal from the parent circuit and generates a timing signal having a predetermined timing with respect to the reference signal,
The parent circuit includes a comparison circuit that compares the period or phase of the reference signal and the internal signal, a control signal generation circuit that changes the control signal according to an output of the comparison circuit, and the control circuit that generates the control signal according to the control signal. A PLL circuit including a voltage control oscillator for a parent circuit that generates an internal signal corresponding to a reference signal, and
The timing signal generation circuit according to claim 1, wherein the slave circuit includes a slave circuit voltage controlled oscillator that outputs the timing signal in response to a control signal from the parent circuit. 4. The timing signal generation circuit according to claim 1, wherein a plurality of the child circuits are provided for one parent circuit. 5. 3. The timing signal generating circuit according to claim 2 , wherein the DLL circuit of the parent circuit takes out taps from a plurality of delay units constituting the variable delay line for the parent circuit, and selects an output of each tap to generate a coarse delay. Configure the coarse delay control unit to control,
The parent circuit further receives a coarse delay control signal, which is the control signal for controlling the DLL circuit in the coarse delay control unit, and a signal subjected to coarse delay control from the coarse delay control unit, and the coarse delay control A fine delay control unit for a parent circuit that performs fine delay control using a phase interpolator from the signal of
The child circuit performs fine delay control using a phase interpolator from the coarse delay control signal output from the parent circuit corresponding to the parent circuit fine delay control unit. timing signal generating circuit, characterized in that it comprises a part. In the timing signal generating circuit according to claim 1, wherein the control signal generating circuit, a charge pump circuit for controlling the output voltage level in accordance with the up signal and the down signal from the comparator circuit A timing signal generation circuit comprising the timing signal generation circuit. In the timing signal generator circuit according to any one of claims 1 to 5, wherein the control signal generating circuit includes an up-down counter for counting the up signal and the down signal from the comparator circuit, the output of the up-down counter A timing signal generation circuit comprising a D / A converter for digital-to-analog conversion . 3. The timing signal generating circuit according to claim 2 , wherein the plurality of phase input signals are three-phase or four-phase clocks . In the timing signal generating circuit according to claim 2, the phase interpolator of the operator circuit, the voltage converting an input signal of a different phase associated with the internal signal is a voltage signal to each current signal - current conversion means Current-voltage conversion means for converting the converted current signal into a voltage signal again by changing a voltage conversion coefficient; and a comparison means for adding the obtained voltage signal and comparing it with the reference signal the timing signal generating circuit, characterized by comprising. In the timing signal generator circuit according to any one of claims 1-9, wherein the operator circuit includes an amplifier circuit response speed changes in accordance with the internal signal and said control signal from said parent circuit, wherein A timing signal generation circuit configured to generate a sinusoidal signal as a timing signal. The timing signal generation circuit according to any one of claims 1 to 10, wherein the child circuit is used to generate a timing signal for controlling a timing of a 1-bit or multiple-bit input or output signal, and The timing signal generating circuit includes timing signal adjusting means that is provided in common to each of the child circuits and adjusts the timing signal so that an S / N ratio of a transmitted / received signal is increased. Timing signal generating circuit. 12. The timing signal generation circuit according to claim 11 , wherein the timing signal adjustment means is selected by a selection means for selecting an input or output signal of a circuit controlled by a timing signal from each child circuit, and the selection means. A timing signal generating circuit comprising timing signal generating means for detecting a level of an input or output signal of the circuit and controlling an output timing of the timing signal . In the timing signal generator circuit according to any one of claims 1 to 10, wherein the operator circuit is used to generate a timing signal for controlling the timing of one or more bits of the input or output signal, and Each of the sub-circuits is provided with timing signal adjusting means for adjusting the timing signal so as to increase the S / N ratio of the transmitted / received signal. 14. A semiconductor integrated circuit device to which the timing signal generating circuit according to claim 1 is applied, wherein the parent circuit and the child circuit are provided in a semiconductor integrated circuit device constituting one chip. A semiconductor integrated circuit device . 14. A semiconductor integrated circuit system to which the timing signal generating circuit according to claim 1 is applied, wherein the parent circuit and the child circuit are provided in a plurality of semiconductor integrated circuit devices as different chips, respectively. A semiconductor integrated circuit system . An analog periodic waveform generating means for generating an analog periodic waveform having an analog value from a digital periodic signal having an amplitude of a digital value;
Weighting control means for receiving an output signal of the analog periodic waveform generating means and controlling weighting of each analog periodic waveform;
An added waveform generating means for receiving the output signal of the weighting control means and adding a plurality of analog periodic waveforms obtained by the analog periodic waveform generating means from the digital periodic signals shifted in time axis to generate an added waveform;
A phase interpolator comprising analog / digital conversion means for converting the addition waveform into a digital waveform . 17. The phase interpolator according to claim 16, wherein the analog periodic waveform generation means includes a sine wave generation circuit, and the weight control means includes a plurality of transfer gates connected in parallel, A phase interpolator characterized by controlling a connection of each transfer gate by controlling a control signal . 18. The phase interpolator according to claim 17, wherein each transfer gate of the weighting control means has a transistor of the same size, and controls a control signal of each transfer gate to conduct among the plurality of transfer gates. A phase interpolator characterized in that weighting of the analog periodic waveform is controlled by controlling the number of transfer gates . 18. The phase interpolator according to claim 17, wherein each of the transfer gates of the weight control means has a transistor of a different size, and the analog period is obtained by conducting at least one transfer gate having a transistor of a predetermined size. A phase interpolator characterized by controlling waveform weighting . 17. The phase interpolator according to claim 16, wherein the analog periodic waveform generation means includes a plurality of CMOS inverters, and the weight control means controls input of the digital periodic signals to the plurality of CMOS inverters. A phase interpolator characterized in that the number of connections of the plurality of CMOS inverters is controlled . 17. The phase interpolator according to claim 16, wherein the analog periodic waveform generating means includes output stages of a plurality of CMOS inverters, and the weight control means includes output transistors of the output stages of the plurality of CMOS inverters. A phase interpolator characterized in that the number is controlled . 17. The phase interpolator according to claim 16, wherein the analog periodic waveform generating means is a high frequency component attenuation circuit for attenuating a high frequency component of the digital periodic signal, and the weighting control means is an output of the high frequency component attenuation circuit. The current is converted by a variable transconductor, the converted current is applied to a common terminal for voltage conversion, and the voltage converted signal is compared with a reference voltage by a comparator. Phase interpolator . 23. The phase interpolator according to claim 22, wherein the analog periodic waveform generating means is an integrating circuit . 17. The phase interpolator according to claim 16 , wherein the analog periodic waveform generating means and the addition waveform generating means are current polarity switching means for switching the polarity of a current flowing from a constant current source to a common capacitive load by the digital periodic signal. A phase interpolator comprising current value control means for controlling the current value of the current source . 25. The phase interpolator according to claim 24, wherein the current value control means controls a current value of the current source based on an output of a D / A converter. Phase interpolator. 17. The phase interpolator according to claim 16 , wherein the analog / digital conversion means is a comparator that compares the added waveform with a reference level to convert it into a digital waveform . 17. The phase interpolator according to claim 16 , wherein the weighting control means includes a D / A converter for current output, and the output of the D / A converter is a capacitor-connected terminal or a complementary terminal thereof. A phase interpolator characterized in that the connection is controlled by switching to one of the input terminals . 17. The phase interpolator according to claim 16 , wherein the weighting control means is configured to control connection with a power supply line and switch the number of current sources connected to a load capacity terminal. Phase interpolator. In the phase interpolator of claim 16, wherein the weighting control means, in that it comprises a clamping circuit for the voltage level of the input terminal of said analog / digital converting means is a comparator within a predetermined range Feature phase interpolator. 30. The timing signal generation circuit according to claim 2, wherein the phase interpolator is the phase interpolator according to any one of claims 16 to 29 .

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