JP3950564B2 - Noise level detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a noise level detection circuit that detects a noise component of a video signal.
[0002]
[Prior art]
A conventional noise detection circuit detects noise of an input video signal for the purpose of controlling a noise suppression circuit, for example, as described in JP-A-4-81076. That is, the high frequency component of the input luminance signal is extracted by the high frequency filtering circuit, and this is full-wave rectified by the full-wave rectification circuit to detect the amount of the video high frequency component. The average value of the vertical sync signal period of the detected signal is detected by the sample and hold circuit, and the detected voltage is held during the effective video signal period. In this case, the noise of the video signal is automatically suppressed by turning on the noise suppression circuit and weakening the input video luminance signal according to the voltage. Thus, the noise detection position of the input video signal is a predetermined period within the vertical blanking period (hereinafter, vertical blanking period).
[0003]
In recent years, there is a video device that outputs a video signal on which a copy guard signal is superimposed. For example, it is a recording / playback device such as a digital video disc (DVD) or home VTR software on which a copy guard signal is recorded and superimposed. This copy guard signal is intended to prevent normal recording with a home VTR. Among such copy guard systems, there is a technique that superimposes a video signal having a white peak in the vertical blanking period. If such a signal is superimposed on the vertical blanking period, the conventional noise detection circuit may erroneously detect the copy guard signal as a noise component.
[0004]
Generally, a character multiplexed signal or the like is superimposed in the vertical blanking period of the TV video signal, but a copy guard signal is further superimposed. Further, in a home VTR, head switching noise occurs during the vertical synchronization period. Such noise detection in the vertical blanking period may cause erroneous detection.
[0005]
In recent TV receivers, digital processing circuits such as a line comb filter and a three-dimensional Y / C separation circuit have been introduced. If noise detection is performed, for example, in the horizontal sync signal portion other than the back porch in the horizontal blanking period, it is necessary to perform quantization including the noise amplitude superimposed on the front end (sync chip) of the horizontal sync signal. In this way, the input range must be included up to a range that is not originally a video scanning period, and the S / N of the video signal at the time of quantization in the A / D conversion circuit is degraded.
[0006]
[Problems to be solved by the invention]
As described above, in the conventional noise detection circuit, there is a risk that the noise detection circuit erroneously determines by the copy guard signal superimposed in the vertical blanking period. Further, if noise detection is performed in the horizontal sync signal portion, the input range of the A / D conversion circuit required for digital processing must be expanded more than necessary, and the S / N of the video signal may be degraded. was there.
[0007]
Accordingly, in view of the above problems, the present invention provides a noise level detection circuit capable of performing stable and highly accurate noise detection even for a video signal on which a copy guard signal is superimposed or a digitally processed video signal. It is for the purpose.
[0015]
[Means for Solving the Problems]
  Claim1The noise level detection circuit according to the present invention includes a circuit for extracting an AC component of a luminance signal and rectifying the AC component, and means for generating a gate pulse for noise level detection during a predetermined period of the back porch in the horizontal blanking period And a sample integration circuit that samples and integrates the signal after the AC component rectification in the period of the gate pulse, and a gate pulse control means that controls the gate pulse at different arbitrary positions.
[0016]
  Claim2The described invention is claimed.1In the described noise level detection circuit, the gate pulse control means controls the gate pulse position so that the noise detection value by the sample integration circuit is minimized.
[0017]
  Claim1, 2According to this invention, the noise component detection accuracy can be improved by setting the noise level detection gate position in the back porch period so that the noise detection value by the sample integration circuit is minimized.
[0018]
  Claim3The noise level detection circuit according to the present invention is a noise level detection circuit that automatically determines an optimum position of a noise level detection gate pulse with respect to an input luminance signal, and the input luminance signal is band-passed by a band pass filter. After limiting, the filter output is subjected to absolute value conversion to limit within a certain level, a detection control circuit that controls a plurality of noise integration circuits based on the input horizontal and vertical synchronization signals, and the luminance Sample integration circuit that integrates N (N is a natural number) pixels by a noise level detection gate pulse that is finally obtained based on a control signal from the detection control circuit in a predetermined period of the back porch of the horizontal blanking period of the signal And a line integration circuit for integrating the output of the sample integration circuit with M (M is a natural number) lines by a control signal from the detection control circuit. A field integration circuit that integrates the output of the line integration circuit by L (L is a natural number) field by a control signal from the detection control circuit, and a noise level detection gate pulse is converted into a luminance signal in response to an instruction from the microcomputer. A determination control circuit for generating various control signals for determining the optimum position for the position, and a position of a noise level detection gate pulse used in the sample integration circuit based on a signal output from the determination control circuit The delay level selection circuit and the noise level detection gate pulse are set arbitrarily n times (n: natural number) at different positions in the delay level selection circuit, and the integration result of the sample line in each state is also obtained. And an optimum position determination circuit for determining an optimum noise level detection gate position, and a determination result from the optimum position determination circuit Based on, controls the delay selection circuit, while maintaining the noise level detection gate in optimum position, characterized in that to enable a stable noise-level detection.
[0019]
  Claim3According to the invention, when the noise level detection gate pulse is set in the back porch period of the horizontal blanking period, the noise level detection gate pulse is arbitrarily set n times (n: natural number) at different positions, Based on the integration results of the sample lines in each state, an optimal position determination circuit that determines the optimal noise level detection gate position is provided, so delay selection based on the determination result from the optimal position determination circuit By controlling the circuit and holding the noise level detection gate at the optimum position, stable noise level detection can be performed.
[0020]
  Claim4The described invention is claimed.3In the described noise level detection circuit, when the delay selection circuit performs the determination by changing the gate pulse position n (n: natural number) times, the optimum noise level is determined among m (m: natural number) determinations near the center. A circuit for providing an offset value so as to be the detection gate position is further provided, so that the optimum position of the noise level detection gate can be stably detected regardless of disturbance.
[0021]
  Claim4According to the present invention, in order to make it difficult to determine the wrong detection position as the optimum due to accidental noise during the determination of the optimum position of the noise level detection gate, it is determined to be the optimum position stably stably. An offset period (identification period) is provided at the position of the range to make it easy to determine an originally stable period as the optimum position (increase the determination probability).
[0022]
  Claim5The described invention is claimed.3In the described noise level detection circuit, it is determined from the input horizontal and vertical synchronization signals whether the input luminance signal is a standard signal or a non-standard signal as in VTR special reproduction, and the determination result is non-standard. It further comprises a standard determination circuit that generates a control signal for re-determining the optimum position of the noise detection gate when it changes from standard to standard, and supplies the control signal to the determination control circuit.
[0023]
  Claim5According to this invention, the standard / non-standard signal is determined from the synchronization signal of the input signal, and when the determination changes from non-standard to standard, the optimum position of the noise level detection gate is determined again. As a result, the position of the noise level detection gate can be determined in a standard state of a stable signal.
[0024]
  Claim6The described invention is claimed.3In the noise level detection circuit described above, when the value of the noise level detection result detected by the field integration circuit changes greatly, a control signal is generated again to determine the optimum position of the noise detection gate, and the determination control A circuit for supplying the circuit is further provided.
[0025]
  Claim6According to this invention, when the value of the noise level detection result changes greatly, the optimum position of the noise level detection gate is determined again. As a result, the claim5Similarly, the position of the noise level detection gate can be determined in a standard state of a stable signal.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a noise level detection circuit according to the first embodiment of the present invention.
[0027]
In FIG. 1, a noise level detection circuit includes an input terminal 101 for inputting an analog luminance signal, an A / D conversion circuit 102 for converting the analog luminance signal into a digital luminance signal, and an AC component of the digital luminance signal. A band-pass filter (BPF) 103 for extraction and full-wave rectification of the AC component to convert it to an absolute value (the entire AC component is expressed by only the absolute value by converting the negative electrode component in the AC component to the positive electrode component) ), A sample integration circuit 105 for sample-integrating the rectified signal in a predetermined period of the back porch in the horizontal blanking period, and integrating the signal after the sample integration for a predetermined scanning line period. A line integration circuit 106 for holding the line integration result, a holding circuit 107 for holding the line integration result, and this holding signal as a noise level detection signal. Output terminal 108, a clock generation circuit 109 for generating a clock pulse used for sampling or the like based on a horizontal synchronization signal (HD), a vertical synchronization signal (VD), a horizontal synchronization signal (HD), and the clock pulse A timing generation circuit 110 that generates a timing signal such as a gate pulse that determines the integration period of each of the sample integration circuit 105 and the line integration circuit 106, and a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) of the input luminance signal Are provided with input terminals 111 and 112, respectively.
[0028]
In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102 and input to the full-wave rectifier circuit 104 via the BPF 103. The BPF 103 extracts a Takashiro AC component of about 2 MHz or more that is visually noticeable from the digital luminance signal. It is assumed that the color burst signal included in the back porch in the horizontal blanking period of the analog luminance signal has been removed by the process preceding the input terminal 101.
[0029]
The output signal of the full-wave rectifier circuit 104 is integrated by a sample integration circuit 105 for a predetermined sample period. Here, the predetermined sample period is set to a relatively stable predetermined period in the back porch of the horizontal blanking period of the luminance signal.
[0030]
The sample integration circuit 105 has the same clock as the sampling clock used in the adder 120, the AND gate 121 to which the gate pulse a from the timing generation circuit 110 is supplied, and the A / D conversion circuit 102 from the clock generation circuit 109. The D flip-flop 122 is supplied and operates.
[0031]
The adder 120 adds the output signal of the full-wave rectifier circuit 104 and the output signal of the flip-flop 122. A gate pulse a is input to the AND gate 121, and an output signal of the adder 120 is guided to the flip-flop 122 only when the gate pulse a is at the ‘H’ level. When the gate pulse a is ‘L’ level, the output signal of the AND gate 121 becomes ‘L’ level regardless of the output signal of the adder 120, and therefore the output signal of the flip-flop 122 also becomes ‘L’ level. That is, the sample integration circuit 105 performs an integration operation on the output signal of the full-wave rectification circuit 104, which is an absolute value circuit, only when the gate pulse a is at the "H" level. FIGS. 2A and 2B show the timing of the gate pulse a.
[0032]
The output signal of the sample integration circuit 105 is input to the line integration circuit 106. The line integration circuit 106 has an adder 123, an AND gate 124 to which the gate pulse b from the timing generation circuit 110 is supplied, and a sampling clock used by the A / D conversion circuit 102 from the clock generation circuit 109. The D flip-flop 125 is supplied and operates.
[0033]
In the adder 123, the output signal of the sample integration circuit 105 and the output signal of the flip-flop 125 are added, and the output signal of the adder 123 is input to the flip-flop 125 via the AND gate 124. That is, the line integration circuit 106 performs the integration operation of the output signal of the sample integration circuit 105 only during the period when the gate pulse b input to the AND gate is at the “H” level, like the sample integration circuit 105. 3A and 3B show the timing of the gate pulse b.
[0034]
In home video tape recorders (VTRs), skew may occur in the vertical blanking period, so it is advantageous to allow for the skew to be retracted and to occur at the timing as shown in FIG. It is sufficient to set the timing at which the gate pulse b rises 50 to 60 lines after the end of the vertical blanking period.
[0035]
The integrated output of the line integration circuit 106 is held in the flip-flop 107 only for a necessary period by the timing signal from the timing generation circuit 110, and is output from the output terminal 108 as a noise level detection signal.
[0036]
For example, if the frequency of the sampling clock CLK is 910 times the horizontal synchronization frequency, the gate pulse a in the back porch in the horizontal blanking period corresponds to 24 samples and has a pulse width of about 1.7 μs. That is, 24 samples are integrated in a predetermined period of the back porch using the gate pulse a having a pulse width of 1.7 μs.
[0037]
If the value obtained by integrating 24 samples is integrated by, for example, 128 lines using the gate pulse b in the line integration circuit 106, 3072 samples per field are obtained, which is the number of samples corresponding to 3 lines or more in the horizontal scanning period. , Stable noise detection becomes possible.
[0038]
FIG. 4A shows the input signal and output signal of the full-wave rectifier circuit 104. The sample signal before full wave rectification after passing through the BPF 103 has a positive electrode part and a negative electrode part centering on the 0 level, but the sample signal after full wave rectification of the positive and negative signals through the full wave rectifier circuit 104 is the negative electrode part. Is folded back to the positive side and converted into an absolute value. The sample signals before and after full-wave rectification are 0, 3, 4, and 5 indicating the absolute value of each sample. Actually, since it is quantized by A / D conversion, 0, 3, 4, and 5 after full-wave rectification are expressed as 000, 011, 100, and 101 as 3-digit binary numbers. The explanation will be made as signals of the decimal numbers 0, 3, 4, and 5.
[0039]
  FIG. 4B is a diagram for explaining the operation of the sample integration circuit 105. The case where the sample signal after the full-wave rectification shown in FIG. 4A (signals having absolute values 0, 3, 4, and 5) is sequentially input to the sample integration circuit 105 as the input S1 will be described. In the sample integration circuit 105, S1 is an output signal (adder) of the full-wave rectification circuit 104.120S2 indicates the output signal of the AND gate 121, and S3 indicates the output signal of the flip-flop 122 (adder).120The other input signal of FIG. In the sample integration circuit 105, during the period when the gate pulse a to the AND gate 121 is at the “H” level, the relationship of S1 + S3 = S2 is established, and the added value S2 is input to the flip-flop 122 at the next stage and It is output as signal S3 at the rising edge of CLK. The integrated output S3 finally becomes 5 + 7 = 12, for the sequential input sample signals (0, 3, 4, 5) of the input S1. When the gate pulse a of the AND gate 121 becomes ‘L’ level, the signal S2 becomes 0, and 0 is output from the flip-flop 122 as the signal S3 at the rising edge of the next clock pulse CLK.
[0040]
FIG. 5 shows a block diagram of a noise level detection circuit according to the second embodiment of the present invention. The difference from FIG. 1 is that a field integration circuit 202 is provided in the subsequent stage of the line integration circuit 106.
[0041]
The integration output of the line integration circuit 106 is held by the flip-flop 201 and then input to the field integration circuit 202.
[0042]
The field integration circuit 202 is supplied with the same clock as the sampling clock used in the A / D conversion circuit 102 from the adder 210, the AND gate 211 to which the gate pulse c from the timing generation circuit 205 is supplied, and the clock generation circuit 109. And the D flip-flop 212 that operates in this manner, and performs an integration operation while the gate pulse c to the AND gate 211 is at the “H” level. That is, the field integration circuit 202 inputs the signal after line integration, integrates it for a predetermined field period defined by the gate pulse c, and outputs it. The timing generation circuit 110 generates gate pulses a and b based on horizontal and vertical synchronization signals (HD and VD) and clock pulses as well as the timing generation circuit 110 of FIG. 1, and also generates horizontal and vertical synchronization signals (HD and V). VD) and a clock pulse are generated based on the clock pulse.
[0043]
The integration output of the field integration circuit 202 is held in the flip-flop 107 only for a necessary period by the timing signal from the timing generation circuit 110, and is output from the output terminal 108 as a noise level detection result.
[0044]
With this configuration, noise level detection is performed on the signal obtained by integrating the noise component sampled in the back porch period of the horizontal blanking period for a predetermined number of scanning line periods and field integrated for a predetermined number of fields. As a result.
[0045]
FIG. 6 is a block diagram of a noise level detection circuit according to the third embodiment of the present invention.
[0046]
In FIG. 6, the noise level detection circuit includes an input terminal 101 for inputting an analog luminance signal, an A / D conversion circuit 102 for converting the analog luminance signal into a digital luminance signal, and an AC component of the digital luminance signal. BPF 103 for extraction, full-wave rectification circuit 104 for full-wave rectification of the AC component to convert it to an absolute value, holding circuit 107 for holding the signal after sample integration, and noise level detection of the holding signal A signal output terminal 108, a detection control circuit 512 for controlling the sample integration circuit 105 based on the input horizontal and vertical synchronization signals (HD, VD), and a rectified signal from the full-wave rectification circuit 104 The noise level is finally obtained based on the control signal from the detection control circuit in a predetermined period of the back porch in the horizontal blanking period. A sample integration circuit 105 for sampling and integrating N (N is a natural number) pixels by the detection gate pulse, and various control signals for determining that the noise level detection gate pulse is at an optimum position with respect to the luminance signal. And a delay selection that varies the gate pulse position by changing the delay amount of the noise level detection gate pulse used in the sample integration circuit 105 based on the signal output from the determination control circuit 521 The circuit 522 and the noise level detection gate pulse are set arbitrarily n times (n: natural number) at different positions in the delay selection circuit 522, and the integration result is based on the sample integration result in each state. The optimum position determination circuit 52 that determines the phase of the gate pulse that has the minimum level as the optimum noise level detection gate position The determination control circuit 521 determines a gate pulse delay amount based on the optimum position determination result from the optimum position determination circuit 523, and controls the delay selection circuit 522 to control the noise level. Stable noise level detection is possible by setting the detection gate to the optimum position.
[0047]
In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102 and input to the full-wave rectifier circuit 104 via the BPF 103. The BPF 103 extracts a Takashiro AC component of about 2 MHz or more that is visually noticeable from the digital luminance signal. Note that the color burst signal included in the back porch in the horizontal blanking period of the analog luminance signal is removed by the process preceding the input terminal 101. The output signal of the full-wave rectifier circuit 104 is supplied to the sample integration circuit 105 for noise level detection, where it is sampled and integrated for a predetermined period in the back porch in the horizontal blanking period. The predetermined period of this sample integration is set to a period in which the waveform level is stable and the noise level is minimized in the back porch in the horizontal blanking period of the luminance signal by optimal position control of the noise level detection gate described later.
[0048]
On the other hand, for the control system for controlling the noise level detection gate to the optimum position, the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) of the input luminance signal are input from the input terminals 112 and 111, respectively, and detection control is performed. This is given to the circuit 512. The detection control circuit 512 gives a control signal such as a reset signal to the sample integration circuit 105 and gives a noise level detection gate pulse to the delay selection circuit 522.
[0049]
The determination control circuit 521 generates a control signal for changing the delay amount of the noise level detection gate pulse output from the detection control circuit 512 in the delay selection circuit 522.
[0050]
The optimum position determination circuit 523 compares each integration result when the phase of the noise level detection gate pulse is changed n times by the determination control circuit 521, and the noise level detection gate pulse whose integration value becomes the minimum level. Is determined as the optimum position, and the optimum position n is returned to the judgment control circuit 521.
[0051]
The determination control circuit 521 gives a control signal to the delay selection circuit 522 so as to hold the optimal position n of the noise level detection gate pulse based on the determination result of the optimal position determination circuit 523.
[0052]
The result of the sample integration circuit 105 is output to the holding circuit 107, held for an arbitrary period by the noise level holding control signal given from the detection control circuit 512, and output as a noise level detection signal from the output terminal 108. Yes. As described above, even if the back porch in the horizontal blanking period of the input luminance signal changes depending on the state of the input signal (television signal by radio wave, VTR signal, DVD signal, game machine signal) (the luminance signal waveform in FIG. 8). The noise level detection gate can be stably detected by setting the noise level detection gate to the optimum position.
[0053]
FIG. 7 shows a block diagram of a noise level detection circuit according to the fourth embodiment of the present invention.
[0054]
In FIG. 7, the noise level detection circuit includes an input terminal 101 for inputting an analog luminance signal, an A / D conversion circuit 102 for converting the analog luminance signal into a digital luminance signal, and an AC component of the digital luminance signal. BPF 103 for extraction, full-wave rectification circuit 104 for full-wave rectification of the AC component to convert it to an absolute value, limiter circuit 603 for limiting the upper limit level of the rectified signal, input horizontal and vertical synchronization Based on the signals (HD, VD), a detection control circuit 512 that controls the plurality of noise integration circuits 106 and 202, and a back porch in the horizontal blanking period of the luminance signal, the control signal from the detection control circuit 512 is A sample integration circuit 105 that integrates N (N is a natural number) pixels by a finally obtained noise level detection gate pulse; A sample integration circuit 105 for integrating M (M is a natural number) lines by a control signal from the detection control circuit 512, and an output of the line integration circuit 106 from the detection control circuit 512. A field integration circuit 202 that integrates L (L is a natural number) fields by a control signal, a holding circuit 107 that holds a signal after field integration, an output terminal 108 that outputs the holding signal as a noise level detection signal, and a microcomputer In response to an instruction from 620, a determination control circuit 521 for generating various control signals for determining that the noise level detection gate pulse is in an optimum position with respect to the luminance signal, and an output from the determination control circuit 521 The noise level detection gate pulse used for the sample integration circuit 105 is based on the processed signal. The delay selection circuit 522 for changing the position of the gate pulse by changing the extension amount, and the noise level detection gate are set arbitrarily n times (n: natural number) at different positions in the delay selection circuit 522, And an optimal position determination circuit 523 that determines the phase of the gate pulse at which the integration result is at the minimum level as the optimal noise level detection gate position based on the result of the sample line integration in the state. Based on the optimal position determination result from the circuit 523, the determination control circuit 521 determines the delay amount of the gate pulse, controls the delay selection circuit 522, and sets the noise level detection gate to the optimal position. Stable noise level detection is possible.
[0055]
In the above configuration, the luminance signal input from the input terminal 101 is converted into a digital signal by the A / D conversion circuit 102 and input to the full-wave rectifier circuit 104 via the BPF 103. The BPF 103 extracts a Takashiro signal that is visually conspicuous in the vicinity of about 2 MHz from the luminance signal and supplies it to the full-wave rectifier circuit 104 in the subsequent stage.
[0056]
In the full-wave rectifier circuit 104, the output of the BPF 103 is converted into an absolute value, and then given to the limiter circuit 603 to limit the upper limit level and supplied to the subsequent sample integration circuit 105.
[0057]
On the other hand, for the control system for controlling the noise level detection gate to the optimum position, the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) of the input luminance signal are input from the input terminals 112 and 111, respectively, and detection control is performed. This is given to the circuit 512.
[0058]
In the detection control circuit 512, a noise level detection gate pulse, a line integration control signal, and a field integration control signal for controlling the sample integration circuit 105, the line integration circuit 106, the field integration circuit 202, and the noise level holding circuit 107, respectively. And a noise level holding control signal.
[0059]
When the determination control circuit 521 receives a noise level determination instruction from the microcomputer 620, the determination control circuit 521 changes the delay amount of the noise level detection gate pulse output from the detection control circuit 512 to the delay selection circuit 522. A control signal for generating
[0060]
In the delay selection circuit 522, the phase of the noise level detection gate pulse output by the control signal from the determination control circuit 521 is set to n (n: natural number) with respect to the back porch in the horizontal blanking period of the input luminance signal. The delay amount can be varied. Then, with the noise level detection gate pulse output from the delay selection circuit 522, the sample integration circuit 105 performs integration for an arbitrary fixed period corresponding to the gate pulse in the back porch of the horizontal blanking period of the luminance signal, The result is given to the line integration circuit 106.
[0061]
The line integration circuit 106 performs integration for a predetermined line period by the line integration control signal given from the detection control circuit 512, and gives the result to the optimum position determination circuit 523 and the field integration circuit 202. The optimum position determination circuit 523 compares the integration results when the phase of the noise level detection gate pulse is changed n times by the determination control circuit 521, and optimizes the phase of the noise level detection gate pulse that becomes the minimum level. The optimum position n is returned to the judgment control circuit 521.
[0062]
In the determination control circuit 521, based on the determination result of the optimal position determination circuit 523, a control signal for holding the optimal position n is given to the delay selection circuit 522, and the delay selection circuit 522 provides an optimal noise level detection gate pulse. , The sample integration in the back porch is performed, the line integration is further performed, and then the integration result is given to the field integration circuit 202.
[0063]
The field integration circuit 202 performs integration for an arbitrary predetermined field period by the field integration control signal given from the detection control circuit 512, and gives the noise integration result to the noise level holding circuit 107.
[0064]
The noise level holding circuit 203 updates the noise level holding signal every arbitrary fixed field period by the noise level holding control signal given from the detection control circuit 512, and outputs it as a noise level detection signal from the output terminal 108. ing.
[0065]
As described above, even if the back porch in the horizontal blanking period of the input luminance signal changes depending on the state of the input signal (television signal by radio wave, VTR signal, DVD signal, game machine signal) (the luminance signal waveform in FIG. 8). The noise level detection gate can be stably detected by setting the noise level detection gate to the optimum position.
[0066]
Next, another embodiment of the operation for determining the optimum position of the noise level detection gate pulse when the noise level detection circuit of FIG. A description will be given with reference to FIG.
[0067]
FIG. 8 shows a situation in which waveform fluctuation occurs at both ends (edges) of the back porch of the luminance signal depending on the type of the luminance signal (television signal by radio, VTR signal, DVD signal, game machine signal, etc.) (indicated by a plurality of solid lines). Even if there is disturbance noise in the originally stable period corresponding to the middle of the back porch, the originally stable period corresponding to the middle of the back porch is determined as the optimum position of the noise level detection gate. In order to increase the probability, there is provided means for giving an offset period (4 hex in the figure, hex means hexadecimal) for making it easy to perform an optimum position determination and an offset period for identifying the originally stable period. Yes. That is, in the back porch period, when the delay selection circuit 522 performs the determination by changing the noise level detection gate position n (n: natural number) times, it is optimal among the determinations m (m: natural number) near the center. Means are further provided for giving a predetermined offset value to the line integral value in the range (offset period) of the gate position m times near the center so as to be the noise level detection gate position.
[0068]
Then, when noise level detection is performed by changing the gate position n times within the back porch period, the offset value is subtracted for m times near the center from the sample / line integration results for each time. As a result, when disturbance noise occurs near the center of the back porch period, the integral value near the center increases due to the disturbance noise, but is subtracted by the offset value, so that the optimum value for determining the optimum position is calculated to be small. The noise level detection gate position can be set near the stable center of the back porch. The means for giving the offset value and the means for subtracting the offset value may be provided in the optimum position determination circuit 523.
[0069]
FIG. 9 is a timing chart for explaining the optimum position determination operation of the noise level detection gate shown in FIG.
[0070]
The gate position control signal in FIG. 9A indicates control information output from the determination control circuit 521.
[0071]
The line integration result in FIG. 9B shows the integration result of the sample line at each gate position.
[0072]
The offset period of FIG. 9 (c) is provided in an originally stable period in which the noise level detection gate pulse is not easily affected by ringing or the like with respect to the back porch in the horizontal blanking period of the input luminance signal. . That is, in the offset period in the back porch, if the type of input luminance signal such as a VTR signal is different, the signal level is unstable at the rising edge of the waveform as shown by a plurality of solid lines in FIG. It is provided for a stable period.
[0073]
The offset value in FIG. 9 (d) is an arbitrary fixed value, and the offset value is set so that the optimal position is not determined at the edge portion of the back porch due to a sudden factor when determining the optimal position. Provided.
[0074]
The judgment input value in FIG. 9 (e) is a value obtained by subtracting each offset value (FIG. 9 (d)) in the offset period in FIG. 9 (c) from the sample line integration result in FIG. 9 (b). .
[0075]
The determination result in FIG. 9 (f) is a result of determining the minimum value (MIN) among the determination input values in FIG. 9 (e).
[0076]
As described above, even when disturbance noise occurs at the originally stable intermediate position of the back porch, by subtracting the offset value at the intermediate position, the noise level detection gate is less affected by disturbance when determining the optimum position, and the noise level The optimum position of the detection gate can be detected stably.
[0077]
FIG. 10 is a block diagram of a noise level detection circuit according to the fifth embodiment of the present invention.
[0078]
In FIG. 10, a standard determination circuit 730 is further provided in the configuration of FIG. Other configurations are the same as those in FIG. The standard determination circuit 730 uses the horizontal and vertical synchronization signals (HD, VD) input from the input terminals 112 and 111 to determine whether the input luminance signal is a standard signal or VTR special playback (for example, rewind playback, fast forward playback, etc.). When the determination result changes from non-standard to standard, a control signal for re-determining the optimum position of the noise detection gate is given to the determination control circuit 521 again. Is for.
[0079]
Specifically, the standard determination circuit 730 includes a means for generating a clear pulse with a vertical synchronization signal (VD) of the input luminance signal, an internal counter for counting the number of horizontal synchronization signals (HD) of the input luminance signal, A holding means for holding a value and a comparator for comparing the held count value with a prepared value are provided, and the clear pulse is supplied to the clear terminal of the internal counter. The internal counter is cleared with a clear pulse to start counting the number of horizontal synchronizing signals (HD), and the internal counter is cleared with a clear pulse by the next vertical synchronizing signal (VD) and at the same time the count value is held in the holding means. . Then, the held value and a prepared value are compared by a comparator, and either one of the count values 262/263 or 312/313 is detected continuously for a predetermined predetermined field period. Sometimes it is judged as standard. Here, 262/263 indicates that the count values 262 and 263 appear alternately for each field when the television system is the M system, and 312/313 indicates that the television system is the B, G, I system, or the like. In this case, the count values 312 and 313 appear alternately for each field. When the determination result shifts from the non-standard to the standard state, the standard determination circuit 730 outputs a control signal for re-determining the optimum position of the noise level detection gate to the determination control circuit 521.
[0080]
As an example of the transition from the non-standard state to the standard state, when switching from the standard state (262/263) receiving, for example, the first channel (1CH) by television radio waves to the VTR playback signal, Until the standard state (262/263) is switched, the standard state (262/263) of 1CH is switched to the standard state (262/263) of VTR playback through the non-standard state (250/270). Also, special playback states such as rewind playback and fast forward playback of the VTR are non-standard states, and there is a case where the non-standard state of special playback shifts to the standard state of VTR playback (262/263).
[0081]
With the configuration of FIG. 10, when performing the optimum position control of the noise level detection gate as in the embodiment of FIG. 7, even if the signal of the input terminal 101 is in a non-standard state as in the VTR special playback, After that, when the standard state is changed to a stable signal state, non-standard → standard change is detected and the optimum position of the noise level detection gate is re-determined. Can be determined.
[0082]
In place of the standard determination circuit 730 in the embodiment of FIG. 10, when the value of the noise level detection signal detected by the holding circuit 107 based on the integration result of the field integration circuit 202 changes significantly, the determination control circuit 521 may be provided with a circuit (not shown) for providing a control signal for re-determining the optimum position of the noise detection gate.
[0083]
According to the embodiment of the present invention described above, the AC component extracted from the input luminance signal is rectified and converted into an absolute value and sampled and integrated in a predetermined period of the back porch in the horizontal blanking period. Therefore, stable and highly accurate noise detection can be performed on a video signal on which a copy guard signal is superimposed and a digitally processed video signal whose input range is limited.
[0084]
Furthermore, it has the following advantages (1) to (3).
[0085]
(1). The optimum noise level detection gate position can be automatically determined according to the state of the back porch within the horizontal blanking period of the input signal, and stable noise level detection is possible.
[0086]
(2). When determining the optimum position of the noise level detection gate, an offset value is given in a period during which noise detection can be performed stably stably, so that it is difficult to be affected by accidental disturbance at the time of determination.
[0087]
(3). When it is detected that the input signal has switched from non-standard to standard, by re-determining the optimum position of the noise level detection gate, a signal that the microcomputer in the normal video equipment cannot grasp the input status, For example, it is possible to detect a noise level with high accuracy even for a VTR signal from an external input terminal.
[0088]
In the embodiment described above, an analog luminance signal is input, and a configuration in which the noise level is detected by A / D conversion of the analog signal is described. However, the present invention is a digital signal. Without being limited to the case where noise level detection is performed, noise level detection is performed by removing the A / D conversion circuit and passing the analog signal from the analog luminance signal without passing through the APF after the BPF. Is possible.
[0089]
【The invention's effect】
As described above, according to the present invention, stable and highly accurate noise detection can be performed for a video signal on which a copy guard signal is superimposed or a digitally processed video signal.
[Brief description of the drawings]
FIG. 1 is a block diagram of a noise level detection circuit according to a first embodiment of this invention.
FIG. 2 is a diagram for explaining a gate pulse a in FIG.
FIG. 3 is a diagram for explaining a gate pulse b in FIG. 1;
FIG. 4 is an explanatory diagram for explaining the operation of FIG. 1;
FIG. 5 is a block diagram of a noise level detection circuit according to a second embodiment of the present invention.
FIG. 6 is a block diagram of a noise level detection circuit according to a third embodiment of the present invention.
FIG. 7 is a block diagram of a noise level detection circuit according to a fourth embodiment of the present invention.
8 is an explanatory diagram for explaining another embodiment of the optimum position determination operation of the noise level detection gate in FIG.
9 is a timing chart for explaining an optimum position determination operation of the noise level detection gate shown in FIG.
FIG. 10 is a block diagram of a noise level detection circuit according to a fifth embodiment of the present invention.
[Explanation of symbols]
101 ... Input luminance signal
102. A / D conversion circuit
103: Band pass filter
104 ... Full-wave rectifier circuit (absolute value circuit)
105: Sample integration circuit
106: Line integration circuit
107: holding circuit
108: Noise level detection signal output terminal
111 ... Vertical synchronization signal
112 ... Horizontal synchronization signal
202 ... Field integration circuit
512. Detection control circuit
521 ... Determination control circuit
522 ... Delay selection circuit
523 ... Optimal position determination circuit
620 ... Microcomputer
730 ... Standard judgment circuit

Claims (6)

A circuit for extracting the AC component of the luminance signal and rectifying the AC component;
Means for generating a gate pulse for noise level detection in a predetermined period of the back porch in the horizontal blanking period;
A sample integration circuit that samples and integrates the signal after the AC component rectification in the period of the gate pulse;
Gate pulse control means for controlling the gate pulse to different arbitrary positions;
A noise level detection circuit comprising: 2. The noise level detection circuit according to claim 1, wherein the gate pulse control means controls a gate pulse position so that a noise detection value by the sample integration circuit is minimized. A noise level detection circuit that automatically determines the optimum position of a noise level detection gate pulse for an input luminance signal,
A circuit that limits the band of the input luminance signal with a band pass filter, then converts the filter output to an absolute value, and gives a limit within a certain level;
A detection control circuit for controlling a plurality of noise integration circuits based on the input horizontal and vertical synchronization signals;
Sample in which N (N is a natural number) pixels are integrated by a noise level detection gate pulse finally obtained based on a control signal from the detection control circuit in a predetermined period of the back porch of the horizontal blanking period of the luminance signal An integration circuit;
A line integration circuit for integrating the output of the sample integration circuit with M (M is a natural number) lines by a control signal from the detection control circuit;
A field integration circuit for integrating the output of the line integration circuit by L (L is a natural number) field by a control signal from the detection control circuit;
In response to an instruction from the microcomputer, a determination control circuit that generates various control signals for determining that the noise level detection gate pulse is in an optimum position with respect to the luminance signal;
A delay selection circuit that varies the position of a noise level detection gate pulse used in the sample integration circuit based on the signal output from the determination control circuit;
The noise level detection gate pulse is set arbitrarily n times (n: natural number) at different positions in the delay selection circuit, and the optimum noise level detection gate is based on the integration result of the sample line in each state. An optimum position determination circuit for determining a position,
Noise that controls the delay selection circuit based on the determination result from the optimal position determination circuit and enables stable noise level detection in a state where the noise level detection gate is held at the optimal position. Level detection circuit. When the delay selection circuit makes a determination by changing the gate pulse position n (n: natural number) times, an offset is set so that the optimum noise level detection gate position is obtained in m (m: natural number) determinations near the center. 4. The noise level detection circuit according to claim 3, further comprising a circuit for giving a value so that the optimum position of the noise level detection gate can be stably detected regardless of disturbance. When the input horizontal and vertical sync signals are used to determine whether the input luminance signal is a standard signal or a non-standard signal such as during VTR special playback, and the determination result changes from non-standard to standard 4. The noise level detection circuit according to claim 3, further comprising a standard determination circuit that generates a control signal for re-determining the optimum position of the noise detection gate and supplies the control signal to the determination control circuit. A circuit that generates a control signal for re-determining the optimum position of the noise detection gate and supplies the determination signal to the determination control circuit when the value of the noise level detection result detected by the field integration circuit changes greatly; 4. The noise level detection circuit according to claim 3, wherein

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