JP3948694B2 - Image reading apparatus and image processing apparatus including the image reading apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image reading apparatus, and more specifically, in image reading in which an original image signal photoelectrically converted by a linear image sensor such as a CCD is converted into a digital signal and processed, an odd pixel and an even pixel in the read image signal are processed. The present invention relates to an image reading apparatus capable of reducing an output difference, and an image processing apparatus such as a scanner, an electrophotographic copying machine, and a fax machine including the image reading apparatus.
[0002]
[Prior art]
A conventional image reading apparatus is used in a scanner, an electrophotographic copying machine, a FAX, or the like, and has an apparatus configuration illustrated in FIG.
The image reading apparatus shown here includes a contact glass 1 on which a document 15 is placed, a halogen lamp 2 for illuminating a document, a first carriage 6 on which a first reflection mirror 3 is mounted, a second reflection mirror 4 and a third reflection mirror. The second carriage 7 on which the mirror 5 is mounted, the lens unit 8 that forms an image of a document transmitted from the document 14 via the first to third reflecting mirrors 3 to 5, and the image of the lens unit 8 on the sensor board 10 A CCD linear image sensor 9 (hereinafter simply referred to as “CCD”) disposed on the surface, a white reference plate 15 for correcting various distortions due to a reading optical system, and the like, and the sensor board 10 drives the CCD 9 to drive an image. And a signal processing unit 12 for processing an image signal output via the signal cable 11.
In the CCD 9 for reading an image, a plurality of pixels (photoelectric conversion elements) are arranged in a line, and electric charges accumulated according to the amount of light received by each pixel are sequentially extracted along a pixel line by main scanning at a predetermined repetition cycle. At the same time, the first carriage 6 and the second carriage 7 are moved by the stepping motor in the sub-scanning direction (A direction in the figure) crossing the main scanning direction, whereby the image on the entire surface of the document is read by the photoelectric conversion element, and is used as an image signal. Output.
[0003]
FIG. 9 shows a more detailed block diagram of the signal processing unit 12 that processes the output image signal of the CCD 9.
In the signal processing performed by the signal processing unit 12 until the digital image signal is obtained from the output of the CCD 9, first, the image signal VO (odd pixel signal) and VE (even pixel signal) are output from the CCD 9 in synchronization with the drive pulse. Then, the image signals VO and VE are sampled by the sample pulse by the sample and hold circuit 16 and are held, thereby making the image signal a continuous analog signal. Next, after the black level correction circuit 17 corrects the variation in the dark output level of the CCD in the analog image signal, the amplification circuit 18 converts each color (not shown, but in the case of color reading, R, G, (The read image signal is processed for each color B) After the odd and even pixel image signals VO and VE are set to a certain level, the multiplex circuit 19 multiplexes the odd and even pixel outputs to multiplex the image signal V. It is said. The image signal V is amplified to the level of the reference voltage for A / D conversion by the amplifier circuit 20 and then converted to 8-bit digital data by the A / D conversion circuit 21. The digital image signal thus obtained is a correction value prepared in the shading correction circuit 22 (that is, a predetermined density level obtained by reading the reflected light of the white reference plate 15 irradiated by the halogen lamp 2 with the CCD 9. The correction value) is used to correct variations in sensitivity of the CCD 9 and uneven light distribution in the irradiation system. Although not shown in the drawing, various digital image processing is performed on the image data, and the external image data is used. Are sent to the circuit or device via I / F 25.
[0004]
By the way, it can be generally said that a CCD shift register for odd pixels and a CCD shift register for even pixels are used. However, the output signal levels of the odd pixel signal VO and the even pixel signal VE are different due to the difference in characteristics of the shift register. There is a difference. In particular, in the case of having a multi-line CCD shift register such as a 3-line color CCD, the interference between the shift registers causes this odd-even difference.
This odd / even difference is also corrected on the white side and the black side in the amplification circuit 18 and the black level correction circuit unit 17 in the signal processing described above, but when the linear characteristics are different between the odd pixel signal and the even pixel signal, In the intermediate gradation region, it is difficult to correct the intensity difference between the odd pixel signal and the even pixel signal.
To solve this problem, the conventionally proposed solution provides a gray scale chart at the reading position in the main scanning or sub-scanning direction, and corrects the odd / even difference by referring to the γ correction table based on the reading data at each step. However, with this method, the mechanism is complicated, and even if the odd / even difference can be corrected unless all the gradations are corrected to some degree, the mechanism is complicated. There is a risk that the linearity of the synthesized image data may be lost.
[0005]
In recent CCDs, due to advances in device technology, interference between shift registers is considerably reduced, and the odd-even difference caused by a single CCD has been reduced. On the other hand, there is a strong demand for high-speed and high-precision image reading devices, and the pixel frequency is increasing. Rather than interference between shift registers, switching noise and amplifiers when multiplexing odd and even pixels are used. Noise superposition due to the step response is a major factor in odd-even differences.
FIG. 10 shows an analog image signal (that is, an A / D conversion circuit 21) of continuous pixels output from an analog signal processing circuit 24 that performs a series of analog processing on the image signal when the white reference plate 15 is read and multiplexes. And the timing of the input clock of the A / D conversion circuit 21). Originally, the level of the image signal when reading the white reference plate must be equal to odd pixels and even pixels, but the analog signal actually input to the A / D conversion circuit 21 is odd pixels, When even-numbered pixels are multiplexed, switching noise and noise due to the step response of the amplifier are superimposed, and when the pixel frequency increases, the period of one pixel is shortened, so the proportion of noise in the pixel waveform is higher. Thus, as shown in FIG. 10, the signal has no periodicity between the waveforms of the odd and even pixels.
[0006]
[Problems to be solved by the invention]
In the A / D conversion circuit 21, the analog image signal in such a state is sampled with a clock having a timing matched to each of the odd and even pixel periods as shown in the figure. At this time, depending on the sampling clock timing, Since there is no periodicity between the waveforms of the odd and even pixels, there is a difference in the level of the image data between the odd and even pixels as shown in FIG.
When white level adjustment is performed in this sampling state, an appropriate gain is applied to the odd-numbered pixel side and even-numbered pixel side, resulting in an analog image signal output state as shown in FIG. In the state shown in the figure, since the image signal levels of the odd-numbered pixels and even-numbered pixels sampled are aligned, the white level is adjusted, but the problem that the linearity at the intermediate gradation cannot be maintained remains.
The present invention has been made in view of the above-described problems of the prior art, and its object is to reduce odd-even differences caused by the influence of noise components superimposed when analog synthesis of odd and even pixels is performed at high speed. Provided is an image reading apparatus capable of obtaining a high-quality read image signal by adjusting an image signal level that can ensure linearity even in an intermediate gradation region, and an image processing apparatus including the image reading apparatus. It is in.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a photoelectric conversion means comprising an array of a plurality of pixels that accepts an optical image from a reading object, and an image signal converted by an odd pixel and an even pixel in the pixel array of the photoelectric conversion means. an analog signal processing circuit you parallel processing in the processing system, taken out by different sampling clocks corresponding to the respective image signals of the odd pixels and the even-numbered pixels from the output signal of the analog signal processing circuit, and the odd pixel to be converted a / D In an image reading apparatus having an A / D conversion circuit prepared according to an image signal of an even pixel, the timing of the sampling clock of the A / D conversion circuit is independent of the image signal of the odd pixel and the even pixel. An image reading apparatus including a clock timing control circuit for adjustment is configured.
[0008]
According to a second aspect of the present invention, in the image reading apparatus according to the first aspect, the clock timing control circuit adjusts the phase of the sampling clock in accordance with a difference value between image signal outputs converted by odd and even pixels. The timing of the sampling clock is adjusted by independent control.
[0009]
According to a third aspect of the present invention, in the image reading apparatus according to the second aspect, the clock timing control circuit has a predetermined optical characteristic for a difference value of the image signal output converted by the odd-numbered pixel and the even-numbered pixel. It is obtained from an output value when an optical image of a reference body is read.
[0010]
According to a fourth aspect of the present invention, in the image reading device according to the second or third aspect, the clock timing control circuit uses the A / D conversion circuit to calculate a difference value between image signal outputs converted by odd and even pixels. It is obtained from the digital data output.
[0011]
According to a fifth aspect of the present invention, there is provided an image processing apparatus comprising the image reading apparatus according to any one of the first to fourth aspects.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
An image reading apparatus according to the present invention will be described based on the following embodiments shown with the accompanying drawings.
FIG. 1 shows a schematic configuration of the image reading apparatus of the present embodiment. As shown in the figure, the image reading apparatus of this embodiment includes a contact glass 24 on which a document 37 is placed, a first carriage 29 on which a halogen lamp 25 for illuminating a document and a first reflection mirror 26 are placed, and a first carriage 29. The second carriage 30 on which the second reflection mirror 27 and the third reflection mirror 28 are mounted, and the original image transmitted from the original 37 through the first reflection mirror 26, the second reflection mirror 27, and the third reflection mirror 28 are formed. The lens unit 31, a CCD linear image sensor 32 (hereinafter simply referred to as “CCD”) disposed on the imaging surface of the lens unit 8, and a sensor board 33 on which the CCD 32 and its drive circuit (not shown) are placed. And a white reference plate 38 for correcting various distortions caused by the reading optical system and the like, and the CCD 32 is driven by the sensor board 33 to read an image, A signal processing unit 35 for processing the image signal output through the table 34, the constructed by providing to the scanner device 36.
[0013]
Referring to FIG. 1, the details relating to the reading operation of the original image by the image reading apparatus of the present embodiment will be described below. The CCD 32 for reading the original image has a plurality of pixels (photoelectric conversion elements) arranged in a line. Charges accumulated according to the amount of light received by each pixel are sequentially taken out along the pixel column by main scanning at a predetermined repetition period, and the first carriage 29 and the second carriage 30 are removed by a stepping motor (not shown). The first carriage 29 and the second carriage 30 are moved in such a manner that the optical path length from the light irradiation surface of the document 37 to the light receiving surface of the CCD 32 is always constant. Driven by). By such two-dimensional scanning, an image on the entire surface of the document is read by a photoelectric conversion element and output as an image signal.
[0014]
FIG. 2 shows a more detailed block diagram of the signal processing unit 35 that processes the output image signal of the CCD 32.
In the signal processing unit 35, analog processing by the analog signal processing circuit 50 is performed on the image output of the CCD 32, and then various correction processes are performed on the image signal, and an image processing apparatus such as a scanner, an electrophotographic copying machine, or a FAX is used. A digital signal processing process is performed until image data in a possible signal form is obtained, and is sent to an external circuit or device via the I / F 51.
Here, first, an image signal VO (odd-numbered pixel signal) from the sensor driving circuit of CCD 32 placed on the board 33 (not shown) in synchronism with the driving motion pulse that occur CCD 32, VE (even-numbered pixel signals ) Is output, and the image signal is converted into a continuous analog signal by sampling and holding the image signals VO and VE by the sample pulse by the sample and hold circuit 39, respectively.
Next, after the black level correction circuit 40 corrects the variation in the dark output level of the CCD 32 in the analog image signal, the amplification circuit 41 converts each color (not shown, but in the case of color reading, R, G, (The read image signal is processed for each color of B) After the output of the odd and even pixel image signals VO and VE are adjusted to a certain level, the multiplex circuit 42 multiplexes the output of the odd and even pixels to obtain the image signal. V. The image signal V is amplified to the level of the reference voltage for A / D conversion by the amplifier circuit 43 and then converted to 8-bit digital data by the A / D conversion circuit 44.
[0015]
A pair of A / D conversion circuits 44 are prepared according to the image signals of odd and even pixels, and the phase of the sampling clock of each conversion circuit is controlled by the phase control circuit 49 so that the sampling timing can be adjusted. Further, in order to generate a phase control command to the phase control circuit 49, a digital value detection register 47 that holds output data of an A / D conversion circuit prepared in accordance with image signals of odd and even pixels, and odd / even detection A circuit 48 is included.
The digital image signal after A / D conversion has a correction value prepared in the shading correction circuit 45 (that is, a predetermined density obtained by reading the reflected light of the white reference plate 38 irradiated by the halogen lamp 25 by the CCD 32. The correction of the level) corrects variations in sensitivity of the CCD 32 and uneven light distribution in the irradiation system.
The timing signal necessary for driving the CCD 32 input to the drive circuit for the CCD 32 on the sensor board substrate 33 or the timing signal necessary for the operation of each circuit on the signal processing substrate 35 on the signal processing substrate 35 is the timing. The signal generation circuit 46 generates the signals by adjusting their timings.
[0016]
Next, the odd / even difference correction operation for reducing the output level difference generated between the image output of the odd and even pixels in this embodiment will be described in more detail according to the operation flow shown in FIG. Note that step symbols in FIG. 3 are shown in parentheses for reference in the following description.
In the amplifier circuit 41 in the analog signal processing circuit 50, AGC is performed by control data from a CPU (not shown), and white level correction is performed by adjusting the output of odd and even pixels of each color signal to a certain level. The odd / even difference correction operation is performed before the correction operation.
In the odd / even difference correction operation, first, the carriages 29 and 30 in the stopped state are moved in the direction A shown in FIG. 1, and the white reference plate 38 positioned immediately before reaching the effective image range from the home position is read. The signal of the read white reference plate 38 is processed with a fixed gain, and the digital white reference plate read data converted by the A / D conversion circuit 44 provided for each of the odd and even signals is held in the digital value detection register 47. (S31).
[0017]
The white reference plate reading data of the odd and even pixels held in the detection register 47 is taken out, and the level difference (odd / even difference) value X is calculated in the odd / even difference detection circuit 48 (S32). It is checked whether the target odd / even difference level value is compared, that is, whether the condition of − | target odd / even difference level | ≦ X ≦ | target odd / even difference level | is satisfied (S33).
If the detected odd / even difference X is out of the target level range (does not satisfy the condition), a phase control command is issued to the phase control circuit 49 and the timing (phase) of the sampling clock input to the A / D conversion circuit 44 is set. Shift. When the timing is changed, the white reference plate 38 is read again, the odd / even difference is calculated and compared, and if necessary, the operation of shifting the timing of the sampling clock for A / D conversion is within the range of the target level value. The process is repeated until it is settled (S34).
When the odd / even difference falls within the target level range, the odd / even difference correction is completed, and the amplification circuit 41 performs white level correction according to the read data of the digital white reference plate (S35). At this time, correction is further performed so that the output of the odd-numbered and even-numbered pixels of each color signal is adjusted to a certain level.
[0018]
The operation (A / D clock shift) of the phase control circuit 49 for controlling the timing (phase) of the sampling clock input to the A / D conversion circuit 44 is specifically shown in accordance with the operation flow illustrated in FIG. Here, every time a phase control command is input, first, the even-numbered clock is fixed (S41), and the odd-numbered clock is shifted by a fixed interval, for example, 3 steps, in the direction in which the phase is delayed. Is shifted by 3 steps in the direction of travel (S42). At this time, an odd / even difference is detected, and it is checked whether the detected odd / even difference falls within the target level range (S43). In either case, when the odd / even difference does not reach the target value, the odd-numbered phase shift is finished (S44), and the even-numbered phase shift is performed.
Next, the odd-numbered clock is fixed (S45), and the same procedure as that performed on the odd-numbered side is performed while shifting the phase of the even-numbered clock by 3 steps in the delay direction and the advance direction to find an appropriate timing (S46-). 48). Here, it is determined that an error has occurred when the odd / even difference has not reached the target value as a result of shifting the phase in the delay direction and the advance direction, and error processing is performed (S49).
[0019]
An image signal processing process according to this procedure will be described with reference to a signal waveform. For example, an analog image signal (that is, an A / D conversion circuit) of continuous pixels output from the analog signal processing circuit 50 when the white reference plate 38 is read. If the timing of the sampling clock input to the A / D conversion circuit 44 and the timing of the sampling clock input to the A / D conversion circuit 44 is not shifted in phase between the odd and even clocks as shown in FIG. And even-numbered pixels have different reading levels, so an odd / even difference occurs. Here, in the phase control circuit 49, if the even-numbered side is fixed and the timing of the A / D input clock is shifted in the direction to advance the odd-numbered phase in the phase control circuit 49, the state shown in FIG. At this timing, the sampled odd and even pixels have the same level, and an output having no odd / even difference is obtained. Therefore, the next time the white reference plate 38 is read with a fixed gain, there is no difference between the reading levels of the odd-numbered pixels and the even-numbered pixels. Is reduced.
[0020]
Next, another embodiment of the odd / even difference correction operation for reducing the output level difference generated between the image outputs of the odd and even pixels according to the present invention will be described.
In this embodiment, as shown in FIG. 6, in addition to the white reference plate 52, a half-tone reference plate 51 having a halftone density provided at the reading position is used, and the procedure of the previous stage of white level correction is performed. As shown in FIG. The reading apparatus shown in FIG. 6 has the same apparatus configuration as that of FIG. 1 except for the halftone reference plate 51, and FIG.
This odd / even difference correction operation will be described in more detail according to the operation flow shown in FIG. Note that step codes in FIG. 7 are shown in parentheses for reference in the following description.
The odd / even difference correction operation of this example is as follows. First, the carriages 29 and 30 in the stopped state are moved in the direction A shown in FIG. 1, and the white reference plate 52 positioned immediately before reaching the effective image range from the home position is moved. read. The white reference plate read signal is processed with a fixed gain, and the gain is set so that the digital white reference plate read data has a predetermined value (S71).
After performing the normal operation at the start of white level correction, this time, the halftone reference plate 51 located immediately before the white reference plate 52 is read from the home position by the carriage movement with the set gain, and the odd and even signals are output. The digital halftone reference plate read data converted by the A / D conversion circuit 44 provided therein is held in the digital value detection register 47 (S72).
[0021]
The halftone reference plate reading data of the odd and even pixels held in the detection register 47 is taken out, the odd / even difference detection circuit 48 calculates the level difference (odd / even difference) value X between them (S73), and the calculated odd / even difference value. And the target odd / even difference level value are compared, that is, it is checked whether or not the condition of − | target odd / even difference level | ≦ X ≦ | target odd / even difference level | is satisfied (S74).
If the detected odd / even difference X is out of the target level range (does not satisfy the condition), a phase control command is issued to the phase control circuit 49 and the timing (phase) of the sampling clock input to the A / D conversion circuit 44 is set. Shift. When the timing is changed, the white reference plate 52 is read again and the gain is set again. Thereafter, the halftone reference plate 51 is read with the set gain, the even-odd difference is calculated and compared, and if necessary, A / D conversion is performed. The operation of shifting the timing of the sampling clock is repeated until the odd / even difference falls within the target level value range (S75).
When the odd / even difference falls within the target level range, the odd / even difference correction is completed, and the amplifier circuit 41 performs white level correction according to the read data of the digital white reference plate. At this time, correction is further performed so that the output of the odd and even pixels of each color signal is adjusted to a certain level.
[0022]
【The invention's effect】
(1) According to the image reading apparatus of the first aspect of the present invention, the timing of the sampling clock of the A / D conversion circuit is adjusted independently with respect to the image signals of the odd-numbered pixel and even-numbered pixel signals to obtain an appropriate timing. the odd pixels at high speed, (complex) analog synthesis of even-numbered pixel signals is reduced parity difference caused by the influence of the noise component superimposed on when cormorants row, it is possible to obtain a read image signal of good quality.
(2) According to the image reading apparatus of the invention of claim 2, independently controlling the phase of the sampling clock in accordance with the difference value of the images the signal output which is converted by the odd-numbered pixels and the even pixels when reading the optical image By providing the feedback system, the timing of the sampling clock can be adjusted, and the odd / even difference correction can be optimized.
(3) According to the image reading apparatus of the invention of claim 3, the amount of adjustment of the timing of the sampling clock is adjusted based on the difference between the image signal outputs of the odd and even pixels when the white reference plate and the halftone reference plate are read. By determining, the odd-even difference can be more accurately reduced, and the linearity of the intermediate gradation can be secured.
(4) According to the image reading apparatus of the fourth aspect of the present invention, the difference between the odd-numbered pixel and the even-numbered image signal output is obtained from the digital data output of the A / D conversion circuit, so that the odd-even difference can be obtained with stable and reliable operation. In addition, the accuracy of processing such as shading correction using digital data can be improved.
(5) The image processing apparatus of the invention of claim 5, odd-numbered pixels at a high speed, parity difference caused by the influence of the noise component superposed analog synthesis even pixels when cormorants line is reduced, linearity even in the middle tone area Therefore, it is possible to perform image processing using a high-quality read image signal in which is secured.
[Brief description of the drawings]
FIG. 1 schematically shows a configuration of an embodiment of an image reading apparatus according to the present invention.
FIG. 2 shows a signal processing unit for an output image signal of a CCD of an image reading apparatus according to the present invention.
FIG. 3 shows a flow of odd / even difference correction operation according to the present invention.
FIG. 4 shows a flow of clock shifting operation of the A / D conversion circuit in the present invention.
FIG. 5 shows the timing of the output image signal of the analog signal processing circuit and the input sampling clock of the A / D conversion circuit in the present invention.
6 shows an embodiment in which a halftone reference plate is added to the image reading apparatus of FIG.
FIG. 7 shows a flow of another embodiment of the odd-even difference correcting operation according to the present invention.
FIG. 8 schematically shows a configuration of a conventional image reading apparatus.
FIG. 9 shows a signal processing unit for an output image signal of a CCD of a conventional image reading apparatus.
FIG. 10 shows the timing of an output image signal of a conventional analog signal processing circuit and an input sampling clock of an A / D conversion circuit.
11 shows the signal waveform of FIG. 10 after gain adjustment.
[Explanation of symbols]
32 ... CCD linear image sensor, 33 ... Sensor board,
35 ... Signal processing unit, 38, 52 ... White reference plate,
44 ... A / D conversion circuit, 48 ... Digital value detection register,
48 ... odd / even difference detection circuit, 49 ... phase control circuit,
50: Analog signal processing circuit 51: Halftone reference plate

Claims (5)

To parallel processing and the photoelectric conversion means comprising a sequence of a plurality of pixels, converted by the odd and even pixels in the array of pixels of the photoelectric conversion unit an image signal to a separate analog processing system for receiving an optical image from the reading target An odd-numbered pixel signal and an even-numbered pixel image signal are extracted from the output signal of the analog signal processing circuit by using different sampling clocks corresponding to the analog signal processing circuit, and A / D conversion is performed according to the odd-numbered pixel signal and even-numbered pixel image signal. And a clock timing control circuit for independently adjusting the timing of the sampling clock of the A / D conversion circuit with respect to the image signals of the odd and even pixels. An image reading apparatus comprising: 2. The image reading apparatus according to claim 1, wherein the clock timing control circuit controls the phase of the sampling clock independently according to a difference value between image signal outputs converted by odd and even pixels. An image reading apparatus that adjusts the timing of the sampling clock.   3. The image reading apparatus according to claim 2, wherein the clock timing control circuit reads an optical image of a reference body having a predetermined optical characteristic from a difference value between image signal outputs converted by odd-numbered pixels and even-numbered pixels. An image reading apparatus characterized in that the image reading apparatus is obtained from an output value obtained at the time.   4. The image reading apparatus according to claim 2, wherein the clock timing control circuit obtains a difference value between image signal outputs converted by odd-numbered pixels and even-numbered pixels from digital data output of the A / D conversion circuit. An image reading apparatus.   An image processing apparatus comprising the image reading apparatus according to claim 1.

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