JP3945190B2 - Time stamp generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a time stamp generation circuit, and more particularly to a time stamp suitable for the timing of a device side clock even when a clock having a phase different from that of a basic system clock is used for compressed video data such as MPEG2 (Moving Picture Experts Group 2). The present invention relates to a time stamp generation circuit for adding.
[0002]
[Prior art]
Recently, video data and audio data are compressed and transmitted based on an information compression code standard such as MPEG2, and the compressed data is decoded and used by a decoding device. Here, in order to synchronize decoding of video data and audio data, two types of time information are generally required, and synchronization control is performed based on these time information. The first time information is a time base reference value called SCR (System Clock Reference), and the other time information is time management information of reproduction output called PTS (Presentation Time Stamp) indicating when to decode and reproduce. This is called a time stamp.
[0003]
In MPEG2, this time stamp is added to the header portion of the PES packet when the beginning of each video or audio access unit (video 1 frame or audio 1 frame) is included in the PES (Packetized Elementary Stream) packet. The
[0004]
Such time stamp addition is generally used, but in order to meet the demand for higher integration and higher efficiency of encoder chips that perform compression in recent years, for example, an encoder separately from the base operation clock inside the apparatus. In some cases, a clock that matches the processing conditions of the chip is supplied and operated. For this reason, the operation clock for generating the system time code and the clock for moving the encoder chip are asynchronous in the apparatus, and as a result, the system time code required for the decoding operation is between the encoder chip and the peripheral circuit. This causes a clock shift.
[0005]
As an example of such a technique, “data transmission device, data reception device” described in Japanese Patent No. 3058263 is known.
[0006]
In this publication, when video data compliant with MPEG-2, uncompressed audio data, and user data are transmitted / received in conformity with MPEG-2, a discrimination flag is transmitted with PES private data, so that uncompressed audio data and user data can be easily transmitted. A technique for discriminating data is described. In addition, when an error correction code, an error detection code, etc. specific to the recording apparatus are added to the video data, the video data obtained by separating them is converted into MPEG-2 video data, and a PES stream, an error correction code, an error detection code, etc. A technique is described in which video data is directly MPEG-2 decoded after error correction and error detection of received data by transmitting and receiving as another packet in a transport stream as a PES private stream.
[0007]
[Problems to be solved by the invention]
In the conventional time stamp generating circuit described above, the operation clock for generating the system time code and the clock for moving the encoder chip become asynchronous inside the apparatus, and as a result, the system time code required for the decoding operation is the encoder chip. And a peripheral circuit have a disadvantage that a clock shift occurs.
[0008]
In addition, after error correction and error detection from received data, there is a drawback that the scale of the circuit configuration for directly MPEG-2 decoding of video data becomes large and complicated.
[0009]
It is an object of the present invention to add a time stamp in a form suitable for the timing of the apparatus even when the encoder chip operates using a clock having a phase different from that of the basic operation clock of the apparatus, and 3: 2 An object of the present invention is to provide a time stamp generating circuit capable of adding a time stamp to data that is subjected to pull-down processing or the like without complicating the circuit configuration.
[0010]
[Means for Solving the Problems]
The time stamp generation circuit according to the present invention is an ES generation circuit that receives a compressed video signal and outputs an ES (Elementary Stream) generation time stamp and ES data in accordance with the supplied first operation clock;
Before SL ES data, before Symbol type the ES generation time stamp and system time code, PES as an operation reference second operation clock having a frequency different from that before being fed Symbol first operation clock (Packetized Elementary Stream) A PES generation circuit for outputting data;
The PES generation circuit determines the difference between the current time stamp value and the previous time stamp value with respect to the ES generation time stamp by a multiple of the time corresponding to one frame, and is detected from the ES data. The system time code corresponding to the determined data is determined according to the determined header timing, added to the header portion of the PES data as a time stamp, and output .
[0012]
The PES generation circuit includes:
The type of ES generation timestamp, the relative ES generation timestamp determined by multiple of the time corresponding to one frame difference between the current timestamp value and the previous time stamp value, the determination result A time stamp determination unit that outputs as determination data ;
A header detector for detecting a header timing of the input ES data and outputting a data read timing signal ;
The determination data, the data read timing signal, and the system time code are input, the system time code is written to the memory in the order of input, and the system time code corresponding to the determination data is determined according to the data read timing signal. A memory control unit that outputs a memory control signal for performing control to read from the memory unit ;
The type of system time code and the memory control signal, on the basis of the memory control signal writing in the input order of the system time code, reads the system time code based on the memory control signal, PES generated as PES additional time stamp A memory unit for outputting to the unit;
A PES generation unit that inputs the PES added time stamp from the memory unit and outputs the packetized PES data;
It is characterized by having.
[0013]
The PES generation circuit includes:
The type of ES generation timestamp, the relative ES generation timestamp determined by multiple of the time corresponding to one frame difference between the current timestamp value and the previous time stamp value, the determination result A time stamp determination unit that outputs as determination data ;
A header detector for detecting a header timing of the input ES data and outputting a data read timing signal ;
The determination data, the data read timing signal, and the system time code are input, the system time code is written to the memory in the order of input, and the system time code corresponding to the determination data is determined according to the data read timing signal. A memory control unit that outputs a memory control signal for performing control to read from the memory unit ;
The inputs the counter value becomes the basis of the system time code and frame pulse, to output the capture a frame pulse becomes a time effective to the counter value in one frame, the counter value the taken as the system time code System time code capture circuit;
The type of system time code and the memory control signal, on the basis of the memory control signal writing in the input order of the system time code, reads the system time code based on the memory control signal, PES generated as PES additional time stamp A memory unit for outputting to the unit;
A PES generation unit that inputs the PES added time stamp from the memory unit and outputs the packetized PES data;
It is characterized by having.
[0015]
The time stamp determination unit
A first determination unit that inputs the ES generation time stamp and outputs first determination data, a second determination unit that outputs second determination data, and a third determination data that outputs third determination data A determination unit,
The difference between the current time stamp value and the previous time stamp value with respect to the input ES generation time stamp is determined by a multiple of the time corresponding to one frame, and if the difference is equivalent to one frame The first determination data is true, the second determination data is true if the difference is equivalent to 1.5 frames, and the third determination data is true if the difference is equivalent to two frames. One of the first, second, and third determination data that is true is output as the determination data to the memory control unit .
[0016]
The memory control unit refers to the write control unit that outputs a control signal to be written to a predetermined address in the order in which the system time codes are input to the memory unit, the data read timing signal, and the determination data. A read control unit that outputs a control signal for reading the system time code from the memory ;
Before Symbol read control unit, based on the judgment data from the time stamp judging section, said first judgment data is read true if the current address, the second decision data read true if the next address If the third determination data is true, read control is performed to read an address obtained by skipping one next address, and time information to be added as a time stamp is adjusted by this read control.
[0017]
The memory unit includes a memory and a calculator.
The arithmetic unit inputs the determination data from the memory control unit, and when there is the determination data that is true including the equivalent of 0.5 frames, 0.5% of the system time code read from the memory It is characterized by performing addition in units of frames and outputting as the PES added time stamp.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0019]
FIG. 1 is a block diagram showing an embodiment of a time stamp generating circuit of the present invention.
[0020]
The present embodiment shown in FIG. 1 includes an ES generation circuit 1 that receives a compressed video signal 3 and outputs an ES (Eliminary Stream) generation time stamp 4 and ES data 9 in response to an operation A clock 6, and the input ES data 9 and The ES generation time stamp 4 includes a system time code 8 and a PES generation circuit 2 that outputs PES (Packetized Elementary Stream) data 5 to which time stamp information is added by an operation B clock 7.
[0021]
Next, the operation will be described with reference to FIG.
[0022]
The operation A clock 6 and the operation B clock 7 are supplied to the ES generation circuit 1 and the PES generation circuit 2, respectively. The operation A clock 6 and the operation B clock 7 are generally asynchronous and the clock frequency or a multiple thereof. Are not consistent on both sides.
[0023]
For the ES generation time stamp 4 output from the ES generation circuit 1 generated based on the operation A clock 6, the PES generation circuit 2 operating at the operation B clock 7 generates based on the operation A clock 6. The time stamp information based on the system time code 8 used in the apparatus is added to the PES header portion instead of the time stamp information.
[0024]
The time stamp to be added to the PES data 5 is generally a value which is increased by one frame from the time stamp attached to the previous picture with respect to the data stream in units of pictures. When the time stamp according to the operation A clock 6 is added as it is to the PES data 5 as a time stamp, a time stamp having a different period from the inside of the apparatus is added, and gradually deviates from the time to be actually added. Will occur.
[0025]
Therefore, the PES generation circuit 2 that outputs the PES data 5 confirms the information of the ES generation time stamp 4 generated by the ES generation circuit 1 and uses the system time code 8 to set the time stamp by the operation B clock 7. In addition, there is no time lag between the rest of the device.
[0026]
In addition, when compression by 3: 2 pull-down detection, which is used when compressing movie material, compression is performed by thinning out frames by pull-down detection. It's not an action. Accordingly, although the circuit configuration is generally complicated, in this configuration, by using the time stamp data output from the ES generation circuit 1, a time stamp can be added without complicating the circuit configuration.
[0027]
As described above, even when the operation clock supplied to the ES generation circuit 1 generally provided before the PES circuit 2 to be PES and the operation clock supplied to the PES generation circuit 2 are asynchronous, The time stamp added to the packetized compressed video signal 3, that is, the so-called PES header portion, can be accurately added to the header portion of the PES data 5.
[0028]
FIG. 2 is a detailed block diagram showing an example of the PES generation circuit of FIG.
[0029]
Referring to FIG. 2, the PES generation circuit inputs the ES generation time stamp 4 and outputs the determination data 10, and inputs the ES data 9 and outputs the header timing signal 19 and the data read timing signal 17. A header detection unit 12 that receives the system time code 8 and outputs a PES added time stamp 18 under the read control of the memory control signal 16, a system time code 8, determination data 10, and a data read timing signal The memory control unit 14 that inputs 17 and outputs the memory control signal 16, and the PES generation unit 15 that inputs the header timing signal 19 and the PES added time stamp 18 and outputs the PES data 5 by the operation of the operation B clock 7. It is configured.
[0030]
Next, the operation will be described with reference to FIG.
[0031]
The header detection unit 12 detects the header timing of the ES data 9, supplies the header timing signal 19 to the PES generation unit 15 and the data read timing signal 17 to the memory control unit 14, and uses them for reading control of the system time code 8. . The PES addition time stamp 18 read from the memory unit 13 is processed by the PES generation unit 15 together with the operation B clock 7 and converted into PES data 5 as a time stamp added to the video data.
[0032]
The time stamp determination unit 11 determines the current state of the time stamp of the ES generation time stamp 4 sent from the previous ES generation circuit 1 and finally sends the time stamp to the PES generation unit 15 A determination process is performed as an information source for stamp reading control.
[0033]
The determination data 10 obtained in this way is supplied to the memory control unit 14 in the same manner as the data read timing signal 17, and corresponds to the inputted ES data 9 from the two types of information of the determination data 10 and the data read timing signal 17. The PES added time stamp 18 is output to the PES generator 15.
[0034]
FIG. 3 is a detailed block diagram showing the time stamp determination unit of FIG.
[0035]
Referring to FIG. 3, the time stamp determination unit 11 receives the ES generation time stamp 4 and determines the determination unit 21 that outputs the determination data 24, the determination unit 22 that outputs the determination data 25, and the determination that outputs the determination data 26. A difference between the current time stamp value and the time stamp value sent to the previous picture for the input ES generation time stamp 4, and that value is one frame. Determine how many times the corresponding time. TSIN (n), which is the ES generation time stamp 4 output from the ES generation circuit 1, is a time stamp value sent at the current time, and TSIN (n-1) is sent to the previous picture. Time stamp value. This difference is calculated to determine how many times the result corresponds to one frame. In FIG. 3, the time stamp value corresponding to one frame is indicated by F.
[0036]
In order to determine the value of TSIN (n) −TSIN (n−1), for example, the determination unit 21 determines that the determination data 24 is true if it is between F−α and F + α. This α absorbs the difference between the operation A clock 6 of the ES generation circuit 1 and the time stamp in the apparatus.
[0037]
Here, in order to absorb the phase difference between the operation A clock 6 and the operation B clock 7, if the value of TSIN (n) −TSIN (n−1) is approximately one frame interval, TSIN (n) −TSIN (n -1) Even if it is not equal to F, it is regarded as an error range, and the determination data 24 is output as true. Therefore, a value indicating the error range is α.
[0038]
The value of α is sufficiently smaller than F.
[0039]
By determining the state of the time stamp generated by the operation A clock 6 based on this determination operation, a time stamp having no phase shift can be added to the time stamp information generated by the ES generation circuit 1.
[0040]
The time stamp determination unit 11 includes three types of determination unit 21, determination unit 22, and determination unit 23. However, this is merely an example, and the ES generation circuit 1 includes the presence or absence of a 3: 2 pull-down function. In accordance with the contents of the time stamp that is output, the determination items can be expanded, for example, detection of a difference of 2.5 frames and detection of a difference of 3 frames.
[0041]
FIG. 4 is a detailed block diagram showing the memory unit and the memory control unit of FIG.
[0042]
Referring to FIG. 4, the memory unit 13 includes a memory 31 and an arithmetic unit 32, and the memory control unit 14 includes a write control unit 33 and a read control unit 34.
[0043]
The write control unit 33 performs a process of writing the system time code 8 in the memory 31 in the input order. The read control unit 34 performs processing for reading data from the memory 31 in accordance with the data read timing signal 17.
[0044]
Further, when data is read, the number of reads is changed based on the determination data 10 from the time stamp determination unit 11, and the time information to which the time stamp is added is adjusted by this change. The computing unit 32 adds the time stamp value in units of 0.5 frames to the data read from the memory 31 only when necessary according to the determination data 10 and outputs the result as the PES added time stamp 18.
[0045]
FIG. 5 is a time chart showing the operation of the time stamp determination unit.
[0046]
The determination data is calculated by calculating a difference value between the ES generation time stamp 4 generated based on the operation A clock 6 sent from the ES generation circuit 1 and the ES generation time stamp sent one before. Output as. The determination data 24, the determination data 25, and the determination data 26 are signals that are true (High level or “1” level) when the conditions shown in the determination unit 21, the determination unit 22, and the determination unit 23 are satisfied. Any of these determination data is finally output as determination data 10.
[0047]
That is, the determination data 24 is true if the difference is equivalent to about 1 frame, the determination data 25 is true if the difference is equivalent to 1.5 frames, and the determination data 26 is true if the difference is equivalent to 2 frames. .
[0048]
It is assumed that there is a time stamp value of A, and then a time stamp value A + F ′ increased by F ′, and thereafter time stamp values of A + 3F ′ and A + 4F ′.
[0049]
Here, F ′ indicates a time corresponding to one frame. As for F ′, there is a value F as the difference value of the time stamp to be originally added. When the time stamp is generated by the operation A clock 6, the difference from the previous time stamp is exactly F or a multiple of F. This is distinguished as F ′. When the time stamp of A + F ′ is input, the difference is F ′ by the calculation with the previous A, so the determination data 24 is made true. When the time stamp of A + 3F ′ is input, since the difference from the previous A + F ′ is 2F ′, the determination data 26 is made true.
[0050]
FIG. 6 is a time chart showing the operation of the memory control unit.
[0051]
The operation of the memory control unit 14 is executed according to the time chart of FIG. Regarding the memory write operation, the system time code 8 is written in the memory unit 13 in the order of input according to the memory write address. Regarding the memory read operation, the memory read control is performed in accordance with the determination data 10 created based on the time stamp according to the operation A clock 6 and the timing of the header portion of the ES data 9 sent from the ES generation circuit 1. To do. For example, when the determination data 24 is true, the written data is read one by one, and the written system time code 8 is sequentially added to the PES header.
[0052]
When the determination data 26 is true as in the example of FIG. 6, the read address is skipped (the memory read address n + 1 is skipped), that is, the written data is skipped and the next data is read. By adding to the PES header, a difference of 2 frames is provided.
[0053]
The system time code value at time I is I.
[0054]
Write the system time code value to memory every frame,
I-> I + F-> I + 2F ...
And the system time code is written in the memory.
[0055]
Each time one time code value is written, the value of the memory write address also increases by +1.
[0056]
That is, every time the memory address increases, the system time code value written in the memory increases by + F.
[0057]
As shown in FIG. 6, when the memory read address is n, that is, the time stamp value added to the PES is I, the timing of the header portion of the next ES data 9 Then, the determination data is referred to determine the time stamp value to be added. Here, since the determination data 24 is true, it is determined that a value obtained by adding one frame to the previous time code value I added to the PES should be added, and the memory read address is incremented by one here. Then, the value of I + F is read from the memory and the value is added to the PES as a time stamp.
[0058]
In addition, when the memory read address is n + 1, that is, when the last time stamp value added to the PES is I + F, it is added at the timing of the header portion of the next ES data 9 The determination data is referred to determine the time stamp value to be performed. Here, since the determination data 26 is true, it is determined that a value obtained by adding two frames to the previous time code value I + F added to the PES should be added. Here, the memory read address is incremented by +2. Then, the value of I + 3F is read from the memory and the value is added to the PES as a time stamp.
[0059]
FIG. 7 is a time chart showing another operation of the memory control unit.
[0060]
When the difference from the previous time stamp according to the operation A clock 6 is 1.5F ′, the arithmetic unit 32 of FIG. 4 is used. When the difference is 1.5F ′, the judgment data 25 becomes true. In this case, the address on the read side is advanced by one, the data at this address is read, and the value of 0.5F is added to the read data. A time stamp to be added to the PES data 5 is read, or when reading, the address is advanced by two, and the PES added time stamp 18 is output as a time stamp to be added to the PES.
[0061]
As shown in FIG. 7, in the 4ES generation time stamp, when the value comes at 1.5 frame intervals compared to the previous time stamp value, for example, the state where the memory read address is n, that is, at the end When the time stamp value to which PES is added is I, the determination data is referred to in order to determine the time stamp value to be added at the timing of the header portion of the next ES data 9. Here, since the determination data 25 is true, it is determined that it is sufficient to add a value obtained by adding 1.5 frames to the time code value I added to the previous PES, and the memory read address is set here. +1 and read the value of I + F from the memory. The value of 0.5 frame is added to the read I + F value by using the adder 32 of FIG. 4, and the value is added to the PES as a time stamp.
[0062]
FIG. 8 is a block diagram showing a second embodiment of the time stamp generation circuit of the present invention.
[0063]
In FIG. 8, components corresponding to those shown in FIG. 2 are denoted by the same reference numerals or symbols, and description thereof is omitted.
[0064]
The PES generation circuit shown in FIG. 8 has a time stamp determination unit 11 that inputs an ES generation time stamp 4 and outputs determination data 10, and a header that inputs ES data 9 and outputs a header timing signal 19 and a data read timing signal 17. The detection unit 12, the system time code capture circuit 46 for inputting the system time code counter value 48 and the frame pulse 49 and outputting the system time code 42, and the system time code 42 for inputting the memory control signal 40. A memory unit 43 that originally outputs the PES added time stamp 41, a memory control unit 44 that inputs the system time code 42, the determination data 10 and the data read timing signal 17 and outputs a memory control signal 40, a header timing signal 19 and PES additional time stamp 4 Enter a, and a PES generator 45 for outputting a PES data 47 by the operation of the operation B clock 7.
[0065]
In this configuration, the system time code is taken in, and instead of the system time code 8 in FIG. 2, a system time code counter value 48 indicating a counter value that is the basis of the system time code 8 is input, and the counter value is input. A frame pulse 49 that is valid once per frame is captured, and the captured data is output to the memory unit 43 as a system time code 42. By inputting the system time code 42 as the write timing to the memory control unit 44, the captured system time code 42 itself can be written in the memory unit 43.
[0066]
FIG. 9 is a time chart showing the operation of FIG.
[0067]
That is, the system time code counter value 48 that is the basis of the system time code is fetched by the frame pulse 49 and the system time code 42 and the memory write pulse of the memory control signal 40 are output.
[0068]
【The invention's effect】
As described above, the time stamp generation circuit according to the present invention uses the time stamp value generated by the operation clock of the ES generation circuit to determine the state of the time transition, and uses the information and the system time code. By generating a time stamp and adding a time stamp to the PES data, it is possible to add a time stamp that is not shifted in time phase under the same conditions as other parts inside the apparatus. Thus, there is an effect that the time stamp does not gradually shift.
[0069]
In addition, since there are a plurality of determination units serving as a difference detection circuit for time stamps generated by the operation clock, for example, a difference for 1.5 frames, a difference for 2 frames, and the like can be detected. There is an effect that a time stamp can be added without error to ES data corresponding to 2 pull-down.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a time stamp generation circuit of the present invention.
FIG. 2 is a detailed block diagram illustrating an example of a PES generation circuit in FIG. 1;
FIG. 3 is a detailed block diagram illustrating a time stamp determination unit in FIG. 2;
4 is a detailed block diagram illustrating a memory unit and a memory control unit of FIG. 2;
FIG. 5 is a time chart showing an operation of a time stamp determination unit.
FIG. 6 is a time chart showing the operation of the memory control unit.
FIG. 7 is a time chart showing another operation of the memory control unit.
FIG. 8 is a block diagram showing a second embodiment of the time stamp generation circuit of the present invention.
FIG. 9 is a time chart showing the operation of FIG. 8;
[Explanation of symbols]
1 ES generation circuit 2 PES generation circuit 3 Compressed video signal 4 ES generation time stamp 5 PES data 6 Operation A clock 7 Operation B clock 8 System time code 9 ES data 10 Determination data 11 Time stamp determination unit 12 Header detection unit 13 Memory unit 14 memory control unit 15 PES generation unit 16 memory control signal 17 data read timing signal 18 PES additional time stamp 19 header timing signal 21, 22, 23 determination unit 24, 25, 26 determination data 31 memory 32 calculator 33 write control unit 34 Read control unit 40 Memory control signal 41 PES additional time stamp 42 System time code 43 Memory unit 44 Memory control unit 45 PES generation unit 46 System time code fetch circuit 47 PES data 48 System time code counter value 4 9 Frame pulse

Claims (6)

An ES generation circuit that inputs a compressed video signal and outputs an ES (Eliminary Stream) generation time stamp and ES data in response to the supplied first operation clock;
Before SL ES data, before Symbol type the ES generation time stamp and system time code, PES as an operation reference second operation clock having a frequency different from that before being fed Symbol first operation clock (Packetized Elementary Stream) A PES generation circuit for outputting data;
The PES generation circuit determines the difference between the current time stamp value and the previous time stamp value with respect to the ES generation time stamp by a multiple of the time corresponding to one frame, and is detected from the ES data. In accordance with the determined header timing, the system time code corresponding to the determined data is determined, added to the header portion of the PES data as a time stamp, and output . The PES generation circuit includes:
The type of ES generation timestamp, the relative ES generation timestamp determined by multiple of the time corresponding to one frame difference between the current timestamp value and the previous time stamp value, the determination result A time stamp determination unit that outputs as determination data ;
A header detector for detecting a header timing of the input ES data and outputting a data read timing signal ;
The determination data, the data read timing signal, and the system time code are input, the system time code is written to the memory in the order of input, and the system time code corresponding to the determination data is determined according to the data read timing signal. A memory control unit that outputs a memory control signal for performing control to read from the memory unit ;
The type of system time code and the memory control signal, on the basis of the memory control signal writing in the input order of the system time code, reads the system time code based on the memory control signal, PES generated as PES additional time stamp A memory unit for outputting to the unit;
A PES generation unit that inputs the PES added time stamp from the memory unit and outputs the packetized PES data;
Time stamp generating circuit according to claim 1 Symbol mounting characterized by comprising a. The PES generation circuit includes:
The type of ES generation timestamp, the relative ES generation timestamp determined by multiple of the time corresponding to one frame difference between the current timestamp value and the previous time stamp value, the determination result A time stamp determination unit that outputs as determination data ;
A header detector for detecting a header timing of the input ES data and outputting a data read timing signal ;
The determination data, the data read timing signal, and the system time code are input, the system time code is written to the memory in the order of input, and the system time code corresponding to the determination data is determined according to the data read timing signal. A memory control unit that outputs a memory control signal for performing control to read from the memory unit ;
The inputs the counter value becomes the basis of the system time code and frame pulse, to output the capture a frame pulse becomes a time effective to the counter value in one frame, the counter value the taken as the system time code System time code capture circuit;
The type of system time code and the memory control signal, on the basis of the memory control signal writing in the input order of the system time code, reads the system time code based on the memory control signal, PES generated as PES additional time stamp A memory unit for outputting to the unit;
A PES generation unit that inputs the PES added time stamp from the memory unit and outputs the packetized PES data;
The time stamp generation circuit according to claim 1, further comprising: The time stamp determination unit
A first determination unit that inputs the ES generation time stamp and outputs first determination data, a second determination unit that outputs second determination data, and a third determination data that outputs third determination data A determination unit,
The difference between the current time stamp value and the previous time stamp value with respect to the input ES generation time stamp is determined by a multiple of the time corresponding to one frame, and if the difference is equivalent to one frame The first determination data is true, the second determination data is true if the difference is equivalent to 1.5 frames, and the third determination data is true if the difference is equivalent to two frames. the first to be true, the second or third determination claim 2 or claim 3 time stamp generating circuit according to any one and outputs to the memory control unit as the judgment data of the data. The memory control unit refers to the write control unit that outputs a control signal to be written to a predetermined address in the order in which the system time codes are input to the memory unit, the data read timing signal, and the determination data. A read control unit that outputs a control signal for reading the system time code from the memory ;
Before Symbol read control unit, based on the judgment data from the time stamp judging section, said first judgment data is read true if the current address, the second decision data read true if the next address and performs read control of said third judgment data is read one skipped address true if the next address, billed you and adjusts the time information to be added as a time stamp by the read control Item 5. A time stamp generation circuit according to Item 4. The memory unit includes a memory and a calculator.
The arithmetic unit inputs the determination data from the memory control unit, and when there is the determination data that is true including the equivalent of 0.5 frames, 0.5% of the system time code read from the memory 5. The time stamp generation circuit according to claim 4 , wherein addition is performed in units of frames and the result is output as the PES added time stamp.

Images