JP3933424B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device using a memory transistor including a charge storage layer and a control gate.
[0002]
[Prior art]
As an EEPROM memory cell, a MOS transistor structure having a charge storage layer and a control gate in a gate portion and injecting a charge into the charge storage layer and discharging a charge from the charge storage layer using a tunnel current is known. It has been. In this memory cell, the difference in threshold voltage due to the difference in charge storage state of the charge storage layer is stored as data “0” and “1”.
[0003]
For example, in the case of an n-channel memory cell using a floating gate as a charge storage layer, in order to inject electrons into the floating gate, the source and drain diffusion layers and the substrate are grounded and a positive high voltage is applied to the control gate. . At this time, electrons are injected from the substrate side into the floating gate by a tunnel current. By this electron injection, the threshold voltage of the memory cell moves in the positive direction. In order to emit electrons from the floating gate, the control gate is grounded and a positive high voltage is applied to any of the source, drain diffusion layer, and substrate. At this time, electrons on the substrate side are emitted from the floating gate by a tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.
[0004]
In the above operation, in order to efficiently perform electron injection and emission, that is, writing and erasing, the relationship of capacitive coupling between the floating gate, the control gate, and the substrate is important. In other words, the larger the capacitance between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate, which facilitates writing and erasing.
[0005]
However, due to advances in semiconductor technology in recent years, particularly advances in microfabrication technology, the size and capacity of EEPROM memory cells are rapidly increasing.
[0006]
Therefore, an important problem is how to secure a large capacity between the floating gate and the control gate because the memory cell area is small.
[0007]
In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them is thinned, the dielectric constant is increased, or the facing area between the floating gate and the control gate is increased. is required.
[0008]
However, thinning the gate insulating film has a limit in reliability.
[0009]
In order to increase the dielectric constant of the gate insulating film, for example, it is conceivable to use a silicon nitrogen film or the like instead of the silicon oxide film, but this also has a problem mainly in reliability and is not practical.
[0010]
Therefore, in order to secure a sufficient capacity, it is necessary to secure an overlap area between the floating gate and the control gate at a certain value or more. This is because the area of the memory cell is reduced and the capacity of the EEPROM is increased. It becomes an obstacle to plan.
[0011]
On the other hand, in the EEPROM described in Japanese Patent No. 2877462, a memory transistor is configured by using the side walls of a plurality of columnar semiconductor layers arranged in a matrix on a semiconductor substrate separated by lattice-like grooves. That is, the memory transistor includes a drain diffusion layer formed on the top surface of each columnar semiconductor layer, a common source diffusion layer formed on the bottom of the groove, a charge storage layer surrounding the entire periphery of each columnar semiconductor layer, and a control gate. The control gate is continuously arranged with respect to a plurality of columnar semiconductor layers in one direction to form a control gate line. In addition, a bit line connected to the drain diffusion layers of the plurality of memory transistors in a direction intersecting with the control gate line is provided. The charge storage layer and the control gate of the memory transistor described above are formed below the columnar semiconductor layer. Also, in the one-transistor / one-cell configuration, when the memory transistor is in an over-erased state, that is, when the read potential is 0 V and the threshold value is in a negative state, the cell current flows even if it is not selected. It is. In order to prevent this surely, a selection gate transistor is provided in which a gate electrode is formed so as to surround at least a part of the periphery of the columnar semiconductor layer so as to overlap with the memory transistor in series. .
[0012]
Thus, the memory cell of the conventional EEPROM has a charge storage layer and a control gate formed so as to surround the columnar semiconductor layer using the side wall of the columnar semiconductor layer. A sufficiently large capacity between the control gates can be secured. Also, the drain diffusion layer connected to the bit line of each memory cell is formed on the upper surface of the columnar semiconductor layer, and is completely electrically separated by the groove. Further, the element isolation region can be reduced, and the memory cell size is reduced. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.
[0013]
A conventional EEPROM having a cylindrical columnar silicon layer 2 is shown in FIG. FIGS. 719 (a) and (b) are cross-sectional views taken along the lines AA 'and BB' of the EEPROM in FIG. 718, respectively. In FIG. 718, the selection gate line in which the gate electrodes of the selection gate and the transistor are continuously formed is not shown because it becomes complicated.
[0014]
In this EEPROM, a p-type silicon substrate 1 is used, and a plurality of columnar p separated by a lattice stripe-like groove 3 thereon.^-The type silicon layers 2 are arranged in a matrix, and each of the columnar silicon layers 2 is a memory cell region. A drain diffusion layer 10 is formed on the upper surface of each silicon layer 2, a common source diffusion layer 9 is formed at the bottom of the groove 3, and an oxide film 4 having a predetermined thickness is embedded in the bottom of the groove 3. Further, a floating gate 6 is formed below the columnar silicon layer 2 via a tunnel oxide film 5 so as to surround the columnar silicon layer 2, and a control gate 8 is formed outside the columnar silicon layer 2 via an interlayer insulating film 7. The memory transistor is formed.
[0015]
Here, as shown in FIG. 718 and FIG. 719 (b), the control gate 8 is continuously arranged for a plurality of memory cells in one direction, and the control gate line, that is, the word line WL (WL1, WL2,. ). Then, a gate electrode 32 is disposed on the upper part of the columnar silicon layer 2 via a gate oxide film 31 so as to surround the periphery of the column like the memory transistor, thereby forming a selection gate transistor. Similar to the control gate 8 of the memory cell, the gate electrode 32 of this transistor is continuously arranged in the same direction as the control gate line to become a selection gate line.
[0016]
As described above, the memory transistor and the select gate transistor are embedded in a state of being stacked inside the trench. One end of the control gate line remains as a contact portion 14 on the surface of the silicon layer, and the selection gate line also leaves a contact portion 15 in the silicon layer at the end opposite to the control gate. Al wirings 13 and 16 to be lines CG are brought into contact.
[0017]
A common source diffusion layer 9 of the memory cells is formed at the bottom of the trench 3, and a drain diffusion layer 10 for each memory cell is formed on the upper surface of each columnar silicon layer 2. The substrate of the memory cell formed in this way is covered with a CVD oxide film 11, a contact hole is opened in this, and a bit line commonly connecting the drain diffusion layers 10 of the memory cells in the direction intersecting the word line WL Al wirings 12 serving as BL (BL1, BL2,...) Are provided.
[0018]
When patterning the control gate line, a mask made of PEP is formed at the columnar silicon layer position at the end of the cell array, and a contact portion 14 made of a polycrystalline silicon film continuous with the control gate line is left on the surface. An Al wiring 13 serving as a word line is brought into contact with an Al film formed simultaneously with the line BL.
[0019]
The above EEPROM can be manufactured as follows.
[0020]
First, a p-type silicon substrate 1 having a high impurity concentration is applied to a p-type silicon substrate 1 having a low impurity concentration.^-A mask layer 21 is deposited on the surface of the wafer on which the type silicon layer 2 is epitaxially grown, a photoresist pattern 22 is formed by a known PEP process, and the mask layer 21 is etched using this (FIG. 720). (A)).
[0021]
Next, using the mask layer 21, the silicon layer 2 is etched by a reactive ion etching method to form a lattice-like groove 3 having a depth reaching the substrate 1. Thereby, the silicon layer 2 is separated into a plurality of islands in a columnar shape. Thereafter, a silicon oxide film 23 is deposited by the CVD method, and this is left on the side wall of each columnar silicon layer 2 by anisotropic etching. Then, n-type impurities are ion-implanted to form the drain diffusion layer 10 on the upper surface of each columnar silicon layer 2, and the common source diffusion layer 9 is formed at the bottom of the groove (FIG. 720 (b)).
[0022]
Thereafter, the oxide film 23 is etched away around each columnar silicon layer 2 by isotropic etching, and then channel ion implantation is performed on the sidewalls of each silicon layer 2 using oblique ion implantation as necessary. Instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used.
[0023]
Then, a CVD silicon oxide film 4 is deposited and etched by isotropic etching to fill the bottom of the groove 3 with a predetermined thickness. Thereafter, a tunnel oxide film 5 of about 10 nm, for example, is formed around each silicon layer 2 by thermal oxidation, and then a first layer polycrystalline silicon film is deposited. This first layer polycrystalline silicon film is etched by anisotropic etching to leave the lower side wall of the columnar silicon layer 2 and form a floating gate 5 surrounding the silicon layer 2 (FIG. 721 (c)).
[0024]
Next, an interlayer insulating film 7 is formed on the surface of the floating gate 6 formed around each columnar silicon layer 2. The interlayer insulating film 7 is, for example, an ONO film. Then, a second-layer polycrystalline silicon film is deposited and etched by anisotropic etching, thereby forming a control gate 8 below the columnar silicon layer 2 (FIG. 721 (d)). At this time, the control gate 8 sets the interval between the columnar silicon layers 2 to a predetermined value or less in advance in the vertical direction of FIG. 718 so that a control gate line continuous in that direction can be used without using a mask process. Formed as. Then, the unnecessary interlayer insulating film 7 and the tunnel oxide film 2 thereunder are removed by etching, and then a CVD silicon oxide film 111 is deposited and etched to the middle of the groove 3, that is, the floating gate 7 and the control of the memory cell. It is embedded until the gate 8 is hidden (FIG. 722 (e)).
[0025]
Thereafter, a gate oxide film 31 of about 20 nm is formed on the exposed columnar silicon layer 2 by thermal oxidation, a third-layer polycrystalline silicon film is deposited, and this is etched by anisotropic etching to form the gate of the MOS transistor. The electrode 32 is formed (FIG. 722 (f)). The gate electrode 32 is also continuously patterned in the same direction as the control gate line to become a selection gate line. Although the selection gate lines can also be formed continuously by self-alignment, it is more difficult than the control gate 8 of the memory cell. This is because the memory transistor portion is a two-layer gate, whereas the selection gate transistor is a single-layer gate, so that the gate electrode interval between adjacent cells is wider than the control gate interval. Therefore, in order to ensure that the gate electrode 32 continues, this is made into a two-layer polycrystalline silicon structure, and the first polycrystalline silicon film is left only in the portion where the gate electrode is connected in the mask process, and the next polycrystalline silicon film is formed. On the other hand, the technique of leaving the side wall may be used.
[0026]
Note that a mask is formed in the etching of the polycrystalline silicon film so that the contact portions 14 and 15 are formed on the upper surface of the columnar silicon layer at different end portions of the control gate line and the selection gate line.
[0027]
Finally, after depositing a CVD silicon oxide film 112 and performing a flattening process if necessary, a contact hole is opened, and Al wiring 12 to become the bit line BL, control gate line CG and control gate line CG are formed by Al deposition and patterning. The Al wiring 13 to be formed and the Al wiring 16 to be the word line WL are simultaneously formed (FIG. 723).
[0028]
FIG. 724 (a) shows a cross-sectional structure of a main part of one memory cell of this conventional EEPROM, and FIG. 724 (b) shows an equivalent circuit.
[0029]
The operation of this EEPROM will be described with reference to FIGS. 724 (a) and (b).
[0030]
First, in the case of using hot carrier injection for writing, a sufficiently high positive potential is applied to the selected word line WL, and a predetermined positive potential is applied to the selection control gate line CG and the selected bit line BL. As a result, a positive potential is transmitted to the drain of the memory transistor Qc via the selection gate transistor Qs, and a channel current is caused to flow through the memory transistor Qc, so that hot carrier injection is performed. Move in the positive direction.
[0031]
In erasing, the selection control gate CG is set to 0 V, a high positive potential is applied to the word line WL and the bit line BL, and electrons in the floating gate are emitted to the drain side. In the case of batch erasing, electrons can be emitted to the source side by applying a high positive potential to the common source. As a result, the threshold value of the memory cell moves in the negative direction.
[0032]
In the read operation, the selection gate transistor Qs is opened by the word line WL, the read potential of the control gate line CG is applied, and “0” or “1” is discriminated by the presence or absence of current. When FN tunneling is used for electron injection, a high positive potential is applied to the selection control gate line CG and the selection word line WL, the selection bit line BL is set to 0 V, and electrons are injected from the substrate to the floating gate.
[0033]
In addition, since this EEPROM has a selection gate transistor, it does not malfunction even if it enters an over-erased state.
[0034]
By the way, in this conventional EEPROM, as shown in FIG. 724 (a), there is no diffusion layer between the select gate transistor Qs and the memory transistor Qc. This is because it is difficult to selectively form a diffusion layer on the side surface of the columnar silicon layer. Therefore, in the structures of FIGS. 719 (a) and (b), it is desirable that the isolation oxide film between the gate portion of the memory transistor and the gate portion of the select gate transistor be as thin as possible. In particular, when hot electron injection is used, the isolation oxide film thickness needs to be about 30 to 40 nm in order to transmit a sufficient “H” level potential to the drain of the memory transistor.
[0035]
Such a minute interval is practically difficult only by filling the oxide film by the CVD method described in the previous manufacturing process. Therefore, the CVD oxide film is buried in a state in which the floating gate 6 and the control gate 8 are exposed, and a thin oxide film is simultaneously formed on the exposed portions of the floating gate 6 and the control gate 8 in the gate oxidation process for the select gate transistor. desirable.
[0036]
Further, according to this conventional example, a columnar silicon layer is arranged with the bottom of the lattice-like groove as an isolation region, and a memory cell having a floating gate formed so as to surround the periphery of the columnar silicon layer is configured. Thus, a highly integrated EEPROM with a small area occupied by the memory cells can be obtained. In addition, although the memory cell occupation area is small, a sufficiently large capacitance between the floating gate and the control gate can be secured.
[0037]
In the conventional example, the control gate of each memory cell is formed to be continuous in one direction without using a mask. This is only possible if the columnar silicon layers are not symmetrically arranged. That is, by making the adjacent interval between the columnar silicon layers in the word line direction smaller than that in the bit line direction, control gate lines that are separated in the bit line direction and connected in the word line direction can be automatically obtained without a mask. . On the other hand, for example, when the columnar silicon layers are arranged symmetrically, a PEP process is required.
[0038]
More specifically, the second-layer polycrystalline silicon film is deposited thick and is selectively etched through the PEP process so as to leave it in a portion to be continued as a control gate line. Next, a third-layer polycrystalline silicon film is deposited, and etching for leaving the side walls is performed in the same manner as described above.
[0039]
Even when the arrangement of the columnar silicon layers is not symmetrical, depending on the arrangement interval, it may not be possible to form a continuous control gate line automatically as in the conventional example.
[0040]
Even in such a case, a control gate line continuous in one direction may be formed by using the mask process as described above.
[0041]
In the conventional example, a memory cell having a floating gate structure is used. However, the charge storage layer does not necessarily have a floating gate structure, and the charge storage layer is realized by trapping in a multilayer insulating film, for example, an MNOS structure. It is also effective in the case of.
[0042]
A memory cell having such an MNOS structure is shown in FIG. Note that the memory cell having the MNOS structure in FIG. 725 corresponds to the memory cell in FIG.
[0043]
The laminated insulating film 24 serving as a charge storage layer has a laminated structure of a tunnel oxide film and a silicon nitride film or a structure in which an oxide film is further formed on the nitride film surface.
[0044]
FIG. 726 shows a conventional example in which the memory transistor and the selection gate transistor are reversed in the MNOS, that is, a memory cell in which the selection gate transistor is formed in the lower part of the columnar silicon layer 2 and the memory transistor is formed in the upper part. Show.
[0045]
This structure in which a select gate transistor is provided on the common source side can be employed when a hot electron injection method is used as a writing method.
[0046]
FIG. 727 shows a conventional example in which a plurality of memory cells are formed in one columnar silicon layer. Portions corresponding to the previous conventional example are denoted by the same reference numerals as those of the previous conventional example, and detailed description thereof is omitted. In this conventional example, a selection gate transistor Qs1 is formed at the bottom of the columnar silicon layer 2, three memory transistors Qc1, Qc2, and Qc3 are overlaid thereon, and a selection gate transistor Qs2 is formed thereon. is doing. This structure is basically obtained by repeating the manufacturing process described above.
[0047]
Also in the conventional example shown in FIGS. 726 and 727, a MNOS structure can be used as a memory transistor instead of the floating gate structure.
[0048]
As described above, according to the above prior art, by using the side wall of the columnar semiconductor layer separated by the lattice-like grooves, a memory cell using a memory transistor having a charge storage layer and a control gate is configured. Thus, it is possible to obtain an EEPROM that achieves a high degree of integration by ensuring a sufficiently large capacitance between the control gate and the charge storage layer and also by reducing the area occupied by the memory cell.
[0049]
[Problems to be solved by the invention]
However, when a plurality of memory cells are connected in series to one columnar semiconductor layer and the threshold value of each memory cell is considered to be the same, a read potential is applied to the control gate line CG and the presence or absence of current is determined. In the read operation for determining “0” and “1”, in the memory cells located at both ends connected in series, the fluctuation of the threshold becomes remarkable due to the back bias effect from the substrate. As a result, the number of memory cells connected in series is restricted on the device, which becomes a problem when the capacity is increased.
[0050]
In addition, this is not only the case where a plurality of memory cells are connected in series to one columnar semiconductor layer, but also the substrate in the in-plane direction not only when one memory cell is formed in one columnar semiconductor layer. There is also a problem that the threshold value of each memory cell fluctuates due to variations in the back bias effect.
[0051]
Furthermore, in the conventional example, the charge storage layer and the control gate are formed in a self-aligned manner with respect to the columnar semiconductor layer. However, when the capacity of the cell array is increased, the columnar semiconductor layer is preferably formed with a minimum processing dimension. . Here, when a floating gate is used as the charge storage layer, the capacitive coupling relationship between the floating gate, the control gate, and the substrate is such that the area around the columnar semiconductor layer and the area around the floating gate, and the columnar semiconductor layer and the floating gate are insulated. It is determined by the thickness of the tunnel oxide to be formed and the thickness of the interlayer insulating film for insulating the floating gate from the control gate. In the conventional example, the side wall of the columnar semiconductor layer is used to have a charge storage layer and a control gate formed so as to surround the columnar semiconductor layer, and a sufficiently large capacitance between the charge storage layer and the control gate is ensured with a small occupied area. However, when the columnar semiconductor layer is formed with the minimum processing size and the tunnel oxide film thickness and the interlayer insulation film thickness are fixed, the capacitance between the charge storage layer and the control gate is simple. The area of the outer periphery of the floating gate, that is, the film thickness of the floating gate. Therefore, it is difficult to increase the capacitance between the charge storage layer and the control gate without increasing the area occupied by the memory cell.
[0052]
In other words, it is difficult to increase the ratio of the capacity of the floating gate and the control gate to the capacity of the floating gate and the island-like semiconductor layer without increasing the area occupied by the memory cell.
[0053]
In addition, when the gate electrode of the transistor is formed for each stage, processing variations in the gate length due to process variations occur. For example, when the gate electrode is formed in a sidewall shape, the deposited electrode material film needs to be etched back to the extent that it is comparable to the height of the columnar semiconductor layer. In other words, when a large capacity is assumed, the number of memory gates formed in the columnar semiconductor layer increases, and thus the height of the columnar semiconductor layer inevitably increases. Therefore, the amount of etch back increases and process variation also increases. These effects become significant when the capacity of the cell array is increased.
[0054]
The present invention has been made in view of these problems, and by improving the degree of integration by reducing the influence of the back bias effect of the semiconductor memory device having the charge storage layer and the control gate, the area occupied by the memory cell is increased. Semiconductor memory device capable of suppressing variation in characteristics of memory cell by increasing capacitance between charge storage layer and control gate without minimizing and minimizing processing variation in gate length of each memory cell transistor An object is to provide a manufacturing method.
[0055]
[Means for Solving the Problems]
According to the present invention, the semiconductor substrate includes at least one island-like semiconductor layer formed by epitaxial growth, a charge storage layer formed on all or part of the periphery of the sidewall of the island-like semiconductor layer, and a control gate. A semiconductor memory device having at least one memory cell,
There is provided a semiconductor memory device in which at least one of the memory cells is electrically insulated from the semiconductor substrate.
[0056]
Further, according to the present invention, a step of forming one or more sets of laminated films composed of three or more different films including the first insulating film on the semiconductor substrate;
Forming a hole reaching the semiconductor substrate in the laminated film;
A step of epitaxially growing a semiconductor in the hole to form an island-shaped semiconductor layer on the semiconductor substrate;
Dividing the first insulating film so as to be disposed only in the peripheral part of the island-shaped semiconductor layer, and covering the divided first insulating film with another insulating film;
Partially exposing the surface of the island-like semiconductor layer so that the first insulating film and the other insulating film remain;
Forming a first conductive film on the exposed sidewall of the island-shaped semiconductor layer via an insulating film;
Forming the second conductive film on the first conductive film with an interlayer insulating film interposed therebetween.
[0057]
Furthermore, according to the present invention, a step of forming one or more sets of laminated films composed of three or more different films including the first insulating film on the semiconductor substrate;
Forming a hole reaching the semiconductor substrate in the laminated film;
A step of epitaxially growing a semiconductor in the hole to form an island-shaped semiconductor layer on the semiconductor substrate;
Dividing the first insulating film so as to be disposed only in the peripheral part of the island-shaped semiconductor layer, and covering the divided first insulating film with another insulating film;
Partially exposing the surface of the island-like semiconductor layer so that the first insulating film and the other insulating film remain;
Forming the first conductive film on the exposed sidewall of the island-shaped semiconductor layer via the charge storage layer made of a laminated insulating film.
[0058]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor memory device of the present invention mainly includes a semiconductor substrate, at least one island-like semiconductor layer formed by epitaxial growth, at least one charge storage layer formed around the sidewall of the island-like semiconductor layer, and at least one And at least one memory cell including a control gate (third electrode), and at least one of the memory cells in the island-shaped semiconductor layer is electrically insulated from the semiconductor substrate.
[0059]
Here, that at least one of the memory cells is electrically insulated from the semiconductor substrate may be one in which the semiconductor substrate and the island-like semiconductor layer are electrically insulated, and there are two or more memory cells. If formed, the memory cells may be electrically insulated so that the memory cells located above the insulated portion are electrically insulated from the semiconductor substrate. As will be described later, when a selection gate (memory gate) is arbitrarily formed below the memory cell, the selection transistor constituted by the selection gate is electrically insulated from the semiconductor substrate. The memory cell located above the insulated region is electrically connected to the semiconductor substrate by electrically insulating the select transistor and the memory cell. Or one that is insulated. In particular, there is a case where a selection transistor is formed between the semiconductor substrate and the island-shaped semiconductor layer or under the memory cell, and the selection transistor and the semiconductor substrate are electrically insulated. preferable. The electrical insulation may be performed, for example, by forming an impurity diffusion layer having a conductivity type different from that of the semiconductor substrate over the entire region to be insulated, or the impurity diffusion layer in a part of the region to be insulated. May be formed by utilizing a depletion layer at the junction, and further, the gap may be spaced so as not to be electrically conductive, resulting in electrical insulation. . Further, the semiconductor substrate and the cell or the selection transistor are made of, for example, SiO.₂It may be electrically insulated by an insulating film such as. Note that when a plurality of memory cells are formed, and when a selection transistor is arbitrarily formed above and below the memory cell, there is a gap between any memory cell and / or between the selection transistor and the memory cell. Can be electrically isolated.
[0060]
Further, the charge storage layer and the control gate may be formed over the entire periphery of the sidewall of the island-shaped semiconductor layer, or may be formed in a region excluding a part of the surrounding region.
Further, only one memory cell may be formed on one island-shaped semiconductor layer, or two or more memory cells may be formed. When three or more memory cells are formed, a selection gate is formed below and / or above the memory cell, and a selection transistor including the selection gate and the island-shaped semiconductor layer is formed. Is preferred.
In the following, a plurality of, for example, two memory cells are arranged in series in one island-like semiconductor layer, and the island-like semiconductor layers are arranged in a matrix, and are selected below and above the memory cells, respectively. A structure in which transistors are arranged one by one will be described. In the following embodiments, the gate electrode of the selection transistor is shown as a lower gate electrode as a second electrode and an upper gate electrode as a fifth electrode. The tunnel insulating film is shown as a third insulating film, the side wall spacer is shown as a fourth insulating film, and the gate insulating film constituting the selection transistor is shown as a thirteenth insulating film.
[0061]
In the semiconductor memory device, an impurity diffusion layer for reading out the charge accumulation state of the memory cell is formed in the island-like semiconductor layer as a source or drain (first wiring) of the memory cell, and the semiconductor substrate is formed by the impurity diffusion layer. And the island-like semiconductor layer are electrically insulated. Furthermore, control gates formed in the plurality of island-like semiconductor layers are continuously arranged in one direction to constitute a control gate line (third wiring). In the island-like semiconductor layer, another impurity diffusion layer is formed as the drain or source of the memory cell, and a plurality of impurity diffusion layers in a direction crossing the control gate line are electrically connected to form a bit line ( 4th wiring) is comprised.
Note that the control gate line and the bit line orthogonal to the control gate line may be formed in any direction three-dimensionally, but in the following, a configuration in which both are formed in the horizontal direction with respect to the semiconductor substrate will be described. To do.
[0062]
Embodiment in plan view of memory cell array
Plan views of a memory cell array in the semiconductor memory device of the present invention will be described with reference to FIGS. FIGS. 1 to 9 are plan views showing an EEPROM memory cell array having a floating gate as a charge storage layer. 10 shows a memory cell array having a MONOS structure having a stacked insulating film as a charge storage layer, FIG. 11 shows a memory cell array having a DRAM structure having a MIS capacitor as a charge storage layer, and FIG. 12 has a MIS transistor as a charge storage layer. It is one Example of the top view which shows the memory cell array which is SRAM structure. In these drawings, the second wiring or fifth wiring is used as a gate electrode (hereinafter referred to as “selection gate”) for selecting a memory cell, the third wiring is used as a control gate, and the fourth wiring is used as a bit line. And the layout of the first wiring which is the source line will be described. Further, the selection gate transistor is omitted because it becomes complicated.
First, a plan view showing an EEPROM memory cell array having a floating gate as a charge storage layer will be described.
[0063]
FIG. 1 shows an arrangement in which cylindrical island-shaped semiconductor portions forming a memory cell are arranged, for example, at intersections where two kinds of parallel lines are orthogonal to each other, and a first for selecting and controlling each memory cell. The wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer are memory cell arrays arranged in parallel to the substrate surface. Further, by changing the arrangement interval of the island-shaped semiconductor portions in the AA ′ direction which is a direction intersecting the fourth wiring layer 2840 and the BB ′ direction which is the fourth wiring layer direction, each memory cell is changed. The second conductive film, which is the control gate, is formed continuously in one direction, in the direction AA ′ in FIG. 1, and becomes the third wiring layer. Similarly, the second conductive film which is the gate of the selection gate transistor is formed continuously in one direction to form the second wiring layer.
[0064]
Further, a terminal for electrically connecting to the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is, for example, an end on the A ′ side of the memory cell connected in the AA ′ direction of FIG. For example, a terminal for electrically connecting to the second wiring layer and the third wiring layer is provided at the end of the memory cell connected in the AA ′ direction in FIG. The fourth wiring layer 2840 disposed on the opposite side of the substrate of the cylindrical semiconductor portion is electrically connected to each of the cylindrical island-shaped semiconductor portions forming the memory cells. For example, in FIG. A fourth wiring layer 2840 is formed in a direction intersecting with the second wiring layer and the third wiring layer. Moreover, the terminal for electrically connecting with the 1st wiring layer is formed by the island-shaped semiconductor part, and the terminal for electrically connecting with the 2nd wiring layer and the 3rd wiring layer is island-shaped The second conductive film is formed by covering the semiconductor portion.
[0065]
Terminals for electrical connection with the first wiring layer, the second wiring layer, and the third wiring layer are the first contact portion 2910, the second contact portions 2921, 2924, and the third contact portion 2932, respectively. , 2933. In FIG. 1, the first wiring layer 2810 is drawn to the upper surface of the semiconductor memory device through the first contact portion 2910. Note that the arrangement of the cylindrical island-shaped semiconductor portions forming the memory cell may not be the arrangement as shown in FIG. 1, and if there is a positional relationship of the wiring layers as described above or an electrical connection relationship, the memory cell is arranged. The arrangement of the cylindrical island-shaped semiconductor portions to be formed is not limited.
In FIG. 1, the island-shaped semiconductor portions connected to the first contact portion 2910 are arranged at all the end portions on the A ′ side of the memory cells connected in the AA ′ direction. May be disposed in part or all of the portion, or in any of the island-shaped semiconductor portions forming the memory cell connected in the direction AA ′ that is the direction intersecting the fourth wiring layer 2840 May be.
In addition, the island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 2921 and 2924 and the third contact portions 2932 and 2933 is the end on the side where the first contact portion 2910 is not disposed. May be arranged in a portion, may be arranged continuously at an end portion on the side where the first contact portion 2910 is arranged, or AA ′ which is a direction intersecting the fourth wiring layer 2840 It may be arranged in any of the island-like semiconductor parts forming the memory cells connected in the direction, or the second contact parts 2921 and 2924, the third contact part 2932, etc. may be arranged separately. Good.
[0066]
The first wiring layer 2810 and the fourth wiring layer 2840 may have any width and shape as long as desired wiring is obtained. Further, when the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is formed in a self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film, The island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer is electrically separated from the second wiring layer and the third wiring layer formed by the second conductive film. However, they are in contact with each other through an insulating film. For example, in FIG. 1, a first conductive film is formed through an insulating film on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 2910 is connected. The second conductive film is formed on the side surface of the first conductive film via the insulating film, and the second conductive film is the fourth conductive film. It is connected to the second wiring layer and the third wiring layer which are continuously formed in the AA ′ direction which is a direction crossing the wiring layer 2840. At this time, the shape of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion is not limited. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is, for example, By setting the film thickness to 2 times or less of the thickness of the conductive film, all of the first conductive film on the side surface of the island-shaped semiconductor portion that becomes a terminal for electrical connection with the first wiring layer may be removed.
In FIG. 1, the second and third contact portions are formed on the second conductive films 2521 to 2524 formed so as to cover the top of the island-like semiconductor portion. The shape of the second and third wiring layers is not limited.
In FIG. 1, the cross section used in the manufacturing process example, that is, the AA ′ cross section, the BB ′ cross section, the CC ′ cross section, the DD ′ cross section, the EE ′ cross section, and the FF ′ cross section are also shown. is doing.
[0067]
FIG. 2 shows an arrangement in which the cylindrical island-shaped semiconductor portions forming the memory cells are arranged, for example, at points where two types of parallel lines intersect without crossing each other, and each memory cell is selected and controlled. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer for the memory cell array are arranged in parallel to the substrate surface. Further, by changing the arrangement interval of the island-shaped semiconductor portions in the AA ′ direction which is a direction intersecting with the fourth wiring layer 2840 and the BB ′ direction in the drawing, it is a control gate of each memory cell. The second conductive film is continuously formed in one direction, and in FIG. 2, in the AA ′ direction, and becomes a third wiring layer. Similarly, the second conductive film which is the gate of the selection gate transistor is formed continuously in one direction to form the second wiring layer.
[0068]
Further, a terminal for electrically connecting to the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is connected to, for example, the end on the A ′ side of the memory cell connected in the AA ′ direction of FIG. 2 and provided with terminals for electrical connection with the second wiring layer and the third wiring layer, for example, at the end on the A side of the memory cell connected in the AA ′ direction in FIG. The fourth wiring layer 2840 arranged on the opposite side of the substrate of the cylindrical semiconductor portion is electrically connected to each of the cylindrical island-shaped semiconductor portions forming the memory cells. For example, in FIG. A fourth wiring layer 2840 is formed in a direction intersecting with the second wiring layer and the third wiring layer. A terminal for electrically connecting to the first wiring layer is formed by an island-shaped semiconductor portion, and a terminal for electrically connecting to the second wiring layer and the third wiring layer is an island-shaped semiconductor portion. It is formed with the 2nd electrically conductive film coat | covered by. Terminals for electrical connection with the first wiring layer, the second wiring layer, and the third wiring layer are the first contact portion 2910, the second contact portions 2921, 2924, and the third contact, respectively. Are connected to the units 2932 and 2933.
[0069]
In FIG. 2, the first wiring layer 2810 is drawn to the upper surface of the semiconductor memory device through the first contact portion 2910. Note that the arrangement of the columnar island-shaped semiconductor portions forming the memory cell does not have to be as shown in FIG. 2024. If there is a wiring layer positional relationship or electrical connection relationship as described above, the memory cell is formed. The arrangement of the cylindrical island-shaped semiconductor portions to be performed is not limited. Further, in FIG. 2, the island-shaped semiconductor portion connected to the first contact portion 2910 is arranged at all end portions on the A ′ side of the memory cells connected in the AA ′ direction. It may be arranged at a part or all of the end portion, or in any of the island-shaped semiconductor portions forming the memory cell connected in the AA ′ direction that intersects the fourth wiring layer 2840 You may arrange.
[0070]
The island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 2921 and 2924 and the third contact portions 2932 and 2933 is the end on the side where the first contact portion 2910 is not disposed. May be arranged in a portion, may be arranged continuously at an end portion on the side where the first contact portion 2910 is arranged, or AA ′ which is a direction intersecting the fourth wiring layer 2840 It may be arranged in any of the island-like semiconductor parts forming the memory cells connected in the direction, or the second contact parts 2921 and 2924, the third contact part 2932, etc. may be arranged separately. Good. The first wiring layer 2810 and the fourth wiring layer 2840 may have any width and shape as long as desired wiring is obtained.
[0071]
When the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is formed in a self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film, Although the island-like semiconductor portion serving as a terminal for electrical connection to the wiring layer is electrically separated from the second wiring layer and the third wiring layer formed of the second conductive film, It has a state of being in contact through an insulating film. For example, in FIG. 2, a first conductive film is formed on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 2910 is connected via an insulating film, and the first conductive film forms a memory cell. A second conductive film is formed on the side surface of the first conductive film via an insulating film, and the second conductive film is a fourth wiring. It is connected to the second wiring layer and the third wiring layer formed continuously in the AA ′ direction which is a direction crossing the layer 2840. At this time, the shape of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion is not limited. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is, for example, The first conductive film on the side surface of the island-shaped semiconductor portion that becomes a terminal for electrical connection with the first wiring layer may be removed by setting the film thickness to two times or less of the thickness of the conductive film.
[0072]
In FIG. 2, the second and third contact portions are formed on the second conductive films 2521 to 2524 formed so as to cover the tops of the island-like semiconductor portions. The shape of the second and third wiring layers is not limited. In FIG. 2, the cross sections used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are also shown.
[0073]
3 and FIG. 4 show the orientation in FIGS. 3 and 4 as an example when the cross-sectional shape of the island-shaped semiconductor portion forming the memory cell is a square compared to FIGS. Each example is different. The cross-sectional shape of the island-like semiconductor portion is not limited to a circle or a rectangle. For example, an elliptical shape, a hexagonal shape or an octagonal shape may be used. However, if the size of the island-shaped semiconductor part is close to the processing limit, even if it has a corner such as a quadrangle, hexagon, or octagon at the time of design, the corner is rounded by the photo process or etching process. The cross-sectional shape of the island-like semiconductor portion is close to a circle or an ellipse.
[0074]
FIG. 5 shows an example in which the number of memory cells formed in series in the island-shaped semiconductor portion forming the memory cell is two and no selection gate transistor is formed. In FIG. 5, the cross sections used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are also shown.
6 shows an example in which the long axis of the ellipse is in the BB ′ direction as an example when the cross-sectional shape of the island-shaped semiconductor portion forming the memory cell is not a circle but an ellipse. Show. FIG. 7 shows an example in which the major axis of the ellipse is in the A-A ′ direction with respect to FIG. 6. The direction of the major axis of the ellipse is not limited to the A-A ′ direction and the B-B ′ direction, and may be in any direction.
FIG. 8 shows an example in which the contact layer is formed in the desired wiring layer by removing the wiring layer, the insulating film, and the like above the desired wiring layer by anisotropic etching, as shown in FIG. An example in which a common contact portion is formed in the lead portion of the three wiring layers is shown. In the example of FIG. 8, a contact portion is formed in a desired wiring layer in common to memory cells arranged continuously in the HH ′ direction and memory cells arranged adjacently in the same manner. In the case where only one of the mutual memory cells is operated, selection of the memory cell is realized by applying a desired potential to every other fourth diffusion layer 2840. Further, in contrast to the example of FIG. 8, a contact portion is formed in a desired wiring layer in common to memory cells arranged continuously in the HH ′ direction and memory cells arranged adjacently in the same manner. Instead, a contact portion may be formed in a desired wiring layer in each memory cell arranged continuously. In FIG. 8, the cross section used in the manufacturing example, that is, the H-H 'cross section and the I1-I1' cross section to I5-I5 'cross section are also shown.
FIG. 9 is different from FIG. 1 in that polycrystalline silicon 2521 to 2524 as the second conductive film is formed in a stepped shape in the contact area, and the insulating film and the like above the desired wiring layer are formed by anisotropic etching. As an example of removing and forming a contact portion in a desired wiring layer, an example is shown in which a common contact portion is formed in the leading portion of the adjacent second and third wiring layers. Moreover, you may form an independent contact part in each wiring layer. In FIG. 9, the cross section used in the manufacturing example, that is, the H-H 'cross section and the I1-I1' cross section to the I5-I5 'cross section are also shown.
[0075]
Although the plan view of the semiconductor memory device having a floating gate as a charge storage layer has been described above, the arrangements and structures shown in FIGS. 1 to 9 may be used in various combinations.
[0076]
A plan view of a memory cell array using a charge storage layer other than a floating gate will also be described.
[0077]
FIG. 10 shows an example in which a stacked insulating film is used for the charge storage layer as in the MONOS structure, for example, except that the charge storage layer is changed from a floating gate to a stacked insulating film. is there. In FIG. 10, the cross section used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are shown together.
[0078]
FIG. 11 shows an example in which a MIS capacitor is used as a charge storage layer, such as a DRAM, as in FIG. 1. The charge storage layer is changed from a floating gate to a MIS capacitor, and a bit line and a source line are parallel to each other. It is the same except that it is arranged. In FIG. 11, the cross section used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are shown.
[0079]
FIG. 12 shows an example in which a MIS transistor is used as a charge storage layer, such as an SRAM. FIG. 12 shows an arrangement in which cylindrical island-shaped semiconductor portions forming a memory cell are arranged, for example, at intersections where two kinds of parallel lines are orthogonal to each other, and impurity diffusion for selecting and controlling each memory cell A first wiring layer formed of a layer 3721, a third wiring layer formed of a control gate 3514, and a fourth wiring layer serving as a bit line indicate a memory cell array arranged in parallel to the substrate surface. A second wiring layer 3840 including the second conductive film 3512 and the third conductive film 3513 is wired in two directions, a vertical direction and a horizontal direction, with respect to the substrate surface. The shapes of the second, third and fourth wiring layers are not limited as long as they can be connected to each other. In FIG. 12, the cross sections used in the manufacturing process example, that is, the J1-J1 ′ cross section, the J2-J2 ′ cross section, the K1-K1 ′ cross section, and the K2-K2 ′ cross section are shown. In FIG. 12, the first wiring layer 3710, the first wiring layer 3850, and terminals for electrical connection with these wiring layers are omitted because of complexity. In order to distinguish the island-shaped semiconductor layer 3110 from each wiring layer, the shape of the island-shaped semiconductor layer is circular, but may be reversed.
[0080]
Embodiment in sectional view of memory cell array
Cross-sectional views of a semiconductor memory device having a floating gate as a charge storage layer are shown in FIGS. In these sectional views of FIGS. 13 to 40, odd-numbered drawings are AA ′ sectional views in FIG. 1, and even-numbered drawings are BB ′ sectional views in FIG. In these embodiments, a plurality of columnar island-shaped semiconductor layers 2110 are arranged in a matrix on a p-type silicon substrate 2100, and a second selection gate is provided above and below each of the island-shaped semiconductor layers 2110. A structure in which a transistor having an electrode or a fifth electrode is arranged, a plurality of, for example, two memory transistors are arranged between selection gate transistors, and the transistors are connected in series along the island-shaped semiconductor layer. It has become. That is, a silicon oxide film 2470, which is an eleventh insulating film having a predetermined thickness, is disposed at the bottom of the groove between the island-shaped semiconductor layers, and a gate insulating film is formed on the island-shaped semiconductor layer side wall so as to surround the island-shaped semiconductor layer 2110. A selection gate 2500 is arranged as a selection gate transistor, and a silicon oxide film 2460 which is a tenth insulating film is formed on the sidewall of the island-shaped semiconductor layer so as to surround the island-shaped semiconductor layer 2110 above the selection gate transistor. A floating gate 2510 is disposed through the control gate 2520, and a control gate 2520 is disposed outside the floating gate 2510 through an interlayer insulating film 2610 formed of a multilayer film to form a memory transistor.
Further, a transistor having a fifth electrode 2500 serving as a selection gate is disposed above a plurality of these memory transistors similarly disposed in the same manner as described above. Further, as shown in FIGS. 1 and 14, the selection gate 2500 and the control gate 2520 are continuously arranged for a plurality of transistors in one direction, and are selected gate lines which are second wirings or fifth wirings. And a control gate line which is a third wiring. A source diffusion layer 2710 of the memory cell is arranged on the semiconductor substrate surface so that the active region of the memory cell is in a floating state with respect to the semiconductor substrate, and the active region of each memory cell is in a floating state. Thus, a diffusion layer 2720 is arranged, and a drain diffusion layer 2725 for each memory cell is arranged on the upper surface of each island-like semiconductor layer 2110. Between the memory cells arranged in this manner, a silicon oxide film 2470 as an eleventh insulating film is arranged so that the upper portion of the drain diffusion layer 2725 is exposed, and the memory cell in the direction intersecting the control gate line is arranged. An Al wiring (fourth wiring layer) 2840 serving as a bit line for commonly connecting the drain diffusion layer 2725 is provided.
Note that the impurity concentration distribution of the diffusion layer 2720 is not uniform, for example, by introducing impurities into the island-shaped semiconductor layer 2110 and performing thermal diffusion treatment, thereby proceeding from the surface of the island-shaped semiconductor layer 2110 toward the inside. It is preferable to have a distribution in which the concentration gradually decreases. As a result, the junction breakdown voltage between the diffusion layer 2720 and the island-shaped semiconductor layer 2110 is improved, and the parasitic capacitance is also reduced. Similarly, the impurity concentration distribution of the source diffusion layer 2710 preferably has such a distribution that the concentration gradually decreases from the surface of the semiconductor substrate 2100 toward the inside of the semiconductor substrate. Thereby, the junction breakdown voltage between the source diffusion layer 2710 and the semiconductor substrate 2100 is improved, and the parasitic capacitance in the first wiring layer is also reduced.
13 and 14 show an example in which the gate insulating film thickness of the selection gate transistor is equal to the gate insulating film thickness of the memory transistor.
FIGS. 15 and 16 show an example in which the interlayer insulating film 2610 is formed as a single layer film with respect to FIGS. 13 and 14.
17 and 18 are different from FIGS. 13 and 14 in that the horizontal film thickness of the control gate 2520 in the memory cell is larger than the horizontal film thickness of the floating gate 2510 in the memory cell, and the third wiring layer has a low resistance. An example is shown in which the conversion can be easily performed.
[0081]
FIGS. 19 and 20 show an example in which the surface of the silicon oxide film 2460 which is the tenth insulating film is located outside the periphery of the island-shaped semiconductor layer 2110 with respect to FIGS.
FIG. 21 and FIG. 22 show an example in which the gate of the selection gate transistor is not formed by one deposition of the conductive film but formed by a plurality of times, for example, two depositions of the conductive film, as compared with FIGS. Indicates.
FIG. 23 and FIG. 24 show an example in which the materials of the control gate 2520 and the floating gate 2510 of the memory cell are different from those of FIG. 13 and FIG.
FIG. 25 and FIG. 26 show an example in which the size of the outer periphery of the control gate 2520 of the memory cell and the size of the outer periphery of the gate 2500 of the selection gate transistor are different from those of FIGS.
27 and 28 show an example in which the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor.
29 and 30 are different from FIGS. 27 and 28 in that the surface of the silicon oxide film 2460 as the tenth insulating film and the surface of the silicon oxide film 2491 as the eighteenth insulating film are larger than the periphery of the island-shaped semiconductor layer 2110. An example in the case of being located outside is shown.
31 and 32 show an example in which the diffusion layer 2720 is not disposed between the transistors.
In FIGS. 33 and 34, the diffusion layer 2720 is not disposed, and a polycrystalline silicon film 2530 which is a third electrode disposed between the gate electrodes 2500, 2510 and 2520 of the memory transistor and the selection gate transistor is formed. An example when formed is shown.
FIG. 35 and FIG. 36 show an example in which the positions of the bottom and top of the polycrystalline silicon film 2530 which is the third electrode are different from the positions of the top of the gate 2500 of the selection gate transistor, respectively. Show. In FIG. 1, the polycrystalline silicon film 2530 which is the third electrode is omitted because it is complicated.
[0082]
37 and 38, the source diffusion layer 2710 is arranged so that the semiconductor substrate 2100 and the island-like semiconductor layer 2110 are connected, and the diffusion layer 2720 is arranged so that the active regions of adjacent transistors are connected. , A semiconductor substrate 2100 having a PN junction or an island shape composed of the source diffusion layer 2710 and the semiconductor substrate or island-shaped semiconductor layer 2110 due to a potential difference between the potential of the source diffusion layer 2710 given at the time of reading or erasing and the potential given to the semiconductor substrate 2100 Due to the depletion layer formed on the semiconductor layer 2110 side, the island-shaped semiconductor layer 2110 and the semiconductor substrate 2100 are in an electrically floating state, and a potential difference due to the potential of the diffusion layer 2720 and the potential applied to the island-shaped semiconductor layer 2110 Consists of a diffusion layer 2720 and an island-shaped semiconductor layer 2110 Shows an example of a case where the active region of the adjacent transistor by a depletion layer formed in the island-like semiconductor layer 2110 side of the PN junction is electrically isolated.
39 and 40 show an example in which the island-like semiconductor layer 2110 is floated by the source diffusion layer 2710, but the active region of each memory cell is not electrically isolated by the diffusion layer 2720. ing.
In addition, cross-sectional views of a semiconductor memory device having a stacked insulating film as a charge storage layer are shown in FIGS. 41 to 52, odd-numbered drawings are cross-sectional views taken along line AA ′ in FIG. 10 which is a plan view showing a memory cell array having a MONOS structure, and even-numbered drawings are cross-sectional views taken along line BB ′ in FIG. It is. These embodiments are the same except that the charge storage layer in FIGS. 13 to 40 is changed from a floating gate to a laminated insulating film.
43 and 44 show the case where the film thickness of the stacked insulating film is larger than the gate film thickness of the selection gate transistor, as compared with FIGS.
45 and 46 show the case where the thickness of the stacked insulating film is thinner than the gate thickness of the selection gate transistor, as compared with FIGS.
[0083]
Furthermore, cross-sectional views of a semiconductor memory device having a MIS capacitor as a charge storage layer are shown in FIGS. 53 to 58, the odd-numbered drawings are cross-sectional views taken along the line AA 'of FIG. 11 which is a plan view showing the memory cell array of the DRAM, and the even-numbered drawings are cross-sectional views taken along the line BB' of FIG. is there. In these embodiments, the charge storage layer is changed from the floating gate to the MIS capacitor with respect to FIGS. 13 to 40, the arrangement of the diffusion layer is located on the side of the memory capacitor, and the bit line which is the fourth wiring And the first wiring source line is the same except that they are arranged in parallel.
In addition, cross-sectional views of a semiconductor memory device having a MIS transistor as a charge storage layer are shown in FIGS. 59 to 62 are sectional views taken along lines J1-J1 ′, J2-J2 ′, K1-K1 ′, and K2-K2 ′ in FIG. 12, which are plan views showing the SRAM memory cell array, respectively.
[0084]
In this embodiment, a plurality of columnar island-like semiconductor layers 3110 are arranged in a matrix on a p-type silicon substrate 3100, and as shown in FIGS. 59 and 61, the upper and lower portions of each of these island-like semiconductor layers 3110 are arranged. In this structure, two MIS transistors are arranged, and each transistor is connected in series along the island-shaped semiconductor layer. In other words, the memory gate 3511 is disposed on the side wall of the island-shaped semiconductor layer via the gate insulating film 3431 so as to surround the island-shaped semiconductor layer 3110, and the periphery of the island-shaped semiconductor layer 3110 is surrounded above the memory gate transistor. As described above, the third electrode 3514 serving as a control gate is disposed on the island-shaped semiconductor layer side wall via the gate insulating film 3434. As shown in FIG. 61, the control gate 3514 is continuously arranged for a plurality of transistors in one direction and serves as a control gate line which is a third wiring.
[0085]
Further, as shown in FIGS. 59 and 61, the first common transistor electrically disposed on the lower surface of the semiconductor substrate surface so that the active region of the transistor is in a floating state with respect to the semiconductor substrate. The impurity diffusion layer 3710 is disposed, and the impurity diffusion layer 3721 is disposed in the island-shaped semiconductor layer 3110 so that the active region of each transistor is in a floating state. Further, an impurity diffusion layer 3724 for each memory cell is disposed on the upper surface of each island-like semiconductor layer 3110. Thus, each transistor is connected in series along the island-shaped semiconductor layer 3110.
[0086]
Further, as shown in FIGS. 59 and 61, a fourth wiring layer 3840 serving as a bit line connecting the second impurity diffusion layer 3724 of the memory cell in the direction intersecting with the control gate line is provided. Here, in the embodiment of the present invention, a memory cell is constituted by four transistors and two high resistance elements each constituted by a pair of island-like semiconductor layers. As shown in FIGS. When the second impurity diffusion layer 3721 arranged in the island-shaped semiconductor layer opposite to the first conductive film 3511 is connected to each other through the second conductive film 3512 and the third conductive film 3513 Composed.
[0087]
As shown in FIGS. 60 and 62, the third conductive film 3513 connected to the second impurity diffusion layer 3721 disposed in each island-like semiconductor layer 3110 is an impurity diffusion that becomes a high resistance element. Each of the second wiring layers 3120 is connected to a fifth wiring which is an electrically common electrode. A first impurity diffusion layer 3710 that is electrically common to memory cells adjacent in the direction of the fourth wiring layer 3840 is an isolation insulating film, for example, a silicon oxide film 3471 that is an eleventh insulating film. It is divided.
[0088]
Between the memory cells and the wirings arranged in this way, for example, an oxide film 3420 as a third insulating film is arranged and insulated from each other. In the embodiment of the present invention, the memory cell is constituted by four transistors and two high-resistance elements formed on the side wall of the p-type island-shaped semiconductor layer. However, a transistor formed on an n-type semiconductor instead of the high-resistance element may be used. Well, the structure is not limited to this as long as it can have a desired function. Note that the fifth wiring layer 3850 is omitted in FIG.
[0089]
Embodiments of memory cell array operating principle
The semiconductor memory device described above has a memory function depending on the state of charges stored in the charge storage layer. In the following, for example, a memory cell having a floating gate as a charge storage layer will be described as an example of the operation principle for reading, writing, and erasing.
As an example of the array structure of the semiconductor memory device of the present invention, a transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are included as selection gate transistors. A plurality of memory cells each having a charge storage layer and a third electrode as a control gate electrode, for example, L (L is a positive integer), and an island-like semiconductor layer connected in series. In the case where a plurality of semiconductor layers, for example, M × N (M and N are positive integers) are provided, and in this memory cell array, a plurality of, eg, M, fourth wirings arranged in parallel to the semiconductor substrate are provided. Connected to one end of each of the island-like semiconductor layers, the first end is connected to the other end, and is arranged in a direction parallel to the semiconductor substrate and intersecting the fourth end. Multiple examples For example, when N × L third wirings are connected to the third electrode of the memory cell, the reading method, the writing method, and the erasing when the first wiring is arranged in parallel with the third wiring An example of each method will be described.
[0090]
FIG. 63 shows an equivalent circuit of the memory cell array structure. The definition of memory cell writing will be described, for example, when the threshold value of the memory cell is 0.5 V or higher, and the definition of erasing is, for example, the threshold value of the memory cell is −0.5 V or lower.
First, as an example of the reading method, FIG. 76 shows an example of the timing of the potential applied to each electrode in reading. First wiring (1-1 to 1-N), second wiring (2-1 to 2-N), third wiring (3-1-1 to 3-NL), fourth wiring For example, 3V is applied to the fourth wiring (4-i) from the state where, for example, 0V is applied to each of the (4-1 to 4-M) and the fifth wiring (5-1 to 5-N), After that, for example, 3V is applied to the second wiring (2-j), 3V is applied to the fifth wiring (5-j), and then the third wiring other than the third wiring (3-jh) is applied. For example, 3V is applied to the wiring (≠ 3-jh) of the first wiring (4-i) or the current flowing through the first wiring (1-j) by applying 3V to “0”, “1”. Determine. Thereafter, the third wiring (≠ 3-jh) other than the third wiring (3-jh) is returned to, for example, 0 V, and the second wiring (≠ 2-j) and the fifth wiring (≠ 5- j) is returned to 0V, for example, and the fourth wiring (4-i) is returned to 0V, for example. At this time, the timing of applying a potential to each wiring may be before or after. In the above description, the reading method in the case where the memory cell having the third wiring (3-jh) as the gate electrode is the selected cell has been described. However, the third wiring other than the third wiring (3-jh) has been described. A reading method in the case where a memory cell having one of the wirings as a gate electrode is a selected cell is similarly performed.
The third wiring (3-j-L) to the third wiring (3-j-1) may be read continuously, or the order may be reversed or random. Further, a plurality of or all of the memory cells connected to the third wiring (3-j-h) may be read simultaneously.
As described above, M × N island-like semiconductor layers having a plurality of (for example, L) memory cells arranged in series and select gate transistors formed so as to sandwich the memory cells arranged in series are arranged, An example of the read operation principle in the case where the first wiring and the third wiring are arranged in parallel has been described. However, by arranging the selection gates above and below the plurality of memory cell portions in this way, the memory When the cell transistor is over-erased, that is, when the threshold value is negative, the non-selected cell prevents a phenomenon in which a cell current flows at a read gate voltage of 0 V, for example.
As an example of the writing method, FIG. 77 shows an example of the timing of the potential applied to each electrode in writing. First, first wiring (1-1 to 1-N), second wiring (2-1 to 2-N), third wiring (3-1-1 to 3-NL), fourth wiring (4-1 to 4-M) and fifth wiring (5-1 to 5-N)), for example, from the state where 0 V is applied, the fourth wiring other than the fourth wiring (4-i) For example, 3V is applied to the wiring (≠ 4-i), and then, for example, 1V is applied to the fifth wiring (5-j), and then the third wiring other than the third wiring (3-jh). For example, 3V is applied to (.noteq.3-jh), and then, for example, 20V is applied to the third wiring (3-jh), and this state is maintained for a desired time, so that the channel portion of the selected cell and the control gate are connected. A state in which a high potential is applied only is created, and electrons are injected from the channel portion into the charge storage layer by the FN tunneling phenomenon. A selection gate including a fifth electrode in an island-like semiconductor layer that does not include a selection cell by applying, for example, 3 V to the fourth wiring (≠ 4-i) except the fourth wiring (4-i). • The transistor is cut off and writing is not performed. After that, for example, the third wiring (3-jh) is returned to, for example, 0V, and then the second wiring (2-j) and the fifth wiring (5-j) are returned to, for example, 0V. The third wiring (≠ 3-jh) other than the third wiring (3-jh) is returned to 0V, for example, and then the fourth wiring (4-i) is returned to 0V, for example. At this time, the timing of applying a potential to each wiring may be before or after. The potential to be applied may be any combination of potentials as long as the condition for accumulating a certain amount or more of negative charges in the charge accumulation layer of a desired cell is satisfied. In the above description, the writing method when the memory cell having the third wiring (3-jh) as the gate electrode is the selected cell has been described, but the third wiring other than the third wiring (3-jh) The writing method in the case where the memory cell having one gate electrode as the selected cell is also performed similarly. Further, writing may be continuously performed from the third wiring (3-j-L) to the third wiring (3-j-1), and the order may be reversed or random. Further, a plurality of or all of the memory cells connected to the third wiring (3-j-h) may be written simultaneously.
[0091]
FIG. 82 shows an example of the timing of the potential applied to each electrode as a case where writing is performed without cutting off the selection gate transistor including the fifth electrode in the island-shaped semiconductor layer not including the selection cell. First, first wiring (1-1 to 1-N), second wiring (2-1 to 2-N), third wiring (3-1-1 to 3-NL), fourth wiring A fourth wiring other than the fourth wiring (4-i) from a state where, for example, 0 V is applied to each of the (4-1 to 4-M) and the fifth wiring (5-1 to 5-N). For example, 7V is applied to (≠ 4-i), and then, for example, 20V is applied to the fifth wiring (5-j). Thereafter, the third wiring (3-jh) other than the third wiring (3-jh) ( ≠ 3-jh), for example, 3V is applied, and then, for example, 20V is applied to the third wiring (3-jh), and this state is maintained for a desired time, so that the channel portion of the selected cell and the control gate are maintained. A potential difference of about 20 V is generated, and writing is performed by injecting electrons from the channel portion to the charge storage layer due to the FN tunneling phenomenon.
Note that a potential difference of about 13 V occurs between the channel portion of the non-selected cell connected to the third wiring (3-jh) and the control gate. However, the threshold value of this cell is changed within the write time of the selected cell. Insufficient electron injection is performed, and thus writing of this cell is not realized.
After that, for example, the third wiring (3-jh) is returned to, for example, 0V, and then the fifth wiring (5-j) is returned to, for example, 0V, and then other than the third wiring (3-jh). A third wiring (≠ 3-jh) is returned to, for example, 0V, and then the fourth wiring (≠ 4-i) is returned to, for example, 0V. At this time, the timing of applying a potential to each wiring may be before or after. The potential to be applied may be any combination of potentials as long as the condition for accumulating a certain amount or more of negative charges in the charge accumulation layer of a desired cell is satisfied. In the above description, the writing method in the case where the memory cell having the third wiring (3-jh) as the gate electrode is the selected cell has been described. However, the third wiring other than the third wiring (3-jh) has been described. A writing method in the case where a memory cell having one of the wirings as a gate electrode is a selected cell is similarly performed. Data may be written continuously from the third wiring (3-j-L) to the third wiring (3-j-1), or the order may be reversed or random. Further, a plurality of or all of the memory cells connected to the third wiring (3-j-h) may be simultaneously written. Next, as an example of the erasing method, FIG. 78 shows an example of the timing of the potential applied to each electrode in erasing. The erasing unit is performed in one block or in one chip as shown in the selection range shown in FIG.
First, the first wiring (1-1 to 1-N), the second wiring (2-j), the third wiring (3-1-1 to 3-NL), the fourth wiring (4- For example, 20V is applied to the fourth wiring (4-1 to 4-M) from the state in which 0V is applied to each of the first wiring 4-M) and the fifth wiring (5-j), for example. For example, 20V is applied to the wiring (1-j), and then 20V is applied to the second wiring (2-j), and 20V is applied to the fifth wiring (5-j). By holding for a desired time, electrons in the charge storage layer of the selected cell are extracted and erased by the FN tunneling phenomenon.
Thereafter, the second wiring (2-j) and the fifth wiring (5-j) are returned to, for example, 0V, and then the fourth wiring (4-1 to 4-M) is returned to, for example, 0V. For example, the first wiring (1-j) is returned to 0V. At this time, the timing of applying a potential to each wiring may be before or after. Further, the potential to be applied may be any combination of potentials as long as the condition for lowering the threshold value of a desired cell is satisfied. In the above description, the erase method when the memory cell having the third wiring (3-j-1 to 3-jL) as the gate electrode is used as the selected cell has been described. However, the third wiring (3-j-1 The same erasing method is performed when a memory cell having one of the third wirings other than (.about.3-jL) as a gate electrode is selected.
[0092]
All the memory cells connected to the third wiring (3-j-1 to 3-jL) may be erased simultaneously, or the third wiring (3-1-1 to 3-NL) A plurality of or all of the connected memory cells may be erased simultaneously.
As an example of the array structure of the semiconductor memory device of the present invention, an island-shaped semiconductor layer having two memory cells each having a charge storage layer and a third electrode as a control gate electrode connected in series is provided. In the case where a plurality of layers, for example, M × N (M and N are positive integers) are provided, and in this memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate Connected to one end of each of the island-like semiconductor layers, the first end is connected to the other end, and is arranged in a direction parallel to the semiconductor substrate and intersecting the fourth end. A plurality of, for example, N × 2 third wirings connected to the third electrode of the memory cell, and a reading method when the first wiring is arranged in parallel with the third wiring; An example of a writing method and an erasing method will be described respectively.
FIG. 64 shows an equivalent circuit of the memory cell array structure. The definition of memory cell writing will be described, for example, when the threshold value of the memory cell is 4 V or more, and the definition of erasing is, for example, the threshold value of the memory cell is 0.5 V or more and 3 V or less.
First, as an example of the reading method, FIG. 79 shows an example of the timing of the potential applied to each electrode in reading. First, first wiring (1-1 to 1-N), third wiring (3-j-1, 3-j-2), third wiring (≠ 3-j-1, ≠ 3-j -2) For example, 1V is applied to the fourth wiring (4-i) from the state where 0V is applied to each of the fourth wirings (4-1 to 4-M), and then the third wiring For example, by applying 5V to (3-j-2), the current flowing through the fourth wiring (4-i) or the first wiring (1-j) (j is a positive integer of 1 ≦ j ≦ N) "0" and "1" are determined by the current flowing through Thereafter, the third wiring (3-j-2) is returned to, for example, 0V, and then the fourth wiring (4-i) is returned to, for example, 0V. At this time, the timing of applying a potential to each wiring may be before or after. In the above description, the reading method in the case where the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell has been described, but the reading method other than the third wiring (3-j-1) is described. The reading method when a memory cell having one of the three wirings as a gate electrode is a selected cell is similarly performed. The third wiring (3-j-2) to the third wiring (3-j-1) may be read continuously, or the order may be reversed or random. A plurality or all of the memory cells connected to the third wiring (3-j-1) may be read simultaneously.
Subsequently, as an example of the writing method, FIG. 80 shows an example of the timing of the potential applied to each electrode in writing. First, each of the first wiring (1-1 to 1-N), the third wiring (3-1-1 to 3-N-2), and the fourth wiring (4-1 to 4-M) For example, from the state where 0 V is applied, the fourth wiring (≠ 4-i) other than the fourth wiring (4-i) is opened, and then the fourth wiring (4-i) is connected to, for example, 6 V Then, for example, 6V is applied to the third wiring (3-j-2), and then, for example, 12V is applied to the third wiring (3-j-1), and this state is maintained for a desired time. As a result, channel hot electrons are generated near the high potential side diffusion layer of the selected cell, and electrons generated in the charge storage layer of the selected cell by the high potential applied to the third wiring (3-j-1) Inject and write.
After that, for example, the third wiring (3-j-1) is returned to, for example, 0V, then the third wiring (3-j-2) is returned to, for example, 0V, and then the fourth wiring (4-i ) Is returned to, for example, 0V, and then the fourth wiring (≠ 4-i) is returned to, for example, 0V. At this time, the timing of applying the potential to each wiring may be before or after. The potential applied may be any combination of potentials as long as the condition for accumulating a certain amount or more of negative charges in the charge accumulation layer of a desired cell is satisfied. In the above description, the writing method when the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell has been described. The writing method in the case where a memory cell having one of the three wirings as a gate electrode is a selected cell is similarly performed. Writing may be performed in the order of the third wiring (3-j-2) and the third wiring (3-j-1), or the order may be reversed. A plurality of or all of the memory cells connected to the third wiring (3-j-1) may be written simultaneously.
As an example of the erasing method, FIG. 81 shows an example of the timing of the potential applied to each electrode in erasing. The erase unit is a block unit, one word line or only the upper stage or the lower stage in the block.
[0093]
First, each of the first wiring (1-1 to 1-N), the third wiring (3-1-1 to 3-N-2), and the fourth wiring (4-1 to 4-M) For example, from the state where 0 V is applied, the fourth wiring (4-1 to 4-M) is opened, and then, for example, 5 V is applied to the first wiring (1-j), and then the third wiring For example, 5V is applied to (3-j-2), and then, for example, -10V is applied to the third wiring (3-j-1), and this state is maintained for a desired time, thereby accumulating charge in the selected cell. The electrons in the layer are extracted and erased by the FN tunneling phenomenon. After that, the third wiring (3-j-1) is returned to, for example, 0V and then the third wiring (3-j-2) is returned to, for example, 0V, and then the first wiring (1-j) Is returned to 0V, for example, and then the fourth wiring (4-1 to 4-M) is returned to 0V. At this time, the timing of applying a potential to each wiring may be before or after. The potential to be applied may be any combination of potentials as long as the condition for lowering the threshold value of a desired cell is satisfied. In the above description, the erasing method when the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell has been described. However, the third wiring (3-j-1) other than the third wiring (3-j-1) has been described. The same erasing method is performed when a memory cell having one of the three wirings as a gate electrode is a selected cell. A plurality of or all of the memory cells connected to the third wiring (3-j-1 to 3-j-2) may be erased simultaneously, or the third wiring (3-1-1 to 3-3) may be simultaneously performed. -N-2) may be performed simultaneously to erase a plurality of or all of the memory cells.
As described above, for reading, writing, and erasing, a plurality of serially arranged memory cells formed of a P-type semiconductor and an island-shaped semiconductor layer having a selection transistor formed so as to sandwich the serially arranged memory cells, or An island-shaped semiconductor layer having two memory cells arranged in series formed of p-type semiconductors is arranged in M × N (M and N are positive integers), and the first wiring and the third wiring are Although an example of the operation principle in the case where the electrodes are arranged in parallel has been described, the polarities of all the electrodes may be switched as in the case of an island-shaped semiconductor layer formed of an N-type semiconductor, for example. At this time, the magnitude relation of the potential is opposite to that described above. In the above-described operation examples of reading, writing, and erasing, the case where the first wiring is arranged in parallel with the third wiring has been described, but the case where the first wiring is arranged in parallel with the fourth wiring and Even when one wiring is shared by the entire array, it can be operated by applying a potential corresponding to each wiring. When the first wiring is arranged in parallel with the fourth wiring, erasing can be performed in block units or bit line units.
Other than the memory cell having the floating gate as the charge storage layer as described above will be described.
[0094]
66 and 67 are equivalent circuit diagrams showing a part of the memory cell array having the MONOS structure shown in FIGS. 10 and 41 to 50.
66 shows an equivalent circuit diagram of a memory cell array having a MONOS structure arranged in one island-like semiconductor layer 2110. FIG. 67 shows an equivalent circuit in the case where a plurality of island-like semiconductor layers 2110 are arranged.
Hereinafter, an equivalent circuit shown in FIG. 66 will be described.
A transistor having a twelfth electrode 12 as a gate electrode and a transistor having a fifteenth electrode 15 as a gate electrode are selected gate transistors, and a stacked insulating film is provided as a charge storage layer between the selection gate transistors. , A plurality of memory cells, for example L, connected in series, each having a thirteenth electrode 13-h (h is a positive integer 1 ≦ h ≦ L, L is a positive integer) as a control gate electrode In the semiconductor semiconductor layer 2110, the fourteenth electrode 14 is connected to one end of each of the island-shaped semiconductor layers 2110, and the eleventh electrode 11 is connected to the other end.
Next, the equivalent circuit shown in FIG. 67 will be described. In this equivalent circuit, in a memory cell array in which a plurality of island-like semiconductor layers 2110 are arranged, connection relations between electrodes of respective circuit elements arranged in the island-like semiconductor layers 2110 shown in FIG. 66 and respective wirings are shown.
When there are a plurality of island-shaped semiconductor layers 2110, for example, M × N (M and N are positive integers, i is a positive integer 1 ≦ i ≦ M, and j is a positive integer 1 ≦ j ≦ N). In this memory cell array, a plurality of, for example, M, 14th wirings arranged in parallel to the semiconductor substrate are connected to the 14th electrode 14 provided in each island-like semiconductor layer 2110, respectively. Further, a plurality of, for example, N × L thirteenth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourteenth wirings 14 are the above-described thirteenth electrodes (13− h) (h is a positive integer 1 ≦ h ≦ L). A plurality of, for example, N eleventh wirings arranged in a direction crossing the fourteenth wiring are connected to the eleventh electrode 11 provided in each island-like semiconductor layer 2110, and the eleventh wiring is Arranged in parallel with the thirteenth wiring. A plurality of, for example, N twelfth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourteenth wiring 14 are connected to the above-described twelfth electrode 12 of each memory cell, and the like A plurality of, for example, N fifteenth wirings arranged in a direction crossing the fourteenth wirings 14 in parallel with the semiconductor substrate are connected to the fifteenth electrode 15 of each memory cell.
68 and 69 are equivalent circuit diagrams showing a part of the memory cell array having the DRAM structure shown in FIGS. 11, 57, and 58. 68 shows an equivalent circuit diagram of a memory cell array having a DRAM structure arranged in one island-like semiconductor layer 2110, and FIG. 69 shows an equivalent circuit when a plurality of island-like semiconductor layers 2110 are arranged.
The equivalent circuit shown in FIG. 68 will be described below.
One memory cell is formed by connecting one transistor and one MIS capacitor in series. A 23rd electrode 23 is connected to one end of the memory cell, a 21st electrode 21 is connected to the other end, and a memory cell having a 22nd electrode 22 as a gate electrode is provided. For example, two sets are connected as shown in FIG. 68, and two 21st electrodes (21-1), (21-2) and two 22nd electrodes (22-1) are connected from one island-like semiconductor layer 2110. ) And (22-2), and the 23rd electrode 23 is provided at one end of the island-shaped semiconductor layer 2110.
Next, the equivalent circuit shown in FIG. 69 will be described. In this equivalent circuit, in a memory cell array in which a plurality of island-like semiconductor layers 2110 are arranged, a connection relation between electrodes of circuit elements arranged in the island-like semiconductor layers 2110 shown in FIG.
When there are a plurality of island-shaped semiconductor layers 2110, for example, M × N (M and N are positive integers, i is a positive integer 1 ≦ i ≦ M, and j is a positive integer 1 ≦ j ≦ N). In this memory cell array, a plurality of, for example, M, twenty-third wirings arranged in parallel to the semiconductor substrate are connected to the twenty-third electrode 23 provided in each island-like semiconductor layer 2110, respectively. Further, a plurality of, for example, 2 × N, twenty-second wirings arranged in a direction parallel to the semiconductor substrate and intersecting the twenty-third wiring 23 are the above-described twenty-second electrodes (22−) of each memory cell. Connect to 1) and (22-2). A plurality of, for example, 2 × N twenty-first wirings arranged in a direction crossing the twenty-third wiring are connected to the above-described twenty-first electrodes (21-1) and (21-2) of each memory cell. To do.
68 and 69 show an example in which two memory cells are arranged in one island-like semiconductor layer 2110, but the number of memory cells arranged in one island-like semiconductor layer 2110 is three or more. However, only one set may be used.
The equivalent circuit shown in FIGS. 68 and 69 is an example in which a MIS capacitor, a transistor, a MIS capacitor, and a transistor are arranged in order from the bottom of the island-shaped semiconductor layer 2110. An example of another arrangement is an island-shaped semiconductor. A case where a transistor, a MIS capacitor, a MIS capacitor, and a transistor are arranged in order from the bottom of the layer 2110 will be described below.
[0095]
70 and 71 are equivalent circuit diagrams showing a part of the memory cell array having the DRAM structure shown in FIGS. 11 and 53 to 56. 70 shows an equivalent circuit diagram of a memory cell array having a DRAM structure arranged in one island-like semiconductor layer 2110, and FIG. 71 shows an equivalent circuit when a plurality of island-like semiconductor layers 2110 are arranged.
Hereinafter, the equivalent circuit shown in FIG. 70 will be described.
As in the previous example, the memory cell is configured by connecting one transistor and one MIS capacitor in series to form one memory cell, and a 23rd electrode 23 is formed at one end of the memory cell. The 21st electrode 21 is connected to the other end, and the 22nd electrode 22 is connected as a gate electrode. For example, two sets of this memory cell are connected as shown in FIG. 70, and two 21st electrodes (21-1), (21-2) and two 22nd electrodes are connected from one island-like semiconductor layer 2110. Electrodes (22-1) and (22-2) are provided, respectively, the 23rd electrode 23 is provided at one end of the island-shaped semiconductor layer 2110, and the 24th electrode 24 is provided at the other end. It is done.
Next, the equivalent circuit shown in FIG. 71 will be described. In this equivalent circuit, in a memory cell array in which a plurality of island-like semiconductor layers 2110 are arranged, connection relations between electrodes of respective circuit elements arranged in the island-like semiconductor layers 2110 shown in FIG. 70 and respective wirings are shown.
When there are a plurality of island-shaped semiconductor layers 2110, for example, M × N (M and N are positive integers, i is a positive integer 1 ≦ i ≦ M, and j is a positive integer 1 ≦ j ≦ N). In this memory cell array, a plurality of, for example, M, twenty-third wirings arranged in parallel to the semiconductor substrate are connected to the twenty-third electrode 23 provided in each island-like semiconductor layer 2110, respectively. Similarly, a plurality of, for example, M, twenty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the above-described twenty-fourth electrode 24 provided in each island-like semiconductor layer 2110. Further, a plurality of, for example, 2 × N twenty-second wirings arranged in a direction parallel to the semiconductor substrate and intersecting the twenty-third wiring 23 and the twenty-fourth wiring 24 are the above-mentioned second wirings of each memory cell. 22 electrodes (22-1) and (22-2) are connected. Similarly, a plurality of, for example, 2 × N twenty-first wirings arranged in a direction crossing the twenty-third wiring 23 and the twenty-fourth wiring 24 are the above-mentioned twenty-first electrodes (21 -1) Connect to (21-2).
72 and 73 are equivalent circuits of the semiconductor device shown in FIGS. 33 to 36, 51 and 52. A diffusion layer 2720 is not disposed between the transistors, and the memory transistor and the selection gate transistor are not provided. FIG. 15 is an equivalent circuit diagram showing a part of a memory cell array in the case where a polycrystalline silicon film 2530 which is a third conductive film disposed between 2500, 2510 and 2520 which are gate electrodes is formed.
In FIG. 72, as a structure disposed on one island-like semiconductor layer 2110, a polycrystalline silicon film 2530 which is a third conductive film disposed between the gate electrodes of each memory transistor and select gate transistor is formed. FIG. 73 shows an equivalent circuit when a plurality of island-like semiconductor layers 2110 are arranged.
The equivalent circuit shown in FIG. 72 will be described below.
A transistor having a thirty-second electrode 32 as a gate electrode and a transistor having a thirty-fifth electrode 35 as a gate electrode are selected gate transistors, and a charge storage layer is provided between the select gate transistors to serve as a control gate electrode. A plurality of, for example, L memory cells including the 33rd electrode (33-h) (h is a positive integer of 1 ≦ h ≦ L and L is a positive integer) are arranged in series and between the transistors. In the island-shaped semiconductor layer 2110 in which the transistor including the 36th electrode as the gate electrode is arranged, the 34th electrode 34 is connected to one end of each of the island-shaped semiconductor layers 2110, and the other end is Thirty-one electrodes 31 are connected, and a plurality of 36 electrodes are all connected together. The thirty-sixth electrode 36 is provided in the island-shaped semiconductor layer 2110.
Next, the equivalent circuit shown in FIG. 73 will be described. This equivalent circuit shows a connection relationship between electrodes of respective circuit elements and wirings arranged in each island-shaped semiconductor layer 2110 shown in FIG. 72 in a memory cell array in which a plurality of island-shaped semiconductor layers 2110 are arranged.
[0096]
When there are a plurality of island-shaped semiconductor layers 2110, for example, M × N (M and N are positive integers, i is a positive integer 1 ≦ i ≦ M, and j is a positive integer 1 ≦ j ≦ N). In the memory cell array, a plurality of, for example, M thirty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the thirty-fourth electrode 34 provided in each island-shaped semiconductor layer 2110, respectively. Further, a plurality of, for example, N × L thirty-third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are the above-described thirty-third electrodes (33−) of each memory cell. Connect to h). A plurality of, for example, N thirty-one wirings arranged in a direction crossing the thirty-fourth wiring are connected to the thirty-first electrode 31 provided in each island-shaped semiconductor layer 2110, and the thirty-first wiring is Arranged in parallel with the 33rd wiring. A plurality of, for example, N thirty-second wirings arranged parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are connected to the above-described thirty-second electrode 32 of each memory cell, and similarly A plurality of, for example, N thirty-fifth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are connected to the above-described thirty-fifth electrode of each memory cell. The thirty-sixth electrodes 36 included in each island-shaped semiconductor layer 2110 are all connected to one by a thirty-sixth wiring.
Note that the above-described thirty-sixth electrodes 36 included in each island-shaped semiconductor layer 2110 do not have to be connected to one by a thirty-sixth wiring, and the memory cell array is divided into two or more by the thirty-sixth wiring. You may connect. That is, the 36th electrode may be connected to each block, for example.
74 and 75 are equivalent circuit diagrams showing a part of the SRAM-structured memory cell array shown in FIGS. 12 and 59 to 62, and show an example in which the transistors constituting the memory cells are composed only of NMOS. Yes.
74 shows an equivalent circuit diagram of one SRAM structure memory cell arranged in two adjacent island-like semiconductor layers 2110, and FIG. 75 shows an equivalent circuit when a plurality of memory cells are arranged. .
Hereinafter, the equivalent circuit shown in FIG. 74 will be described.
As shown in FIG. 74, two island-shaped semiconductor layers 2110 in which transistors each having a 43rd electrode and a 45th electrode as gate electrodes are arranged in series are adjacent to each other. Connect to each other. That is, the 46th electrode (46-2) and the 45th electrode (45-1) of the transistor having the 43rd electrode (43-2) as the gate electrode are connected, and the 43rd electrode (43-1) The 46th electrode (46-1) and 45th electrode (45-2) of the transistor having the gate electrode connected to each other are connected. In addition, in the two adjacent island-like semiconductor layers 2110, the 44th electrode (44-1) is connected to one end of one island-like semiconductor layer 2110, and one of the other island-like semiconductor layers 2110 is connected. The 44th electrode (44-2) is connected to the end of the. In the two island-like semiconductor layers 2110, the 41st electrode 41 is connected as a common electrode to the other end portion to which the 44th electrodes (44-1) and (44-2) are not connected. In addition, two high resistance elements are connected to these four transistors as shown in FIG. 74, and a forty-second electrode 42 is connected as a common electrode to the end on the side not connected to the transistor.
Next, the equivalent circuit shown in FIG. 75 will be described. In this equivalent circuit, in a memory cell array in which a plurality of island-like semiconductor layers 2110 are arranged, the connection between the electrodes of the circuit elements arranged in units of two adjacent island-like semiconductor layers 2110 shown in FIG. Show the relationship.
[0097]
A plurality of island-shaped semiconductor layers 2110, for example, 2 × M × N (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N). In this case, in the memory cell array, a plurality of, for example, 2 × M forty-fourth wirings arranged in parallel with the semiconductor substrate are provided in each island-shaped semiconductor layer 2110. ) And (44-2). A plurality of, for example, N forty-third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the forty-fourth wiring 44 are the 43rd electrodes (43-1) of each memory cell. ), (43-2). A plurality of, for example, N forty-first wirings arranged in a direction crossing the forty-fourth wiring are connected to the forty-first electrode 41 provided in each island-shaped semiconductor layer 2110. The forty-first wiring may be commonly connected to the forty-first electrode 41 provided in each island-shaped semiconductor layer 2110. The above-mentioned forty-second electrodes 42 of each high-resistance element may be all connected together by a forty-second wiring.
The transistor constituting the memory cell may be composed only of PMOS, or may be replaced with a transistor of the opposite type to the transistor having the 43rd or 45th electrode as a gate electrode instead of the above-described high resistance element. Also good.
Further, the selection gate transistor, the memory cell adjacent to the selection gate transistor and the adjacent memory cells are not connected via the impurity diffusion layer, and instead, the interval between the selection transistor, the memory cell, and the memory cell is about 30 nm or less. The operation principle of a semiconductor device having a structure very close to that of a case where a selection transistor, a memory cell, and memory cells are connected through an impurity diffusion layer will be described.
When adjacent elements are sufficiently close, the channel formed by the potential higher than the threshold applied to the gate of the select gate transistor and the control gate of the memory cell is connected to the channel of the adjacent element, and the gates of all elements are connected. When a potential higher than the threshold value is applied, the channels of all elements are connected. Since this state is almost equivalent to the case where the selection transistor and the memory cell or memory cell are connected via the impurity diffusion layer, the operation principle is also that the selection transistor and the memory cell or memory cell are connected via the impurity diffusion layer. It is the same as if
Further, the semiconductor device has a structure in which the selection gate transistor and the memory cell are not connected via the impurity diffusion layer, and a third conductive film is disposed between the selection transistor and the gate electrode of the memory cell or memory cell instead. The operation principle of is described.
The third conductive film is located between the elements and is connected to the island-shaped semiconductor layer through an insulating film, for example, a silicon oxide film. That is, the third conductive film, the insulating film, and the island-shaped semiconductor layer form a MIS capacitor. When a potential is applied to the third conductive film so that an inversion layer is formed at the interface between the island-shaped semiconductor layer and the insulating film, a channel is formed. The formed channel functions in the same way as an impurity diffusion layer connecting each element for adjacent elements. Therefore, when a potential capable of forming a channel is applied to the third conductive film, the operation is similar to that when the select gate transistor or the memory cell is connected through the impurity diffusion layer. Even when a potential capable of forming a channel is not applied to the third conductive film, for example, when the island-shaped semiconductor layer is a P-type semiconductor, and electrons are extracted from the charge storage layer, a selection gate transistor or a memory The operation is the same as when the cells are connected via the impurity diffusion layer.
[0098]
Embodiment of Memory Cell Array Manufacturing Method
An impurity diffusion layer is formed so that the active region of each memory cell formed in a semiconductor substrate or semiconductor layer processed into a columnar shape compared to the conventional example is in a floating state with respect to the semiconductor substrate. Before forming the semiconductor substrate or semiconductor layer to be formed, the region in which the charge storage layer is formed by the multi-layered laminated film is accurately defined by controlling each film thickness in the direction perpendicular to the surface of the semiconductor substrate, and then charge storage An embodiment in which a layer is formed in this region will be described.
[0099]
Production Example 1
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multilayer film composed of multiple layers, and then + epitaxial growth is performed in a hole-like groove opened by a photoresist mask. An island-shaped semiconductor layer is formed in a columnar shape, and a floating gate is formed as a tunnel oxide film and a charge storage layer on a side wall of the island-shaped semiconductor layer and in a region where the charge storage layer is formed, and the island-shaped semiconductor layer is electrically connected to the semiconductor substrate. The semiconductor device is manufactured by bringing the active region of each memory cell electrically into a floating state.
[0100]
In this semiconductor memory device, select gate transistors are disposed above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are disposed between the select gate transistors. The tunnel oxide film and the floating gate of each memory transistor are formed together, and the transistors are connected in series along the island-shaped semiconductor layer. The gate insulating film thickness of the select gate transistor is equal to the gate insulating film thickness of the memory transistor.
FIGS. 83 to 115 and FIGS. 116 to 147 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, which are plan views showing the memory cell array of the EEPROM, respectively.
First, arsenic 1 × 10 as a first insulating film is formed on the surface of the p-type silicon substrate 2100 by CVD, for example.¹⁸~ 1x10^{twenty two}/ Cm^ThreeA silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm. At this time, for the insulating film containing impurities, after the insulating film is deposited by a CVD method, the impurities may be introduced into the insulating film by using ion implantation. For example, after depositing a silicon oxide film 2411 as a first insulating film by 50 to 500 nm, arsenic 1 × 10 at an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 45 °.¹⁴~ 1x10¹⁶/ Cm²About a dose is introduced into the silicon oxide film 2411 which is the first insulating film. Further, the introduction of impurities into the silicon oxide film 2411 that is the first insulating film by ion implantation may not be performed immediately after the silicon oxide film 2411 that is the first insulating film is deposited. When an impurity is introduced into the silicon oxide film 2411 which is the first insulating film by ion implantation, the implantation inclination angle is not limited as long as a desired impurity concentration can be obtained. Further, the introduction of impurities into the silicon oxide film 2411 as the first insulating film is not limited to ion implantation, and any means such as solid phase vapor phase diffusion may be used.
Thereafter, for example, a silicon nitride film 2321 is deposited as a fourth insulating film by 10 to 100 nm. Here, when the impurity introduction into the silicon oxide film 2411 that is the first insulating film described above is performed by ion implantation, the first insulating film is formed by ion implantation through the silicon nitride film 2321 that is the fourth insulating film. Impurities may be introduced into the silicon oxide film 2411.
Subsequently, as the third insulating film, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm, and as the second insulating film, for example, a silicon nitride film 2312 is deposited by 10 to 100 nm, and the impurity which is the first insulating film is deposited. The included silicon oxide film 2412 is deposited by 50 to 500 nm, the fourth insulating film silicon nitride film 2322 is deposited by 10 to 100 nm, and the third insulating film silicon oxide film 2422 is deposited by 50 to 500 nm. 83 and 116, a silicon oxide film 2415 containing impurities as a first insulating film is deposited to a thickness of 50 to 500 nm, and a silicon nitride film 2325 as a fourth insulating film is formed. Deposit from 500 to 5000 nm.
Subsequently, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 83 and 116), the silicon nitride film 2325 as the fourth insulating film and the first insulating film are formed by, for example, reactive ion etching. A silicon oxide film 2415 as a film, a silicon nitride film 2315 as a second insulating film, a silicon oxide film 2424 as a third insulating film, a silicon nitride film 2324 as a fourth insulating film, and a first insulating film A silicon oxide film 2414, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2323 as a fourth insulating film, and silicon as a first insulating film Oxide film 2413, second insulating film silicon nitride film 2313, third insulating film silicon oxide film 2422, fourth A silicon nitride film 2322 as an edge film, a silicon oxide film 2412 as a first insulating film, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, and a fourth insulating film The silicon nitride film 2321 and the silicon oxide film 2411 as the first insulating film are sequentially etched to form a fourth groove 2240 (FIGS. 84 and 117).
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth trench 2240 (FIGS. 85 and 118), and the island-like semiconductor layer 2110 is made into a silicon nitride film 2325 as a fourth insulating film. Is flattened. At this time, etch back using isotropic etching, etch back using anisotropic etching, planarization embedding using CMP, or various combinations may be used.
[0101]
Thereafter, for example, a polycrystalline silicon film 2540 is deposited to a thickness of about 100 to 300 nm as the fourth conductive film, and a silicon nitride film 2330 is deposited to a thickness of about 200 to 2000 nm as the fifth insulating film (FIGS. 86 and 119). .
Subsequently, using the resist R2 patterned by a known photolithography technique as a mask (FIGS. 87 and 120), the silicon nitride film 2330 as the fifth insulating film and the fourth conductive film are formed by, for example, reactive ion etching. A polycrystalline silicon film 2540 as a film, a silicon nitride film 2325 as a fourth insulating film, and a silicon oxide film 2415 as a first insulating film are sequentially etched to expose a silicon nitride film 2315 as a second insulating film. Let At this time, the silicon nitride film 2315 as the second insulating film may be etched until the silicon oxide film 2424 as the third insulating film is exposed.
After removing the resist R2 (FIGS. 88 and 121), a silicon nitride film 2340 is deposited as a sixth insulating film to a thickness of about 5 to 50 nm, and silicon nitride, which is the fifth insulating film, is formed using, for example, anisotropic etching. A side wall is formed on the sidewalls of the film 2330, the polycrystalline silicon film 2540 as the fourth conductive film, the silicon nitride film 2325 as the fourth insulating film, and the silicon oxide film 2415 as the first insulating film. A silicon nitride film 2340 which is an insulating film is disposed (FIGS. 89 and 122). At this time, the silicon oxide film 2415 containing impurities as the first insulating film is replaced with the silicon nitride film 2325 as the fourth insulating film, the silicon nitride film 2315 as the second insulating film, and the silicon as the sixth insulating film. The nitride film 2340 is isolated from the parts other than the island-shaped semiconductor layer 2110.
Subsequently, using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film as a mask, the silicon nitride film 2315 as the second insulating film and the silicon oxide as the third insulating film are used. A film 2424, a silicon nitride film 2324 as a fourth insulating film, a silicon oxide film 2414 as a first insulating film, a silicon nitride film 2314 as a second insulating film, and a silicon oxide film 2423 as a third insulating film , A silicon nitride film 2323 as a fourth insulating film, a silicon oxide film 2413 as a first insulating film, a silicon nitride film 2313 as a second insulating film, a silicon oxide film 2422 as a third insulating film, The silicon nitride film 2322 as the fourth insulating film, the silicon oxide film 2412 as the first insulating film, and the silicon nitride film 2312 as the second insulating film are sequentially etched. Silicon oxide film 2421 as a third insulating film to form a third groove 2230 so as to expose Te (FIG. 90 and FIG. 123).
Next, after a silicon nitride film 2342 as a sixth insulating film is deposited to about 5 to 50 nm, a silicon oxide film 2412 containing impurities as at least a first insulating film becomes a silicon nitride film 2342 as a sixth insulating film, Silicon nitride film 2312 as the second insulating film, silicon nitride film 2312 as the fourth insulating film, and silicon nitride film as the sixth insulating film so as to be isolated from the portions other than the island-shaped semiconductor layer 2110 by the silicon nitride film 2322 as the fourth insulating film 2342 is arranged. For example, after a silicon nitride film 2342 as a sixth insulating film is deposited to a thickness of about 5 to 50 nm, it is etched back by anisotropic etching and a silicon nitride film as a sixth insulating film at the bottom of the third groove 2230. 2342 is removed to expose a silicon oxide film 2421 which is a third insulating film (FIGS. 91 and 124).
Thereafter, to a desired depth, for example, a silicon oxide film 2432 is deposited as a seventh insulating film, for example, and silicon containing an impurity as the first insulating film through a silicon nitride film 2342 as the sixth insulating film A silicon oxide film 2432 which is a seventh insulating film is embedded in the third groove 2230 so that the oxide film 2412 is embedded (FIGS. 92 and 125).
Thereafter, the exposed portion of the silicon nitride film 2342 as the sixth insulating film is removed by isotropic etching using the silicon oxide film 2432 as the seventh insulating film as a mask, and the silicon nitride film 2342 as the sixth insulating film is removed. (FIGS. 93 and 126).
Subsequently, for example, a silicon oxide film 2443 is deposited as an eighth insulating film, and the silicon oxide film 2443 that is the eighth insulating film is formed on the side of the silicon oxide film 2422 that is the third insulating film by, for example, anisotropic etching. It embeds in the 3rd groove part 2230 so that it may arrange | position to a part (FIG. 94 and FIG. 128). At this time, the depth at which the silicon oxide film 2443 as the eighth insulating film is buried is adjusted so that the side surface of the silicon oxide film 2413 containing impurities as the first insulating film is exposed.
[0102]
Next, after depositing a silicon nitride film 2343 as a sixth insulating film of about 5 to 50 nm in the same manner as described above, at least a silicon oxide film 2413 containing an impurity as a first insulating film is a silicon that is a sixth insulating film. In the sixth insulating film, the nitride film 2343, the silicon nitride film 2313 that is the second insulating film, and the silicon nitride film 2323 that is the fourth insulating film are isolated from the parts other than the island-shaped semiconductor layer 2110. A silicon nitride film 2343 is disposed. Thereafter, in the same manner as described above, for example, a silicon oxide film 2444 is deposited as an eighth insulating film, and the silicon oxide film 2444 as the eighth insulating film is formed by, for example, anisotropic etching to form silicon as the third insulating film. The third groove 2230 is buried so as to be disposed on the side of the oxide film 2423 (FIGS. 95 and 128).
Further, after depositing a silicon nitride film 2344 as a sixth insulating film of about 5 to 50 nm in the same manner as described above, a silicon oxide film 2414 containing an impurity as at least a first insulating film becomes a silicon as a sixth insulating film. In the sixth insulating film, the nitride film 2344, the silicon nitride film 2314 as the second insulating film, and the silicon nitride film 2324 as the fourth insulating film are isolated from the parts other than the island-shaped semiconductor layer 2110. A silicon nitride film 2344 is disposed (FIGS. 96 and 129).
Thereafter, silicon oxide films 2442, 2443, 2444 as the eighth insulating film, silicon oxide films 2421, 2422, 2423, 2424 as the third insulating film, and silicon oxide films 2432, 2433 as the seventh insulating film. , 2434 are removed by, for example, isotropic etching to expose the side surfaces of the island-shaped semiconductor layer 2110 (FIGS. 97 and 130).
Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 of about 10 to 100 nm (FIGS. 98 and 131).
Next, the thermal oxide film 2450 that is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching (FIGS. 99 and 132).
Thereafter, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 2110 using oblique ion implantation as necessary. For example, implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the impurity introduction from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 which is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be introduced. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2421, 2422, 2423, 2424 which are the third insulating films, and the silicon oxide films 2421, 2422, 2423 which are the third insulating films. , 2424 may be removed by introducing heat into the island-shaped semiconductor layer 2110 by heat treatment or any other means may be used as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is equal.
[0103]
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film which becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 using, for example, a thermal oxidation method (FIGS. 100 and 133). . At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
Next, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 that is a fifth insulating film and silicon nitride films 2340 and 2342 that are sixth insulating films, Using polysilicon 2343 and 2344 as a mask, a polycrystalline silicon film 2510 which is a first conductive film is dividedly formed into polycrystalline silicon films 2511, 2512, 2513 and 2514 which are first conductive films by anisotropic etching, for example (FIG. 101 and FIG. 134).
Subsequently, for example, a silicon oxide film 2470 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film.
Next, the silicon oxide film 2470 as the eleventh insulating film is formed in the third groove 2230 so as to bury the polycrystalline silicon film 2511 as the first conductive film by, for example, anisotropic etching and isotropic etching. (FIGS. 102 and 135). At this time, the embedding depth of the silicon oxide film 2470 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2342 as the sixth insulating film is exposed.
Thereafter, polycrystalline silicon films 2512 to 2514 that are the first conductive film on the inner wall of the third groove 2230, and silicon nitride films 2340, 2342, 2343, and 2344 that are the sixth insulating films, and the eleventh insulating film For example, a silicon nitride film 2350, which is a twelfth insulating film, is deposited on the surface of the silicon oxide film 2470 by 5 to 50 nm (FIGS. 103 and 136), and a sidewall is formed by, for example, anisotropic etch back.
[0104]
Subsequently, the silicon oxide film 2470 as the eleventh insulating film is etched back by, for example, isotropic etching to the extent that the side portion of the polycrystalline silicon film 2511 as the first conductive film is exposed (FIG. 104 and FIG. FIG. 137).
Thereafter, for example, a polycrystalline silicon film 2521 to be a second conductive film is deposited by 15 to 150 nm (FIGS. 105 and 138).
Next, as shown in FIG. 139, the polycrystalline silicon film 2521 which is the second conductive film is etched back by, for example, anisotropic etching, and then the polycrystalline silicon film 2521 which is the second conductive film and the self-conductive film. The silicon nitride film 2321 that is the fourth insulating film, the silicon oxide film 2411 that is the first insulating film, and the p-type silicon substrate 2100 that is the semiconductor substrate are sequentially etched in order, and the p-type silicon substrate 2100 is subjected to the second etching. A second groove 2220 is formed and the impurity diffusion layer 2710 is separated. That is, the first wiring layer isolation is formed in a self-aligned manner with the second conductive film isolation (FIGS. 106 and 139).
Next, as an eleventh insulating film, for example, a silicon oxide film 2470 is deposited to a thickness of 30 to 300 nm, and then etched back by, for example, anisotropic etching to form a silicon oxide film as an eleventh insulating film in the second groove 2220. The membrane 2470 is embedded. At this time, the height of the silicon oxide film 2470 as the eleventh insulating film is adjusted so as to bury the polycrystalline silicon film 2511 as the first conductive film (FIGS. 107 and 140).
Subsequently, the polycrystalline silicon film 2521 as the second conductive film is etched back by anisotropic or isotropic etching to the extent that it can come into contact with the polycrystalline silicon film 2511 as the first conductive film. (FIGS. 108 and 141). At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer.
Thereafter, the sidewall of the silicon nitride film 2250 which is the twelfth insulating film is removed by isotropic etching (FIGS. 109 and 142), and for example, a silicon oxide film 2471 having a thickness of 50 to 500 nm is formed as the eleventh insulating film. Deposition to a degree.
Subsequently, the silicon oxide film 2471 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2521 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2471 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2342 as the sixth insulating film is exposed.
[0105]
Next, an interlayer insulating film 2612 is formed on the surfaces of the exposed polycrystalline silicon films 2512 to 2514 which are the first conductive films (FIGS. 110 and 143). The interlayer insulating film 2612 is, for example, an ONO film. Specifically, a 5-10 nm silicon oxide film, a 5-10 nm silicon nitride film, and a 5-10 nm silicon oxide film are sequentially deposited on the surface of the polycrystalline silicon film by a thermal oxidation method.
Subsequently, a polycrystalline silicon film 2522 serving as a second conductive film is similarly deposited to a thickness of 15 to 150 nm and etched back, so that an interlayer insulating film 2612 is formed on the side of the polycrystalline silicon film 2512 serving as the first conductive film. A polycrystalline silicon film 2522 which is a second conductive film is disposed via At this time, by setting the AA ′ direction in FIG. 1 below a predetermined value in advance, it is formed as a third wiring layer that becomes a control gate line continuous in that direction without using a mask process. The
Next, as an eleventh insulating film, for example, a silicon oxide film 2472 is deposited to about 50 to 500 nm. Subsequently, the silicon oxide film 2472 as the eleventh insulating film is formed in the third groove 2230 so as to bury the polycrystalline silicon film 2522 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2472 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2343 as the sixth insulating film is exposed.
Subsequently, by repeating similarly, a polycrystalline silicon film 2523 as a second conductive film is disposed on the side of the polycrystalline silicon film 2513 as a first conductive film with an interlayer insulating film 2613 interposed therebetween, and the second A polycrystalline silicon film 2523 which is a conductive film is buried with a silicon oxide film 2473 which is an eleventh insulating film. In the polycrystalline silicon film 2514 which is the uppermost first conductive film, it can be in contact with the polycrystalline silicon film 2514 which is the first conductive film, similarly to the polycrystalline silicon film 2511 which is the lowermost first conductive film. Then, the polycrystalline silicon film 2524 which is the second conductive film is etched back (FIGS. 108 to 112 and FIGS. 141 to 145).
Next, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, the silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2340 that is the sixth insulating film are, for example, isotropically etched. (FIGS. 113 and 146).
Further, a silicon oxide film 2474, which is an eleventh insulating film, is deposited on the polycrystalline silicon film 2524, which is the second conductive film, to a thickness of 100 to 500 nm, and the fourth conductive film is formed by etch back or CMP. The upper part of the polycrystalline silicon film 2540 is exposed, and the fourth wiring layer 2840 is connected to the upper part of the island-like semiconductor layer 2110 so that the direction intersects with the second or third wiring layer (FIGS. 114 and 147). 114 shows a state in which the fourth wiring layer 2840 is arranged on the polycrystalline silicon film 2540 that is the fourth conductive film without misalignment. However, even if alignment misalignment occurs, FIG. As shown at 115, the fourth wiring layer 2840 can be connected to the polycrystalline silicon film 2540 which is the fourth conductive film (the same applies to the following manufacturing examples).
Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0106]
Further, in this embodiment, a semiconductor substrate or a polycrystal such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film. The film formed on the surface of the silicon film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
Introduction of impurities into the polycrystalline silicon film 2510 or 2511 to 2514 as the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 as the second conductive film, and the polycrystalline silicon film 2540 as the fourth conductive film May be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
In the embodiment, the control gate of each memory cell is formed to be continuous in one direction without using a mask. This is possible when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the third wiring layer direction can be obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
[0107]
Production Example 2
In Manufacturing Example 1, a specific manufacturing process example in the case where the first, second, and third wiring layers are separated by a resist patterning process by photolithography will be described.
FIGS. 148 to 153 and FIGS. 154 to 159 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, which are plan views showing the memory cell array of the EEPROM, respectively.
In this manufacturing example, the isolation part of the first wiring layer is not formed in a self-aligned manner with the isolation part of the polycrystalline silicon 2521 which is the second conductive film by anisotropic etching, and is also the second conductive film. The polycrystalline silicon 2521 to 2524 need not be deposited and etched so as to be separated in the BB ′ direction in FIG.
Until the silicon oxide film 2474 as the eleventh insulating film is deposited on the upper layer of the polycrystalline silicon film 2524 as the second conductive film to a thickness of 100 to 500 nm (FIGS. 148 to 151 and FIGS. 154 to 157) 1 to FIG. 83 to FIG. 114 and FIG. 116 to FIG.
Thereafter, using the resist R4 patterned by a known photolithography technique as a mask (FIGS. 152 and 158), etching is performed by anisotropic etching until the p-type silicon substrate 2100 is reached. The polysilicon films 2521 to 2524 which are the second conductive films are separated in the BB ′ direction.
Thereafter, a silicon oxide film 2475 which is an eleventh insulating film is deposited, and the upper portion of the polycrystalline silicon film 2540 which is the fourth conductive film is exposed by an etch back or CMP method, and the fourth wiring layer 2840 is formed. It connects with the upper part of the island-like semiconductor layer 2110 so that the direction intersects with the second or third wiring layer (FIGS. 158 and 159). Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring. As a result, a semiconductor memory device having effects equivalent to those of Production Example 1 is realized.
Further, by separating the first, second, and third wiring layers by resist patterning by photolithography, for example, there is an advantage that formation is possible even when the island-shaped semiconductor layers are arranged symmetrically.
[0108]
Further, by arranging selection gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.
[0109]
In the manufacturing examples 1 and 2, the lattice island-shaped third groove 2230 is formed on the P-type semiconductor substrate. However, in the p-type impurity diffusion layer or the p-type silicon substrate formed in the n-type semiconductor substrate. A lattice island-shaped third groove 2230 may be formed in a p-type impurity layer further formed in the n-type impurity diffusion layer formed in the step. The conductivity type of each impurity diffusion layer may be a reverse conductivity type. These production examples can be applied to the following various production examples.
[0110]
Production Example 3
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then a columnar shape is formed by selective epitaxial silicon growth in a hole-like groove opened by a photoresist mask. An island-shaped semiconductor layer is formed on the side wall of the island-shaped semiconductor layer, and a floating gate is formed as a tunnel oxide film and a charge storage layer in a region where the charge storage layer is formed. In the floating state, the active regions of the memory cells are manufactured to be electrically common.
[0111]
In this semiconductor memory device, select gate transistors are disposed above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are disposed between the select gate transistors. The tunnel oxide film and the floating gate of each memory transistor are formed together, and the transistors are connected in series along the island-shaped semiconductor layer. The gate insulating film thickness of the select gate transistor is equal to the gate insulating film thickness of the memory transistor.
160 to 181 and FIGS. 182 to 203 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, which are plan views showing the memory cell array of the EEPROM, respectively.
[0112]
First, on the surface of the p-type silicon substrate 2100, an insulating film containing an impurity is formed by CVD, for example, arsenic 1 × 10 as a first insulating film.¹⁸~ 1x10^{twenty two}/ Cm²A silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm. At this time, the insulating film containing impurities may be introduced into the insulating film by ion implantation after the insulating film is deposited by a CVD method. For example, after depositing a silicon oxide film 2411 as a first insulating film by 50 to 500 nm, arsenic 1 × 10 at an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 45 °.¹⁴~ 1x10¹⁶/ Cm²About a dose is introduced into the silicon oxide film 2411 which is the first insulating film. Further, the introduction of impurities into the silicon oxide film 2411 that is the first insulating film by ion implantation may not be performed immediately after the silicon oxide film 2411 that is the first insulating film is deposited. When an impurity is introduced into the silicon oxide film 2411 which is the first insulating film by ion implantation, the implantation inclination angle is not limited as long as a desired impurity concentration is obtained. Further, the introduction of impurities into the silicon oxide film 2411 which is the first insulating film is not limited to ion implantation, and various methods such as solid phase vapor phase diffusion can be used. Thereafter, for example, a silicon nitride film 2321 is deposited as a fourth insulating film by 10 to 100 nm. Here, when the impurity introduction into the silicon oxide film 2411 which is the first insulating film described above is performed by ion implantation, the first insulating film is formed by ion implantation over the silicon nitride film 2321 which is the fourth insulating film. Impurities may be introduced into the silicon oxide film 2411.
[0113]
Subsequently, as the third insulating film, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm, and as the second insulating film, for example, a silicon nitride film 2312 is deposited by 10 to 100 nm, and silicon oxide as the first insulating film is deposited. A film 2412 is deposited to 50 to 500 nm. After sequentially forming in this way, as shown in FIGS. 160 and 182, as a first insulating film, for example, a silicon oxide film 2415 is deposited to a thickness of 50 to 500 nm, and then a silicon nitride film 2325 as a fourth insulating film is formed to 500. Deposit ~ 5000 nm.
[0114]
Next, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 160 and 182), the silicon nitride film 2325 as the fourth insulating film and the first insulating film are formed by, for example, reactive ion etching. A silicon oxide film 2415 as a film, a silicon nitride film 2315 as a second insulating film, a silicon oxide film 2424 as a third insulating film, a silicon nitride film 2314 as a second insulating film, and a third insulating film A silicon oxide film 2423, a silicon nitride film 2313 as a second insulating film, a silicon oxide film 2422 as a third insulating film, a silicon nitride film 2312 as a second insulating film, and a silicon as a third insulating film An oxide film 2421, a silicon nitride film 2321 as a fourth insulating film, and a silicon oxide film 2411 as a first insulating film are sequentially formed. And etching to form a fourth groove 2240 (FIG. 161 and FIG. 183).
[0115]
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240 (FIGS. 162 and 184).
[0116]
Further, the island-like semiconductor layer 2110 is planarized with respect to the silicon nitride film 2325 which is the fourth insulating film (FIGS. 163 and 185). At this time, etch back using isotropic etching, etch back using anisotropic etching, flattening embedding using CMP, various combinations, or any means may be used. Thereafter, for example, a polycrystalline silicon film 2540 is deposited to a thickness of about 100 to 300 nm as a fourth conductive film, and a silicon nitride film 2330 is deposited to a thickness of about 200 to 2000 nm as a fifth insulating film.
[0117]
Subsequently, using the resist R2 patterned by a known photolithography technique as a mask (FIGS. 164 and 186), the silicon nitride film 2330 as the fifth insulating film and the fourth conductive film are formed by, for example, reactive ion etching. A polycrystalline silicon film 2540 as a film, a silicon nitride film 2325 as a fourth insulating film, and a silicon oxide film 2415 as a first insulating film are sequentially etched to expose a silicon nitride film 2315 as a second insulating film. Let At this time, the silicon nitride film 2315 as the second insulating film may be etched until the silicon oxide film 2424 as the third insulating film is exposed.
[0118]
After removing the resist R2 (FIGS. 165 and 187), a silicon nitride film 2340 is deposited as a sixth insulating film to a thickness of about 5 to 50 nm, and silicon nitride, which is the fifth insulating film, is formed using, for example, anisotropic etching. A side wall is formed on the sidewalls of the film 2330, the polycrystalline silicon film 2540 as the fourth conductive film, the silicon nitride film 2325 as the fourth insulating film, and the silicon oxide film 2415 as the first insulating film. A silicon nitride film 2340 which is an insulating film is disposed (FIGS. 166 and 188). At this time, the silicon oxide film 2415 containing impurities as the first insulating film is replaced with the silicon nitride film 2325 as the fourth insulating film, the silicon nitride film 2315 as the second insulating film, and the silicon as the sixth insulating film. The nitride film 2340 is isolated from the parts other than the island-shaped semiconductor layer 2110.
[0119]
Subsequently, using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film as a mask, the silicon nitride film 2315 as the second insulating film and the silicon oxide as the third insulating film are used. A film 2424, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, and a silicon oxide film 2422 as a third insulating film Then, the third groove 2230 is exposed so that the silicon nitride film 2312 as the second insulating film and the silicon oxide film 2421 as the third insulating film are sequentially etched to expose the silicon nitride film 2321 as the fourth insulating film. (FIGS. 167 and 189).
[0120]
Thereafter, the silicon oxide films 2421, 2422, 2423, and 2424, which are third insulating films, are removed by, for example, isotropic etching, and the side surfaces of the island-shaped semiconductor layer 2110 are exposed. Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth oxide film, for example, a thermal oxide film 2450, for example, having a thickness of 10 to 100 nm (FIGS. 168 and 190).
[0121]
Next, the thermal oxide film 2450 that is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching (FIGS. 169 and 191), and oblique ion implantation is used as necessary. Then, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 2110. For example, implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation. Impurities are introduced into the silicon oxide films 2421, 2422, 2423, and 2424 that are the third insulating films, and heat treatment is performed before removing the silicon oxide films 2421, 2422, 2423, and 2424 that are the third insulating films. Impurities may be introduced into the island-shaped semiconductor layer 2110, and means are not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is equal.
[0122]
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film which becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 using, for example, a thermal oxidation method (FIGS. 170 and 192). . At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0123]
Next, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 which is a fifth insulating film and silicon nitride films 2340 and 2314 which are sixth insulating films are deposited. The polycrystalline silicon film 2510, which is the first conductive film, is dividedly formed into the polycrystalline silicon films 2511, 2512, 2513, 2514, which are the first conductive films, for example, by anisotropic etching using 2313 and 2312 as masks (FIG. 171 and FIG. 193).
[0124]
Subsequently, for example, a silicon oxide film 2470 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film. Next, the silicon oxide film 2470 as the eleventh insulating film is formed in the third groove 2230 so as to bury the polycrystalline silicon film 2511 as the first conductive film by, for example, anisotropic etching and isotropic etching. (FIGS. 172 and 194). At this time, the embedding depth of the silicon oxide film 2470 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2312 as the second insulating film is exposed. Thereafter, the polycrystalline silicon films 2512 to 2514 as the first conductive film and the silicon nitride films 2312, 2313, 2314, and 2315 as the sixth insulating film on the inner wall of the third groove 2230, the eleventh insulating film For example, a silicon nitride film 2350, which becomes a twelfth insulating film, is deposited on the surface of the silicon oxide film 2470 having a thickness of 5 to 50 nm, and a sidewall is formed by, for example, anisotropic etch back (FIGS. 173 and 195).
[0125]
Next, the silicon oxide film 2470 as the eleventh insulating film is etched back by, for example, isotropic etching to the extent that the side portion of the polycrystalline silicon film 2511 as the first conductive film is exposed (FIGS. 174 and 174). FIG. 196).
[0126]
Further, for example, a polycrystalline silicon film 2521 to be the second conductive film is deposited by 15 to 150 nm (FIGS. 175 and 197).
[0127]
Thereafter, as shown in FIG. 198, the polycrystalline silicon film 2521 which is the second conductive film is etched back by, for example, anisotropic etching, and is self-aligned with the polycrystalline silicon film 2521 which is the second conductive film. The silicon nitride film 2321 that is the first insulating film, the silicon oxide film 2411 that is the first insulating film, and the p-type silicon substrate 2100 that is the semiconductor substrate are sequentially etched, and the second groove 2220 is formed in the p-type silicon substrate 2100. The formation and impurity diffusion layer 2710 is separated. That is, the isolation part of the first wiring layer is formed in self-alignment with the isolation part of the second conductive film (FIGS. 176 and 198).
[0128]
Next, as an eleventh insulating film, for example, a silicon oxide film 2470 is deposited to a thickness of 30 to 300 nm, and then etched back by, for example, anisotropic etching to form a silicon oxide film as an eleventh insulating film in the second groove 2220. The membrane 2470 is embedded. At this time, the height of the silicon oxide film 2470 as the eleventh insulating film is adjusted so as to bury the polycrystalline silicon film 2511 as the first conductive film. Subsequently, the polycrystalline silicon film 2521 as the second conductive film is etched back by anisotropic or isotropic etching to the extent that it can come into contact with the polycrystalline silicon film 2511 as the first conductive film. And At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer.
[0129]
Thereafter, the sidewall of the silicon nitride film 2350, which is the twelfth insulating film, is removed by isotropic etching, and a silicon oxide film 2471, for example, is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film.
[0130]
Subsequently, the silicon oxide film 2471 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2521 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2471 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2342 as the sixth insulating film is exposed.
[0131]
Next, an interlayer insulating film 2612 is formed on the surfaces of the exposed polycrystalline silicon films 2512 to 2514 which are the first conductive films (FIGS. 177 and 199). The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0132]
Subsequently, similarly, a polycrystalline silicon film 2522 serving as a second conductive film is deposited by 15 to 150 nm and etched back, whereby an interlayer insulating film 2612 is formed on the side of the polycrystalline silicon film 2512 serving as the first conductive film. Then, a polycrystalline silicon film 2522 which is a second conductive film is disposed. At this time, by setting the AA ′ direction in FIG. 1 below a predetermined value in advance, it is formed as a third wiring layer that becomes a control gate line continuous in that direction without using a mask process. (FIGS. 178 and 200).
[0133]
Next, as an eleventh insulating film, for example, a silicon oxide film 2472 is deposited to about 50 to 500 nm.
[0134]
Subsequently, the silicon oxide film 2472 as the eleventh insulating film is formed in the third groove 2230 so as to bury the polycrystalline silicon film 2522 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2472 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2343 as the sixth insulating film is exposed.
[0135]
Next, by repeating similarly, the polycrystalline silicon film 2523 which is the second conductive film is arranged on the side portion of the polycrystalline silicon film 2513 which is the first conductive film with the interlayer insulating film 2613 interposed therebetween, and the second conductive A polycrystalline silicon film 2523 which is a film is buried by a silicon oxide film 2473 which is an eleventh insulating film (FIGS. 179 and 201).
[0136]
In the polycrystalline silicon film 2514 which is the uppermost first conductive film, it can be in contact with the polycrystalline silicon film 2514 which is the first conductive film, similarly to the polycrystalline silicon film 2511 which is the lowermost first conductive film. Then, the polycrystalline silicon film 2524 which is the second conductive film is etched back (FIGS. 178 to 180 and FIGS. 200 to 202).
[0137]
Subsequently, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, the silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2340 that is the sixth insulating film are, for example, isotropically etched. The silicon oxide film 2475 which is the eleventh insulating film is deposited on the polycrystalline silicon film 2524 which is the second conductive film to a thickness of 100 to 500 nm, and the fourth conductive film is etched back or by the CMP method or the like. The upper part of the polycrystalline silicon film 2540 is exposed, and the fourth wiring layer 2840 is connected to the upper part of the island-shaped semiconductor layer 2110 so that the direction intersects the second or third wiring layer (FIGS. 181 and 203). ).
[0138]
Thereafter, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0139]
Further, in this embodiment, a semiconductor substrate or a polycrystal such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film. The film formed on the surface of the silicon film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0140]
Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0141]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible for the first time when the island-like semiconductor layers are not contrasted. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the arrangement of island-like semiconductor layers is targeted, the wiring layers may be separated by a resist patterning process by photolithography.
Further, by arranging selection gates at the upper and lower portions of the plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, and the threshold value is in a negative state. A phenomenon in which a cell current flows even in a non-selected cell can be prevented.
[0142]
Production Example 4
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then a columnar shape is formed by selective epitaxial silicon growth in a hole-like groove opened by a photoresist mask. An island-like semiconductor layer is formed on the side wall of the island-like semiconductor layer, and a stacked insulating film is formed as a charge-accumulating layer on a region where the charge-accumulating layer is formed, and the island-like semiconductor layer is electrically floated with respect to the semiconductor substrate. In this state, the active region of each memory cell is manufactured in common electrically.
[0143]
In this semiconductor memory device, select gate transistors are disposed above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are disposed between the select gate transistors. The stacked insulating films of the memory transistors are formed in a lump, and the transistors are connected in series along the island-shaped semiconductor layers. The gate insulating film thickness of the select gate transistor is equal to the gate insulating film thickness of the memory transistor.
204 to 216 and FIGS. 217 to 229 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 10, which are plan views showing the memory cell array of the EEPROM, respectively.
[0144]
First, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 is formed to have a thickness of 10 to 100 nm. The process up to the etching removal of the thermal oxide film 2450 (FIGS. 204 and 217) is performed in the same manner as in Production Example 3 (FIGS. 160 to 169 and FIGS. 182 to 191).
[0145]
Subsequently, as a twenty-fourth insulating film, for example, a silicon oxide film 2496 is deposited by CVD to a thickness of 50 to 500 nm and etched back to the extent that the silicon nitride film 2312 as the second insulating film is exposed. A silicon oxide film 2496, which is the fourth insulating film, is buried (FIGS. 205 and 218).
[0146]
For example, a stacked insulating layer serving as a charge storage layer is formed around each island-shaped semiconductor layer 2110 and the silicon nitride film 2340 as the sixth insulating film and the silicon nitride films 2313 to 2315 as the second insulating film using a thermal oxidation method. A film 2620 is formed (FIGS. 206 and 219). Here, when the laminated insulating film has an MNOS structure, a silicon nitride film of 4 to 10 nm and a silicon oxide film of 2 to 5 nm may be sequentially deposited on the surface of the island-like semiconductor layer by, for example, CVD. Alternatively, a silicon nitride film of 4 to 10 nm may be deposited on the surface of the island-like semiconductor layer by a CVD method, and the silicon oxide film of 2 to 5 nm may be formed by oxidizing the surface of the silicon nitride film. In the case of the MONOS structure, for example, a 2 to 5 nm silicon oxide film, a 4 to 8 nm silicon nitride film, and a 2 to 5 nm silicon oxide film are sequentially deposited on the surface of the island-like semiconductor layer by a CVD method. Alternatively, a silicon oxide film having a thickness of 2 to 5 nm and a silicon nitride film having a thickness of 4 to 10 nm are sequentially deposited on the surface of the island-shaped semiconductor layer by a CVD method, and further, the surface of the silicon nitride film is oxidized to have a thickness of 2 to 5 nm. A silicon oxide film may be formed, a 2 to 5 nm silicon oxide film may be formed by oxidizing the surface of the island-shaped semiconductor layer, and the above methods may be combined in various ways.
[0147]
Subsequently, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 500 nm (FIGS. 207 and 220).
[0148]
Using the silicon nitride film 2330 as the fifth insulating film, the silicon nitride film 2340 as the sixth insulating film, and the silicon nitride films 2314, 2313, and 2312 as the second insulating film as masks, for example, anisotropic etching is performed. A polycrystalline silicon film 2510 which is one conductive film is divided into polycrystalline silicon films 2512, 2513 and 2514 which are first conductive films (FIGS. 208 and 221).
[0149]
Thereafter, the silicon oxide film 2496 which is the twenty-fourth insulating film is removed, and the island-shaped semiconductor layer 2110 is exposed. Further, for example, a silicon oxide film 2491 is formed as an eighteenth insulating film that becomes a select gate oxide film of about 10 nm by using, for example, a thermal oxidation method. The eighteenth insulating film is not limited to a thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0150]
Subsequently, for example, a polycrystalline silicon film 2521 to be a second conductive film is deposited by 15 to 150 nm.
[0151]
Thereafter, as shown in FIG. 222, the polycrystalline silicon film 2521 as the second conductive film is etched back by, eg, anisotropic etching (FIGS. 209 and 222).
[0152]
Subsequently, the silicon nitride film 2321 as the fourth insulating film, the silicon oxide film 2411 as the first insulating film, and the p-type silicon as the semiconductor substrate are self-aligned with the polycrystalline silicon film 2521 as the second conductive film. The substrate 2100 is sequentially etched to form a second groove 2220 in the p-type silicon substrate 2100 and to separate the impurity diffusion layer 2710. That is, the isolation part of the first wiring layer is formed in a self-aligned manner with the isolation part of the second conductive film. The second groove 2220 is formed by etching back the polycrystalline silicon film 2521 as the second conductive film from at least the lower surface of the first conductive film 2512 by, for example, anisotropic etching, and then forming the island-shaped semiconductor layer 2110. For example, a silicon oxide film may be embedded only in the narrower space by, for example, a CVD method, and this silicon oxide film may be used as a mask in a self-aligning manner.
[0153]
Subsequently, the polycrystalline silicon film 2521 which is the second conductive film is etched back to the extent that it can be in contact with the polycrystalline silicon film 2511 which is the first conductive film, to form a selection gate. At that time, by setting the interval between the island-shaped semiconductor layers 2110 to a predetermined value or less in advance in the AA ′ direction in FIG. Formed as a second wiring layer.
[0154]
Thereafter, for example, a silicon oxide film 2471 is embedded as an eleventh insulating film. At this time, at least the polycrystalline silicon film 2512 as the first conductive film is exposed in the silicon oxide film 2471 as the eleventh insulating film (FIGS. 211 and 224).
[0155]
Subsequently, a polycrystalline silicon film 2522 serving as a second conductive film is similarly deposited by 15 to 150 nm and etched back, so that the second conductive film is formed on the side of the polycrystalline silicon film 2512 as the first conductive film. A polycrystalline silicon film 2522 is disposed. At this time, the silicon oxide film 2472 as the eleventh insulating film exposes at least the polycrystalline silicon film 2513 as the first conductive film. By repeating in the same manner, a polycrystalline silicon film 2523 as a second conductive film is deposited on the side portion of the polycrystalline silicon film 2513 as a first conductive film to a thickness of 50 to 500 nm and etched back.
[0156]
Thereafter, for example, a silicon oxide film 2473 is embedded as an eleventh insulating film. At this time, at least the polycrystalline silicon film 2514 as the first conductive film is exposed in the silicon oxide film 2473 as the eleventh insulating film (FIGS. 213 and 226).
[0157]
Subsequently, the polycrystalline silicon film 2514 which is the first conductive film and the stacked insulating film 2620 which is not covered with the silicon oxide film 2473 which is the eleventh insulating film are removed, and the island-shaped semiconductor layer 2110 is exposed. Let
[0158]
Thereafter, for example, a silicon oxide film 2492 is formed as an eighteenth insulating film to be a select gate oxide film of about 10 nm by using, eg, thermal oxidation (FIGS. 214 and 227). The eighteenth insulating film is not limited to a thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0159]
Subsequently, a polycrystalline silicon film 2524 which is the second conductive film is deposited by 50 to 500 nm and etched back. Thereafter, a silicon oxide film 2474, which is an eleventh insulating film, is deposited on the polycrystalline silicon film 2524, which is the second conductive film, to a thickness of 100 to 500 nm, and the upper end of the polycrystalline silicon film 2540, which is the fourth conductive film. Etch back to a position lower than the portion (FIGS. 215 and 228).
[0160]
Next, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, the silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2340 that is the sixth insulating film are anisotropically etched, for example. The upper portion of the polycrystalline silicon film 2540 that is the fourth conductive film is exposed by etch back or CMP, and the fourth wiring layer 2840 crosses the direction of the second or third wiring layer. It connects with the upper part of the island-like semiconductor layer 2110 (FIGS. 216 and 229).
[0161]
Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0162]
In this manufacturing example, a semiconductor substrate such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, or a silicon nitride film 2350 as a twelfth insulating film is used. The film formed on the surface of the crystalline silicon film may be a multilayer film of silicon oxide film / silicon nitride film from the silicon surface side.
[0163]
Further, impurities of the polycrystalline silicon film 2510 or 2512 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0164]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0165]
Production Example 5
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then a columnar shape is formed by selective epitaxial silicon growth in a hole-like groove opened by a photoresist mask. An island-shaped semiconductor layer is formed, a floating gate is formed as a tunnel oxide film and a charge storage layer in a region where the charge storage layer is formed on the side wall of the island-shaped semiconductor layer, and the island-shaped semiconductor layer is electrically connected to the semiconductor substrate. The floating region is formed by electrically setting the active region of each memory cell to the floating state.
[0166]
Select gate transistors are arranged above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are arranged between the select gate transistors. The tunnel oxide film and floating gate of each memory transistor are formed together, each transistor is connected in series along the island-like semiconductor layer, and the gate insulation film thickness of the select gate transistor is the gate insulation of the memory transistor. The structure is larger than the film thickness.
[0167]
230 to 231 and FIGS. 232 to 233 are sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0168]
The process is the same as that in Manufacturing Example 1 (FIGS. 83 to 97 and FIGS. 116 to 130) until channel ion implantation is performed on the sidewall of each semiconductor layer 2110.
[0169]
Thereafter, for example, a silicon oxide film 2471 to be an eleventh insulating film is deposited to a thickness of 50 to 500 nm, and the third groove portion is formed to a height at which the upper end of the lower selection gate is located by anisotropic etching or isotropic etching. Embedded in 2230.
[0170]
Thereafter, for example, a silicon nitride film 2351 to be a twelfth insulating film is deposited to 5 to 50 nm to form a sidewall.
[0171]
Subsequently, a silicon oxide film 2472, which is an eleventh insulating film, is similarly deposited to a thickness of 50 to 500 nm, and is anisotropically etched or isotropically etched to a height at which the lower end of the upper select gate is located. It is embedded in the groove 2230.
[0172]
Thereafter, the silicon nitride film sidewall 2351 as the twelfth insulating film is partially removed by isotropic etching using the silicon oxide film 2472 as the eleventh insulating film as a mask.
[0173]
Subsequently, for example, a silicon oxide film 2491 having a thickness of about 15 to 25 nm to be an eighteenth insulating film is formed around each semiconductor layer 2110 using a thermal oxidation method.
[0174]
Next, the silicon nitride film sidewall 2351 which is the twelfth insulating film is removed by isotropic etching, and a tunnel oxide film having a thickness of, for example, about 10 nm is formed around each semiconductor layer 2110 using, for example, a thermal oxidation method. A silicon oxide film 2460 is formed as the tenth insulating film. At this time, the silicon oxide film 2491 which is the eighteenth insulating film is increased in thickness to become the silicon oxide film 2492 which is the eighteenth insulating film, and is thicker than the silicon oxide film 2460 which is the tenth insulating film. Turn into. The film thickness of the silicon oxide film 2492 as the eighteenth insulating film is arbitrarily determined depending on the film thickness of the silicon oxide film 2491 as the eighteenth insulating film and the film thickness of the silicon oxide film 2460 as the tenth insulating film. Can be set. The tunnel oxide film is not limited to a thermal oxide film, and may be a CVD oxide film or a nitrogen oxide film.
[0175]
Subsequently, after depositing, for example, a polycrystalline silicon film 2510 of about 50 to 200 nm, which becomes the first conductive film, in accordance with Production Example 1 (FIGS. 101 to 114 and FIGS. 134 to 147) (FIGS. 230 and 232). ) Complete the semiconductor memory device (FIGS. 231 and 233).
[0176]
In addition to the manufacturing example 1, a film formed on the surface of the semiconductor substrate such as the silicon nitride film 2351, which becomes the above-mentioned tenth insulating film, is formed from the silicon surface side to the silicon oxide film / silicon nitride film. It is good also as a multilayer film.
The same effects as in Production Example 1 can be obtained by this production example.
[0177]
Production Example 6
In the semiconductor memory device formed in this manufacturing example, a region where a charge storage layer is formed in advance is defined by a multilayer film formed of a plurality of layers on a semiconductor portion of a semiconductor substrate into which an oxide film is inserted, for example, an SOI substrate. An island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth in a hole-shaped groove opened by a photoresist mask, and floats as a tunnel oxide film and a charge storage layer in the region where the charge storage layer is formed on the side wall of the island-shaped semiconductor layer. A gate is formed, the island-like semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically floated.
[0178]
Select gate transistors are arranged above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are arranged between the select gate transistors. The tunnel oxide film and floating gate of each memory transistor are formed together, each transistor is connected in series along the island-like semiconductor layer, and the gate insulation film thickness of the selection gate transistor is the gate insulation of the memory transistor. Equal to film thickness.
[0179]
FIGS. 234 to 235 and FIGS. 236 to 237 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0180]
In accordance with Manufacturing Example 1 and Manufacturing Example 5 (FIGS. 234 and 236), a semiconductor memory device is formed (FIGS. 235 and 237).
[0181]
The same effects as in Production Example 1 can be obtained by this production example. Further, the junction capacitance of the impurity diffusion layer 2710 serving as the first wiring layer is suppressed or excluded.
Note that the use of an SOI substrate as the substrate can be applied to all the embodiments of the present invention.
[0182]
Production Example 7
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then a columnar shape is formed by selective epitaxial silicon growth in a hole-like groove opened by a photoresist mask. An island-shaped semiconductor layer is formed, a floating gate is formed as a tunnel oxide film and a charge storage layer in a region where the charge storage layer is formed on the side wall of the island-shaped semiconductor layer, and the island-shaped semiconductor layer is electrically connected to the semiconductor substrate. The floating state is set, and the active region of each memory cell is set to an electrically floating state.
[0183]
Two memory transistors are arranged on the island-like semiconductor layer, and a tunnel oxide film and a floating gate of each memory transistor are formed at a time. Each transistor is connected in series along the island-shaped semiconductor layer.
[0184]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 238 to 263 and FIGS. 264 to 289 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
First, an insulating film containing an impurity is formed on the surface of the p-type silicon substrate 2100 by CVD, for example, arsenic 1 × 10 as a first insulating film.¹⁸~ 1x10^{twenty two}/ Cm^ThreeA silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm. At this time, the insulating film containing impurities may be introduced into the insulating film by ion implantation after the insulating film is deposited by a CVD method. For example, after depositing a silicon oxide film 2411 as a first insulating film by 50 to 500 nm, arsenic 1 × 10 at an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 45 °.¹⁴~ 1x10¹⁶/ Cm²About a dose is introduced into the silicon oxide film 2411 which is the first insulating film. Further, the introduction of impurities into the silicon oxide film 2411 which is the first insulating film by ion implantation may not be performed immediately after the silicon oxide film 2411 which is the first insulating film is deposited. When an impurity is introduced into the silicon oxide film 2411 which is the first insulating film by ion implantation, the implantation inclination angle is not limited as long as a desired impurity concentration can be obtained. Further, the introduction of impurities into the silicon oxide film 2411 which is the first insulating film is not limited to ion implantation, and various means such as solid phase vapor phase diffusion can be used.
Thereafter, for example, a silicon nitride film 2321 is deposited as a fourth insulating film by 10 to 100 nm. Here, when the impurity is introduced into the silicon oxide film 2411 as the first insulating film by ion implantation, the first insulating film is formed by ion implantation through the silicon nitride film 2321 as the fourth insulating film. Impurities may be introduced into a certain silicon oxide film 2411.
Subsequently, as the third insulating film, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm, and as the second insulating film, for example, a silicon nitride film 2312 is deposited by 10 to 100 nm, and the impurity which is the first insulating film is deposited. The included silicon oxide film 2412 is deposited by 50 to 500 nm, the fourth insulating film silicon nitride film 2322 is deposited by 10 to 100 nm, the third insulating film silicon oxide film 2422 is deposited by 50 to 500 nm, A silicon nitride film 2313 that is a second insulating film is deposited to 10 to 100 nm, a silicon oxide film 2413 that contains an impurity that is a first insulating film is deposited to 50 to 500 nm, and a silicon nitride film 2323 that is a fourth insulating film. Is deposited at 500 to 5000 nm.
[0185]
Subsequently, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 238 and 264), for example, the silicon nitride film 2323, which is the fourth insulating film, is formed by reactive ion etching, the first insulating film, and the like. A silicon oxide film 2413 as a film, a silicon nitride film 2313 as a second insulating film, a silicon oxide film 2422 as a third insulating film, a silicon nitride film 2322 as a fourth insulating film, and the first insulating film A silicon oxide film 2412, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, a silicon nitride film 2321 as a fourth insulating film, and silicon as a first insulating film The oxide film 2411 is sequentially etched to form a fourth groove 2240 (FIGS. 239 and 265).
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240 (FIGS. 240 and 266).
[0186]
Further, the island-like semiconductor layer 2110 is planarized with respect to the silicon nitride film 2323 which is the fourth insulating film. At this time, etch back using isotropic etching, etch back using anisotropic etching, flattening embedding using CMP, various combinations, or any means may be used.
Thereafter, for example, a polycrystalline silicon film 2540 is deposited to a thickness of about 100 to 300 nm as a fourth conductive film, and a silicon nitride film 2330 is deposited to a thickness of about 200 to 2000 nm as a fifth insulating film (FIGS. 241 and 267). .
Subsequently, using the resist R2 patterned by a known photolithography technique as a mask (FIGS. 242 and 268), for example, the silicon nitride film 2330 as the fifth insulating film and the fourth conductive film are formed by reactive ion etching. A polycrystalline silicon film 2540 as a film, a silicon nitride film 2323 as a fourth insulating film, and a silicon oxide film 2413 as a first insulating film are sequentially etched to expose a silicon nitride film 2313 as a second insulating film. Let At this time, the silicon nitride film 2313 as the second insulating film may be etched until the silicon oxide film 2422 as the third insulating film is exposed.
After removing the resist R2 (FIGS. 243 and 269), a silicon nitride film 2340 is deposited to a thickness of about 5 to 50 nm as a sixth insulating film, and silicon nitride, which is the fifth insulating film, is formed using, for example, anisotropic etching. A sidewall 2 is formed on the sidewalls of the film 2330, the polycrystalline silicon film 2540 as the fourth conductive film, the silicon nitride film 2323 as the fourth insulating film, and the silicon oxide film 2413 as the first insulating film. A silicon nitride film 2340 which is an insulating film is disposed (FIGS. 244 and 270). At this time, a silicon oxide film 2413 containing an impurity as a first insulating film is a silicon nitride film 2323 as a fourth insulating film, a silicon nitride film 2313 as a second insulating film, and silicon as a sixth insulating film. The nitride film 2340 is isolated from the parts other than the island-shaped semiconductor layer 2110.
Subsequently, using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film as a mask, the silicon nitride film 2313 as the second insulating film and the silicon oxide as the third insulating film are used. A film 2422, a silicon nitride film 2322 as a fourth insulating film, a silicon oxide film 2412 as a first insulating film, and a silicon nitride film 2312 as a second insulating film are sequentially etched to form a third insulating film. A third groove 2230 is formed so as to expose a silicon oxide film 2421 (FIGS. 245 and 271).
Next, after depositing a silicon nitride film 2342 as a sixth insulating film of about 5 to 50 nm, a silicon oxide film 2412 containing an impurity as at least a first insulating film becomes a silicon nitride film 2342 as a sixth insulating film. The silicon nitride film 2312 as the second insulating film and the silicon nitride film 2322 as the fourth insulating film are isolated from the silicon nitride film 2322 other than the island-like semiconductor layer 2110 by the silicon nitride film as the sixth insulating film. A membrane 2342 is disposed. For example, after a silicon nitride film 2342 as a sixth insulating film is deposited to a thickness of about 5 to 50 nm, it is etched back by anisotropic etching and a silicon nitride film as a sixth insulating film at the bottom of the third groove 2230. 2342 is removed to expose a silicon oxide film 2421 which is a third insulating film (FIGS. 246 and 272).
Thereafter, for example, a silicon oxide film 2432 is deposited as a seventh insulating film to a desired depth, for example, and a silicon oxide containing an impurity serving as a first insulating film is interposed through a silicon nitride film 2342 serving as a sixth insulating film. A silicon oxide film 2432 which is a seventh insulating film is embedded in the third groove 2230 so that the film 2412 is embedded (FIGS. 247 and 273).
[0187]
Next, the exposed portion of the silicon nitride film 2342 as the sixth insulating film is removed by isotropic etching using the silicon oxide film 2432 as the seventh insulating film as a mask, and the silicon nitride film as the sixth insulating film 2342 are arranged (FIGS. 248 and 274).
Thereafter, the silicon oxide films 2421 and 2422 as the third insulating film and the silicon oxide film 2432 as the seventh insulating film are removed by, for example, isotropic etching to expose the side surface of the island-shaped semiconductor layer 2110 (FIG. 249 and FIG. 275).
Next, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 having a thickness of 10 to 100 nm (FIGS. 250 and 276). Next, the thermal oxide film 2450 which is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching (FIGS. 251 and 277), and oblique ion implantation is used as necessary. Then, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 2110. For example, implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °, boron 1 × 0¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2421 and 2422 as third insulating films, and heat treatment may be performed before the silicon oxide films 2421 and 2422 as third insulating films are removed. Impurities may be introduced into the island-shaped semiconductor layer 2110 by any means, and means are not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is equal.
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film that becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 by using, for example, a thermal oxidation method (FIGS. 252 and 278). . At this time, the tunnel oxide film is not limited to the thermal oxide film but may be a CVD oxide film or a nitrogen oxide film.
Subsequently, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 as a fifth insulating film and silicon nitride films 2340 and 2342 as sixth insulating films. As a mask, the polycrystalline silicon film 2510 as the first conductive film is dividedly formed into the polycrystalline silicon films 2511 and 2512 as the first conductive film by anisotropic etching, for example (FIGS. 253 and 279).
Next, an interlayer insulating film 2612 is formed on the surfaces of the exposed polycrystalline silicon films 2511 to 2512 which are the first conductive films (FIGS. 254 and 280). The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
Thereafter, anisotropic etching is performed on the interlayer insulating film 2612 to expose the silicon nitride film 2321 as the fourth insulating film (FIGS. 255 and 281), and then the second conductive film, for example, polycrystalline A silicon film 2521 is deposited to a thickness of 15 to 150 nm. Further, for example, a polycrystalline silicon film 2521 that becomes the second conductive film as it is without etching back the interlayer insulating film 2612 may be deposited by 15 to 150 nm.
Thereafter, as shown in FIG. 282, the polycrystalline silicon film 2521 which is the second conductive film is etched back by, eg, anisotropic etching (FIGS. 256 and 282). Subsequently, the silicon nitride film 2321 as the fourth insulating film, the silicon oxide film 2411 as the first insulating film, and the p-type silicon as the semiconductor substrate are self-aligned with the polycrystalline silicon film 2521 as the second conductive film. The substrate 2100 is sequentially etched to form a second groove 2220 in the p-type silicon substrate 2100 and to separate the impurity diffusion layer 2710. That is, the isolation part of the first wiring layer is formed in a self-aligned manner with the isolation part of the second conductive film (FIGS. 257 and 283).
[0188]
Next, as an eleventh insulating film, for example, a silicon oxide film 2470 is deposited to a thickness of 30 to 300 nm, and then etched back by, for example, anisotropic etching to form a silicon oxide film as an eleventh insulating film in the second groove 2220. The film 2470 is embedded (FIGS. 258 and 284). At this time, the polycrystalline silicon film 2521 as the second conductive film is buried by the silicon oxide film 2470 as the eleventh insulating film. At this time, by setting the interval between the island-shaped semiconductor layers 2110 to be equal to or less than a predetermined value in the AA ′ direction in FIG. Formed as a third wiring layer.
Thereafter, the interlayer insulating film 2612 is removed by etching in a region not buried in the silicon oxide film 2470 which is the eleventh insulating film (FIGS. 259 and 285).
Similarly, an interlayer insulating film 2613 is formed on the exposed surface of the polycrystalline silicon film 2512 which is the first conductive film (FIGS. 260 and 286), and then the second conductive film, for example, a polycrystalline silicon film 2522 is deposited to a thickness of 15 to 150 nm, etched back by anisotropic etching or the like, and a polycrystalline silicon film serving as a second conductive film is formed on the side of the polycrystalline silicon film 2512 serving as the first conductive film with an interlayer insulating film 2613 interposed therebetween. A silicon film 2522 is disposed (FIGS. 261 and 287).
Subsequently, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, an interlayer insulating film 2613, a silicon nitride film 2330 that is the fifth insulating film, and a silicon nitride film 2340 that is the sixth insulating film, For example, it is removed by isotropic etching (FIGS. 262 and 288).
A silicon oxide film 2472 as an eleventh insulating film is deposited to a thickness of 100 to 500 nm on the polycrystalline silicon film 2522 as the second conductive film, and the fourth conductive film as the fourth conductive film is formed by etch back or CMP. The upper part of the crystalline silicon film 2540 is exposed, and the fourth wiring layer 2840 is connected to the upper part of the island-shaped semiconductor layer 2110 so that the direction intersects with the second or third wiring layer.
Thereafter, an interlayer insulating film is formed by a known technique to form contact holes and metal wiring (FIGS. 263 and 289). Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0189]
In this manufacturing example, the film formed on the surface of the semiconductor substrate or the polycrystalline silicon film, such as the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film, is on the silicon surface side. Alternatively, a multilayer film of silicon oxide film / silicon nitride film may be used.
[0190]
Further, introduction of impurities into the polycrystalline silicon film 2510 or 2511 to 2512 which is the first conductive film, the polycrystalline silicon films 2521 to 2522 which are the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. May be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0191]
In the embodiment, the control gate of each memory cell is formed to be continuous in one direction without using a mask. This is possible for the first time when the island-like semiconductor layers are not contrasted. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the arrangement of island-like semiconductor layers is targeted, the wiring layers may be separated by a resist patterning process by photolithography.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0192]
Production Example 8
In the semiconductor memory device formed in this manufacturing example, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then a columnar shape is formed by selective epitaxial silicon growth in a hole-like groove opened by a photoresist mask. An island-shaped semiconductor layer is formed, a floating gate is formed as a tunnel oxide film and a charge storage layer in a region where the charge storage layer is formed on the side wall of the island-shaped semiconductor layer, and the island-shaped semiconductor layer is electrically connected to the semiconductor substrate. In a semiconductor memory device in which the active region of each memory cell is electrically common in a floating state, a selection gate transistor is arranged above and below the island-like semiconductor layer, and the memory is sandwiched between the selection gate transistors. A plurality of, for example, two transistors are arranged, and a tunnel oxide film and a floating gate of each memory transistor are formed at once. Each transistor is connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is equal to the gate insulating film thickness of the memory transistor, and the potential is transmitted to the active region of each memory transistor. Therefore, an embodiment of the present invention, which has a structure in which a transmission gate is arranged between each transistor, will be described.
[0193]
Such a semiconductor memory device can be formed by the following manufacturing method. 290 and 291 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0194]
In this manufacturing example, after the polycrystalline silicon films 2521, 2522, 2523, and 2524 which are the second conductive films are formed, the gate electrode is formed using the polycrystalline silicon film 2530 which is the third conductive film. Except for the addition, the same procedure as in Production Example 1 is performed.
[0195]
That is, after the polycrystalline silicon films 2521, 2522, 2523, and 2524 which are the second conductive films are formed, the island-shaped semiconductor layer 2110 between the polycrystalline silicon films 2521 and 2522 which are the second conductive films is exposed. After the silicon oxide films 2412 to 2415 and the interlayer insulating films 2612 and 2613 as the first insulating film are removed by isotropic etching, the 22nd insulating film is formed by using, for example, a thermal oxide film method. A certain silicon oxide film 2494 is formed on the surface of the island-shaped semiconductor layer 2110 between the selection gate and the memory cell and the polycrystalline silicon films 2511, 2512, 2513, 2514, 2521, 2522, 2523, 2524 that are the first and second conductive films. After the formation on the exposed portion, a polycrystalline silicon film 2530 which is a third conductive film is deposited on the entire surface.
[0196]
Thereafter, the polycrystalline silicon film 2530 as the third conductive film is etched back by anisotropic etching to such an extent that the space portions of the polycrystalline silicon films 2523 and 2524 as the second conductive film are not exposed.
Thereafter, the semiconductor memory device shown in FIGS. 290 and 291 is formed in the same manner as in Manufacturing Example 1 (FIGS. 83 to 114 and FIGS. 116 to 147).
[0197]
Production Example 9
In the semiconductor memory device formed in this manufacturing example, a tunnel oxide film and an interlayer capacitance film of a floating gate and a control gate are collectively formed in a method in which a region where a charge storage layer is formed in advance by a multilayer film consisting of multiple layers. To do.
[0198]
Such a semiconductor memory device can be formed by the following manufacturing method. 292 to 301 and 302 to 311 are cross-sectional views taken along lines AA ′ and BB ′ of FIG.
[0199]
For example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 as a fifth insulating film and silicon nitride films 2340, 2342, 2343, and 2344 as sixth insulating films. Production Example 1 until the polycrystalline silicon film 2510 as the first conductive film is divided into the polycrystalline silicon films 2511, 2512, 2513, and 2514 as the first conductive film by anisotropic etching, for example, using (FIGS. 292 and 302).
[0200]
Thereafter, the polycrystalline silicon films 2511, 2512, 2513, and 2514, which are the first conductive films formed separately, are retracted by about 25 to 100 nm, for example, by isotropic etching in order to recede in the horizontal direction. At this time, the etching film thickness is adjusted so that the silicon oxide film 2460 which is the tenth insulating film is not exposed (FIGS. 293 and 303).
[0201]
Thereafter, for example, a silicon oxide film 2470 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film.
[0202]
Subsequently, the silicon oxide film 2470 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2511 as the first conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2470 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2342 as the sixth insulating film is exposed.
[0203]
Thereafter, polycrystalline silicon films 2512 to 2514 that are the first conductive film on the inner wall of the third groove 2230, and silicon nitride films 2340, 2342, 2343, and 2344 that are the sixth insulating films, and the eleventh insulating film As a twelfth insulating film, for example, a silicon nitride film 2350 is deposited to a thickness of 5 to 50 nm on the surface of the silicon oxide film 2470 (FIGS. 294 and 304), and the eleventh insulating film is formed by anisotropic etch back, for example. A silicon oxide film 2470 is exposed.
[0204]
Subsequently, the silicon oxide film 2470 as the eleventh insulating film is etched back by, for example, isotropic etching so that the side portion of the polycrystalline silicon film 2511 as the first conductive film is exposed. For example, a polycrystalline silicon film 2521 to be a conductive film is deposited to a thickness of 15 to 150 nm.
[0205]
Thereafter, the polycrystalline silicon film 2521 as the second conductive film is etched back by, for example, anisotropic etching, and then the fourth insulating film is self-aligned with the polycrystalline silicon film 2521 as the second conductive film. A silicon nitride film 2321 that is a film, a silicon oxide film 2411 that is a first insulating film, and a p-type silicon substrate 2100 that is a semiconductor substrate are sequentially etched to form a second groove 2220 in the p-type silicon substrate 2100 and The impurity diffusion layer 2710 is separated. That is, the isolation part of the first wiring layer is formed in a self-aligned manner with the isolation part of the second conductive film.
[0206]
Subsequently, the polycrystalline silicon film 2521 which is the second conductive film is etched back to the extent that it can be in contact with the polycrystalline silicon film 2511 which is the first conductive film, to form a selection gate. At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer. In addition, the polycrystalline film that is the second conductive film is exposed so that the silicon nitride film 2350 that is the twelfth insulating film on the sides of the polycrystalline silicon films 2512 to 2524 that are the first and second conductive films is exposed. The silicon film 2521 is etched back.
[0207]
Thereafter, the sidewall of the silicon nitride film 2350, which is the twelfth insulating film, is removed by isotropic etching, and a silicon oxide film 2471, for example, is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film.
[0208]
Subsequently, the silicon oxide film 2471 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2521 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the silicon oxide film as the eleventh insulating film is exposed so that a part of the silicon nitride film 2342 as the sixth insulating film or the side parts of the polycrystalline silicon films 2512 to 2514 as the first conductive film are exposed. The embedding depth of the film 2471 is adjusted.
[0209]
Next, an interlayer insulating film 2612 is formed on the surfaces of the exposed polycrystalline silicon films 2512 to 2514 which are the first conductive films (FIGS. 295 and 305). The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0210]
Subsequently, a polycrystalline silicon film 2520 to be the second conductive film is similarly deposited by 15 to 150 nm (FIGS. 296 and 306), and etched back, so that the polycrystalline silicon film 2512 which is the first conductive film, Polycrystalline silicon films 2522, 2523, and 2524, which are second conductive films, are dividedly formed on the side portions of 2513 and 2514 through an interlayer insulating film 2612 (FIGS. 297 and 307).
[0211]
As the thirteenth insulating film, for example, a silicon nitride film 2360 having a thickness of 50 to 500 nm is deposited, and a resist R8 patterned by a known photolithography technique is used as a mask (FIGS. 298 and 308), for example, reactive ion etching. Thus, the silicon nitride film 2360, which is the thirteenth insulating film, is partially removed to form the fifth groove 2250. At this time, the resist R8 is patterned so as to be formed as a third wiring layer serving as a control gate line continuous in the A-A 'direction of FIG.
[0212]
Thereafter, a polycrystalline silicon film 2532 to be a third conductive film is deposited by 15 to 150 nm and etched back to form a third conductive film on the side of the polycrystalline silicon film 2522 which is the second conductive film. A polycrystalline silicon film 2532 is formed (FIGS. 299 and 309).
[0213]
Thereafter, for example, a silicon oxide film 2472 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film, and isotropically etched, for example. Etchback is performed so that the side portion of the polycrystalline silicon film 2523 which is the second conductive film is exposed.
[0214]
By repeating similarly, the polycrystalline silicon film 2533 which is the third conductive film is arranged on the side of the polycrystalline silicon film 2523 which is the second conductive film.
[0215]
Subsequently, for example, a silicon oxide film 2473 of about 50 to 500 nm is deposited as the eleventh insulating film and is etched, for example. Etchback is performed so that the side portion of the polycrystalline silicon film 2524 which is the second conductive film is exposed.
[0216]
After that, after removing the polycrystalline silicon film 2524 and the interlayer insulating film 2612 which are the second conductive films by, for example, isotropic etching, the third conductive film is formed on the side of the polycrystalline silicon film 2514 which is the first conductive film. A polycrystalline silicon film 2534 which is a conductive film is provided. For example, a polycrystalline silicon film 2534 serving as a third conductive film is deposited to a thickness of 15 to 150 nm, and etch back is performed to such an extent that it can be in contact with the polycrystalline silicon film 2514 serving as the first conductive film (FIGS. 300 and 310). . As described above, the case where the resist R8 is patterned so as to form the third wiring layer serving as the control gate line has been described. However, as shown in FIG. By setting it to a predetermined value or less, the polycrystalline silicon films 2532 to 2534 as the third conductive film are deposited and etched back without using a mask process, so that AA ′ in FIG. A third wiring layer serving as a control gate line continuous in the direction can be formed.
[0217]
Subsequently, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, the silicon nitride film 2330 that is the fifth insulating film, the silicon nitride film 2340 that is the sixth insulating film, and the thirteenth insulating film. The silicon nitride film 2360 is removed by, for example, isotropic etching, and a silicon oxide film 2474 as an eleventh insulating film is deposited on the polycrystalline silicon film 2524 as the second conductive film to a thickness of 100 to 500 nm. The upper part of the polycrystalline silicon film 2540 which is the fourth conductive film is exposed by etch back or CMP, and the fourth wiring layer 2840 is island-shaped so that the direction intersects with the second or third wiring layer. It connects with the upper part of the semiconductor layer 2110 (FIGS. 301 and 311).
[0218]
Thereafter, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0219]
Further, in this manufacturing example, a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, a silicon nitride film 2350 as a twelfth insulating film, and a thirteenth insulating film A film formed on the surface of a semiconductor substrate or a polycrystalline silicon film such as a silicon nitride film 2360 may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0220]
Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0221]
The control gate of each memory cell is formed to be continuous in one direction using a mask. On the other hand, when the island-like semiconductor layer is not symmetrically arranged, each memory cell can be controlled without using a mask. The control gate can be formed to be continuous in one direction. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0222]
Production Example 10
An example of a specific manufacturing process in which a side wall of a silicon nitride film, which is a protective film of a PSG oxide film, is formed in a self-aligned manner in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers is shown. .
[0223]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 312 to 321 and FIGS. 322 to 331 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0224]
In this manufacturing example, the silicon nitride film 2315 that is the second insulating film and the third insulating film are formed using the silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2341 that is the sixth insulating film as a mask. A silicon oxide film 2424, a silicon nitride film 2324 as a fourth insulating film, a silicon oxide film 2414 as a first insulating film, a silicon nitride film 2314 as a second insulating film, and a silicon oxide as a third insulating film A film 2423, a silicon nitride film 2323 as a fourth insulating film, a silicon oxide film 2413 as a first insulating film, a silicon nitride film 2313 as a second insulating film, and a silicon oxide film 2422 as a third insulating film Then, a silicon nitride film 2322 as a fourth insulating film, a silicon oxide film 2412 as a first insulating film, and a silicon nitride film 2312 as a second insulating film are sequentially etched. Until the third groove 2230 is formed so as to expose the silicon oxide film 2421 which is the third insulating film (FIG. 312), manufacture example 1 (FIGS. 83 to 90 and FIGS. 116 to 123). The silicon oxide films 2412, 2413, and 2414, which are first insulating films, are selectively retracted in the horizontal direction with respect to the surface of the semiconductor substrate.
[0225]
For example, each of the silicon oxide films 2412, 2413, and 2414 that is the first insulating film is selectively retracted by isotropic etching that is selectively etched with respect to the impurity concentration contained in the oxide film or has an etching rate that is different. (FIGS. 313 and 323).
[0226]
Thereafter, a silicon nitride film 2341 is deposited to a thickness of about 25 to 250 nm as a sixth insulating film (FIGS. 314 and 324).
[0227]
Thereafter, the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film are etched using, for example, anisotropic etching as a mask, so that the silicon as the first insulating film is formed. It becomes possible to leave the silicon nitride film 2341 as the sixth insulating film only on the side walls of the oxide films 2412, 2413, and 2414. Alternatively, when the thickness of the silicon nitride film 2341 as the sixth insulating film is set to ½ or more of the thickness of the silicon oxide films 2412, 2413, and 2414 as the first insulating film, for example, isotropic etching Thus, by performing etching corresponding to the deposited film thickness, it is possible to leave the silicon nitride film 2341 as the sixth insulating film only on the side walls of the silicon oxide films 2412, 2413, and 2414 as the first insulating film. (FIGS. 315 and 325). As a result, the silicon oxide film 2412 containing impurities as the first insulating film becomes a silicon nitride film 2341 as the sixth insulating film, the silicon nitride film 2312 as the second insulating film, and the silicon nitride as the fourth insulating film. The film 2322 is isolated from the parts other than the island-shaped semiconductor layer 2110. The same is true for the silicon oxide films 2413 and 2414 containing impurities as the first insulating film.
[0228]
In addition to this, as a method of isolating the silicon oxide films 2412, 2413, and 2414 containing impurities as the first insulating film, for example, silicon nitride films 2324, 2323, and 2322 as the fourth insulating film by anisotropic etching, for example. The silicon nitride film 2341 as the sixth insulating film is etched back using the mask as a mask to expose the silicon oxide films 2412, 2413, and 2414 as the first insulating films while exposing the silicon oxide film 2421 as the third insulating film. A silicon nitride film 2341 which is a sixth insulating film may be left on the side wall.
[0229]
Thereafter, the silicon oxide films 2421, 2422, 2423, and 2424, which are the third insulating films, are removed by, for example, isotropic etching, and the side surfaces of the island-shaped semiconductor layer 2110 are exposed.
[0230]
Thereafter, the same process as in Manufacturing Example 1 (FIGS. 98 to 114 and 131 to 147) is performed to accumulate in the charge storage layer using the polycrystalline silicon film serving as the first conductive film as a floating gate. A semiconductor memory device having a memory function is realized depending on the charge state (FIGS. 316 and 326).
[0231]
Subsequently, using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2341 as the sixth insulating film as a mask, the silicon nitride film 2315 as the second insulating film and the silicon oxide as the third insulating film A film 2424, a silicon nitride film 2324 as a fourth insulating film, a silicon oxide film 2414 as a first insulating film, a silicon nitride film 2314 as a second insulating film, and a silicon oxide film 2423 as a third insulating film , A silicon nitride film 2323 as a fourth insulating film, a silicon oxide film 2413 as a first insulating film, a silicon nitride film 2313 as a second insulating film, a silicon oxide film 2422 as a third insulating film, The silicon nitride film 2322 as the fourth insulating film, the silicon oxide film 2412 as the first insulating film, and the silicon nitride film 2312 as the second insulating film are sequentially etched. Until the third groove 2230 is formed so that the silicon oxide film 2421 as the third insulating film is exposed (FIGS. 317 and 327), the first manufacturing example (FIGS. 83 to 90 and FIGS. 116 to 123). The silicon oxide films 2412, 2413, 2414 as the first insulating film and the silicon oxide films 2421, 2422, 2423, 2424 as the third insulating film are selectively retracted in the horizontal direction with respect to the surface of the semiconductor substrate. (FIGS. 318 and 328).
[0232]
Thereafter, a silicon nitride film 2341 is deposited to a thickness of about 25 to 250 nm as a sixth insulating film (FIGS. 319 and 329). At this time, the thickness of the silicon nitride film 2341 as the sixth insulating film is ½ or more of the thickness of the silicon oxide films 2412, 2413, and 2414 as the first insulating film, and the third insulating film The silicon oxide films 2421, 2422, 2423, and 2424 are preferably set to ½ or less of the film thickness. That is, the thickness of the silicon oxide films 2412, 2413, and 2414 as the first insulating film is made smaller than the thickness of the silicon oxide films 2421, 2422, 2423, and 2424 as the third insulating film, and the sixth insulating film is used. The film thickness of the silicon nitride film 2341 which is a film is larger than half the film thickness of the silicon oxide films 2412, 2413 and 2414 which are the first insulating films, and the silicon oxide films 2421, 2422 and 2423 which are the third insulating films. It is preferably less than half of the 2424 film thickness.
[0233]
Thereafter, by performing etching equivalent to the deposited film thickness by, for example, isotropic etching, the silicon nitride film as the sixth insulating film is formed only on the side walls of the silicon oxide films 2412, 2413, and 2414 as the first insulating film. 2341 can be left (FIGS. 320 and 330). As a result, the silicon oxide film 2412 containing impurities as the first insulating film becomes a silicon nitride film 2341 as the sixth insulating film, the silicon nitride film 2312 as the second insulating film, and the silicon nitride as the fourth insulating film. The film 2322 is isolated from the parts other than the island-shaped semiconductor layer 2110. The same is true for the silicon oxide films 2413 and 2414 containing impurities as the first insulating film.
[0234]
In addition to this, as a method of isolating the silicon oxide films 2412, 2413, and 2414 containing impurities as the first insulating film, for example, silicon nitride films 2324, 2323, and 2322 as the fourth insulating film by anisotropic etching, for example. The silicon nitride film 2341 as the sixth insulating film is etched back using the mask as a mask to expose the silicon oxide films 2412, 2413, and 2414 as the first insulating films while exposing the silicon oxide film 2421 as the third insulating film. A silicon nitride film 2341 which is a sixth insulating film may be left on the side wall.
[0235]
Thereafter, the silicon oxide films 2421, 2422, 2423, and 2424, which are the third insulating films, are removed by, for example, isotropic etching, and the side surfaces of the island-shaped semiconductor layer 2110 are exposed.
[0236]
Thereafter, the same process as in Manufacturing Example 1 (FIGS. 97 to 114 and 130 to 147) is performed, and the polycrystalline silicon film serving as the first conductive film is stored in the charge storage layer using the floating gate. A semiconductor memory device having a memory function is realized depending on the charge state.
[0237]
In this manufacturing example, a semiconductor substrate or polycrystalline silicon such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2341 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film. The film formed on the surface of the film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0238]
Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0239]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask.
[0240]
On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0241]
Production Example 11
In this manufacturing example, in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of a plurality of layers is used, a specific case of using vapor phase solid phase diffusion for introducing impurities into an island-shaped semiconductor layer is described. An example of a manufacturing process is shown.
[0242]
Such a semiconductor memory device can be formed by the following manufacturing method. 332 to 352 and 353 to 373 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0243]
First, for example, a silicon nitride film 2321 is deposited on the surface of the p-type silicon substrate 2100 as a fourth insulating film by a CVD method to a thickness of 10 to 100 nm.
[0244]
Subsequently, as the third insulating film, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm, and as the second insulating film, for example, a silicon nitride film 2312 is deposited by 10 to 100 nm, and a silicon oxide film as a third insulating film is formed. 2422 is deposited to 50-500 nm.
[0245]
After sequentially forming in this way, as shown in FIGS. 332 and 353, a silicon oxide film 2424 as a third insulating film is deposited by 50 to 500 nm, and a silicon nitride film 2315 as a second insulating film is deposited by 20 to 200 nm. accumulate.
[0246]
Subsequently, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 332 and 353), the silicon nitride film 2315 as the second insulating film and the third insulating film are formed by, for example, reactive ion etching. A silicon oxide film 2424 as a film, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, and a third insulating film A silicon oxide film 2422, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, and a silicon nitride film 2321 as a fourth insulating film are sequentially etched to form a fourth groove portion. 2240 is formed (FIGS. 333 and 354).
[0247]
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240 (FIGS. 334 and 355).
[0248]
Further, the island-like semiconductor layer 2110 is planarized with respect to the silicon nitride film 2315 which is the second insulating film (FIGS. 335 and 356). At this time, etch back using isotropic etching, etch back using anisotropic etching, planarization embedding using CMP, or various combinations may be used.
[0249]
Further, a silicon nitride film 2330 is deposited to a thickness of about 200 to 2000 nm as a fifth insulating film.
[0250]
Subsequently, using the resist R2 patterned by a known photolithography technique as a mask (FIGS. 336 and 357), the silicon nitride film 2315 as the second insulating film and the third insulating film are formed by reactive ion etching, for example. A silicon oxide film 2424 as a film, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, and a third insulating film A p-type silicon substrate is formed by sequentially etching a silicon oxide film 2422, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, and a silicon nitride film 2321 as a fourth insulating film. 2100 is exposed (FIGS. 337 and 358). At this time, the silicon nitride film 2321 which is the fourth insulating film may remain.
[0251]
Next, after removing the resist R 2, the silicon oxide films 2421, 2422, 2423, and 2424 that are third insulating films are removed by, for example, isotropic etching to expose the side surfaces of the island-shaped semiconductor layer 2110.
[0252]
Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 having a thickness of 10 to 100 nm (FIGS. 338 and 359).
[0253]
Next, the thermal oxide film 2450 that is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching, and then each island-shaped semiconductor layer is utilized using oblique ion implantation as necessary. Channel ion implantation is performed on the side wall of 2110. For example, implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2421, 2422, 2423, 2424 which are the third insulating films, and the silicon oxide films 2421, 2422, 2423 which are the third insulating films. , 2424 may be removed by introducing heat into the island-shaped semiconductor layer 2110 by heat treatment or the like, and the means is not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is the same.
[0254]
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film that becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 by using, for example, a thermal oxidation method (FIGS. 339 and 360). At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0255]
Next, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm (FIGS. 340 and 361).
[0256]
Using the silicon nitride films 2314, 2313, and 2312 as the second insulating film as a mask, the polycrystalline silicon film 2510 as the first conductive film is converted into the polycrystalline silicon film 2511 as the first conductive film by anisotropic etching, for example. , 2512, 2513, and 2514 (FIGS. 341 and 362).
[0257]
Next, the silicon nitride films 2312, 2313, and 2314 that are the second insulating films and the silicon nitride film 2321 that is the fourth insulating film are selectively removed, and the polycrystalline silicon that is the divided first conductive film Impurities are introduced into the island-shaped semiconductor layer 2110 and the semiconductor substrate 2100 in self-alignment with the films 2511, 2512, 2513, and 2514. For example, arsenic 1 × 10 as an N-type impurity diffusion layer of 2710 to 2724 using solid phase vapor phase diffusion¹⁸~ 1x10^{twenty one}/ Cm^ThreeIt is formed with a moderate dose. At this time, the impurity concentration of the impurity diffusion layer 2710 serving as the first wiring layer may be adjusted by an ion implantation method or the like (FIGS. 342 and 363). For example, implantation energy of 5 to 100 keV from a direction inclined by about 0 to 7 °, and phosphorus of 1 × 10¹³~ 1x10¹⁵/ Cm²About a dose.
[0258]
Subsequently, for example, a silicon oxide film 2470 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film. Next, a silicon oxide film 2470 that is an eleventh insulating film is buried in the third groove 2230 so as to bury a polycrystalline silicon film 2511 that is a first conductive film that is anisotropically etched (see FIG. 343 and FIG. 343). 364). At this time, the gap between the polycrystalline silicon films 2511 and 2512 as the first conductive film, the gap between the polycrystalline silicon films 2512 and 2513 as the first conductive film, and the polycrystalline silicon film as the first conductive film A silicon oxide film 2470 which is an eleventh insulating film is buried in a gap between 2513 and 2514.
[0259]
Thereafter, the surfaces of the polycrystalline silicon films 2512 to 2514 as the first conductive film and the silicon oxide film 2470 as the eleventh insulating film on the inner wall of the third groove portion 2230 become the twelfth insulating film. For example, a silicon nitride film 2350 is deposited to 5 to 50 nm, and a sidewall is formed by, for example, anisotropic etch back (FIGS. 344 and 365).
[0260]
Subsequently, the silicon oxide film 2470 as the eleventh insulating film is etched back by, for example, isotropic etching to the extent that the side portion of the polycrystalline silicon film 2511 as the first conductive film is exposed. For example, a polycrystalline silicon film 2521 to be a second conductive film is deposited by 15 to 150 nm.
[0261]
Thereafter, the polycrystalline silicon film 2521 as the second conductive film is etched back by anisotropic etching, for example, and then the eleventh insulating film is self-aligned with the polycrystalline silicon film 2521 as the second conductive film. The silicon oxide film 2470 which is a film and the p-type silicon substrate 2100 which is a semiconductor substrate are sequentially etched, a second groove 2220 is formed in the p-type silicon substrate 2100, and the impurity diffusion layer 2710 is separated. That is, the isolation part of the first wiring layer is formed in a self-aligned manner with the isolation part of the second conductive film.
[0262]
Subsequently, the polycrystalline silicon film 2521 as the second conductive film is etched back to the extent that it can come into contact with the polycrystalline silicon film 2511 as the first conductive film to form a selection gate (FIGS. 345 and 366). At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer.
[0263]
Thereafter, as the eleventh insulating film, for example, a silicon oxide film 2471 is deposited to a thickness of about 50 to 500 nm, and the polycrystalline silicon film 2521 as the second conductive film is buried by, for example, anisotropic etching and isotropic etching. In addition, a silicon oxide film 2471 which is an eleventh insulating film is buried in the third groove 2230. At this time, the embedding depth of the silicon oxide film 2471 as the eleventh insulating film is adjusted so that the polycrystalline silicon film 2512 as the second conductive film can be exposed in the future.
[0264]
Thereafter, the sidewall of the silicon nitride film 2350 as the twelfth insulating film is removed by isotropic etching, and an interlayer insulating film 2612 is formed on the exposed surfaces of the polycrystalline silicon films 2512 to 2514 as the first conductive film. Form. The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0265]
Subsequently, a polycrystalline silicon film 2522 serving as a second conductive film is similarly deposited to a thickness of 15 to 150 nm and etched back, so that an interlayer insulating film 2612 is formed on the side of the polycrystalline silicon film 2512 serving as the first conductive film. A polycrystalline silicon film 2522 which is a second conductive film is disposed via At this time, by setting the AA ′ direction in FIG. 1 below a predetermined value in advance, it is formed as a third wiring layer that becomes a control gate line continuous in that direction without using a mask process. (FIGS. 346 and 367).
[0266]
By repeating in the same manner, the polycrystalline silicon film 2523 as the second conductive film is arranged on the side of the polycrystalline silicon film 2513 as the first conductive film with the interlayer insulating film 2613 interposed therebetween (FIGS. 347 and 368). .
[0267]
Thereafter, for example, a silicon oxide film 2472 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film. Subsequently, the silicon oxide film 2472 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2522 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed. At this time, the embedding depth of the silicon oxide film 2472 as the eleventh insulating film is adjusted so that the polycrystalline silicon film 2522 as the second conductive film can be exposed in the future. In the polycrystalline silicon film 2514 which is the uppermost first conductive film, it can be in contact with the polycrystalline silicon film 2514 which is the first conductive film, similarly to the polycrystalline silicon film 2511 which is the lowermost first conductive film. Then, the polycrystalline silicon film 2524 which is the second conductive film is etched back.
[0268]
Subsequently, in order to expose the polycrystalline silicon film 2540 as the fourth conductive film, the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film are formed by, for example, isotropic etching. The silicon oxide film 2475 as the eleventh insulating film is deposited to a thickness of 100 to 500 nm on the polycrystalline silicon film 2524 as the second conductive film, and the fourth conductive film is formed by etch back or CMP. The upper part of the polycrystalline silicon film 2540 is exposed, and the fourth wiring layer 2840 is connected to the upper part of the island-shaped semiconductor layer 2110 so that the direction intersects with the second or third wiring layer.
[0269]
Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0270]
In this manufacturing example, a semiconductor substrate or a polycrystalline silicon film such as a silicon nitride film 2321 which is a fourth insulating film, a silicon nitride film 2330 which is a fifth insulating film, and a silicon nitride film 2350 which is a twelfth insulating film. The film formed on the surface may be a multilayer film of silicon oxide film / silicon nitride film from the silicon surface side.
[0271]
Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0272]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask.
[0273]
On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0274]
Production Example 12
In this manufacturing example, in order to obtain a structure in which the direction of the first wiring layer and the direction of the fourth wiring layer are parallel to each other in a method in which a region in which the charge storage layer is formed in advance by a multilayer film including multiple layers is defined. The example of a specific manufacturing process of is shown.
[0275]
Such a semiconductor memory device can be formed by the following manufacturing method. 374 to 384 and 385 to 395 are sectional views taken along lines AA ′ and BB ′ in FIG.
[0276]
First, in this manufacturing example, the polycrystalline silicon films 2512 to 2514 as the first conductive film and the silicon nitride films 2340, 2342, 2343, 2344 as the sixth insulating films on the inner wall of the third groove 2230, the first For example, a silicon nitride film 2250 to be a twelfth insulating film, for example, 5 to 50 nm is deposited on the surface of the silicon oxide film 2470 which is the eleventh insulating film, and a sidewall is formed by, for example, anisotropic etch back.
[0277]
Subsequently, the silicon oxide film 2470 that is the eleventh insulating film is etched to the extent that the side portion of the polycrystalline silicon film 2511 that is the first conductive film is exposed, for example, until it is etched back by isotropic etching. 1 (FIGS. 83 to 104 and FIGS. 116 to 137).
[0278]
Thereafter, for example, a polycrystalline silicon film 2550 serving as a fifth conductive film is deposited to a thickness of about 50 to 200 nm (FIGS. 374 and 385).
[0279]
Thereafter, for example, a silicon nitride film 2390 is deposited to a thickness of 100 to 300 nm as a nineteenth insulating film by a CVD method (FIGS. 375 and 386). At this time, as shown in FIG. 375, the film thickness is such that the third groove 2230 only in the direction in which the interval between the semiconductor layers 2110 is narrow is filled with the silicon nitride film 2390 which is the nineteenth insulating film.
[0280]
Subsequently, an etch back corresponding to the thickness of the silicon nitride film 2390 which is the nineteenth insulating film deposited by isotropic etching is performed (FIGS. 376 and 387). At this time, as shown in FIG. 376, the upper end portion of the polycrystalline silicon film 2550 as the fifth conductive film is exposed, but the third groove portion 2230 only in the direction in which the interval between the semiconductor layers 2110 is narrow is the nineteenth insulating film. In this state, the silicon nitride film 2390 is buried.
[0281]
Next, a silicon oxide film 2493 is deposited to a thickness of about 50 to 200 nm as a twentieth insulating film (FIGS. 377 and 388). At this time, as shown in FIG. 388, the third groove 2230 only in the direction in which the distance between the semiconductor layers 2110 is wide is filled with the silicon oxide film 2490 which is the sixteenth insulating film.
[0282]
Subsequently, etch back corresponding to the thickness of the deposited silicon oxide film 2493, which is the twentieth insulating film, is performed, and silicon, which is the nineteenth insulating film, remaining in the third groove portion 2230 in FIG. The nitride film 2390 is removed by isotropic etching, and the polycrystalline silicon film 2550 which is the fifth conductive film is etched back by anisotropic etching. At this time, as shown in FIG. 389, the upper end portion of the polycrystalline silicon film 2550, which is the fifth conductive film only in the direction in which the distance between the semiconductor layers 2110 is wide, is exposed and removed, but the third groove portion 2230 is formed in the twentieth portion. Therefore, the lower end portion of the polycrystalline silicon film 2550 which is the fifth conductive film is not removed.
[0283]
Subsequently, a second groove 2220 is formed in the semiconductor substrate 2100 using the polycrystalline silicon film 2550 having a sidewall shape as a mask (FIGS. 378 and 389).
[0284]
Next, a silicon oxide film 2470 which is an eleventh insulating film is buried in the second groove portion 2220. Thereafter, the same process as in Production Example 1 (FIGS. 110 to 114 and 143 to 147) is performed (FIGS. 379 and 390). Thus, a semiconductor having a memory function depending on a charge state stored in a charge storage layer having a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer 2840 are parallel to each other as a floating gate. A storage device is realized.
[0285]
In this manufacturing example, a film formed on the surface of a semiconductor substrate or a polycrystalline silicon film, such as the silicon nitride film 2390 which is the nineteenth insulating film, is a composite of silicon oxide film / silicon nitride film from the silicon surface side. It may be a layer film.
[0286]
In this manufacturing example, the third groove 2230 is opened only in the direction in which the interval between the semiconductor layers 2110 is narrow without using a mask, and the separation groove of the first wiring layer is formed in the semiconductor substrate 2100.
[0287]
On the other hand, for example, the separation groove of the first wiring layer may be formed by a resist patterning process by photolithography. This manufacturing example is shown below.
[0288]
In this manufacturing example, a polycrystalline silicon film 2510 which is a first conductive film, for example, a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 which is a fifth insulating film and a sixth insulating film are formed. Using the silicon nitride films 2340, 2342, 2343, and 2344 as films as masks, the polycrystalline silicon film 2510 as the first conductive film is converted into the polycrystalline silicon films 2511 and 2512 as the first conductive film by anisotropic etching, for example. 2513 and 2514 are the same as in Production Example 1 (FIGS. 83 to 101 and FIGS. 116 to 134).
[0289]
Thereafter, for example, a silicon oxide film 2493 is deposited to a thickness of about 100 to 300 nm as a twentieth insulating film by a CVD method (FIGS. 380 and 391).
[0290]
Subsequently, the silicon oxide film 2493, which is the twentieth insulating film, is etched by reactive ion etching using the resist R4 patterned by a known photolithography technique as a mask.
[0291]
Next, anisotropic etching is performed using the silicon nitride film 2321 as the fourth insulating film, the silicon oxide film 2411 as the first insulating film, and the silicon oxide film 2493 as the twentieth insulating film as a mask. As a result, a second groove 2220 is formed in the semiconductor substrate 2100 (FIGS. 381 and 392).
[0292]
Next, an oxide film 2470 which is an eleventh insulating film is buried in the second groove 2220.
[0293]
Thereafter, the same process as in Production Example 1 (FIGS. 110 to 114 and 143 to 147) is performed (FIGS. 382 and 393). Thus, a semiconductor memory having a memory function depending on a charge state stored in a charge storage layer having a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer are parallel as a floating gate. The device is realized.
[0294]
As another method, until the silicon oxide film 2493 which is the twentieth insulating film is etched by reactive ion etching using the resist R4 patterned by a known photolithography technique as a mask, FIG. 380 and FIG. Same as 391.
[0295]
Thereafter, the silicon oxide film 2493 which is the twentieth insulating film partially remaining in the third groove 2230 is removed by isotropic etching, and the direction of FIG. 383 is the twentieth insulating film in the third groove 2230. The silicon oxide film 2493 is not left, and the silicon oxide film 2493 which is the twentieth insulating film is left in the third groove 2230 in the direction of FIG. 394 (FIGS. 383 and 394).
[0296]
Subsequently, anisotropic etching is performed using the silicon nitride film 2321 as the fourth insulating film, the silicon oxide film 2411 as the first insulating film, and the silicon oxide film 2493 as the twentieth insulating film as a mask. As a result, the second groove 2220 is formed in the semiconductor substrate 2100 (FIGS. 384 and 395).
[0297]
Next, a silicon oxide film 2470 which is an eleventh insulating film is buried in the second groove 2220.
[0298]
Thereafter, the same process as in Production Example 1 (FIGS. 110 to 114 and FIGS. 143 to 147) is performed. Thus, a semiconductor memory having a memory function depending on a charge state stored in a charge storage layer having a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer are parallel as a floating gate. The device is realized.
[0299]
Production Example 13
An example of a specific manufacturing process for obtaining a structure in which the first wiring layer is common to the memory array in a technique in which a region in which the charge storage layer is formed in advance by a multilayer film composed of a plurality of layers will be described.
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 396 to 397 and 398 to 399 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0300]
In this manufacturing example, the second groove portion 2220 is not formed in the semiconductor substrate 2100, and the process related to this is omitted from the manufacturing example 1 (FIGS. 83 to 114 and FIGS. 116 to 147).
As a result, at least the first wiring layer in the array is shared without being divided, and has a memory function depending on the charge state stored in the charge storage layer using the polycrystalline silicon film serving as the first conductive film as a floating gate. A semiconductor memory device is realized.
[0301]
Production Example 14
An example of a specific manufacturing process for obtaining a structure in which the surface area of the floating gate is increased will be described in a method in which a region in which the charge storage layer is formed in advance by a multilayer film composed of multiple layers is defined.
[0302]
Such a semiconductor memory device can be formed by the following manufacturing method. 400 to 403 and 404 to 407 are sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
As shown in FIGS. 400 to 403 and 404 to 407, the polycrystalline silicon film 2510, which is the first conductive film covered with the semiconductor layer 2110, is uniform along the concave shape in which the floating gate is defined. To deposit. This increases the junction capacitance of the control gate.
[0303]
Production Example 15
An example of a manufacturing process in which the lengths in the vertical direction of the gates of these transistors are different in a method in which a region in which a charge storage layer is formed in advance by a multilayer film composed of multiple layers will be described.
[0304]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 408 to 411 and FIGS. 412 to 415 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0305]
The length in the direction perpendicular to the semiconductor substrate 2100 of the polycrystalline silicon films 2511 to 2514 which are the first conductive films to be the gates or select gates of the memory cells is shown in FIGS. 408 to 409 and FIGS. 412 to 413. As shown in FIGS. 410 to 411 and FIGS. 414 to 415, even if the gate lengths of the polycrystalline silicon films 2512 and 2513 which are the first conductive films are different, Even if the selection gate lengths of the crystalline silicon films 2511 and 2514 are different, the lengths in the vertical direction of the polycrystalline silicon films 2511 to 2514 which are the first conductive films may not be the same length.
[0306]
Production Example 16
A specific example of a manufacturing process in which the shape of the island-like semiconductor layer is different in a method in which a region in which the charge storage layer is formed in advance by a multilayer film including multiple layers will be described.
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 416 to 417 and 418 to 419 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0307]
When the first groove 2210 is formed by reactive ion etching, as shown in FIGS. 416 and 418, even if the outer shapes of the upper and lower ends of the semiconductor layer 2110 are different, as shown in FIGS. The horizontal position of the upper end portion and the lower end portion of the semiconductor layer 2110 may be shifted.
[0308]
For example, when the island-like semiconductor layer 2110 has a circular shape as shown in FIG. 1, it has a conical shape in FIGS. 416 and 418, and an oblique cylinder in FIGS. 417 and 419.
[0309]
Further, the shape of the island-shaped semiconductor layer 2110 is not particularly limited as long as memory cells can be arranged in series in a direction perpendicular to the semiconductor substrate 2100.
[0310]
Production Example 17
A specific example of a manufacturing process in which the bottom shape of the island-like semiconductor layer is different in a method in which a region in which the charge storage layer is formed in advance by a multilayer film including multiple layers will be described.
Such a semiconductor memory device can be formed by the following manufacturing method. 420 to 427 and 428 to 435 are sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0311]
The bottom shape of the first groove 2210 may have a partially or entirely rounded inclined structure as shown in FIGS. 420 and 428, 424 and 432, 426 and 434.
[0312]
Thereafter, the semiconductor memory device shown in FIGS. 421 and 429, FIGS. 425 and 433, FIGS. 427 and 435 is formed by a method according to Manufacturing Example 1. Here, even if the lower end portion of the polycrystalline silicon film 2511 serving as the first conductive film reaches the inclined portion of the bottom portion of the first groove 2210, the lower end portion of the polycrystalline silicon film 2511 serving as the first conductive film. However, it does not have to go to the inclined portion at the bottom of the first groove 2210.
[0313]
Further, as shown in FIGS. 422 to 423 and FIGS. 430 to 431, the bottom shape of the first groove 2210 having a lattice pattern may have an inclined structure.
[0314]
Production Example 18
A specific manufacturing process for forming a sidewall of a silicon oxide film on the inner side of a hole-like groove in which an island-like semiconductor layer is formed in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers An example is shown.
Such a semiconductor memory device can be formed by the following manufacturing method. 436 to 437 and 438 to 439 are cross-sectional views taken along lines AA ′ and BB ′ in FIG.
[0315]
As shown in FIGS. 436 and 438, after forming a hole, a silicon oxide film 2495, for example, is deposited as a twenty-third insulating film by CVD, for example, 2-20 nm inside the hole, for example, anisotropic. A side wall is formed inside the hole by etching. As a result, when the island-shaped semiconductor layer is formed by selective epitaxial silicon growth from the semiconductor substrate, the island-shaped semiconductor layer is not in contact with the silicon nitride film, and nitridation of the island-shaped semiconductor layer can be prevented (FIGS. 437 and 439).
[0316]
Production Example 19
An example of a specific manufacturing process in which the shape of the polycrystalline silicon film deposited on the base step portion is made different in the method in which the region where the charge storage layer is formed in advance by the multilayer film composed of a plurality of layers is shown.
Such a semiconductor memory device can be formed by the following manufacturing method. 440 to 445 and 446 to 451 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0317]
As shown in FIGS. 440 to 441 and FIGS. 446 to 447, FIGS. 442 to 443, and FIGS. 448 to 449, the polycrystalline silicon film 2510 which is the first conductive film covered with the semiconductor layer 2110 You may exhibit the structure deposited uniformly along the bottom shape of the one groove part 2210. FIG. Further, as shown in FIGS. 444 and 450, 445 and 451, a structure in which the first groove 2210 is partially unevenly deposited may be exhibited depending on the bottom shape.
[0318]
Production Example 20
A specific example of a manufacturing process in the case where there is no polycrystalline silicon film 2540 as a fourth conductive film in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers will be described.
Such a semiconductor memory device can be formed by the following manufacturing method. 452 to 453 and FIGS. 454 to 455 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
The semiconductor memory device shown in FIGS. 452 to 453 and FIGS. 454 to 455 is formed by a method according to Manufacturing Example 1.
[0319]
Production Example 21
A specific manufacturing process in which a hole-like groove portion in which an island-like semiconductor layer is formed by a photoresist mask is misaligned with respect to a floating gate in a technique in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers An example is shown.
Such a semiconductor memory device can be formed by the following manufacturing method. 456 to 458 and 459 to 461 are sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0320]
As shown in FIGS. 456 to 458 and FIGS. 459 to 461, the charge storage region defined by the semiconductor layer 2110 and the resist R2 defined by the resist R1 is not necessarily symmetrical due to the misalignment of the resists R1 and R2. The semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer even if it is not formed in a symmetric shape.
[0321]
Production Example 22
After defining the region where the charge storage layer is formed in advance by the multilayer film consisting of multiple layers, the island-like semiconductor layer, the floating gate and the control gate are formed in a self-aligned manner from the same mask, and the hole-like groove is opened. An island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth, and a floating gate is formed as a tunnel oxide film and a charge storage layer on a side wall of the island-shaped semiconductor layer and in a region where the charge storage layer is formed. In the semiconductor memory device in which the floating region is electrically floated with respect to the substrate and the active region of each memory cell is electrically floated, select gate transistors are disposed on the top and bottom of the island-shaped semiconductor layer, A plurality of, for example, two memory transistors are disposed between the select gate transistors, and each of the memory transistors includes a tunnel oxide film and a floating oxide film. The present invention has a structure in which gates are formed in a lump, each transistor is connected in series along the island-like semiconductor layer, and the gate insulating film thickness of the selection gate transistor is equal to the gate insulating film thickness of the memory transistor. The embodiment will be described.
[0322]
Such a semiconductor memory device can be formed by the following manufacturing method. 462 to 469 and 470 to 477 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0323]
An insulating film containing an impurity is formed on the surface of the p-type silicon substrate 2100 by a CVD method. For example, arsenic 1 × 10 as a first insulating film¹⁸~ 1x10^{twenty two}/ Cm^ThreeA silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm. At this time, the insulating film containing impurities may be introduced into the insulating film by ion implantation after the insulating film is deposited by a CVD method. For example, after depositing a silicon oxide film 2411 as a first insulating film by 50 to 500 nm, arsenic 1 × 10 at an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 45 °.¹⁴~ 1x10¹⁶/ Cm²About a dose is introduced into the silicon oxide film 2411 which is the first insulating film. Further, the introduction of impurities into the silicon oxide film 2411 that is the first insulating film by ion implantation may not be performed immediately after the silicon oxide film 2411 that is the first insulating film is deposited. When an impurity is introduced into the silicon oxide film 2411 which is the first insulating film by ion implantation, the implantation inclination angle is not limited as long as a desired impurity concentration can be obtained. Further, the introduction of impurities into the silicon oxide film 2411 as the first insulating film is not limited to ion implantation, and solid phase vapor phase diffusion may be used. Thereafter, for example, a silicon nitride film 2321 is deposited as a fourth insulating film by 10 to 100 nm. Here, when the impurity introduction into the silicon oxide film 2411 which is the first insulating film described above is performed by ion implantation, the first insulation is performed by the ion implantation method through the silicon nitride film 2321 which is the fourth insulating film. Impurities may be introduced into the silicon oxide film 2411 which is a film.
[0324]
Subsequently, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm as the third insulating film, and a silicon nitride film 2312 is deposited by 10 to 100 nm as the second insulating film, and the silicon oxide film 2412 as the first insulating film is deposited. Is deposited in a thickness of 50 to 500 nm.
[0325]
After sequentially forming in this way, as shown in FIGS. 462 and 470, as a first insulating film, for example, a silicon oxide film 2415 is deposited by 50 to 500 nm, and then a silicon nitride film 2325 as a fourth insulating film is formed by 10 For example, a silicon oxide film 2480 is deposited to a thickness of 100 to 1000 nm as the fourteenth insulating film.
[0326]
Subsequently, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 462 and 470), the silicon oxide film 2480 and the fourth insulating film, which are fourteenth insulating films, are formed by reactive ion etching, for example. A silicon nitride film 2315 as a first insulating film, a silicon nitride film 2315 as a second insulating film, a silicon oxide film 2424 as a third insulating film, and a second insulating film A silicon nitride film 2314, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, a silicon oxide film 2422 as a third insulating film, and a silicon as a second insulating film A nitride film 2312; a silicon oxide film 2421 as a third insulating film; a silicon nitride film 2321 as a fourth insulating film; Forming a fourth groove 2240 are sequentially etched silicon oxide film 2411 is an insulating film (FIG. 463 and FIG. 471).
[0327]
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240 to form a sixth groove 2260 (FIGS. 464 and 472). At this time, the island-shaped semiconductor layer 2110 may be grown on the upper surface of the silicon nitride film 2325 which is the fourth insulating film, or is epitaxially grown at least to the side of the silicon oxide film 2415 which is the first insulating film. Alternatively, after the semiconductor layer is selectively epitaxially grown, it does not reach the lower surface of the silicon nitride film 2315 which is the fourth insulating film by etch back using isotropic etching or etch back using anisotropic etching. Etchback is performed to the extent to form the island-shaped semiconductor layer 2110 described above. Further, the island-shaped semiconductor layer 2110 may be formed by combining the etch-back after planarizing and embedding the island-shaped semiconductor layer 2110 using CMP.
[0328]
Thereafter, for example, a polycrystalline silicon film 2540 is deposited to a thickness of about 100 to 300 nm as the fourth conductive film, etched back to remain at the bottom of the sixth groove 2260, and further, the fifth groove 2260 has a fifth After a silicon nitride film 2330 is deposited as an insulating film to a thickness of about 200 to 2000 nm, etch back using isotropic etching or anisotropic etching, planarization embedding using CMP, or the like is performed. At this time, at least the silicon oxide film 2480 which is the fourteenth insulating film is exposed (FIGS. 465 and 473).
[0329]
Subsequently, the silicon oxide film 2480 as the fourteenth insulating film is selectively removed, and after removing the silicon oxide film 2480 as the fourteenth insulating film by, for example, isotropic etching, the fifteenth insulating film is removed. After a silicon nitride film 2370 is deposited to a thickness of about 20 to 200 nm as a film, a sidewall is formed on the sidewall of the silicon nitride film 2330 which is the fifth insulating film by using anisotropic etching. Using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2370 as the fifteenth insulating film as a mask, for example, by reactive ion etching, the silicon nitride film 2325 as the fourth insulating film, The silicon oxide film 2415 that is the insulating film is sequentially etched to expose the silicon nitride film 2315 that is the second insulating film. At this time, the silicon nitride film 2315 as the second insulating film may be etched until the silicon oxide film 2424 as the third insulating film is exposed.
[0330]
Subsequently, a silicon nitride film 2340 is deposited as a sixth insulating film to a thickness of about 5 to 50 nm, and a silicon nitride film 2330 as a fifth insulating film and a fourth conductive film are formed using anisotropic etching, for example. A silicon nitride film 2340 which is a sixth insulating film having a sidewall shape is disposed on the side walls of the crystalline silicon film 2540, the silicon nitride film 2325 which is the fourth insulating film, and the silicon oxide film 2415 which is the first insulating film. (FIGS. 467 and 475). At this time, the silicon oxide film 2415 containing impurities as the first insulating film is replaced with the silicon nitride film 2325 as the fourth insulating film, the silicon nitride film 2315 as the second insulating film, and the silicon as the sixth insulating film. The nitride film 2340 is isolated from the parts other than the island-shaped semiconductor layer 2110 (FIGS. 468 and 476).
[0331]
Thereafter, the same process as in Manufacturing Example 1 (FIGS. 90 to 114 and FIGS. 124 to 147) is performed to form an interlayer insulating film and a contact hole and a metal wiring by a known technique.
[0332]
Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0333]
In this manufacturing example, a semiconductor substrate or polycrystalline silicon such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film. The film formed on the surface of the film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0334]
Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0335]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
[0336]
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0337]
Production Example 23
In the semiconductor memory device formed in this embodiment, a region in which a charge storage layer is formed in advance is defined by a multi-layered film, and then the island-shaped semiconductor layer, the floating gate, and the control gate are self-aligned from the same mask. The island-shaped semiconductor layer is formed in a column shape by selective epitaxial silicon growth in the opened hole-shaped groove, and is floated as a tunnel oxide film and a charge storage layer in the region where the charge storage layer is formed on the side wall of the island-shaped semiconductor layer In a semiconductor memory device in which a gate is formed, the island-shaped semiconductor layer is electrically floated with respect to a semiconductor substrate, and an active region of each memory cell is electrically common, A selection gate transistor is arranged at the bottom, and a plurality of memory transistors, for example two, are arranged between the selection gate transistors. The tunnel oxide film and the floating gate of the star are formed together, and each transistor is connected in series along the island-like semiconductor layer, and the gate insulating film thickness of the selection gate transistor is the gate insulating film thickness of the memory transistor. An embodiment of the present invention having the same structure as will be described.
[0338]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 478 to 516 and FIGS. 517 to 555 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0339]
First, for example, arsenic 1 × 10 as a first insulating film that becomes an insulating film containing impurities on the surface of the p-type silicon substrate 2100 by a CVD method.¹⁸~ 1x10^{twenty two}/ Cm^ThreeA silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm. At this time, the insulating film containing impurities may be introduced into the insulating film by ion implantation after the insulating film is deposited by a CVD method. For example, after depositing a silicon oxide film 2411 as a first insulating film by 50 to 500 nm, arsenic 1 × 10 at an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 45 °.¹⁴~ 1x10¹⁶/ Cm²About a dose is introduced into the silicon oxide film 2411 which is the first insulating film. Further, the introduction of impurities into the silicon oxide film 2411 that is the first insulating film by ion implantation may not be performed immediately after the silicon oxide film 2411 that is the first insulating film is deposited. When an impurity is introduced into the silicon oxide film 2411 which is the first insulating film by ion implantation, the implantation inclination angle is not limited as long as a desired impurity concentration can be obtained. Further, the introduction of impurities into the silicon oxide film 2411 as the first insulating film is not limited to ion implantation, and solid phase vapor phase diffusion may be used.
[0340]
Thereafter, for example, a silicon nitride film 2321 is deposited as a fourth insulating film by 10 to 100 nm. Here, when the impurity introduction into the silicon oxide film 2411 which is the first insulating film described above is performed by ion implantation, the first insulating film is formed by ion implantation over the silicon nitride film 2321 which is the fourth insulating film. Impurities may be introduced into the silicon oxide film 2411.
[0341]
Subsequently, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm as a third insulating film, and a silicon nitride film 2312 is deposited by 10 to 100 nm as a second insulating film, and a silicon oxide film 2412 as a first insulating film is formed. Deposit 50-500 nm.
[0342]
After sequentially forming in this way, as shown in FIGS. 478 and 517, as a first insulating film, for example, a silicon oxide film 2415 is deposited to a thickness of 50 to 500 nm, and then a silicon nitride film 2325 which is a fourth insulating film is formed to 100. A silicon nitride film 2325, which is a fourth insulating film, is formed by reactive ion etching, for example, by using as a mask a resist R1 deposited by ˜1000 nm and then patterned by a known photolithography technique (FIGS. 479 and 518). , A silicon oxide film 2415 as a first insulating film, a silicon nitride film 2315 as a second insulating film, a silicon oxide film 2424 as a third insulating film, a silicon nitride film 2314 as a second insulating film, A silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, and a third insulating film A silicon oxide film 2422, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, a silicon nitride film 2321 as a fourth insulating film, and silicon as a first insulating film The oxide film 2411 is sequentially etched to form a fourth groove 2240 (FIGS. 480 and 519).
[0343]
After removing the resist R1 (FIGS. 481 and 520), the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240 (FIGS. 482 and 521).
[0344]
Further, the island-like semiconductor layer 2110 is planarized with respect to the silicon nitride film 2325 which is the fourth insulating film (FIGS. 483 and 522). At this time, etch back using isotropic etching, etch back using anisotropic etching, planarization embedding using CMP, or various combinations may be used.
[0345]
The silicon nitride film 2325 as the fourth insulating film is etched back by, for example, anisotropic etching to form a seventh groove 2270 (FIGS. 484 and 523).
[0346]
Thereafter, a silicon oxide film 2490 is deposited to a thickness of about 20 to 200 nm as a sixteenth insulating film in the seventh groove 2270, and etched back by anisotropic etching, for example, and a sidewall is formed on the side of the island-shaped semiconductor layer 2110. (FIGS. 485 and 524).
[0347]
Subsequently, as a seventeenth insulating film in the seventh groove 2270, for example, a silicon nitride film 2380 is deposited to a thickness of about 20 to 200 nm, and etched back by, for example, anisotropic etching, and the seventeenth groove 2270 is in the seventeenth groove 2270. A silicon nitride film 2380 which is an insulating film is buried.
[0348]
Subsequently, the island-shaped semiconductor layer 2110 is etched back by anisotropic etching, for example, to form an eighth groove 2280. At this time, the etch back may be performed to the extent that a part of the silicon nitride film 2325 as the fourth insulating film is exposed, the etch back may be performed to the extent that it is not exposed, or the first insulating film It suffices if the island-shaped semiconductor layer 2110 remains on the side portion of the silicon oxide film 2415 (FIGS. 487 and 526).
[0349]
Thereafter, the silicon oxide film 2490, which is the sixteenth insulating film, is selectively removed by, for example, isotropic etching (FIGS. 488 and 527), and a fourth conductive film is formed in the eighth groove 2280 as, for example, polycrystalline. A silicon film 2540 is deposited to a thickness of about 100 to 300 nm, and is embedded in the eighth groove 2280 later using CMP (FIGS. 489 and 528).
[0350]
Using the polycrystalline silicon film 2540 as the fourth conductive film as a mask, the silicon nitride film 2380 as the seventeenth insulating film, the silicon nitride film 2325 as the fourth insulating film, and the silicon oxide film as the first insulating film 2415 is sequentially etched by, for example, anisotropic etching to form a third groove 2230 (FIGS. 490 and 529).
[0351]
Subsequently, a silicon nitride film 2340 is deposited to a thickness of about 5 to 50 nm as a sixth insulating film, and the fourth conductive film is a polycrystalline silicon film 2540 and a fourth insulating film, for example, using anisotropic etching. A silicon nitride film 2340 which is a sixth insulating film having a sidewall shape is disposed on the side walls of the silicon nitride film 2325 and the silicon oxide film 2415 which is the first insulating film (FIGS. 491 and 530). At this time, the silicon oxide film 2415 containing impurities as the first insulating film is replaced with the silicon nitride film 2325 as the fourth insulating film, the silicon nitride film 2315 as the second insulating film, and the silicon as the sixth insulating film. The nitride film 2340 is isolated from the parts other than the island-shaped semiconductor layer 2110 (FIGS. 492 and 531).
[0352]
Subsequently, using the polycrystalline silicon film 2540 as the fourth conductive film and the silicon nitride film 2340 as the sixth insulating film as a mask, the silicon nitride film 2315 as the second insulating film and the silicon as the third insulating film are used. Oxide film 2424, silicon nitride film 2314 as the second insulating film, silicon oxide film 2423 as the third insulating film, silicon nitride film 2313 as the second insulating film, silicon oxide film as the third insulating film 2422 and the silicon nitride film 2312 as the second insulating film are sequentially etched to form the third groove 2230 so that the silicon oxide film 2421 as the third insulating film is exposed (FIGS. 492 and 531).
[0353]
Thereafter, the silicon oxide films 2421, 2422, 2423, and 2424, which are third insulating films, are removed by, for example, isotropic etching to expose the side surfaces of the island-shaped semiconductor layer 2110 (FIGS. 493 and 532).
[0354]
Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form, for example, a thermal oxide film 2450 having a thickness of 10 to 100 nm, which becomes a ninth insulating film.
[0355]
Next, the thermal oxide film 2450 that is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching, and then each island-shaped semiconductor layer is utilized using oblique ion implantation as necessary. Channel ion implantation is performed on the side wall of 2110. For example, implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2421, 2422, 2423, 2424 which are the third insulating films, and the silicon oxide films 2421, 2422, 2423 which are the third insulating films. , 2424 may be removed by introducing heat into the island-shaped semiconductor layer 2110 by heat treatment or the like, and the means is not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is the same.
[0356]
Next, for example, a silicon oxide film 2460 is formed as a tenth insulating film that becomes a tunnel oxide film of, for example, about 10 nm around each island-shaped semiconductor layer 2110 by using, for example, a thermal oxidation method. At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0357]
Subsequently, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm (FIGS. 494 and 533), and the fourth conductive film is a polycrystalline silicon film 2540 and a sixth insulating film. Using the silicon nitride film 2340 and the silicon nitride films 2342, 2343, and 2344, which are the second insulating films, as a mask, the polycrystalline silicon film 2510, which is the first conductive film, is formed, for example, by anisotropic etching or isotropic etching. Are divided into polycrystalline silicon films 2511, 2512, 2513, and 2514, which are conductive films (FIGS. 495 and 534).
[0358]
Subsequently, for example, a silicon oxide film 2470 of about 50 to 500 nm is deposited as the eleventh insulating film (FIGS. 496 and 535).
[0359]
Next, the silicon oxide film 2470 as the eleventh insulating film is formed in the third groove 2230 so as to bury the polycrystalline silicon film 2511 as the first conductive film by, for example, anisotropic etching and isotropic etching. (FIGS. 497 and 536). At this time, the embedding depth of the silicon oxide film 2470 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2312 as the second insulating film is exposed.
[0360]
Thereafter, polycrystalline silicon films 2512 to 2514 that are the first conductive film on the inner wall of the third groove portion 2230, a silicon nitride film 2340 that is the sixth insulating film, and a silicon nitride film 2342 that is the second insulating film, 2343, 2344, and a silicon oxide film 2470 as an eleventh insulating film, for example, a silicon nitride film 2350 to be a twelfth insulating film is deposited in a thickness of 5 to 50 nm. At this time, a mask for forming a control gate line continuous in one direction without using a new photoresist mask process by setting the AA ′ direction in FIG. 1 to a predetermined value or less in advance. Are self-aligned. That is, the deposited film thickness of the silicon nitride film 2350, which is the twelfth insulating film, is set to ½ or more of the width of the third groove 2230 determined by the silicon nitride film 2340, which is the sixth insulating film. In this case, the third groove 2230 is filled with the silicon nitride film 2350 which is the twelfth insulating film only in the AA ′ direction in FIG. Note that the concave portion in which the deposited film thickness of the silicon nitride film 2350 as the twelfth insulating film is determined by the polycrystalline silicon films 2511, 2512, 2513, and 2514 as the first conductive film is the silicon as the twelfth insulating film. The film thickness is set so that it is not completely filled with the nitride film 2350 (FIGS. 498 and 537).
[0361]
Subsequently, the silicon nitride film 2350, which is the twelfth insulating film, is etched back by anisotropic etching, for example, so that the silicon oxide film 2470, which is the eleventh insulating film, is exposed as shown in FIG. Form side walls. At this time, as shown in FIG. 499, the third groove 2230 in the A-A ′ direction of FIG. 1 is filled with the silicon nitride film 2350 which is the twelfth insulating film.
[0362]
Next, the silicon oxide film 2470 as the eleventh insulating film is etched back by, for example, isotropic etching to the extent that the side portion of the polycrystalline silicon film 2511 as the first conductive film is exposed (FIG. 500). Then, for example, a polycrystalline silicon film 2521 to be a second conductive film is deposited by 15 to 150 nm.
[0363]
Thereafter, the polycrystalline silicon film 2521 as the second conductive film is etched back by, for example, anisotropic etching (FIGS. 501 and 540), and then, as shown in FIG. A silicon nitride film 2321 that is a fourth insulating film, a silicon oxide film 2411 that is a first insulating film, and a p-type silicon substrate 2100 that is a semiconductor substrate are sequentially etched in a self-aligned manner with a polycrystalline silicon film 2521 to form a p-type. A second groove 2220 is formed in the silicon substrate 2100 and the impurity diffusion layer 2710 is separated.
[0364]
That is, the isolation part of the first wiring layer is formed in a self-aligned manner with the isolation part of the second conductive film (FIGS. 502 and 541). At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer.
[0365]
Thereafter, the silicon nitride film 2350 as the twelfth insulating film on the surfaces of the polycrystalline silicon films 2512, 2513, and 2514 as the first conductive film is removed by isotropic etching (FIGS. 503 and 542). That is, the surfaces of the polycrystalline silicon films 2512, 2523, and 2514 that are the first conductive films are exposed by performing isotropic etching corresponding to the deposited film thickness of the silicon nitride film 2350 that is the twelfth insulating film. Can do. At this time, as shown in FIG. 503, the third groove 2230 in the A-A ′ direction of FIG. 1 is filled with the silicon nitride film 2350 which is the twelfth insulating film.
[0366]
Subsequently, as an eleventh insulating film, for example, a silicon oxide film 2471 is deposited to a thickness of about 50 to 500 nm, and a polycrystalline silicon film 2521 that is a second conductive film is buried by, for example, anisotropic etching and isotropic etching. In this manner, the silicon oxide film 2471 which is the eleventh insulating film is buried in the second groove portion 2220 and the third groove portion 2230 (FIGS. 504 and 543). At this time, the embedding depth of the silicon oxide film 2471 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2312 as the second insulating film is exposed.
[0367]
Next, an interlayer insulating film 2612 is formed on the exposed surfaces of the polycrystalline silicon films 2512 to 2514 which are the first conductive films (FIGS. 505 and 544). The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0368]
Subsequently, a polycrystalline silicon film 2520 to be the second conductive film is similarly deposited by 15 to 150 nm (FIGS. 506 and 545).
[0369]
A silicon oxide film 2472 that is an eleventh insulating film is deposited to a thickness of about 50 to 500 nm, and is then passed through a polycrystalline silicon film 2520 and an interlayer insulating film 2612 that are second conductive films by, for example, anisotropic etching and isotropic etching. Then, the silicon oxide film 2472 as the eleventh insulating film is buried in the third groove 2230 so as to bury the polycrystalline silicon film 2513 as the first conductive film (FIGS. 507 and 546).
[0370]
Next, using the silicon oxide film 2472 as the eleventh insulating film as a mask to expose the polycrystalline silicon film 2514 as the first conductive film, the polycrystalline film as the second conductive film is formed by, for example, isotropic etching. The silicon film 2520 and the interlayer insulating film 2612 are partially removed (FIGS. 508 to 509 and FIGS. 547 to 548).
[0371]
Subsequently, after removing the silicon oxide film 2472 as the eleventh insulating film (FIGS. 510 and 549), the polycrystalline silicon films 2522 and 2523 as the second conductive film are dividedly formed by anisotropic etching, for example. To do. At this time, since the polysilicon films 2522 and 2523 which are the second conductive films are previously separated by the silicon nitride film 2350 which is the twelfth insulating film, the first conductive film is formed. Polycrystalline silicon films 2522 and 2523, which are second conductive films, can be simultaneously disposed on the sides of the polycrystalline silicon film 2512 with an interlayer insulating film 2612 interposed therebetween (FIGS. 511 and 550).
[0372]
Next, a silicon oxide film 2473, which is an eleventh insulating film, is deposited to a thickness of about 50 to 500 nm (FIGS. 512 and 551), and a polycrystal which is a second conductive film is formed by anisotropic etching and isotropic etching, for example. A silicon oxide film 2473 which is an eleventh insulating film is buried in the third groove 2230 so as to bury the silicon films 2522 and 2523 (FIGS. 513 and 552). In the polycrystalline silicon film 2514 which is the uppermost first conductive film, the polycrystalline silicon film 2524 which is the second conductive film is etched back to such an extent that it can come into contact with the polycrystalline silicon film 2514 which is the first conductive film. (FIGS. 514 and 553).
[0373]
Subsequently, a silicon oxide film 2474 as an eleventh insulating film is deposited to a thickness of 100 to 500 nm on the polycrystalline silicon film 2524 as the second conductive film, and the fourth conductive film is formed by etch back or CMP. The upper part of the polycrystalline silicon film 2540 is exposed, and the fourth wiring layer is connected to the upper part of the island-like semiconductor layer 2110 so that the direction intersects with the second or third wiring layer.
[0374]
Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring.
[0375]
Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0376]
In this manufacturing example, the film formed on the surface of the semiconductor substrate or polycrystalline silicon film, such as the silicon nitride film 2340 as the sixth insulating film and the silicon nitride film 2350 as the twelfth insulating film, is on the silicon surface side. Alternatively, a multilayer film of silicon oxide film / silicon nitride film may be used. Further, impurities of the polycrystalline silicon film 2510 or 2511 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0377]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0378]
Production Example 24
Example of a specific manufacturing process for obtaining a structure in which a wiring layer is separated by a photolithography resist patterning process in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers Shown below.
Such a semiconductor memory device can be formed by the following manufacturing method. 556 to 562 and FIGS. 563 to 569 are sectional views taken along lines AA ′ and BB ′ in FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0379]
First, the polycrystalline silicon films 2512 to 2514 as the first conductive film and the silicon nitride films 2340, 2342, 2343, and 2344 as the sixth insulating films on the inner wall of the third trench 2230, the eleventh insulating film For example, a silicon nitride film 2350, which becomes a twelfth insulating film, is deposited on the surface of the silicon oxide film 2470, which is 5 to 50 nm, and a sidewall is formed by, for example, anisotropic etch back.
[0380]
Subsequently, the silicon oxide film 2470 that is the eleventh insulating film is etched to the extent that the side portion of the polycrystalline silicon film 2511 that is the first conductive film is exposed, for example, until it is etched back by isotropic etching. 1 (FIGS. 83 to 104 and FIGS. 116 to 137).
[0381]
Thereafter, for example, a polycrystalline silicon film 2521 to be a second conductive film is deposited by 30 to 300 nm (FIGS. 556 and 563).
[0382]
Next, the polycrystalline silicon film 2521 that is the second conductive film is etched back by, for example, anisotropic etching, and then the second conductive film is contacted with the polycrystalline silicon film 2511 that is the first conductive film. The polycrystalline silicon film 2521 which is the second conductive film is etched back to form a selection gate (FIGS. 557 and 564).
[0383]
Subsequently, the sidewall of the silicon nitride film 2350, which is the twelfth insulating film, is removed by isotropic etching, and a silicon oxide film 2471, for example, is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film.
[0384]
Next, the silicon oxide film 2471 as the eleventh insulating film is formed in the third groove portion 2230 so as to bury the polycrystalline silicon film 2521 as the second conductive film by, for example, anisotropic etching and isotropic etching. Embed in. At this time, the embedding depth of the silicon oxide film 2471 as the eleventh insulating film is adjusted so that a part of the silicon nitride film 2342 as the sixth insulating film is exposed.
[0385]
Subsequently, an interlayer insulating film 2612 is formed on the exposed surfaces of the polycrystalline silicon films 2512 to 2514 which are the first conductive films. The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0386]
Next, similarly, a polycrystalline silicon film 2522 serving as a second conductive film is deposited to a thickness of 30 to 300 nm, and etched back, so that an interlayer insulating film 2612 is formed on the side of the polycrystalline silicon film 2512 serving as the first conductive film. A polycrystalline silicon film 2522 which is a second conductive film is disposed via By repeating in the same manner, the polycrystalline silicon film 2523 as the second conductive film is disposed on the side of the polycrystalline silicon film 2513 as the first conductive film with the interlayer insulating film 2613 interposed therebetween. In the polycrystalline silicon film 2514 which is the uppermost first conductive film, it can be in contact with the polycrystalline silicon film 2514 which is the first conductive film, similarly to the polycrystalline silicon film 2511 which is the lowermost first conductive film. Then, the polycrystalline silicon film 2524 which is the second conductive film is etched back (FIGS. 558 and 565).
[0387]
Next, in order to expose the polycrystalline silicon film 2540 that is the fourth conductive film, the silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2340 that is the sixth insulating film are formed by isotropic etching, for example. After removing (FIGS. 559 and 566), a silicon oxide film 2474 as an eleventh insulating film is deposited on the upper layer of the polycrystalline silicon film 2524 as the second conductive film to a thickness of 100 to 500 nm. Using the resist R3 patterned by the lithography technique as a mask (FIGS. 560 and 567), the silicon oxide film 2474, which is the eleventh insulating film, is etched by, for example, reactive ion etching, and then the second conductive A polycrystalline silicon film 2524 as a film, a silicon oxide film 2473 as an eleventh insulating film, and a polycrystalline silicon film as a second conductive film. CON film 2523, interlayer capacitor film 2613, silicon oxide film 2472 as the eleventh insulating film, polycrystalline silicon film 2522 as the second conductive film, interlayer capacitor film 2612, silicon oxide as the eleventh insulating film A film 2471, a polycrystalline silicon film 2521 as a second conductive film, a silicon nitride film 2321 as a fourth insulating film, a silicon oxide film 2411 as a first insulating film, and a p-type silicon substrate 2100 as a semiconductor substrate are formed. Etching is performed sequentially to form a second groove 2220 in the p-type silicon substrate 2100 and to separate the impurity diffusion layer 2710 (FIGS. 561 and 568).
[0388]
Subsequently, a silicon oxide film 2475 which is an eleventh insulating film is deposited to a thickness of 100 to 500 nm, and an upper portion of the polycrystalline silicon film 2540 which is the fourth conductive film is exposed by an etch back or CMP method. The wiring layer is connected to the upper part of the island-shaped semiconductor layer 2110 so that the direction intersects with the second or third wiring layer.
[0389]
Thereafter, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0390]
In this manufacturing example, a semiconductor substrate or polycrystalline silicon such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film. The film formed on the surface of the film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0390]
Introduction of impurities into the polycrystalline silicon film 2510 or 2511 to 2514 as the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 as the second conductive film, and the polycrystalline silicon film 2540 as the fourth conductive film May be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0392]
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0393]
Production Example 25
An example of a specific manufacturing process in which impurities are introduced into the island-shaped semiconductor layer during the epitaxial growth of the island-shaped semiconductor layer in a method in which a region where the charge storage layer is formed in advance by a multilayer film composed of multiple layers is shown below. .
Such a semiconductor memory device can be formed by the following manufacturing method. 570 to 572 and 573 to 575 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1 showing the memory cell array of the EEPROM, respectively.
[0394]
In this manufacturing example, as shown in FIGS. 570 and 573, when selective epitaxial silicon is grown from a semiconductor substrate after forming holes, for example, epitaxial silicon having a high concentration of N-type impurities and a low concentration of P-type impurities are used. Are grown alternately (FIGS. 571 and 574). Thus, a semiconductor memory device having a memory function is realized depending on the charge state stored in the charge storage layer (FIGS. 572 and 575).
[0395]
Production Example 26
A specific example of a manufacturing process for forming an island-shaped semiconductor layer after forming a region for separating the first wiring layer and then preliminarily defining a region where the charge storage layer is formed by a multilayer film composed of multiple layers Show.
Such a semiconductor memory device can be formed by the following manufacturing method. 576 to 578 and 579 to 581 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0396]
First, an insulating film containing an impurity is formed on the surface of the p-type silicon substrate 2100 by CVD, for example, arsenic 1 × 10 as a first insulating film.¹⁸~ 1x10^{twenty two}/ Cm^ThreeA silicon oxide film 2411 containing a certain amount of impurities is deposited to a thickness of 50 to 500 nm.
[0397]
Subsequently, using the resist R4 patterned by a known photolithography technique as a mask (FIGS. 576 and 579), the silicon oxide film 2411 as the first insulating film is etched by, for example, reactive ion etching. A fourth groove 2240 is formed.
[0398]
After removing the resist R4, a silicon nitride film 2491 which is the 21st insulating film is buried in the fourth groove 2240 (FIGS. 577 and 580). Thereby, the region of the impurity diffusion layer 2710 to be the first wiring layer is defined.
[0399]
Thereafter, the semiconductor device is completed in the same manner as in Production Example 1 (FIGS. 578 and 581).
[0400]
Production Example 27
A specific manufacturing process example in which the island-shaped semiconductor layer is formed after the region in which the charge storage layer is formed in advance is defined in advance by a multilayer film including multiple layers will be described below.
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 582 and 583 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, respectively, showing an EEPROM memory cell array.
[0401]
After exposing the side surface of the island-shaped semiconductor layer 2110, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, the first around the island-shaped semiconductor layer 2110 that forms the thermal oxide film 2450. In the method of Manufacturing Example 1 (FIGS. 83 to 99 and FIGS. 116 to 132) in which the thermal oxide film 2450 which is the ninth insulating film is removed by etching to form a memory cell, as shown in FIGS. For example, the thermal oxide film 2450 serving as the ninth insulating film may not be formed.
[0402]
Production Example 28
A specific example of a manufacturing process will be described below in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers is defined.
Such a semiconductor memory device can be formed by the following manufacturing method. 584 to 585 and FIGS. 586 to 587 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0403]
FIGS. 584 to 585 and FIGS. 586 to 587 show the manufacturing method 1 in which the polycrystalline silicon film 2540 which is the fourth conductive film at the end of the island-shaped semiconductor portion is connected to the fourth wiring layer. As described above, the polycrystalline silicon film 2540 that is the fourth conductive film may be connected to the wiring layer 2840 through the contact portion 2940.
[0404]
Production Example 29
An example of a specific manufacturing process in which impurities are introduced into the island-like semiconductor layer by using vapor phase solid phase diffusion in a method in which a region where a charge storage layer is formed in advance by a multilayer film composed of multiple layers is shown below. .
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 588 to 605 and FIGS. 606 to 623 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0405]
First, for example, a silicon nitride film 2321 as a fourth insulating film is deposited on the surface of the p-type silicon substrate 2100 by CVD to have a thickness of 10 to 100 nm.
[0406]
Subsequently, as the third insulating film, for example, a silicon oxide film 2421 is deposited by 50 to 500 nm, and as the second insulating film, for example, a silicon nitride film 2312 is deposited by 10 to 100 nm, and silicon oxide as the third insulating film is deposited. A film 2422 is deposited to 50-500 nm.
[0407]
After sequentially forming in this manner, as shown in FIGS. 588 and 606, after depositing a silicon oxide film 2424 as a third insulating film by 50 to 500 nm, a silicon nitride film 2315 as a second insulating film is formed by 20 steps. For example, a silicon oxide film 2495 is deposited to 50 to 500 nm as the twenty-third insulating film.
[0408]
Subsequently, using the resist R1 patterned by a known photolithography technique as a mask (FIGS. 588 and 606), the silicon oxide film 2495, which is the twenty-third insulating film, is formed by reactive ion etching, for example. The silicon nitride film 2315 as the insulating film and the silicon oxide film 2424 as the third insulating film, the silicon nitride film 2314 as the second insulating film, the silicon oxide film 2423 as the third insulating film, and the second insulating film A silicon nitride film 2313 as a film, a silicon oxide film 2422 as a third insulating film, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, and a fourth insulating film A certain silicon nitride film 2321 is sequentially etched to form a fourth groove 2240 (FIGS. 589 and 607).
[0409]
After removing the resist R1, the island-shaped semiconductor layer 2110 is embedded in the fourth groove 2240. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 2100 located at the bottom of the fourth groove 2240. In addition, the island-shaped semiconductor layer 2110 is planarized with respect to the silicon nitride film 2315 that is the second insulating film. At this time, etch back using isotropic etching, etch back using anisotropic etching, planarization embedding using CMP, or various combinations may be used.
[0410]
Subsequently, the island-like semiconductor layer 2110 is etched back to the vicinity of the upper surface portion of the silicon nitride film 2315 that is the second insulating film by, eg, anisotropic etching (FIGS. 590 and 608), and further, the fourth conductive film is used. A polycrystalline silicon film 2540 and a silicon nitride film 2330 which is a fifth insulating film are embedded (FIGS. 591 and 609).
[0411]
Subsequently, the silicon oxide film 2495 which is the twenty-third insulating film is removed by etching, for example, by isotropic etching, and a silicon nitride film 2340, for example, is deposited to a thickness of about 20 to 200 nm as a sixth insulating film. Sidewalls are formed by anisotropic etch back. At this time, the silicon nitride film 2315 as the second insulating film is simultaneously etched using the sidewall as a mask. Note that the etching of the silicon nitride film 2315 as the second insulating film may not be performed simultaneously with the formation of the sidewall.
[0412]
Thereafter, as a twenty-third insulating film, for example, a silicon oxide film 2496 is deposited to a thickness of 50 to 500 nm, and then a silicon oxide film 2496 as a twenty-third insulating film is deposited as a silicon nitride film 2330 as a fifth insulating film. Etchback is performed to such an extent that the upper surface of the silicon nitride film 2340 as the sixth insulating film is exposed (FIGS. 592 and 610).
[0413]
Further, the silicon nitride film 2330 which is the fifth insulating film and the silicon nitride film 2340 which is the sixth insulating film are more than the upper surface portions of the silicon oxide film 2496 whose upper surface portions are at least the twenty-third insulating films. Etch back until the thickness is lowered, and for example, a polycrystalline silicon film 2550 is deposited to a thickness of about 15 to 150 nm as a fifth conductive film. Further, the polycrystalline silicon film 2550 which is the fifth conductive film is planarized with respect to the silicon oxide film 2496 which is the twenty-third insulating film (FIGS. 593 and 611). At this time, etch back using isotropic etching, etch back using anisotropic etching, planarization embedding using CMP, or various combinations may be used. The silicon nitride film 2330 that is the fifth insulating film and the silicon nitride film 2340 that is the sixth insulating film have a silicon nitride film 2314 that is the second insulating film, and the silicon nitride film 2313 that is the second insulating film. When the total thickness of the silicon nitride film 2312 that is the second insulating film and the silicon nitride film 2321 that is the fourth insulating film is thicker, the polycrystalline silicon film 2550 that is the fifth conductive film may not be used. . Further, the polycrystalline silicon film 2550 as the fifth conductive film is not necessarily a conductive film, and may be made of a material different from that of the silicon oxide film and the silicon nitride film.
[0414]
Subsequently, the silicon oxide film 2496 which is the twenty-third insulating film is removed by etching, for example, by isotropic etching, and the polycrystalline silicon film 2550, which is the fifth conductive film, is used as a mask, for example, by reactive ion etching. A silicon oxide film 2424 as a third insulating film, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, a silicon nitride film 2313 as a second insulating film, and a third A silicon oxide film 2422 as an insulating film, a silicon nitride film 2312 as a second insulating film, a silicon oxide film 2421 as a third insulating film, and a silicon nitride film 2321 as a fourth insulating film are sequentially etched to p The mold silicon substrate 2100 is exposed (FIGS. 594 and 612). At this time, the silicon nitride film 2321 which is the fourth insulating film may remain.
[0415]
Next, the silicon oxide films 2421, 2422, 2423, and 2424 that are the third insulating films are removed by, for example, isotropic etching to expose the side surfaces of the island-shaped semiconductor layer 2110. Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 having a thickness of 10 to 100 nm (FIGS. 595 and 613).
[0416]
Next, the thermal oxide film 2450 which is the ninth insulating film around each island-shaped semiconductor layer 2110 is removed by etching, for example, by isotropic etching, and then each island-shaped semiconductor layer 2110 is utilized using oblique ion implantation as necessary. Channel ion implantation is performed on the sidewalls of. For example, implantation energy of 5 to 100 keV from a direction inclined about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2421, 2422, 2423, 2424 which are the third insulating films, and the silicon oxide films 2421, 2422, 2423 which are the third insulating films. , 2424 may be removed by introducing heat into the island-shaped semiconductor layer 2110 by heat treatment or the like, and the means is not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is the same.
[0417]
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film that becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 by using, for example, a CVD method (FIGS. 596 and 614). At this time, the tunnel oxide film is not limited to the CVD oxide film but may be a thermal oxide film or a nitrogen oxide film.
[0418]
Next, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and the silicon nitride films 2314, 2313, and 2312 that are the second insulating films are used as a mask to perform the first etching by, for example, anisotropic etching. The polycrystalline silicon film 2510 which is the conductive film is divided into polycrystalline silicon films 2511, 2512, 2513 and 2514 which are the first conductive films (FIGS. 597 and 615).
[0419]
Next, as a twenty-third insulating film, for example, a silicon oxide film 2497 is deposited to a thickness of 50 to 500 nm, and is buried to such an extent that at least the polycrystalline silicon film 2511 as the first conductive film is buried by isotropic etching ( 598 and 616).
[0420]
Subsequently, the tunnel oxide film disposed on the side surface of the island-shaped semiconductor layer 2110 is exposed by, for example, isotropic etching so that the polycrystalline silicon films 2512, 2513, and 2514, which are the first conductive films, are retracted horizontally. Retreat as much as possible.
[0421]
Thereafter, an interlayer insulating film 2612 is formed on the exposed surfaces of the polycrystalline silicon films 2512 to 2514 which are the first conductive films. The interlayer insulating film 2612 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
[0422]
Subsequently, using the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film as a mask, the interlayer insulating film 2612 and the twenty-third insulating film are formed by anisotropic etching, for example. The silicon oxide film 2497 is etched back to expose the polycrystalline silicon film 2511 which is the first conductive film (FIGS. 599 and 617).
[0423]
Next, a polycrystalline silicon film 2520 to be a second conductive film, for example, is deposited to a thickness of about 15 to 150 nm, and etched back by, for example, anisotropic etching, so that the second conductive film and the polycrystalline silicon film 2520 are self-assembled. The silicon oxide film 2470 that is the eleventh insulating film and the p-type silicon substrate 2100 that is the semiconductor substrate are sequentially etched to form a second groove 2220 in the p-type silicon substrate 2100 (FIGS. 600 and 618). .
[0424]
Subsequently, for example, a silicon oxide film 2470 is embedded as an eleventh insulating film in the second trench 2220, and then a silicon nitride film 2330 as a fifth insulating film and a silicon nitride film 2340 as a sixth insulating film are used. The polysilicon film 2520 as the second conductive film is etched back to the extent that it can be in contact with the polycrystalline silicon film 2511 as the first conductive film using the mask as a selection gate. A certain polycrystalline silicon film 2522, 2523, 2524 is dividedly formed. At this time, the interval between the island-shaped semiconductor layers 2110 is set to a predetermined value or less in advance in the direction AA ′ in FIG. Formed as a second wiring layer.
[0425]
Next, the silicon oxide film 2497 which is the twenty-third insulating film is removed by, for example, isotropic etching, and further, the silicon nitride films 2312 to 2315 which are the second insulating film and the silicon which is the fourth insulating film. The nitride film 2321 is selectively removed.
[0426]
Next, impurities are introduced into the island-shaped semiconductor layer 2110 and the semiconductor substrate 2100 in a self-aligned manner with the polycrystalline silicon films 2521, 2522, 2523, and 2524 that are the divided second conductive films. For example, arsenic 1 × 10 as an N-type impurity diffusion layer of 2710 to 2724 using solid phase vapor phase diffusion¹⁸~ 1x10^{twenty one}/ Cm^ThreeIt is formed with a moderate dose. At this time, the impurity diffusion layer 2710 serving as the first wiring layer may be adjusted in impurity concentration by an ion implantation method or the like (FIGS. 601 and 619). For example, implantation energy of 5 to 100 keV from a direction inclined by about 0 to 7 °, and phosphorus of 1 × 10¹³~ 1x10¹⁵/ Cm²About a dose.
[0427]
Thereafter, for example, a silicon oxide film 2470 is deposited to a thickness of about 50 to 500 nm as the eleventh insulating film. Subsequently, the polycrystalline silicon film 2511 as the first conductive film and the polycrystalline silicon film 2521 as the second conductive film are embedded by, for example, anisotropic etching and isotropic etching, and the island-shaped semiconductor layer 2110 is embedded. A silicon oxide film 2470 as an eleventh insulating film is buried in the third groove 2230 so that the polycrystalline silicon films 2512 to 2514 as the first conductive film are buried on the side surfaces of the first trench. Further, for example, a polycrystalline silicon film 2560 is deposited in a thickness of 15 to 150 nm as a sixth conductive film (FIGS. 602 and 620). At this time, a space as shown in FIG. 602 can be created by setting the thicknesses of the silicon nitride films 2313 and 2314, which are the second insulating films, to a predetermined value or more in advance.
[0428]
Subsequently, the polycrystalline silicon film 2560 as the sixth conductive film is etched back to the same extent as the deposited film thickness of the polycrystalline silicon film 2560 as the sixth conductive film by isotropic etching to form a control gate line. At this time, by setting the interval between the island-shaped semiconductor layers 2110 to be equal to or less than a predetermined value in the AA ′ direction in FIG. Formed as a third wiring layer.
[0429]
Next, as the eleventh insulating film, for example, a silicon oxide film 2472 is embedded to the extent that the polycrystalline silicon film 2564 which is the sixth conductive film is embedded, and as the sixth insulating film, for example, a silicon nitride film 2342 is 20 to 20%. About 200 nm is deposited, and a sidewall is formed by anisotropic etching, for example.
[0430]
Thereafter, the silicon oxide film 2472 as the eleventh insulating film is buried to such an extent that the polycrystalline silicon film 2563 as the sixth conductive film is buried (FIGS. 603 and 621).
[0431]
The polycrystalline silicon film 2564 as the sixth conductive film, the polycrystalline silicon film 2524 as the second conductive film, and the stacked insulating film 2612 formed on the side surfaces of the polycrystalline silicon film 2514 as the first conductive film are removed. After that, as the seventh conductive film, for example, a polycrystalline silicon film 2574 is deposited to a thickness of about 15 to 150 nm, and the seventh conductive film is in contact with the polycrystalline silicon film 2514 which is the first conductive film. The polycrystalline silicon film 2574 is etched back (FIGS. 604 and 622).
[0432]
Subsequently, the silicon nitride film 2330 as the fifth insulating film and the silicon nitride film 2340 as the sixth insulating film are exposed to the extent that the polycrystalline silicon film 2540 as the fourth conductive film is exposed, for example, by anisotropic etching. Etchback is performed, and a silicon oxide film 2475 as an eleventh insulating film is deposited on the polycrystalline silicon film 2574 as the second conductive film to a thickness of 100 to 500 nm, and the fourth conductive film is formed by etchback or CMP. The upper part of the polycrystalline silicon film 2540 is exposed, and the fourth wiring layer is connected to the upper part of the island-like semiconductor layer 2110 so that the direction intersects with the second or third wiring layer.
[0433]
Thereafter, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate (FIGS. 605 and 623).
[0434]
In this manufacturing example, a semiconductor substrate or polycrystalline silicon such as a silicon nitride film 2321 which is a fourth insulating film, a silicon nitride film 2330 which is a fifth insulating film, and a silicon nitride film 2350 which is a twelfth insulating film. The film formed on the surface of the film may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
Polycrystalline silicon film 2510 or 2511 to 2514 as the first conductive film, polycrystalline silicon film 2520 or 2521 to 2523 as the second conductive film, and polycrystalline silicon film 2560 or 2562 or 2563 as the sixth conductive film. The introduction of impurities into the polycrystalline silicon film 2574 which is the seventh conductive film and the polycrystalline silicon film 2540 which is the fourth conductive film may be performed at the time of forming the polycrystalline silicon film, or after the formation or separation. It may be performed after the formation, or the introduction time is not limited as long as it is a conductive film.
[0435]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
Further, by arranging selection gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.
[0436]
Production Example 30
In contrast to Production Example 1, the third groove 2230 is formed using a resist patterned by a photolithography technique without forming the silicon nitride film 2340 which is the sixth insulating film serving as a sidewall mask. The example of a specific manufacturing process is shown.
[0437]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 624 to 652 and 653 to 681 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
First, the process is the same as that in Production Example 1 until the resist R2 patterned by a known photolithography technique is disposed on the silicon nitride film 2330 as the fifth insulating film (FIGS. 624 to 627 and FIGS. 653 to 656). .
Thereafter, using the resist R2 as a mask (FIGS. 628 and 657), for example, by reactive ion etching, a silicon nitride film 2330 as a fifth insulating film, a polycrystalline silicon film 2540 as a fourth conductive film, a fourth A silicon nitride film 2325 as a first insulating film, a silicon oxide film 2415 as a first insulating film, a silicon nitride film 2315 as a second insulating film, a silicon oxide film 2424 as a third insulating film, and a fourth insulating film. A silicon nitride film 2324 as a film, a silicon oxide film 2414 as a first insulating film, a silicon nitride film 2314 as a second insulating film, a silicon oxide film 2423 as a third insulating film, and a fourth insulating film A silicon nitride film 2323, a silicon oxide film 2413 as a first insulating film, a silicon nitride film 2313 as a second insulating film, and a third insulating film The third insulating film 2422, the fourth insulating film silicon nitride film 2322, the first insulating film silicon oxide film 2412, and the second insulating film silicon nitride film 2312 are sequentially etched to form a third insulating film. A third groove 2230 is formed so that the silicon oxide film 2421 which is a film is exposed (FIGS. 629 and 658).
[0438]
Subsequently, after depositing a silicon nitride film 2342 as a sixth insulating film of about 5 to 50 nm, a silicon nitride film 2342 including an impurity as at least a first insulating film is a silicon nitride film 2342 as a sixth insulating film. The silicon nitride film 2312 as the second insulating film and the silicon nitride film 2322 as the fourth insulating film are isolated from the silicon nitride film 2322 other than the island-like semiconductor layer 2110 by the silicon nitride film as the sixth insulating film. A membrane 2342 is disposed. For example, after a silicon nitride film 2342 as a sixth insulating film is deposited to about 5 to 50 nm, it is etched back by anisotropic etching, and a silicon nitride film as a sixth insulating film at the bottom of the third groove 2230 2342 is removed to expose a silicon oxide film 2421 which is a third insulating film (FIGS. 630 and 659).
After that, for example, a silicon oxide film 2432 is deposited as a seventh insulating film to a desired depth, and a silicon oxide film containing an impurity as a first insulating film through a silicon nitride film 2342 as a sixth insulating film A silicon oxide film 2432 which is a seventh insulating film is embedded in the third groove 2230 so as to embed 2412 (FIGS. 631 and 660).
[0439]
Next, using the silicon oxide film 2432 as the seventh insulating film as a mask, the exposed portion of the silicon nitride film 2342 as the sixth insulating film is removed by isotropic etching, and the silicon nitride film 2342 as the sixth insulating film is removed. (FIGS. 632 and 661). Subsequently, for example, a silicon oxide film 2443 is deposited as an eighth insulating film, and the silicon oxide film 2443 that is the eighth insulating film is formed on the side of the silicon oxide film 2422 that is the third insulating film by, for example, anisotropic etching. It is embedded in the third groove 2230 so as to be arranged in the part (FIGS. 633 and 662). At this time, the depth at which the silicon oxide film 2443 as the eighth insulating film is buried is adjusted so that the side surface of the silicon oxide film 2413 containing impurities as the first insulating film is exposed.
Next, a silicon nitride film 2343 that is a sixth insulating film is deposited to a thickness of about 5 to 50 nm, and a silicon oxide film 2413 containing an impurity that is at least a first insulating film is silicon that is a sixth insulating film. In the sixth insulating film, the nitride film 2343, the silicon nitride film 2313 that is the second insulating film, and the silicon nitride film 2323 that is the fourth insulating film are isolated from the parts other than the island-shaped semiconductor layer 2110. A silicon nitride film 2343 is disposed.
After that, as in the previous case, for example, a silicon oxide film 2433 is deposited as a seventh insulating film to a desired depth, and an impurity which is the first insulating film is interposed via the silicon nitride film 2343 which is the sixth insulating film. A silicon oxide film 2433 which is a seventh insulating film is embedded in the third groove 2230 so that the silicon oxide film 2413 containing the silicon oxide film 2413 is embedded.
Next, the exposed portion of the silicon nitride film 2343 as the sixth insulating film is removed by isotropic etching using the silicon oxide film 2433 as the seventh insulating film as a mask, and the silicon nitride film 2343 as the sixth insulating film is removed. Place.
Subsequently, for example, a silicon oxide film 2444 is deposited as an eighth insulating film, and the silicon oxide film 2444 that is the eighth insulating film is formed on the side of the silicon oxide film 2423 that is the third insulating film by anisotropic etching, for example. It is embedded in the third groove 2230 so as to be disposed in the portion.
Further, after depositing a silicon nitride film 2344 as a sixth insulating film of about 5 to 50 nm in the same manner as before, a silicon oxide film 2414 containing an impurity as at least a first insulating film is a silicon as a sixth insulating film. In the sixth insulating film, the nitride film 2344, the silicon nitride film 2314 as the second insulating film, and the silicon nitride film 2324 as the fourth insulating film are isolated from the parts other than the island-shaped semiconductor layer 2110. A silicon nitride film 2344 is disposed.
[0440]
After that, as in the previous case, for example, a silicon oxide film 2434 is deposited as a seventh insulating film to a desired depth, and the first insulating film is doped via a silicon nitride film 2344 that is the sixth insulating film. A silicon oxide film 2434, which is a seventh insulating film, is embedded in the third groove 2230 so that the silicon oxide film 2414 containing silicon is embedded.
Subsequently, the exposed portion of the silicon nitride film 2344 as the sixth insulating film is removed by isotropic etching using the silicon oxide film 2434 as the seventh insulating film as a mask, so that the silicon nitride film as the sixth insulating film is obtained. 2344 is arranged.
Next, for example, a silicon oxide film 2445 is deposited as an eighth insulating film, and the silicon oxide film 2445 which is the eighth insulating film is formed on the side portion of the silicon oxide film 2424 which is the third insulating film by anisotropic etching, for example. It is embedded in the third groove 2230 so as to be disposed at the bottom.
Further, after depositing a silicon nitride film 2345 as a sixth insulating film of about 5 to 50 nm as in the previous case, at least a silicon oxide film 2415 containing impurities as a first insulating film and a fourth conductive film are formed. The crystalline silicon film 2540 is isolated from other than the island-shaped semiconductor layer 2110 by the silicon nitride film 2345 as the sixth insulating film, the silicon nitride film 2315 as the second insulating film, and the silicon nitride film 2330 as the fifth insulating film. A silicon nitride film 2345, which is a sixth insulating film, is disposed so as to be in the state (FIGS. 634 and 663).
Note that the silicon nitride film 2345, which is the sixth insulating film, is arranged so as to cover only the exposed portion of the silicon oxide film 2415 containing impurities, which is the first insulating film, and the polysilicon film 2540, which is the fourth conductive film. The exposed portion may not be disposed so as to be completely covered. At that time, the exposed polycrystalline silicon film 2540, which is the fourth conductive film, is oxidized during sacrificial oxidation and tunnel oxide film formation, and is eroded by removing the oxidized portion during isotropic etching of the silicon oxide film. Since the eroded portion is buried when the polycrystalline silicon film 2510 to be the first conductive film is deposited, the same effect can be obtained. Subsequently, silicon oxide films 2442, 2443, and 2444 as eighth insulating films, silicon oxide films 2421, 2422, 2423 and 2424 as third insulating films, and silicon oxide films 2432 and 2433 as seventh insulating films. , 2434 are removed by isotropic etching, for example, and the side surfaces of the island-shaped semiconductor layer 2110 are exposed, following the manufacturing example 1 (FIGS. 635 to 652 and FIGS. 664 to 681).
This manufacturing example also provides the same effect as that of Manufacturing Example 1, and further reduces the structure of the structure compared with Manufacturing Example 1 by reducing one silicon nitride film sidewall necessary for forming the semiconductor memory device. There is an advantage that it becomes simple and leads to easy formation, that is, improved device reliability.
[0441]
Production Example 31
After the region where the charge storage layer is formed in advance is defined by the multilayer film composed of multiple layers, the island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth in the hole-shaped groove opened by the photoresist mask. A laminated insulating film is formed as a charge storage layer in a region where the charge storage layer is formed on the side wall, the island-like semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a common semiconductor memory device, select gate transistors are arranged above and below the island-like semiconductor layer, and a plurality of, for example, two memory transistors are arranged between the select gate transistors. The stacked insulating films of the transistors are formed together, each transistor is connected in series along the island-shaped semiconductor layer, and the selection gate The gate insulating film thickness of the transistor is a description of embodiments of the present invention which is equal structure and the gate insulating film thickness of the memory transistor.
[0442]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 682 to 686 and FIGS. 687 to 691 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 10 showing the memory cell array of the EEPROM, respectively.
[0443]
The steps up to the formation of the polycrystalline silicon films 2511 to 2514 (FIGS. 682 and 687) as the first conductive film are performed in the same manner as in Production Example 1 (FIGS. 83 to 101 and FIGS. 116 to 134). However, the silicon nitride films 2313 and 2314 that are the second insulating films and the silicon nitride films 2322 and 2323 that are the fourth insulating films are impurity diffusion layers 2721, 2722, 2723, which are adjacent N-type semiconductor layers, respectively. Thicken 2724 so that it is not completely covered.
[0444]
Subsequently, the polycrystalline silicon films 2511 to 2514 which are the first conductive films are etched back by, for example, isotropic etching (FIGS. 683 and 688).
[0445]
Thereafter, the silicon nitride films 2312 to 2315 as the second insulating film, the silicon nitride films 2321 to 2324 as the fourth insulating film, and the silicon nitride film 2330 as the fifth insulating film are formed by, for example, isotropic etching. Etching is performed to such an extent that the semiconductor layer is not exposed (FIGS. 684 and 689).
[0446]
Subsequently, as a fifth conductive film, for example, a polycrystalline silicon film 2550 is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 that is a fifth insulating film and a silicon oxide film 2412 that includes an impurity that is a first insulating film. ˜2414 as a mask, the polycrystalline silicon film 2550 as the fifth conductive film is divided and formed into the polycrystalline silicon films 2551, 2552, 2553, and 2554 as the fifth conductive film by anisotropic etching, for example (FIG. 685). And FIG. 690).
[0447]
Next, a silicon oxide film 2470 which is an eleventh insulating film is deposited, and thereafter, the same process as in Production Example 1 (FIGS. 102 to 114 and FIGS. 135 to 147) is performed to form a first conductive film. A semiconductor memory device having a memory function is realized by a charge state stored in a charge storage layer having a crystalline silicon film as a floating gate (FIGS. 686 and 691).
[0448]
In this manufacturing example, the silicon nitride films 2312 and 2315 that are the second insulating films and the silicon nitride films 2321 and 2324 that are the fourth insulating films are replaced with the silicon nitride films 2313 and 2314 that are the second insulating films and the first insulating film. Although the film thickness is about the same as the silicon nitride films 2322 and 2323 that are the fourth insulating films, the silicon nitride films 2313 and 2314 that are the second insulating films and the silicon nitride films 2322 and 2323 that are the fourth insulating films A thin film thickness may be used.
[0449]
Formed on the surface of a semiconductor substrate or polycrystalline silicon film such as a silicon nitride film 2330 as a fifth insulating film, a silicon nitride film 2340 as a sixth insulating film, and a silicon nitride film 2350 as a twelfth insulating film The film to be formed may be a silicon oxide film / silicon nitride film multilayer film from the silicon surface side.
[0450]
Further, impurities of the polycrystalline silicon film 2510 or 2512 to 2514 which is the first conductive film, the polycrystalline silicon film 2520 or 2521 to 2524 which is the second conductive film, and the polycrystalline silicon film 2540 which is the fourth conductive film. The introduction may be performed at the time of forming the polycrystalline silicon film, may be performed after the film formation or after the separation formation, and the introduction time is not limited as long as the conductive film is formed.
[0451]
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
In addition, by arranging selection gates at the upper and lower portions of a plurality of memory cell portions, the memory cell transistor is in an over-erased state, that is, the read voltage is 0 V, the threshold value is in a negative state, and non-selected Even in a cell, a phenomenon in which a cell current flows can be prevented.
[0452]
Production Example 32
In the method of forming the selection gate and floating gate of each transistor in a lump, a specific manufacturing process example of a terminal that realizes electrical connection between the first, second and third wiring layers and the peripheral circuit is as follows. Show.
[0453]
Such a semiconductor memory device can be formed by the following manufacturing method. 692 and 698 are sectional views taken along the line H-H 'in FIG. 1 showing the memory cell array of the EEPROM, and FIGS. 693 to 697 are sectional views taken along the line I-I' in FIG. FIG. 699 to FIG. 703 are cross-sectional views of the respective stages translated from the II ′ line cross-sectional view of FIG. 9 in the direction of HH ′. In order to apply a voltage from the outside to the wiring layer, for example, a portion (contact portion) 2921 where a terminal arranged on the upper surface of the semiconductor device and the embedded wiring layers 2521, 2522, 2523, 2524, 2710 are electrically coupled, Sectional views at positions where 3232, 2933, 2924, and 2910 can be respectively confirmed are shown.
[0454]
The process is the same as in Production Example 1 until, for example, a silicon oxide film 2474 of 100 to 500 nm is deposited as a tenth insulating film.
[0455]
Thereafter, the surface of the silicon oxide film 2474, which is the tenth insulating film, is planarized by etch back or CMP, if necessary, and a resist patterned by a known photolithography technique is used as a mask to make the reactivity. Etching is performed until reaching the wiring layer to be extracted by ion etching. This is repeated as many times as the number of wiring layers to draw out.
More specifically, for example, when the first wiring layer is drawn out, the resist diffused by reactive ion etching is used only in a region where the drawing portion of the wiring layer is used, using a resist patterned by a known photolithography technique as a mask. Etching is performed from the upper surface of the silicon oxide film 2474 which is the tenth insulating film until the layer 2710 is reached.
Subsequently, for example, when pulling out the lowermost second wiring layer, using a resist patterned by a known photolithography technique as a mask, a certain range of the wiring layer leading portion other than the previously etched region is formed. Etching is performed from the upper surface of the silicon oxide film 2474 as the tenth insulating film until the polycrystalline silicon film 2521 as the second conductive film is reached by reactive ion etching.
[0456]
The order of performing the etching for extracting the wiring layer may be performed from any wiring layer. Also, for example, two grooves reaching the wiring layer are formed at the same time in the wiring layer lead portion, and then one is masked with a resist, the other is further etched, and a groove is formed so as to reach the lower wiring layer. Also good. Any means may be used as long as grooves that reach each wiring layer are formed independently in the wiring layer leading portion by the number of wiring layers to be pulled out. There are also restrictions on the arrangement of the portions (contact portions) 2921, 2932, 2933, 2924, and 2910 where the terminals arranged on the upper surface of the semiconductor device and the embedded wiring layers 2521, 2522, 2523, 2524, and 2710 are electrically coupled. Absent.
[0457]
Thereafter, as a twenty-sixth insulating film, for example, a silicon oxide film 2499 is deposited to a thickness of 10 to 100 nm, and then etched back for about the deposited film thickness, so that a twenty-second insulating film is formed on the inner wall of the groove formed in the wiring layer lead portion. A sidewall of the silicon oxide film 2499 which is the sixth insulating film is formed.
[0458]
At this time, the twenty-sixth insulating film is not limited to a silicon oxide film, and may be a silicon nitride film, and is not limited as long as it is an insulating film.
[0459]
The subsequent steps are in accordance with Manufacturing Example 1, and the metal or conductive film is formed in the groove formed in the wiring layer lead portion when the fourth wiring layer is formed through the side wall of the silicon oxide film 2499 as the 26th insulating film. The first wiring layer and the second and third wiring layers are pulled out to the upper surface of the semiconductor (FIGS. 692 to 697).
[0460]
In addition, the second and third wiring layers in the wiring layer lead-out portion are arranged as shown in FIGS. 698 to 703, and the grooves formed in the wiring layer lead-out portion provide other wiring layers and insulating films that are not intended to be drawn out. It is also possible to take a structure such that a certain distance is interposed therebetween. In this case, a reduction in the resistance of the contact portion can be expected by not forming a sidewall of the silicon oxide film 2499 which is the 26th insulating film. Further, since there is no extra wiring layer around the groove formed in the wiring layer lead portion, an effect of suppressing the parasitic capacitance between the wiring layers is expected.
[0461]
Drawing out the first wiring layer and the second and third wiring layers to the upper surface of the semiconductor by the above method can be applied to all the embodiments of the present invention.
Production Example 33
In the method for forming the impurity diffusion layer, the semiconductor substrate 2100 and the island-shaped semiconductor layer 2110 are not separated by the impurity diffusion layer, and the semiconductor substrate 2100 and the island-shaped semiconductor layer 2110 are electrically separated by a depletion layer present at the junction. Specific examples of structures that can be separated are shown below.
[0462]
Such a semiconductor memory device can be formed by the following manufacturing method. 704 and 705 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
704 and 705 show a state in which the island-shaped semiconductor layer 2110 and the semiconductor substrate 2100 are structurally connected. In this manufacturing example, for example, an impurity diffusion layer which is a first wiring layer at the time of reading or erasing A PN formed between the impurity diffusion layer 2710 which is the first wiring layer and the island-shaped semiconductor layer 2110 or the semiconductor substrate 2100 due to the potential difference between the potential applied to the 2710 and the potential applied to the island-shaped semiconductor layer 2110 or the semiconductor substrate 2100. The island-shaped semiconductor layer 2110 and the semiconductor substrate 2100 are electrically separated from each other by the depletion layer formed on the island-shaped semiconductor layer 2110 or the semiconductor substrate 2100 side of the junction.
In other words, when the width of the depletion layer formed on the island-shaped semiconductor layer 2110 or the semiconductor substrate 2100 side is W, the space Sa1 or Sb1 of the impurity diffusion layer 2710 which is the first wiring layer shown in FIGS. If at least one of these is twice or less W, they are electrically separated. Similarly to the impurity diffusion layer 710 that is the first wiring layer, the impurity diffusion layers 2721 to 2723 that are N-type semiconductor layers are at least one of Sa2 or Sb2, Sa3 or Sb3, Sa4 or Sb4, and W If it is 2 times or less, the active region of each transistor is electrically isolated.
The above state may be used at the time of reading and erasing, or the above state may be used only at the time of erasing. Further, the above-described state may be obtained at the time of writing. Also, various combinations may be used for the above state.
[0463]
Production Example 34
After the region where the charge storage layer is formed in advance is defined by the multilayer film composed of multiple layers, the island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth in the hole-shaped groove opened by the photoresist mask. A MIS capacitor is formed as a charge storage layer on a side wall of the region where the charge storage layer is to be formed, the island-like semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a semiconductor memory device in which one memory cell is composed of one transistor and one capacitor, a plurality of, for example, two memory cells are arranged in an island-shaped semiconductor layer, and each memory cell is connected to the island. The MIS capacitor and the transistor of each memory cell are formed in a lump together along the semiconductor layer, and the memory cell The gate insulating film thickness of the transistor is a description of embodiments of the present invention which is equal structure and capacitive insulating film thickness of the capacitor of the memory cell.
[0464]
Such a semiconductor memory device can be formed by the following manufacturing method. 706 to 709 and FIGS. 710 to 713 are cross-sectional views taken along lines AA ′ and BB ′ of FIG.
[0465]
An insulating film containing an impurity is formed on the side wall of the semiconductor layer 2110 in a region to be an impurity diffusion layer in a later process by a CVD method.¹⁸~ 1x10^{twenty two}/ Cm^ThreeUntil the silicon oxide films 2415, 2416, and 2417, which are first insulating films containing a certain amount of impurities, are arranged and the third groove 2230 is formed, the same method as in Production Example 1 is used. At this time, the silicon oxide film 2416 as the third insulating film may be etched back to the extent that the silicon nitride film 2321 as the fourth insulating film is exposed.
[0466]
Subsequently, as a sixth insulating film, for example, after depositing a silicon nitride film 2342 of about 5 to 50 nm, for example, by performing a heat treatment, impurities contained in the silicon oxide films 2415, 2416, and 2417 which are the first insulating films are removed. Diffusion is introduced into the island-shaped semiconductor layer 2110 (FIGS. 706 and 710). Note that the impurity introduction from the surface of the island-shaped semiconductor layer 2110 may be introduced at the time of formation of the island-shaped semiconductor layer 2110, or means is not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is equal.
[0467]
Next, the silicon nitride film 2342 that is the sixth insulating film is removed by, for example, isotropic etching, and the silicon oxide films 2416 and 2417 that are the first insulating film and the silicon oxide film that is the third insulating film. 2422 and 2424 are removed by isotropic etching, for example.
[0468]
Thereafter, the surface of the island-shaped semiconductor layer 2110 is oxidized to form a ninth insulating film, for example, a thermal oxide film 2450 having a thickness of 10 to 100 nm (FIGS. 707 and 711). The thermal oxide film 2450 which is the ninth insulating film around the semiconductor layer 2110 is removed by etching.
[0469]
Thereafter, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 2110 using oblique ion implantation as necessary. For example, implantation energy of 5 to 100 keV from a direction inclined about 5 to 45 °, boron 1 × 10¹¹~ 1x10¹³/ Cm²About a dose. In channel ion implantation, it is preferable to implant from multiple directions of the island-shaped semiconductor layer 2110 because the surface impurity concentration can be made uniform. Alternatively, instead of channel ion implantation, an oxide film containing boron may be deposited by CVD, and boron diffusion from the oxide film may be used. Note that the introduction of impurities from the surface of the island-shaped semiconductor layer 2110 may be performed before the surface of the island-shaped semiconductor layer 2110 is covered with the thermal oxide film 2450 that is the ninth insulating film, or the island-shaped semiconductor layer 2110 may be used. May be introduced at the time of formation, or impurities may be introduced into the silicon oxide films 2422 and 2424 which are third insulating films, and heat treatment may be performed before the silicon oxide films 2422 and 2424 which are third insulating films are removed. Impurities may be introduced into the island-shaped semiconductor layer 2110 by any means, and means are not limited as long as the impurity concentration distribution of the island-shaped semiconductor layer 2110 is equal.
[0470]
Subsequently, for example, a silicon oxide film 2460 is formed as a tenth insulating film that becomes a tunnel oxide film of about 10 nm, for example, around each island-shaped semiconductor layer 2110 using a thermal oxidation method. At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film.
[0471]
Next, for example, a polycrystalline silicon film 2510 to be a first conductive film is deposited to a thickness of about 50 to 200 nm, and a silicon nitride film 2330 as a fifth insulating film and a silicon nitride film 2340 as a sixth insulating film are used as a mask. For example, the polycrystalline silicon film 2510 which is the first conductive film is divided and formed into the polycrystalline silicon films 2511, 2512, 2513 and 2514 which are the first conductive films by anisotropic etching (FIGS. 708 and 712).
[0472]
Thereafter, the same method as in Production Example 13 (FIGS. 396 to 397 and 398 to 399) is used (FIGS. 709 and 713). However, no interlayer capacitance film is formed.
[0473]
In addition, silicon oxide films 2411, 2416, 2417, and 2415 that are first insulating films are arranged as shown in FIGS. 714 and 716, and polycrystalline silicon films 2511, 2512, 2513, and 2514 that are first conductive films. Then, the MIS capacitor is used as the charge storage layer in the island-like semiconductor layer 2110 by performing (FIGS. 715 and 717) in the same manner as in Production Example 12 (FIGS. 374 to 379 and 385 to 390). A semiconductor memory device having a plurality of memory cells may be used.
[0474]
【The invention's effect】
According to the semiconductor memory device and the manufacturing method thereof of the present invention, the island-shaped semiconductor layer is formed by epitaxial growth, and the island-shaped semiconductor layer can be formed without etching the semiconductor layer. Therefore, damage due to the etching process can be avoided. In addition, when the diameter of the semiconductor substrate cylinder including the memory transistors is formed with the minimum processing dimension and the shortest distance of the space width between the semiconductor substrate pillars is configured with the minimum processing dimension, the number of memory transistor stages per semiconductor substrate cylinder is If there are two stages, a capacity twice that of the conventional one can be obtained. That is, the capacity can be increased by a factor of the number of memory transistor stages per cylinder of the semiconductor substrate. In general, the larger the number of stages, the greater the capacity. As a result, the cell area per bit is reduced, and the chip can be reduced in size and cost. Further, by increasing the drive current and avoiding the back bias effect, the number of cells connected in series between the bit line and the source line is increased, and the capacity can be increased. Further, the vertical direction, which is the direction for determining the device performance, does not depend on the minimum processing dimension, and the device performance can be maintained.
[0475]
Furthermore, according to the method for manufacturing a semiconductor memory device of the present invention, after processing a semiconductor substrate into a columnar shape using a circular pattern, the side surface of the semiconductor substrate is sacrificial oxidized, thereby removing damage, defects and irregularities on the substrate surface. By removing it, it can be used as a good active region surface. At this time, it is possible to control the diameter of the column by controlling the oxide film thickness, and the capacitance between the floating gate and the control gate is determined by the surface area of the tunnel oxide film and the surface area of the interlayer capacitance film of the floating gate and the control gate. Can be easily increased. In addition, by using a circular pattern, the occurrence of local electric field concentration on the active region surface can be avoided, and electrical control can be easily performed. Furthermore, the drive current and the S value can be increased by arranging the gate electrode of the transistor so as to surround the columnar semiconductor substrate. By forming an impurity diffusion layer so that the active region of each memory cell is in a floating state with respect to the substrate, the back bias effect from the substrate is eliminated, and the memory cell characteristics are reduced due to a decrease in the threshold value of each memory cell during reading. Variation does not occur.
[0476]
In addition, after the tunnel oxide film and the floating gate are deposited, a plurality of sidewalls of the insulating film are formed in the vertical direction on the side wall of the floating gate, so that the floating gate can be processed at once. That is, the same tunnel oxide film can be obtained for each memory cell. Alternatively, by forming the tunnel oxide film after forming the floating gate control gate, the same tunnel oxide film can be obtained for each memory cell. In addition, after the region where the floating gate or control gate is to be formed is defined in advance by the thickness of the plurality of deposited films, the floating gate or control gate is formed. It can be suppressed to the extent of process variation in thickness. By using these methods, variation in memory cell characteristics is suppressed, variation in device performance is suppressed, control is facilitated, and cost reduction is realized.
[Brief description of the drawings]
FIG. 1 is a plan view showing a memory cell array of an EEPROM having a floating gate as a charge storage layer in a semiconductor memory device of the present invention.
FIG. 2 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 3 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 4 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 5 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 6 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 7 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 8 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 9 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 10 is a plan view showing a memory cell array having a MONOS structure having a laminated insulating film as a charge storage layer in the semiconductor memory device of the present invention.
FIG. 11 is a plan view showing a memory cell array having a DRAM structure having a MIS capacitor as a charge storage layer in the semiconductor memory device of the present invention.
FIG. 12 is a plan view showing a memory cell array having an SRAM structure having a MIS transistor as a charge storage layer in the semiconductor memory device of the present invention.
13 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer in the semiconductor memory device of the present invention.
14 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.
15 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.
16 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
17 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
18 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
19 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
20 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
21 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
22 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
23 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.
24 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
25 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
26 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.
27 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
28 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
29 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
30 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
31 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
32 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.
33 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
34 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.
35 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
36 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.
37 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
38 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
39 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
40 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.
41 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer in the semiconductor memory device of the present invention.
42 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer in the semiconductor memory device of the present invention.
43 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
44 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
45 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
46 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer.
47 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
48 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer.
49 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
50 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
51 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
52 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer.
53 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer in the semiconductor memory device of the present invention.
54 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer in the semiconductor memory device of the present invention.
55 is a cross-sectional view corresponding to the AA ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer in the semiconductor memory device of the present invention.
56 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer in the semiconductor memory device of the present invention.
57 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 11 of the semiconductor memory device having a MIS capacitor as a charge storage layer in the semiconductor memory device of the present invention.
58 is a cross-sectional view corresponding to the BB ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer in the semiconductor memory device of the present invention.
59 is a cross-sectional view corresponding to the J1-J1 ′ cross-sectional view in FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer in the semiconductor memory device of the present invention.
60 is a cross-sectional view corresponding to the J2-J2 ′ cross-sectional view of FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer in the semiconductor memory device of the present invention.
61 is a cross-sectional view corresponding to the K1-K1 ′ cross-sectional view in FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer in the semiconductor memory device of the present invention.
62 is a cross-sectional view corresponding to the K2-K2 ′ cross-sectional view in FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer in the semiconductor memory device of the present invention.
FIG. 63 is an equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 64 is an equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 65 is an equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 66 is an equivalent circuit diagram showing a part of a memory cell array having a MONOS structure according to the present invention.
FIG. 67 is an equivalent circuit diagram showing a part of a memory cell array having a MONOS structure according to the present invention.
FIG. 68 is an equivalent circuit diagram showing a part of a memory cell array having a DRAM structure according to the present invention;
FIG. 69 is an equivalent circuit diagram showing a part of a memory cell array having a DRAM structure according to the present invention;
FIG. 70 is an equivalent circuit diagram showing a part of a memory cell array having a DRAM structure according to the present invention;
FIG. 71 is an equivalent circuit diagram showing a part of a memory cell array having a DRAM structure according to the present invention;
72 is an equivalent circuit diagram of the semiconductor memory device of the present invention. FIG.
FIG. 73 is an equivalent circuit diagram of the semiconductor memory device of the invention.
74 is an equivalent circuit diagram showing a part of a memory cell array having an SRAM structure according to the present invention; FIG.
FIG. 75 is an equivalent circuit diagram showing a part of a memory cell array having an SRAM structure according to the present invention;
FIG. 76 is a diagram showing an example of a timing chart at the time of reading in the semiconductor memory device of the present invention.
FIG. 77 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.
FIG. 78 is a diagram showing an example of a timing chart at the time of erasing of the semiconductor memory device of the present invention.
FIG. 79 is a diagram showing an example of a timing chart at the time of reading in the semiconductor memory device of the present invention.
FIG. 80 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.
FIG. 81 is a diagram showing an example of a timing chart at the time of erasing of the semiconductor memory device of the present invention.
FIG. 82 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.
FIGS. 83 to 115 and FIGS. 116 to 147 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 1, which are plan views showing the memory cell array of the EEPROM, respectively.
FIG. 83 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 84 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
85 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
86 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 87 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
88 is a cross-sectional process (line A-A ′ in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 89 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 90 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 91 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 92 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 93 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 94 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 95 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
96 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 97 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 98 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
99 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 100 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 101 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 102 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 103 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
104 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 105 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 106 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 107 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
FIG. 108 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 109 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 110 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
FIG. 111 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 112 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 113 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
114 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 115 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
116 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 117 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
118 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 119 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
120 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 121 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
122 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 123 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
124 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
125 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 126 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 127 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
128 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 129 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating the manufacture example 1 of the semiconductor memory device of the present invention;
130 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
131 is a cross-sectional process view (B-B ′ line in FIG. 1) showing the manufacture example 1 of the semiconductor memory device of the present invention; FIG.
132 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
133 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 134 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 135 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
136 is a cross-sectional process view (B-B ′ line in FIG. 1) showing the manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 137 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention;
FIG. 138 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing the manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 139 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating a manufacturing example 1 of the semiconductor memory device of the present invention;
140 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 141 is a cross-sectional process view (B-B ′ line in FIG. 1) showing the manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 142 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
143 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.
144 is a cross-sectional process view (B-B ′ line in FIG. 1) showing the manufacture example 1 of the semiconductor memory device of the present invention; FIG.
145 is a cross-sectional process view (B-B ′ line in FIG. 1) showing the manufacture example 1 of the semiconductor memory device of the present invention;
146 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
147 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
148 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacture example 2 of the semiconductor memory device of the present invention; FIG.
149 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 2 of the semiconductor memory device of the present invention;
FIG. 150 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 151 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
152 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention; FIG.
FIG. 153 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 154 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating a manufacturing example 2 of the semiconductor memory device of the present invention;
155 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention; FIG.
FIG. 156 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 2 of the semiconductor memory device of the present invention;
FIG. 157 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 2 of the semiconductor memory device of the present invention;
158 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
159 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 2 of the semiconductor memory device of the present invention; FIG.
FIG. 160 is a sectional view (A-A ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 161 is a cross-sectional process diagram (A-A ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 162 is a sectional view (A-A ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 163 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 164 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 165 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 166 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
167 is a cross-sectional view (A-A ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
168 is a cross-sectional process (line A-A ′ in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 169 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 170 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 171 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 172 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 173 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
174 is a cross-sectional view (A-A ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
175 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention; FIG.
FIG. 176 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 177 is a cross-sectional process view (A-A ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 178 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 179 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 180 is a cross-sectional process diagram (A-A ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 181 is a cross-sectional (line A-A ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 182 is a cross-sectional process (B-B ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 183 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
184 is a cross-sectional process view (B-B ′ line in FIG. 66) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 185 is a cross-sectional (line B-B ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 186 is a cross-sectional process (B-B ′ line in FIG. 66) showing the manufacture example 3 of the semiconductor memory device of the present invention.
FIG. 187 is a cross-sectional process view (B-B ′ line in FIG. 66) showing the manufacture example 3 of the semiconductor memory device of the present invention.
FIG. 188 is a cross-sectional process (B-B ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
189 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention. FIG.
FIG. 190 is a sectional view (B-B ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 191 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
192 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 193 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 194 is a cross-sectional process (B-B ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
195 is a cross-sectional (line B-B ′ line in FIG. 66) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 196 is a cross-sectional process view (B-B ′ line in FIG. 66) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 197 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention.
198 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention.
FIG. 199 is a cross-sectional process (B-B ′ line in FIG. 66) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 200 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention.
FIG. 201 is a sectional view (B-B ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
202 is a cross-sectional process view (B-B ′ line in FIG. 66) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 203 is a sectional view (B-B ′ line in FIG. 66) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
204 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 205 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 206 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
207 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention; FIG.
FIG. 208 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 209 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention.
FIG. 210 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 211 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 212 is a sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention;
213 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 214 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
215 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
216 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
217 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
218 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
219 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 220 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 221 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention;
FIG. 222 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
223 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
224 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
225 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
226 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 227 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention;
228 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
229 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
230 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 5 of the semiconductor memory device of the present invention;
FIG. 231 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 5 of the semiconductor memory device of the present invention;
232 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 5 of the semiconductor memory device of the present invention; FIG.
233 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 5 of the semiconductor memory device of the present invention.
FIG. 234 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
235 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
236 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
237 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
238 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 239 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
240 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 241 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 242 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 243 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 244 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
245 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
246 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
247 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
248 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 249 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 250 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention.
FIG. 251 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 252 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 253 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 254 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 255 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
256 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 257 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 258 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
259 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
260 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 261 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
262 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 263 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
264 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 265 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
266 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 267 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
268 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
FIG. 269 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
270 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 271 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 272 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
273 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
FIG. 274 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
275 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 276 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating the manufacture example 7 of the semiconductor memory device of the present invention;
FIG. 277 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
278 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 279 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
280 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 281 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
282 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 283 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
284 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
285 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 286 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention;
FIG. 287 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 288 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention.
FIG. 289 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 7 of the semiconductor memory device of the present invention.
FIG. 290 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 8 of the semiconductor memory device of the present invention;
FIG. 291 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 8 of the semiconductor memory device of the present invention;
FIG. 292 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
293 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 294 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 295 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
296 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 297 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 298 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 299 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram illustrating Manufacturing Example 9 of the semiconductor memory device of the present invention;
300 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
301 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 302 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 303 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating a manufacturing example 9 of the semiconductor memory device of the present invention;
304 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 9 of the semiconductor memory device of the present invention; FIG.
FIG. 305 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
306 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 307 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 308 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
309 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 9 of the semiconductor memory device of the present invention;
FIG. 310 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 311 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 312 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
313 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
314 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
315 is a cross-sectional view (taken along the line A-A 'in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 316 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 317 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
318 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 319 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram illustrating Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 320 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention.
FIG. 321 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 322 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 323 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 324 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
325 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention; FIG.
326 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 327 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
328 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
329 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention; FIG.
FIG. 330 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 331 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 332 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
333 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 334 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
335 is a cross-sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
336 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 337 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
338 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 339 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
340 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 341 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 342 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 343 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 344 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
345 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 346 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 347 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 348 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 349 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
350 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 351 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 352 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 353 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 354 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 355 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
356 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 357 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
358 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 359 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
360 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
361 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention; FIG.
362 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 363 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
364 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 365 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 366 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 367 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 368 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
369 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 370 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 371 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 372 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 373 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 374 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 375 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention;
FIG. 376 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacture example 12 of the semiconductor memory device of the present invention;
FIG. 377 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 378 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 379 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
380 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention; FIG.
381 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention; FIG.
FIG. 382 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 383 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention;
FIG. 384 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 385 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 386 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 387 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 388 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 389 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
390 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention; FIG.
FIG. 391 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 392 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
393 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention.
394 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 12 of the semiconductor memory device of the present invention;
FIG. 395 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 396 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 13 of the semiconductor memory device of the present invention;
FIG. 397 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 13 of the semiconductor memory device of the present invention;
FIG. 398 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 13 of the semiconductor memory device of the present invention;
FIG. 399 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 13 of the semiconductor memory device of the present invention;
400 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention; FIG.
401 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention; FIG.
FIG. 402 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the invention.
403 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention; FIG.
404 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention; FIG.
FIG. 405 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention;
406 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 14 of the semiconductor memory device of the present invention;
407 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention. FIG.
FIG. 408 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 15 of the semiconductor memory device of the present invention;
FIG. 409 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 15 of the semiconductor memory device of the present invention;
FIG. 410 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention;
FIG. 411 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 15 of the semiconductor memory device of the present invention;
FIG. 412 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention.
413 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention; FIG.
414 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention; FIG.
415 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention; FIG.
416 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention; FIG.
417 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention; FIG.
418 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention; FIG.
419 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention; FIG.
FIG. 420 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention;
FIG. 421 is a sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
FIG. 422 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
FIG. 423 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
424 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
FIG. 425 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
426 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
FIG. 427 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
428 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.
FIG. 429 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention;
430 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
FIG. 431 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
FIG. 432 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
433 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
434 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
FIG. 435 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
436 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention; FIG.
437 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention; FIG.
438 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention; FIG.
FIG. 439 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention;
440 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention; FIG.
FIG. 441 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 442 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 443 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 444 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacture example 19 of the semiconductor memory device of the present invention;
FIG. 445 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 446 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 447 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 448 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention;
FIG. 449 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention;
FIG. 450 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 19 of the semiconductor memory device of the present invention;
FIG. 451 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
452 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
FIG. 453 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 20 of the semiconductor memory device of the present invention;
FIG. 454 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 20 of the semiconductor memory device of the present invention;
FIG. 455 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 20 of the semiconductor memory device of the present invention;
456 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 21 of the semiconductor memory device of the present invention;
FIG. 457 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 21 of the semiconductor memory device of the present invention;
FIG. 458 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 21 of the semiconductor memory device of the present invention;
FIG. 459 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 21 of the semiconductor memory device of the present invention;
460 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 21 of the semiconductor memory device of the present invention;
FIG. 461 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 21 of the semiconductor memory device of the present invention;
FIG. 462 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 463 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 464 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 465 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention;
FIG. 466 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 467 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
468 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 469 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention;
470 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention; FIG.
FIG. 471 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 472 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 473 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention;
FIG. 474 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
475 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention;
476 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 22 of the semiconductor memory device of the present invention; FIG.
477 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 22 of the semiconductor memory device of the present invention;
FIG. 478 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 479 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 480 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
481 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 482 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 483 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 484 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 485 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 486 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 487 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 488 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 489 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 490 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 491 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
492 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 493 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
494 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
495 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
496 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 497 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
498 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
499 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
500 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 501 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 502 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 503 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 504 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 505 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 506 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 507 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 508 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 509 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 510 is a cross-sectional view (taken along the line A-A ′ of FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 511 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 512 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 513 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
514 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
515 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 516 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 517 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention;
518 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
519 is a cross-sectional process (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
520 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 521 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
522 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
523 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
524 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
525 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
526 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
527 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
528 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
529 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 530 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
531 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 532 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
533 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
534 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
535 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
536 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
537 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
538 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
539 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
540 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 541 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 542 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 543 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
544 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
545 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
546 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
FIG. 547 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
548 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 549 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention;
FIG. 550 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram illustrating Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 551 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 552 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
FIG. 553 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention;
554 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 23 of the semiconductor memory device of the present invention; FIG.
555 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 23 of the semiconductor memory device of the present invention; FIG.
556 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention; FIG.
FIG. 557 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 24 of the semiconductor memory device of the present invention;
558 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention; FIG.
FIG. 559 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 24 of the semiconductor memory device of the present invention;
560 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention; FIG.
FIG. 561 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 24 of the semiconductor memory device of the present invention;
FIG. 562 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 24 of the semiconductor memory device of the present invention;
FIG. 563 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 24 of the semiconductor memory device of the present invention;
564 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention;
FIG. 565 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention;
FIG. 566 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention;
FIG. 567 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention;
FIG. 568 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 24 of the semiconductor memory device of the present invention;
569 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 24 of the semiconductor memory device of the present invention; FIG.
570 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 25 of the semiconductor memory device of the present invention; FIG.
FIG. 571 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 25 of the semiconductor memory device of the present invention;
572 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 25 of the semiconductor memory device of the present invention; FIG.
FIG. 573 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 25 of the semiconductor memory device of the present invention;
FIG. 574 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 25 of the semiconductor memory device of the present invention;
FIG. 575 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 25 of the semiconductor memory device of the present invention;
576 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 26 of the semiconductor memory device of the present invention; FIG.
FIG. 577 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 26 of the semiconductor memory device of the present invention;
FIG. 578 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 26 of the semiconductor memory device of the present invention;
FIG. 579 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 26 of the semiconductor memory device of the present invention;
580 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 26 of the semiconductor memory device of the present invention; FIG.
FIG. 581 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 26 of the semiconductor memory device of the present invention;
FIG. 582 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 27 of the semiconductor memory device of the present invention;
FIG. 583 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 27 of the semiconductor memory device of the present invention;
FIG. 584 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 28 of the semiconductor memory device of the present invention;
FIG. 585 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 28 of the semiconductor memory device of the present invention;
FIG. 586 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 28 of the semiconductor memory device of the present invention;
FIG. 587 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 28 of the semiconductor memory device of the present invention;
588 is a cross-sectional process (line A-A ′ of FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention. FIG.
589 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 590 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 591 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 592 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 593 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 594 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 595 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 596 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 597 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
598 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 599 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 600 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 601 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
FIG. 602 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
603 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 604 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 605 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
606 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
607 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 608 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 29 of the semiconductor memory device of the present invention;
609 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 610 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 611 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 29 of the semiconductor memory device of the present invention;
612 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
613 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
614 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention. FIG.
FIG. 615 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
FIG. 616 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
617 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
618 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention;
619 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
620 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 621 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 29 of the semiconductor memory device of the present invention;
622 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
623 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 29 of the semiconductor memory device of the present invention; FIG.
FIG. 624 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
625 is a cross-sectional view (taken along the line A-A ′ in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention. FIG.
FIG. 626 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
FIG. 627 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
628 is a cross-sectional view (taken along the line A-A 'in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention.
FIG. 629 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
630 is a cross-sectional view (taken along the line A-A ′ of FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 631 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 632 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 633 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 634 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
FIG. 635 is a cross-sectional view (taken along the line A-A ′ of FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
636 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
637 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 638 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
FIG. 639 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
640 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 641 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 642 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 643 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 30 of the semiconductor memory device of the present invention;
FIG. 644 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 645 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 646 is a cross-sectional process (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
FIG. 647 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 648 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 649 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
650 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 651 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
652 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 653 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
654 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 655 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 656 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 657 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention.
FIG. 658 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
659 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 660 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
661 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
662 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 663 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 30 of the semiconductor memory device of the present invention;
FIG. 664 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 30 of the semiconductor memory device of the present invention;
FIG. 665 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 666 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 667 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
668 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 669 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
670 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
671 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
672 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 673 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 30 of the semiconductor memory device of the present invention;
FIG. 674 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 675 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 676 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 677 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
678 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
679 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
FIG. 680 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention;
681 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 30 of the semiconductor memory device of the present invention; FIG.
FIG. 682 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention;
FIG. 683 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 31 of the semiconductor memory device of the present invention;
FIG. 684 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 31 of the semiconductor memory device of the present invention;
FIG. 685 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention.
FIG. 686 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 31 of the semiconductor memory device of the present invention;
FIG. 687 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention;
FIG. 688 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention;
FIG. 689 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention.
FIG. 690 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention;
691 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 31 of the semiconductor memory device of the present invention; FIG.
692 is a cross-sectional view (taken along the line H-H ′ in FIG. 1) showing a manufacturing example 32 of the semiconductor memory device of the present invention. FIG.
693 is a cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
694 is a cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction).
695 is a cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
FIG. 696 is a cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
FIG. 697 is a cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
698 is another cross-sectional view (taken along the line H-H ′ in FIG. 1) showing a manufacturing example 32 of the semiconductor memory device of the present invention; FIG.
699 is another cross section showing a semiconductor memory device manufacture example 32 according to the present invention (translated along the line II ′ in FIG. 8 in the direction HH ′); FIG.
FIG. 700 is another cross-sectional view showing the manufacturing example 32 of the semiconductor memory device of the present invention (the cross-sectional view taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
701 is another cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
702 is another cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction);
703 is another cross section showing a manufacturing example 32 of the semiconductor memory device of the present invention (the cross section taken along the line II ′ of FIG. 8 is translated in the HH ′ direction); FIG.
704 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 33 of the semiconductor memory device of the present invention; FIG.
705 is a cross-sectional process (B-B ′ line in FIG. 1) showing a manufacturing example 33 of the semiconductor memory device of the present invention; FIG.
FIG. 706 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 34 of the semiconductor memory device of the present invention;
707 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention; FIG.
708 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention; FIG.
709 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 34 of the semiconductor memory device of the present invention; FIG.
FIG. 710 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention;
FIG. 711 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention;
712 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 34 of the semiconductor memory device of the present invention; FIG.
FIG. 713 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention;
FIG. 714 is another cross-sectional process (A-A ′ line in FIG. 1) process diagram showing a manufacturing example 34 of the semiconductor memory device of the present invention;
715 is another cross-sectional view (taken along the line A-A ′ of FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention; FIG.
FIG. 716 is another cross-sectional (B-B ′ line in FIG. 1) process drawing showing the manufacturing example 34 of the semiconductor memory device of the present invention;
FIG. 717 is another cross-sectional process (B-B ′ line in FIG. 1) showing a manufacturing example 34 of the semiconductor memory device of the present invention;
FIG. 718 is a plan view showing a conventional EEPROM.
719 is a cross-sectional view taken along A-A ′ and B-B ′ of FIG. 800. FIG.
FIG. 720 is a cross-sectional process diagram illustrating a conventional EEPROM manufacturing method;
FIG. 721 is a process cross-sectional view illustrating the conventional EEPROM manufacturing method.
FIG. 722 is a cross-sectional process diagram illustrating a conventional method of manufacturing an EEPROM;
723 is a cross-sectional process diagram illustrating a conventional method of manufacturing an EEPROM; FIG.
FIG. 724 is a plan view of a conventional EEPROM and a corresponding equivalent circuit diagram.
725 is a cross-sectional view of a conventional MNOS structure memory cell; FIG.
726 is a cross-sectional view of another conventional MNOS structure memory cell; FIG.
727 is a cross-sectional view of a semiconductor device in which a plurality of memory cells are formed in one columnar silicon layer. FIG.
[Explanation of symbols]
1100, 2100, 3100 Silicon substrate (semiconductor substrate)
1101, 2101 SOI semiconductor substrate layer
1110, 2110, 3110 island-like semiconductor layer
2210 First groove
2220 Second groove
2230 Third groove
2240 Fourth groove
2250 Fifth groove
2260 Sixth groove
2270 Seventh groove
2280 Eighth groove
2910, 2921, 2924, 2932, 2933, 2940 Contact part
2810, 3710, 3721, 3850 First wiring layer
3120, 3840 Second wiring layer
3514, a third wiring layer,
2840, 3840 Fourth wiring layer (bit line)
3850 Fifth wiring layer
2521, 2522, 2523, 2524, 2710 Wiring layer
2720, 2721, 2722, 2723, 2724, 3710, 3721, 3724 Impurity diffusion layer
2710 Source diffusion layer
2725 Drain diffusion layer
2500 selection gate
2510 floating gate
2520, 3514 Control gate
3511 Memory Gate
2610, 2612, 2613 Interlayer insulating film
2620 Multilayer insulation film
3431, 3434 Gate insulating film
2500 Gate electrode
2510, 2511, 2512, 2513, 2514, 3511 First conductive film
2520, 2521, 2522, 2523, 2524, 3512 Second conductive film
2530, 2532, 2533, 2534, 3513, 3514 Third conductive film
2540 Fourth conductive film
2550, 2551, 2552, 2553, 2554 fifth conductive film
2560, 2562, 2563, 2564 sixth conductive film
2574 7th conductive film
2411, 2412, 2413, 2414, 2415, 2416, 2417 First insulating film
2312, 2313, 2314, 2315 Second insulating film
2421, 2422, 2423, 2424, 3420 Third insulating film
2321, 2322, 2323, 2324, 2325 Fourth insulating film
2330 Fifth insulating film
2340, 2341, 2342, 2343, 2344, 2345 Sixth insulating film
2432, 2433, 2434 Seventh insulating film
2442, 2443, 2444, 2445 Eighth insulating film
2450 Ninth insulating film
2460 Tenth insulating film
2470, 2471, 2472, 2473, 2474, 2475, 3471 Eleventh insulating film
2250, 2350, 2351 12th insulating film
2360 13th insulating film
2480 Fourteenth Insulating Film
2370 The fifteenth insulating film
2490 Sixteenth Insulating Film
2491, 2492 Eighteenth insulating film
2380 Seventeenth insulating film
2390 Nineteenth insulating film
2493 The 20th insulating film
2491 The 21st Insulating Film
2494 22nd insulating film
2495, 2496, 2497 23th insulating film
2496 24th insulating film
2499 26th insulating film
R1, R2, R3, R4, R8 resist

Claims (19)

A semiconductor substrate;
At least one island-like semiconductor layer formed by epitaxial growth on the semiconductor substrate;
A semiconductor memory device having at least one memory cell comprised of the island charge storage layer formed on all or part of the periphery of the side wall of the shaped semiconductor layer and a control gate,
The at least one memory cell is an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed at a boundary portion between the semiconductor substrate and the island-shaped semiconductor layer, or the semiconductor formed in the island-shaped semiconductor layer. A semiconductor memory device, wherein the semiconductor memory device is electrically insulated from the semiconductor substrate by at least one of a substrate and a reverse conductivity type impurity diffusion layer . A plurality of the memory cells are formed for one island-like semiconductor layer, and at least one of the plurality of memory cells is formed from another memory cell in the island-like semiconductor layer. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is electrically insulated by an impurity diffusion layer having a conductivity type opposite to that of the semiconductor device. 3. The semiconductor memory device according to claim 1, wherein an impurity diffusion layer having the same conductivity type as that of the semiconductor substrate is formed in an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate. A semiconductor substrate;
  At least one island-like semiconductor layer formed by epitaxial growth on the semiconductor substrate;
  A semiconductor memory device having a charge storage layer formed on all or part of the periphery of the sidewall of the island-shaped semiconductor layer and at least one memory cell composed of a control gate;
  The at least one memory cell includes an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed at a boundary portion between the semiconductor substrate and the island-shaped semiconductor layer, and the impurity diffusion layer and the semiconductor substrate or the island-shaped layer. A combination with a depletion layer formed at a junction with a semiconductor layer, or an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed in the island-shaped semiconductor layer, the impurity diffusion layer, and the island-shaped semiconductor layer A semiconductor memory device characterized by being electrically insulated from the semiconductor substrate by at least one of a combination with a depletion layer formed at a junction with the semiconductor substrate. A plurality of the memory cells are formed for one island-like semiconductor layer, and at least one of the plurality of memory cells is formed from another memory cell in the island-like semiconductor layer. 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is electrically insulated by an impurity diffusion layer having a conductivity type opposite to that of the impurity diffusion layer and a depletion layer formed at a junction between the impurity diffusion layer and the island-shaped semiconductor layer. Comprising an impurity diffusion layer of the semiconductor substrate and the opposite conductivity type formed in the boundary portion between the semiconductor substrate and the island-shaped semiconductor layer, wherein said impurity diffusion layer is a common wiring for at least one or more of said memory cells Item 6. The semiconductor memory device according to any one of Items 1 to 5. It said memory cells, are formed in plural to one of the island-shaped semiconductor layer, and a semiconductor memory device according to any one of claims 1 to 6, these memory cells are arranged in series. The island-shaped semiconductor layer is a plurality arranged in a matrix, the island-like semiconductor layer, the wiring for reading the charge storage states of the memory cells are formed, and a plurality of said control gate, in one direction Consecutively arranged to constitute the control gate line,
The semiconductor memory device according to claim 1, wherein a plurality of the wirings in a direction crossing the control gate line are connected to form a bit line. A gate electrode for selecting the memory cell formed so as to surround the part or its surrounding sidewalls of the island-like semiconductor layer, at least one end of said memory cells formed in the island-shaped semiconductor layer The semiconductor memory device according to claim 1, wherein a gate electrode for selection is arranged in series with respect to the memory cell. The island-like semiconductor layer opposed to the gate electrode for the selection, the semiconductor substrate or the memory cell, formed in the boundary portion or the island-like semiconductor layer and said island-shaped semiconductor layer and the semiconductor substrate The semiconductor memory device according to claim 9, wherein the semiconductor memory device is electrically insulated from the semiconductor substrate by an impurity diffusion layer having a reverse conductivity type. Claim wherein the memory cells, are formed in plural to one of the island-shaped semiconductor layer, a channel layer between the memory cell so as to be electrically connected, said control gates is disposed in close proximity The semiconductor memory device according to any one of 1 to 8. The island the semiconductor layer channel layer that will be positioned in such a channel layer of the memory cell is electrically connected, the gate electrode for the selection and the control gate which faces the gate electrode for the selection 11. The semiconductor memory device according to claim 9, wherein and are arranged close to each other. Said memory cells, are formed in plural to one of the island-shaped semiconductor layer, around the sidewall of the island-shaped semiconductor layer between the control gate of each of said memory cells, further, the channel layer between the memory cell The semiconductor memory device according to claim 1 , further comprising an electrode that applies a potential for electrically connecting the two to the island-shaped semiconductor layer . Around the sidewall of the island-shaped semiconductor layer between the gate electrode for the selection and the control gate further includes: a channel layer that will be positioned in the island-like semiconductor layer opposed to the gate electrode for the selection 11. The semiconductor memory device according to claim 9 , further comprising an electrode for applying a potential for electrically connecting the channel layer of the memory cell to the island-shaped semiconductor layer . 15. The semiconductor memory device according to claim 9, wherein all or part of the control gate and the gate electrode for selection in the film thickness direction are formed of the same material. The semiconductor memory device according to claim 9, wherein the charge storage layer and the gate electrode for selection are formed of the same material. The island-shaped semiconductor layer is a plurality arranged in a matrix, the width of the one-way of the island-shaped semiconductor layer, any of the island-like semiconductor layers of small claims 1-16 than the distance adjacent the same direction 1 The semiconductor memory device described in one. The island-shaped semiconductor layers are arranged in a matrix, and a distance between island-shaped semiconductor layers in one direction is smaller than a distance between island-shaped semiconductor layers in different directions. Semiconductor memory device. A plurality of gates including at least the control gate are arranged on the sidewall of the island-shaped semiconductor layer along the perpendicular direction of the semiconductor substrate, and the island-shaped semiconductor layers on which the memory cells are formed are arranged in a matrix 19. The electrode according to claim 1, wherein an electrode is led out to the surface of the semiconductor memory device in the order of the gate located below from the gate located above in the perpendicular direction at the end of the memory cell array. Semiconductor memory device.

Images