JP3917209B2 - Active matrix display device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a circuit and an element for improving the image quality of a display screen of an active matrix display device. In particular, the present invention uses a circuit having a thin film transistor (TFT) as a switching element, and the active layer of the TFT is composed of a silicon semiconductor crystallized using a catalytic element that promotes crystallization of amorphous silicon. About.
[0002]
[Prior art]
An active matrix display device is a display device having a mechanism in which a switching element is provided in each pixel and a signal supplied from a video signal line is supplied to the pixel by the switching element, and has a larger capacity than a simple matrix display device. Can be clearly displayed. Conventionally, a TFT using an amorphous silicon semiconductor has been used as a switching element. However, TFTs using crystalline silicon semiconductors are more than 10 times faster than conventional amorphous silicon semiconductors and are suitable for large-capacity display. Development is underway. However, there are some problems with crystalline silicon semiconductors.
[0003]
The first problem was silicon crystallization. Crystalline silicon is obtained by crystallizing amorphous silicon. Two methods have been known in the past. One is a method of crystallizing instantaneously by irradiating strong light such as a laser, which is called optical annealing. The problem with this method is that a stable, high-energy laser oscillator cannot be obtained, so that reproducibility and mass productivity are poor.
[0004]
The other method is called a thermal annealing method or a solid phase growth method. Usually, the amorphous silicon is crystallized by solid phase growth by performing thermal annealing at a temperature of 600 ° C. or higher. In this method, the time required for crystallization depends on the annealing temperature, and crystallization can be completed within one hour at a high temperature of about 1000 ° C. However, there is no substrate that can be used at such high temperatures other than quartz, and the substrate cost has increased. Further, the crystallinity of the obtained silicon film was not preferable.
[0005]
On the other hand, a silicon film with good crystallinity was obtained by annealing at about 600 ° C. in which many borosilicate glasses can be used. However, the time required for crystallization is 24 hours or more, so that mass production is possible. There was a problem.
[0006]
The second problem is that a TFT using crystalline silicon has a large leakage current (OFF current) when a reverse bias voltage is applied to the gate electrode. This is considered to be caused by a crystal grain boundary, and has been the biggest problem in manufacturing an active matrix display device using crystalline silicon.
[0007]
In the case of an N-channel TFT, the OFF current when the gate voltage is negatively biased is a PN formed between the P-type layer induced on the surface of the semiconductor thin film and the N-type layers of the source region and the drain region. It is defined by the current flowing through the junction. Since many traps exist in the semiconductor thin film (especially grain boundaries), this PN junction is incomplete and a junction leakage current tends to flow. As the gate voltage is negatively biased, the OFF current increases because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases, and the width of the energy barrier of the PN junction is narrowed. This is due to an increase in junction leakage current.
[0008]
The OFF current generated in this way largely depends on the source / drain voltage. For example, it is known that the OFF current increases dramatically as the voltage applied between the source and drain of the TFT increases. That is, when the voltage of 5 V is applied between the source / drain and when the voltage of 10 V is applied, the latter OFF current may be 10 times or 100 times, not twice the former. Such nonlinearity also depends on the gate voltage. In general, when the reverse bias value of the gate voltage is large (in the N-channel type, a large negative voltage), the difference between the two is significant.
[0009]
[Problems to be solved by the invention]
Regarding the first problem, the present inventors have found that crystallization of amorphous silicon can be promoted by adding a small amount of nickel, platinum, iron, cobalt, palladium, or the like (Japanese Patent Laid-Open No. 6-244104). As a result of the addition of these metal elements (hereinafter referred to as catalyst elements), crystallization can be accomplished typically by thermal annealing at 550 ° C. for 4 hours and at a lower temperature for a shorter time. In addition, in the conventional thermal annealing method, amorphous silicon hardly crystallized with a thickness of 1000 mm or more. However, when a catalytic element is used, a crystal having a thickness of 1000 mm or less, typically 300 to 800 mm, is sufficient. It was found that crystallization occurred.
[0010]
In addition, as a result of the inventor's research, when fabricating TFTs using silicon crystallized using these catalytic elements, from the viewpoint of the crystallization process, from the viewpoint of characteristics and reliability. The residual concentration of catalyst element in silicon is 1 × 10 ¹⁵ ~ 1x10 ¹⁹ Atom / cm ^Three It became clear that it was preferable.
[0011]
Thus, although the first problem has been solved, the second problem has remained unsolved. Conversely, the silicon film crystallized using a catalytic element has crystal growth that progresses in a needle shape (growth in the conventional thermal annealing method), and the major axis of the crystal is several μm or more (conventional thermal annealing method). Therefore, TFT characteristics are greatly affected by grain boundaries, and a large variation in OFF current has emerged as a new problem. Typically, the OFF current fluctuated by three orders of magnitude, from 1000 pA to 1 pA.
[0012]
FIG. 2A shows a schematic diagram of a conventional example of an active matrix display device. A region 204 surrounded by a broken line in the figure is a display region, in which TFTs 201 are arranged in a matrix. A wiring connected to the source electrode of the TFT 201 is an image (data) signal line 206, and a wiring connected to the gate electrode of the TFT 201 is a gate (selection) signal line 205.
[0013]
In this circuit, the switching element is a TFT 201, and data is switched according to the signal of the gate signal line 205 to drive the liquid crystal cell 203. The auxiliary capacitor 202 is a capacitor for reinforcing the capacity of the liquid crystal cell 203, and is used for holding image data. In an actual matrix, a large number of these circuits are arranged in a matrix.
[0014]
In order to perform uniform display over the entire surface of the matrix, it is necessary that all TFTs 201 have the same characteristics. In particular, the OFF current is required to be 10 pA or less, preferably 1 pA or less. If the TFT 201 whose OFF current reaches 1000 pA cannot hold a sufficient charge, the image signal is lost instantly.
[0015]
If there are several such defective TFTs in all the pixels, this is not a problem. However, when the number of defective TFTs reaches several percent, the display becomes very difficult to see. This was particularly remarkable in TFTs using crystalline silicon obtained using the catalyst elements as described above.
[0016]
In order to solve this problem, for example, as described in Japanese Patent Publication No. 5-44195 and Japanese Patent Publication No. 5-44196, a method of connecting TFTs in series (multigate method) has been proposed. This is intended to reduce the OFF current of the individual TFT by reducing the voltage applied to the source / drain of the individual TFT. For example, when two TFTs are connected in series as shown in FIG. 2B, the voltage applied to the source / drain of each TFT is halved. If the voltage applied to the source / drain is halved, the OFF current becomes 1/10 or 1/100 from the above discussion.
[0017]
However, if the characteristics required for image display of a liquid crystal display become severe, it has become difficult to reduce the OFF current as much as necessary even with the above multigate method. That is, even if the number of gate electrodes (the number of thin film transistors) is increased to 3, 4, and 5, the voltage applied to the source / drain of each TFT is 1/3, 1/4, and 1/5. It is because it decreases only little by little. In order to reduce the voltage applied to the source / drain to 1/100, 100 TFTs were required.
[0018]
In other words, this method is most effective when the number of gates is set to two, but it cannot be expected that a large effect can be expected even if more gates are provided. In particular, in a TFT using a silicon film crystallized using a catalytic element, as described above, a very large OFF current appears at a very high frequency. However, in order to sufficiently cancel this influence. It was not effective.
[0019]
[Means for Solving the Problems]
The present invention has been made in view of the above problems, and the voltage applied to the source / drain of the TFT connected to the pixel electrode is 1/10 or less of the normal case, preferably 1/100 or less. An object of the present invention is to provide a pixel circuit that reduces the OFF current. Furthermore, what is characteristic is that the number of TFTs for the above purpose is sufficiently reduced. The above goal is achieved by preferably 5 or less, more preferably 3 TFTs.
[0020]
That is, the present invention relates to an active matrix circuit, wherein at least three TFTs are connected in series to one pixel electrode, and at least one of the TFTs connected in series is not connected to an image signal line. A circuit in which individual TFTs are in an ON state at all times or most of the time is used as a switching element. In the present invention, the active layer of the TFT is made of crystalline silicon and is 1 × 10 6. ¹⁵ ~ 1x10 ¹⁹ Atom / cm ^Three The catalyst element that promotes the crystallization of silicon is contained, or the active layer of the TFT is crystallized using the catalyst element.
[0021]
Here, the other end of the TFTs connected in series may be connected to the pixel electrode. In addition, the gate electrodes of the TFTs connected in series may be shared except for TFTs that are always ON. Of course, it may be driven independently, but the former is advantageous in terms of integration. Further, an LDD region or an offset region may be provided at both ends of the TFT channel connected to the pixel electrode in the TFT.
[0022]
The basic idea of the present invention is that three or more TFTs are connected, and at least one of the central TFTs is always turned on by applying a constant voltage to the gate electrode, or other Most of the time when the TFT is OFF is used as the ON state.
[0023]
In the example of FIG. 1A, among the TFTs 103, 104, and 105 connected in series, the source of the TFT 103 is connected to the image signal line 101, and the drain of the TFT 104 is connected to the pixel electrode 106. The gate voltages of the TFTs 103 and 104 are controlled by the gate signal line 102.
[0024]
Then, an appropriate positive voltage is always applied from the power source 107 to the gate electrode of the center TFT 105 to turn on the TFT 105. If necessary, an auxiliary capacitor 108 may be added in parallel with the pixel cell 106.
[0025]
FIG. 1D shows a state in the vicinity of the gate electrodes of the TFTs 103, 104, and 105 in the circuit diagram shown in FIG. Since a method for manufacturing this circuit will be described in the embodiment with reference to FIG. 4, only an outline will be described here.
[0026]
In the circuit, three TFTs 103, 104, and 105 (representing conceptual regions by dotted lines) are formed on one silicon semiconductor film (active layer), and gate electrodes 405, 407, and 406 of the individual TFTs are formed. It is provided across the semiconductor coating. In the semiconductor region, the image signal line 101 is connected to the left end region 411 (= source of the TFT 103), and the pixel electrode of the pixel cell 106 is connected to the right end region 414 (= drain of the TFT 104). .
[0027]
An equivalent circuit of the circuit in FIG. 1A is shown in FIG. The same reference numerals as those in FIG. 1A denote the same members. Equivalently, the TFT 105 is represented as a combination of a substantially static capacitance component 223 and a resistance component 225. Strictly speaking, these capacitance / resistance components 223 and 225 vary according to the variation in the potential of the source / drain of the TFT 105, but as long as the gate potential of the TFT 105 is maintained at an appropriate value. Such fluctuations can be ignored. Strictly speaking, the capacitance component 223 and the resistance component 225 have a distributed constant circuit configuration. However, in the following, since there is no substantial problem, the circuit configuration as shown in FIG. Show.
[0028]
[Action]
A specific operation will be described. When a selection signal is sent to the gate signal line 102, both the TFT 103 on the image signal line 101 side and the TFT 104 on the pixel cell 106 side are turned on. On the other hand, in the central TFT 105, the capacitance component 223 and the pixel cell 226 are charged in accordance with a signal from the image signal line 101. In a fully charged (equilibrium) stage, the voltage between the source and drain of the TFT 104 on the pixel cell 106 side is almost equal.
[0029]
When the selection signal of the gate signal line 102 is turned off in this state, both the TFT 103 on the image signal line 101 side and the TFT 104 on the pixel cell 106 side are turned off. After that, signals from other pixels are applied to the image signal line 101, and the TFT 103 on the image signal line 101 side has a finite OFF current. Therefore, the charge charged in the capacitor component 223 formed in the center TFT 105 is charged. Will be released and the voltage will drop. However, this speed proceeds at the same speed as the voltage drop of the capacitor 202 of the normal active matrix circuit shown in FIG.
[0030]
On the other hand, regarding the TFT 104 on the pixel electrode side, since the voltage between the source and the drain was initially almost zero, the OFF current was very small, but thereafter, the voltage of the capacitive component 223 of the center TFT 105 drops. Therefore, since the voltage between the source / drain gradually increases, the OFF current also increases. However, it goes without saying that the voltage drop of the pixel cell 106 due to the increase in the OFF current is sufficiently gentler than that in the normal active matrix circuit shown in FIG. In addition, since the resistance component 225 is also present in the central TFT 105, there is an effect of further reducing the OFF current.
[0031]
Thus, although it has the effect which can reduce an OFF current on average, according to this invention, the generation | occurrence | production probability of a switching element with a large OFF current can also be reduced drastically. For example, in FIG. 1A, even if either one of the TFTs 103 or 104 has a very large OFF current, the other is normal, so that the effect of suppressing the OFF current is shown as a whole. Because. Therefore, since both of the TFTs 103 and 104 have a large OFF current and the probability that they are defective is very small, 99% of the TFT can have an OFF current of 1 pA or less and 99.99% of 10 pA or less. The occurrence rate of switching elements having an OFF current of 100 pA or more that causes an image failure can be 1 ppm or less.
[0032]
In particular, when the OFF current of the TFT 104 is large, the capacitance of the TFT 105 exhibits the same action as the auxiliary capacitor 202 in FIG. 2A, and the charge holding ability of the pixel can be maintained.
[0033]
Needless to say, when LDD regions or offset regions are formed in the channels of the TFTs 103 and 104, these regions become drain resistances / source resistances, so that the electric field strength of the drain junction can be relaxed and the OFF current can be further reduced. Yes. In particular, it is effective to form LDD (low concentration impurity) regions and offset regions at both ends of the channel of the TFT 104 on the pixel electrode side.
[0034]
Further, for example, assuming that the TFT 201 shown in FIG. 2A and the TFT 103 shown in FIG. 2C have the same characteristics, the capacitors 202 and 108 each have a voltage of 90% from the initial 10 V during one frame. 9V. In the case of FIG. 2A, the voltage of the pixel cell 203 drops to 9V during one frame.
[0035]
On the other hand, in the case of FIG. 2C, even if the voltage of the capacitor 223 drops to 9 V, the voltage between the source and drain of the TFT 103 is 1 V, so the OFF current is extremely small, and it is 1 frame. Since it is a story at the end time, the cumulative amount of charge discharged from the pixel cell 206 and the capacitor 106 is extremely small, and therefore the voltage of the pixel cell 106 is almost the same as 10V.
[0036]
Although the comparison with the case of FIG. 2B is not easy, in FIG. 2B, the voltage applied to the source / drain of one TFT is 5 V which is half of 10 V in the case of FIG. Thus, unlike the TFT 104 in FIG. 2C, the voltage between the source and the drain cannot be 1V. Therefore, the superiority of the present invention is clear also from this aspect.
[0037]
In the example of FIG. 1A, the center TFT 105 has the same conductivity type (in this case, N-channel type) as the TFTs 103 and 104 at both ends, but as shown in FIG. , P-channel type) TFT 115 may be provided. However, in this case, the polarity of the voltage applied to the gate electrode of the central TFT 115 is opposite to that in the case of FIG.
[0038]
Further, a circuit may be configured by connecting more TFTs in series. For example, as shown in FIG. 1C, TFTs 121 to 125 having different conductivity types may be alternately connected in series. Power sources 126 and 127 are connected to the gates of the TFTs 122 and 124, respectively, so that the TFTs 122 and 124 are always turned on. Note that the TFTs 121 to 125 may all have the same conductivity.
[0039]
An equivalent circuit of FIG. 1C is illustrated in FIG. The same reference numerals as those in FIG. 1C denote the same members. The TFTs 122 and 124 are represented as a connection circuit of the capacitance components 221 and 223 and the resistance components 222 and 224.
[0040]
In FIG. 1C, since five TFTs are used in total, the effect of reducing the OFF current is further increased as compared with the case where three TFTs are used. However, even if 7 or 9 TFTs are used, the effect of reducing the OFF current does not increase so much. Considering the circuit configuration and the like, it is preferable that the number of TFTs is 5 or less.
[0041]
1A to 1C have a structure in which the TFTs at both ends of the series TFTs are connected to the gate signal line 102. Of these, the TFTs connected to the pixel electrodes are always or almost always connected. You may make it become time ON. For example, a circuit in which the TFT 125 in FIG. 1C is removed may be used. Such a circuit is obtained by adding a capacitor by a TFT between the pixel electrode and the TFT 104 in the circuit of FIG. 1A, and this TFT corresponds to the auxiliary capacitor 108.
[0042]
【Example】
[Embodiment 1] In this embodiment, an operation example of FIG. 1A will be described. The TFTs 103 to 105 are all N-channel type, but the same applies to the P-channel type. Rather, in a thin film transistor using a crystalline silicon semiconductor obtained by using a catalytic element, the P channel type has an advantage that the OFF current is smaller and the deterioration is less likely.
[0043]
The two thin film transistors 103 and 104 share the gate wiring and are connected to the gate signal line 102. The source of the TFT 103 is connected to the image signal line 101. Between the two TFTs 103 and 104, a TFT 105 which is always ON is connected. In order to always turn on the TFT 105, it is desirable to apply a sufficiently high positive potential to the gate by the power source 107 so as not to be affected by the image signal or the like.
[0044]
For example, when the image signal fluctuates between -5V and + 5V, it is desirable that the gate of the TFT 105 is always kept at a potential of + 8V or more, preferably + 10V or more. For example, if the gate potential of the TFT 105 is +6 V, the potential difference between the gate and the source fluctuates between +1 to +11 V near the threshold voltage of the TFT, and the capacitance obtained in the TFT 105 is affected by the image signal. Greatly fluctuate. On the other hand, if the gate potential of the TFT 105 is +10 V, the potential difference between the gate and the source fluctuates between +5 and +15 V, but is sufficiently away from the threshold voltage, and thus the capacitance obtained in the TFT 105 There is almost no fluctuation.
[0045]
The liquid crystal cell 106 (and the auxiliary capacitor 108 if necessary) is connected to the drain of the TFT 104. The other end of the liquid crystal cell 106 (and the auxiliary capacitor 108) may be connected to the ground level. Note that the size of the MOS capacitor of the TFT 105 may be determined optimally in the ratio with the liquid crystal cell 105 (and the sum of the capacitance with the auxiliary capacitor 108 if necessary).
[0046]
The operation of FIG. 1A will be described below. First, an “H” level voltage is applied to the gates of the two TFTs 103 and 104, and the TFTs 103 and 104 are turned on. A current corresponding to the image signal flows through the source of the TFT 103, and the TFT 105 at the center at this time mainly functions as a capacitor and is charged. At the same time, since the TFT 105 is always on, current flows from the source to the drain of the TFT 104 to charge the liquid crystal cell 106.
[0047]
Next, when an 'L' level voltage is applied to the gates of the TFTs 103 and 104, the TFTs 103 and 104 are turned off, the voltage at the source of the TFT 103 drops, and the charge stored in the TFT 105 that is always on. On the other hand, an OFF current flows to start discharging. However, the voltage drop between the drain / source of the TFT 104 connected to the pixel is delayed due to the capacitance of the TFT 105. The OFF current is also reduced by the resistance component of the TFT 105. Due to the above effects, the charge of the liquid crystal cell 106 is gradually decreased, and the voltage of the liquid crystal cell 106 is lowered until the TFTs 103 and 104 are turned on in the next screen.
[0048]
In FIG. 1A, consider a circuit in which the N-channel TFT 105 that is always ON is deleted. The two N-channel TFTs 103 and 104 share a gate wiring, and the liquid crystal cell 106 is connected to the drain of the TFT 104. This is a so-called multigate type circuit shown in FIG.
[0049]
First, an “H” level voltage is applied to the gate electrodes of the two TFTs 103 and 104, and the TFTs are turned on. Then, a current flows through the source of the TFT, and the liquid crystal cell 106 is charged.
[0050]
Next, an “L” level voltage is applied to the gates of the TFTs 103 and 104, the TFTs 103 and 104 are turned off, and the voltage at the source of the TFT 103 decreases, so that the voltage at the drain of the TFT 104 also decreases. Therefore, the liquid crystal cell 106 starts discharging. However, since there is no capacitance component or resistance component between the two TFTs 103 and 104, the voltage drop of the liquid crystal cell 106 becomes larger than that of the circuit of FIG.
[0051]
The active matrix switching element shown in the circuit diagram of FIG. 1A may have the configuration shown in FIG. 1D, but the configuration shown in FIG. 3 can reduce the occupied area. Hereinafter, the description of FIG. 3 will be given. First, a crystalline silicon semiconductor film 301 having a substantially U shape, a U shape, or a horseshoe shape is formed. The semiconductor coating is crystallized using a catalytic element, typically 1 × 10 ¹⁵ ~ 1x10 ¹⁹ Atom / cm ^Three Containing the catalytic element. (Fig. 3 (A))
[0052]
A gate signal line 302 and a capacitor line 303 are arranged on the semiconductor film as shown in FIG. That is, the semiconductor film 301 has two intersections with the gate signal line 302 and one intersection with the capacitance line 303. The capacitor line 303 is formed on the matrix in parallel with the gate signal line 302, but is maintained at a constant voltage. As a result, the TFT formed by the semiconductor film 301 and the capacitor line 303 mainly functions as a static capacitor / resistance. This corresponds to the TFT 105 in FIG.
[0053]
On the other hand, the TFTs 103 and 104 in FIG. 1A correspond to two intersections formed by the gate signal line 302 and the semiconductor film 301. When N-type (or P-type) doping is performed on the semiconductor film 301 using the gate signal line 302 and the capacitor line 303 as a mask, a region 304 corresponding to the source of the TFT 103 and a region 307 corresponding to the drain of the TFT 104 are formed. Are respectively connected to the image signal line and the pixel electrode.
[0054]
A region 305 corresponding to the drain of the TFT 103 and a region 306 corresponding to the source of the TFT 104 are also formed. That is, the semiconductor region shows two N-type (or P-type) conductivity types separated by a region having an image signal line and a contact, a region having a pixel electrode and a contact, and a gate signal line and a capacitor line. A region is formed.
[0055]
Note that as shown in FIG. 3C, there is no problem even if the capacitor line 303 and the semiconductor film 301 do not completely overlap with each other and a region 308 that partially protrudes the semiconductor film 301 is formed. What is necessary is that the regions 305 and 306 are completely separated by the capacitor line 303 and the gate signal line 302.
[0056]
As described above, circuit integration can be improved mainly by devising the shape of the semiconductor coating (active layer). If a switching element having five TFTs as shown in FIG. 1C is formed, the semiconductor film may be roughly N-shaped or S-shaped, and a capacitor line or gate signal line may be overlaid thereon. .
[0057]
[Example 2]
This embodiment relates to a manufacturing process of the circuit shown in the first embodiment. This embodiment is characterized by forming an offset gate by anodizing the gate electrode and further reducing the OFF current. A technique for anodizing the gate electrode is disclosed in JP-A-5-267667.
[0058]
4A to 4D show the steps of this example. First, a silicon oxide film 402 was formed as a base film on a substrate 401 (Corning 7059, 100 mm × 100 mm) to 1000 to 5000 mm, for example, 3000 mm. The silicon oxide film 402 was formed by decomposing and depositing TEOS by plasma CVD. This step may be performed by sputtering.
[0059]
Thereafter, an amorphous silicon film was deposited in an amount of 300 to 1500, for example, 500 by plasma CVD or LPCVD, and crystallized by thermal annealing. At that time, in accordance with the technique disclosed in JP-A-6-144204, a small amount of nickel was added as a catalyst element for crystallization. As a method for adding nickel, a 1 ppm nickel acetate aqueous solution was applied and dried on an amorphous silicon film on which a thin silicon oxide film was formed. Thereafter, this was left in an atmosphere at 550 ° C. for 4 hours.
[0060]
Note that after the thermal annealing step, optical annealing such as laser irradiation may be added to further improve the crystallinity. Then, the silicon film crystallized in this way was etched to form island regions 403. Further, a gate insulating film 404 is formed thereon. Here, a silicon oxide film having a thickness of 700 to 1500 mm, for example, 1200 mm was formed by plasma CVD. This step may be performed by sputtering.
[0061]
Thereafter, a film having a thickness of 1000 to 3 μm, for example, 5000 mm of aluminum containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc is formed by sputtering, and this is etched to form a gate electrode 405. 406 and 407 were formed. (Fig. 4 (A))
[0062]
Then, the gate electrodes 405 to 407 were anodized through an electric current in an electrolytic solution to form an anodic oxide having a thickness of 500 to 2500 mm, for example, 2000 mm. The electrolytic solution used is prepared by diluting L-tartaric acid in ethylene glycol to a concentration of 5% and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate is immersed in the solution, the positive side of the constant current source is connected to the gate electrode on the substrate, the platinum electrode is connected to the negative side, and a voltage is applied in a constant current state of 20 mA until 150V is reached. Oxidation continued. Furthermore, the oxidation was continued in a constant voltage state of 150 V until the current became 0.1 mA or less. As a result, aluminum oxide films 408, 409, and 410 having a thickness of 2000 mm were obtained.
[0063]
Thereafter, impurities (here, phosphorus) are self-aligned in the island-like region 403 by ion doping using the gate electrode portions (that is, the gate electrodes 405 to 407 and the surrounding anodic oxide films 408 to 410) as a mask. To form an N-type impurity region. Here, as the doping gas, phosphine (PH _Three ) Was used. The dose in this case is 1 × 10 ¹⁴ ~ 5x10 ¹⁵ Atom / cm ² The acceleration voltage is 60 to 90 kV, for example, the dose is 1 × 10 ¹⁵ Atom / cm ² The acceleration voltage was 80 kV. As a result, N-type impurity regions 411 to 414 were formed. FIG. 1D shows a state where the element is viewed from above at this stage. (Fig. 4 (B))
[0064]
Further, the doped impurity regions 411 to 414 were activated by irradiation with a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec). Laser energy density is 200-400mJ / cm ² , Preferably 250-300 mJ / cm ² Was appropriate. This step may be performed by thermal annealing. In this embodiment, since the island-like region 403 contains a catalytic element (nickel), it can be activated by low-temperature thermal annealing as compared with a normal case (see Japanese Patent Laid-Open No. 6-267789).
[0065]
In this way, the N-type impurity region is formed. In this embodiment, the impurity regions 411 to 414 are far from the gate electrodes 404 to 407 by the thickness of the anodic oxide films 408 to 410, so-called offset. It is a gate.
[0066]
Next, a silicon oxide film 415 having a thickness of 5000 mm was formed as an interlayer insulating film by a plasma CVD method. At this time, TEOS and oxygen were used as source gases. Then, the interlayer insulating film 415 and the gate insulating film 404 were etched to form contact holes in the N-type impurity region 411. Thereafter, an aluminum film was formed by sputtering and etched to form a source electrode / wiring 416. This is an extension of the image signal line. (Fig. 4 (C))
[0067]
Thereafter, a passivation film 417 was formed. Here, NH _Three / SiH _Four / H ₂ A silicon nitride film was formed to a thickness of 2000 to 8000 mm, for example, 4000 mm by a plasma CVD method using a mixed gas to obtain a passivation film. Then, the passivation film 417, the interlayer insulating film 415, and the gate insulating film 404 were etched to form a contact hole for the pixel electrode in the N-type impurity region 414. Then, an indium tin oxide (ITO) film was formed by a sputtering method, and this was etched to form a pixel electrode 418.
[0068]
In this way, three series TFTs 421, 420, and 422 were formed. Among these, the TFT 420 can be used as a static capacitance / resistance by applying a certain positive voltage to the gate electrode 406 of the TFT 420. (Fig. 4 (D))
[0069]
4E, the passivation film 417, the interlayer insulator 418, and the gate insulating film 404 over the gate electrode 406 are etched to form a pixel electrode contact hole in the N-type impurity region 414. At the same time, a contact hole may be formed on the gate electrode 406. Since the etching rate of the anodic oxide (aluminum oxide) is extremely low in the hydrofluoric acid-based etchant that etches silicon oxide, the etching is substantially stopped at the anodic oxide 409.
[0070]
Then, when the pixel electrode 418 is formed so as to cover the hole formed in this manner, the pixel electrode 418 is opposed to the gate electrode 406 with the anodic oxide film 409 interposed therebetween, and a capacitor 419 can be formed. This capacitor 419 corresponds to the auxiliary capacitor 108 in FIG. 1A, and a capacitor can be added without increasing the opaque portion of the pixel electrode (that is, without decreasing the aperture ratio). (Fig. 4 (E))
[0071]
FIG. 5 shows the steps of this example. First, a base silicon oxide film 502 (thickness: 2000 mm) was deposited on a substrate 501, and crystallized by thermal annealing at 550 ° C. for 4 hours using nickel as a catalyst element in the same manner as in Example 2. An island-like region 503 is formed using a conductive silicon film. Further, a gate insulating film 504 is formed thereon.
[0072]
Thereafter, an aluminum film having a thickness of 5000 mm is formed by sputtering. Further, a thin anodic oxide film having a thickness of 100 to 400 mm may be formed on the surface of the aluminum film in order to improve the adhesion with the photoresist in the subsequent porous anodic oxide film forming step. Thereafter, a photoresist having a thickness of about 1 μm is applied by spin coating to form photoresist masks 508, 509, and 510. Then, gate electrodes 505, 506, and 507 were formed by etching by a known photolithography method. Photoresist masks 508, 509, and 510 were left on the gate electrodes 505 to 507. (Fig. 5 (A))
[0073]
Next, the substrate was immersed in a 10% oxalic acid aqueous solution, the positive side of the constant current source was connected to the gate electrodes 505 and 507 on the substrate, and the platinum electrode was connected to the negative side to perform anodization. This technique is disclosed in JP-A-6-338612. That is, by performing anodization at a constant voltage of 5 to 50 V, for example, 8 V, for 10 to 500 minutes, for example, 200 minutes, porous anodic oxides 511 and 512 having a thickness of 5000 mm are formed on the gate electrodes 505 and 507. Formed on the side. The obtained anodic oxides 511 and 512 were porous. Since the masks 508 and 510 exist on the upper surfaces of the gate electrodes 505 and 507, the anodic oxidation hardly progressed. Further, since no current was passed through the gate electrode 506, no anodic oxide was formed. (Fig. 5 (B))
[0074]
Thereafter, the mask material was removed to expose the upper surfaces of the gate electrodes 505 to 507. Then, in the same manner as in Example 2, L-tartaric acid was diluted with ethylene glycol to a concentration of 5% and the pH was adjusted to 7.0 ± 0.2 using ammonia, and the gate electrodes 505, 506, 507 were used. And anodized through a current to form an anodic oxide having a thickness of 500 to 2500 mm, for example, 2000 mm. As a result, dense aluminum oxide films 513, 514, and 515 having a thickness of 2000 mm were obtained.
[0075]
Thereafter, an impurity (phosphorus in this case) is implanted into the island-like silicon region 503 in a self-aligning manner using the gate electrode portion as a mask by ion doping to form a P-type impurity region. Here, diborane (B ₂ H ₆ ) Was used. The dose in this case is 1 × 10 ¹⁴ ~ 5x10 ¹⁵ Atom / cm ² The acceleration voltage is 40 to 90 kV, for example, the dose is 1 × 10 ¹⁵ cm ^-2 The acceleration voltage was 65 kV. As a result, P-type impurity regions 516 to 519 are formed. (Fig. 5 (C))
[0076]
Further, irradiation of KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate the doped impurity regions 516 to 519. Although described in the second embodiment, this step may be performed by thermal annealing.
[0077]
Next, a silicon oxide film 520 having a thickness of 3000 mm was formed as an interlayer insulating film by a plasma CVD method. Further, the interlayer insulating film 520 and the gate insulating film 504 were etched to form contact holes in the P-type impurity region 516. Thereafter, an aluminum film was formed by a sputtering method and etched to form an image signal line 521. (Fig. 5 (D))
[0078]
Thereafter, a passivation film 522 is formed, and the passivation film 522, the interlayer insulating film 520, and the gate insulating film 504 are etched to form an opening on the anodic oxide film 514 and a pixel electrode in the P-type impurity region 519. A contact hole was formed. And after forming ITO into a film by sputtering method, this was etched and the pixel electrode 523 was formed. Similarly to FIG. 4E, the pixel electrode 523 is opposed to the gate electrode 506 using the anodic oxide film 514 as a dielectric, and forms an auxiliary capacitor 524. (Fig. 5 (E))
[0079]
Through the steps as described above, switching elements of an active matrix circuit having P-channel thin film transistors 526, 527, and 525 and an auxiliary capacitor 524 were formed. In this embodiment, the conductivity type of the transistor is opposite, but it is the same as the circuit shown in FIG.
[0080]
In this embodiment, the offset width of the thin film transistors 526 and 527 that need to suppress the OFF current is made wider than that in the second embodiment. On the other hand, since there is no need for the offset in the MOS capacitor, the offset is reduced.
[0081]
Example 4 FIG. 6 shows a state in which a circuit is formed using the present invention. The specific process may be performed using a known technique (or the technique shown in Examples 2 and 3), and thus will not be described in detail here.
First, an amorphous silicon film is crystallized using a catalytic element by the means shown in the second embodiment, and this is etched to obtain a substantially U-shaped (or U-shaped or horseshoe-shaped) semiconductor region (active layer). ) 601-604 were formed. Here, when the active layer 601 is used as a reference, the active layer 602 means the same column next row, the active layer 603 means the next column / same row, and the active layer 604 means the next column / next row. (Fig. 6 (A))
[0082]
Thereafter, a gate insulating film (not shown) was formed, and the same film was etched to form gate signal lines 605 and 606 and capacitance lines 607 and 608. Here, the positional relationship between the gate signal lines 605 and 606 and the capacitor lines 607 and 608 and the active layers 601 to 604 is the same as that in FIG. (Fig. 6 (B))
[0083]
Then, after doping the active layers 601 to 604, contact holes (for example, indicated by 611) were formed at the left ends of the active layers 601 to 604, and image signal lines 609 and 610 were further formed. (Fig. 6 (C))
[0084]
Thereafter, pixel electrodes 612 and 613 were formed in regions surrounded by the gate signal lines 605 and 606 and the image signal lines 609 and 610. In this way, the TFT 614, that is, the static capacitance / resistance is formed in the capacitor line 607 and the active layer 601, but at this time, the capacitor line 607 does not overlap with the pixel electrode 613 in the row, The pixel electrodes 612 in one row are arranged so as to overlap. That is, in the case of the pixel electrode 613, the capacitor line 608 in one row overlaps with the pixel electrode 613 to form a capacitor 615. Needless to say, the capacitor lines 607 and 608 are held at a constant potential. (Fig. 6 (D))
[0085]
In this manner, a circuit as shown in FIG. 6E is formed by arranging the capacitor line so as to overlap the pixel electrode one row above (or below) the row. The capacitor 615 corresponds to the capacitor 108 in FIG. 1A, and can be added without substantially reducing the aperture ratio, which is effective in improving the degree of circuit integration. .
[0086]
Example 5
This example
In an active matrix display device,
A pair of pixel electrodes 707, 708;
A pair of gate signal lines 702 and 706 disposed between the pair of pixel electrodes;
A capacitor line 703 disposed between the gate signal lines;
Two thin film transistors disposed for each of the pair of pixel electrodes;
Have
The active layers 705 and 706 of the thin film transistor have one crystalline silicon semiconductor film having a substantially U shape, a U shape or a horseshoe shape,
The pair of gate signal lines 702 and 704 are disposed corresponding to the active layers 705 and 706 of the thin film transistors,
The capacitor line 703 is characterized in that it is commonly disposed in the active layers 705 and 706 of the thin film transistors.
[0087]
In an active matrix display device,
A pair of pixel electrodes 707, 708;
A pair of gate signal lines 702 and 704 disposed between the pair of pixel electrodes;
A capacitor line 703 disposed between the gate signal lines;
Active layers 705 and 706 of a pair of thin film transistors disposed for each of the pair of pixel electrodes;
Have
The active layers 705 and 706 are generally U-shaped, U-shaped or horseshoe-shaped,
One of the pair of gate signal lines 702 is disposed across one of the pair of active layers 705,
The other 704 of the pair of gate signal lines is disposed across the other 706 of the pair of active layers,
The capacitor line 703 is characterized by being disposed across both the pair of active layers 705 and 706.
[0088]
This embodiment is characterized in that capacitor lines are arranged in common in thin film transistor groups connected to adjacent pixel electrodes. FIG. 7 shows a schematic configuration of the present embodiment.
[0089]
In FIG. 7, adjacent pixel electrodes 707 and 705 are connected to a thin film transistor group composed of a horseshoe type active layer 705 and a thin film transistor group composed of a horseshoe type active layer 706. A capacitor line 703 that overlaps the active layers 705 and 706 is disposed in common.
[0090]
Each of the active layers 705 and 706 forms two thin film transistors connected in series by intersecting with the gate lines 703 and 704, respectively. One ends of the active layers 705 and 706 are connected to an image signal line.
[0091]
FIG. 8 shows an equivalent circuit having the configuration shown in FIG. When the structure shown in this embodiment is employed, the number of capacitor lines can be reduced, so that the aperture ratio of the pixel can be increased. FIG. 9 shows an example in which the configuration shown in FIG. 7 is modified.
[0092]
【The invention's effect】
As described above, the voltage drop of the liquid crystal cell can be suppressed by appropriately connecting a plurality of TFTs as shown in the present invention. In the present invention, in particular, the voltage between the source and drain of the TFT 105 shown in FIG. 1C is kept sufficiently low in all driving processes. In general, deterioration of a TFT depends on a voltage between a source and a drain. Therefore, by using the present invention, the deterioration can be prevented.
[0093]
The present invention is effective in applications that require higher image display. That is, in order to express very delicate shading of 256 gradations or more, the discharge of the liquid crystal cell needs to be suppressed to 1% or less during one frame. In the conventional system, neither of FIG. 2A nor 2B is suitable for this purpose.
Thus, the present invention is industrially useful.
[Brief description of the drawings]
FIG. 1 shows an example of a switching element of an active matrix circuit according to the present invention.
FIG. 2 is a circuit diagram / equivalent circuit of a switching element of a conventional and the active matrix circuit of the present invention.
FIG. 3 shows an arrangement example of semiconductor regions and gates of switching elements of the active matrix circuit in the first embodiment.
4 shows a manufacturing process of a switching element of an active matrix circuit in Example 2. FIG.
5 shows a manufacturing process of a switching element of an active matrix circuit in Example 3. FIG.
6 shows a manufacturing process of a switching element of an active matrix circuit in Example 4. FIG.
7 shows an example of an active matrix circuit in Embodiment 5. FIG.
8 shows an equivalent circuit of FIG.
9 is a modification of FIG. 7 and shows an example of an active matrix circuit.
[Explanation of symbols]
101... Image signal line
102... Gate signal line
103, 104... Thin film transistor (N channel type)
105 ・ ・ ・ ・ Thin film transistor (N-channel type, always ON)
106... Pixel cell
107.. Power supply
108 ・ ・ ・ ・ Auxiliary capacity

Claims (13)

In an active matrix display device,
An image signal of the thin film transistor having the pixel electrode in a matrix in which the image signal line and the gate signal line are orthogonally arranged, and having at least three thin film transistors connected in series to the one pixel electrode. A circuit in which at least one thin film transistor except a thin film transistor connected to a line is always ON is used as a switching element,
And the active layer of the thin film transistor active matrix display device characterized by comprising at crystallized crystalline silicon using a metal element which promotes crystallization of silicon. In an active matrix display device,
An image signal of the thin film transistor having the pixel electrode in a matrix in which the image signal line and the gate signal line are orthogonally arranged, and having at least three thin film transistors connected in series to the one pixel electrode. At least one thin film transistor except for a thin film transistor connected to a line is always in an ON state, and a circuit functioning as a resistor and a capacitor is a switching element.
And the active layer of the thin film transistor active matrix display device characterized by comprising at crystallized crystalline silicon using a metal element which promotes crystallization of silicon. 3. The active matrix display device according to claim 1, wherein LDD regions are provided at both ends of a channel of the thin film transistor connected to the pixel electrode. 4. The crystalline silicon according to claim 1, wherein the crystalline silicon is 1 × 10 6. ¹⁵ ~ 1x10 ¹⁹ Atom / cm ³ An active matrix display device comprising the metal element. In an active matrix display device,
Having pixel electrodes arranged in a matrix,
On one island-like crystalline silicon semiconductor film provided on each of the pixel electrodes has a gate site electrode 3 or more,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon, and is provided with an N-type or P-type region doped using the gate electrode as a mask,
Of the N-type or P-type regions provided in the crystalline silicon semiconductor film , one of the regions at both ends is connected to the pixel electrode, and the other is connected to the image signal line.
Among the gate electrodes, one or two gate electrodes adjacent to any one gate electrode connected to the gate signal line of the pixel are given a potential at which the thin film transistor is always in an ON state. An active matrix display device. In an active matrix display device,
Having pixel electrodes arranged in a matrix,
On one island-like crystalline silicon semiconductor film provided on each of the pixel electrodes has three gate electrodes even without low,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon, and an N-type or P-type region is provided using the gate electrode as a mask,
One of the N-type or P-type region at the end of the crystalline silicon semiconductor film is connected to an image signal line,
Wherein among the gate electrode, the gate electrodes of the thin film transistors arranged in connection with the image signal line is connected to the gate signal line of the pixel,
An active matrix display device, wherein a potential at which a thin film transistor is always on is given to a gate electrode of at least one thin film transistor, excluding the thin film transistor connected to the image signal line . According to claim 5 or 6, wherein the crystalline silicon semiconductor film is an active matrix display device, characterized in that has a shape or horseshoe-type U-shaped or U. In an active matrix display device,
A plurality of image signal lines;
A plurality of gate signal lines arranged perpendicular to the image signal lines;
One not a One parallel-arranged capacitor line between the gate signal line,
A pixel electrode provided in a region surrounded by the gate signal line and the image signal line;
A switching element connected to each of the pixel electrodes,
Each of the switching elements has one U-shaped, U-shaped or horseshoe-shaped crystalline silicon semiconductor film,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon, and is at least one intersection with the gate signal line and at least one capacitor line. have a point of intersection of the place,
An active matrix display device , wherein the capacitor line is given a potential at which a thin film transistor formed by the crystalline silicon semiconductor film and the capacitor line is always in an ON state . In an active matrix display device,
A plurality of image signal lines;
A plurality of gate signal lines arranged perpendicular to the image signal lines;
One not a One parallel-arranged capacitor line between the gate signal line,
A pixel electrode provided in a region surrounded by the gate signal line and the image signal line;
A switching element connected to each of the pixel electrodes,
Each of the switching elements has one crystalline silicon semiconductor film,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon, and is at least one intersection with the gate signal line and at least one capacitor line. A region having an intersection of the image signal line and the contact, a region having the pixel electrode and the contact, and two or more regions separated by the gate signal line and the capacitor line are N shows the type or P-type conductivity,
An active matrix display device , wherein the capacitor line is given a potential at which a thin film transistor formed by the crystalline silicon semiconductor film and the capacitor line is always in an ON state . According to claim 8 or 9, wherein the capacitor line do not overlap the pixel electrode in the row, the active-matrix display device characterized by overlapping the pixel electrode of the row adjacent to the row. In an active matrix display device,
A pair of pixel electrodes;
A pair of gate signal lines disposed between the pair of pixel electrodes;
A capacitance line disposed between the pair of gate signal lines;
Two switching elements arranged for each of the pair of pixel electrodes;
Have
Each of the switching elements has one crystalline silicon semiconductor film having a U shape , a U shape, or a horseshoe shape ,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon ,
Each of the pair of gate signal lines is disposed corresponding to the crystalline silicon semiconductor film of each of the switching elements , and has at least two intersections with the crystalline silicon semiconductor film,
The capacitance line is disposed in common to the crystalline silicon semiconductor film of each of the switching elements , and has at least one intersection with each of the crystalline silicon semiconductor film. An active matrix display device, wherein a potential at which a thin film transistor formed by a crystalline silicon semiconductor film and the capacitor line is always in an ON state is applied. In an active matrix display device,
A pair of pixel electrodes;
A pair of gate signal lines disposed between the pair of pixel electrodes;
A capacitance line disposed between the pair of gate signal lines;
A pair of switching elements disposed for each of the pair of pixel electrodes;
Have
Each of the switching elements has one crystalline silicon semiconductor film having a U shape , a U shape, or a horseshoe shape ,
The crystalline silicon semiconductor film is crystallized using a metal element that promotes crystallization of silicon,
One of the pair of gate signal lines is disposed so as to traverse one of the pair of crystalline silicon semiconductor coatings and to have at least two intersections ;
The other of the pair of gate signal lines is disposed so as to cross the other of the pair of crystalline silicon semiconductor films and have at least two intersections ;
The capacitor line is disposed across both the pair of crystalline silicon semiconductor films , and the thin film transistor formed by the crystalline silicon semiconductor film and the capacitor line is always in an ON state in the capacitor line. An active matrix display device which is provided with a potential . The crystalline silicon semiconductor film according to any one of claims 5 to 12, wherein the crystalline silicon semiconductor film is 1x10. ¹⁵ ~ 1x10 ¹⁹ Atom / cm ³ An active matrix display device comprising the metal element.

Images