JP3906556B2 - Regenerative clock extraction device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a reproduction clock extraction apparatus suitable for extracting a reproduction clock from, for example, a differential waveform signal reproduced from a recording medium.
[0002]
[Prior art]
In reproducing digital data from a magnetic tape or the like, a reproduction clock extracting device is required to extract a reproduction clock from the reproduced differential waveform signal. Conventionally, as this type of regenerative clock extraction device, for example, an invited paper “Recent Development of Signal Processing Technology for Magnetic Disks” at page 618 in the IEICE Transactions (Vol. J75-C-2 / No. 11) There is a configuration described in.
[0003]
FIG. 11 shows the configuration of this conventional reproduction clock extraction apparatus.
In FIG. 11, reference numeral 11 denotes an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit), which samples an inputted reproduction differential waveform signal with a data rate reproduction clock (sampling clock) and outputs it as digital data. This digital data is output as reproduced data via a D flip-flop (hereinafter abbreviated as DFF) 20 for timing adjustment.
[0004]
A ternary discrimination circuit 12 performs ternary discrimination of input digital data and outputs the discrimination result. That is, if the input digital data is larger than the positive threshold level (positive th in FIG. 11), it is determined as “1”, and if it is smaller than the negative threshold level (negative th in FIG. 11), “−1” is determined. ”And“ 0 ”otherwise.
[0005]
A voltage controlled oscillation circuit 18 outputs a recovered clock generated by adjusting the phase and frequency based on the input error calculation result and error accumulation result. That is, the frequency of the recovered clock generated is instantaneously increased if the input error calculation result is a positive value, and instantaneously decreased if the input error calculation result is a negative value. Further, if the value of the input error accumulation result is large, the frequency is large, and if the value is small, the frequency is small. That is, the phase of the recovered clock is adjusted based on the error calculation result, and the frequency of the recovered clock is adjusted based on the error accumulation result. The recovered clock is supplied to the A / D conversion circuit 11 and the DFFs 20, 211, and 212.
[0006]
An error calculation circuit 21 includes two DFFs 211 and 212 for timing adjustment, a subtractor 213, and a multiplier 214. The DFFs 211 and 212 delay the current digital data by 2 clocks of the reproduction clock, and The subtracter 213 subtracts the digital data two clocks before from the current digital data, and the subsequent multiplier 214 multiplies the subtraction result by the discrimination result by the ternary discrimination circuit 12 to indicate the sampling timing error. Output as error calculation result.
[0007]
The input data to the ternary discrimination circuit 12 is delayed by one clock of the reproduction clock by the DFF 20, and the input data to the (+) terminal of the subtractor 213 of the error calculation circuit 21 is input by the two DFFs 211 and 212. Since the reproduction clock is delayed by two clocks, the ternary discriminating circuit 12 determines the data that is one clock earlier than the data input to the (−) terminal of the subtractor 213 by the reproduction clock. 214 is added.
[0008]
An error accumulation circuit 22 receives the output of the error calculation circuit 21 and outputs a result of accumulating the error calculation results as an error accumulation result.
[0009]
FIG. 12 is a timing chart showing the relationship between the reproduction differential waveform signal and the reproduction clock (sampling clock) in the conventional reproduction clock extracting apparatus shown in FIG.
[0010]
In FIG. 12, points a to h are sampling timings based on the reproduction clock in the A / D conversion circuit 11, that is, the sampling clock. Here, the values of the digital data obtained by sampling are represented by symbols “A” to “A”, respectively. “H”. In FIG. 11, the reproduction differential waveform signal is sampled by the A / D conversion circuit 11 and latched by the DFF 20 every time the reproduction clock rises, so that the reproduction data is “A” to “G”.
[0011]
FIG. 12A shows the characteristics when the reproduced differential waveform signal and the reproduced clock are in phase. In this case, the determination result output by the ternary determination circuit 12 is other than “0” when the determination result for “C” is “1” and the determination result for “F” is “−1”. The error calculation results output from the error calculation circuit 21 are “BD” (= {BD} × {1}) and “GE” (= {E−G} × {−1}). Each value. Here, since the values of “BD” and “EG” are both almost zero in the phase of FIG. 12A, the frequency of the recovered clock generated in the voltage controlled oscillation circuit 18 is maintained, and the phase Will remain matched to the reproduced differential waveform signal.
[0012]
(A) in FIG. 12 shows characteristics when the phase of the reproduction clock is advanced with respect to the reproduction differential waveform signal. Also in this case, the determination result output by the ternary determination circuit 12 is other than “0” when the determination result for “C” is “1” and the determination result for “F” is “−1”. The error calculation results output from the error calculation circuit 21 are “BD” (= {BD} × {1}) and “GE” (= {GE} × {−1}). ). Here, since the values of “BD” and “GE” are both negative in the phase of FIG. 12A, the frequency of the regenerated clock generated by the voltage controlled oscillation circuit 18 is instantaneously reduced. The phase shifts in a direction that is delayed with respect to the reproduced differential waveform signal, that is, in a direction in which the phases match.
[0013]
FIG. 12C shows characteristics when the phase of the reproduction clock is delayed with respect to the reproduction differential waveform signal. Also in this case, the determination result output by the ternary determination circuit 12 is other than “0” when the determination result for “C” is “1” and the determination result for “F” is “−1”. The error calculation results output from the error calculation circuit 21 are “BD” (= {BD} × {1}) and “GE” (= {GE} × {−1}). ). Here, in the phase of FIG. 12C, the values of “BD” and “GE” are both positive, so that the frequency of the recovered clock generated by the voltage controlled oscillation circuit 18 increases instantaneously. The phase shifts in the direction of advance with respect to the reproduced differential waveform signal, that is, in the direction in which the phases match.
[0014]
As described above, the conventional reproduction clock extracting apparatus having the above-described configuration shown in FIG. 11 is automatically controlled so that the phase of the reproduction clock matches the differential waveform signal so that accurate signal reproduction can be performed. Yes.
[0015]
[Problems to be solved by the invention]
However, in the conventional regenerative clock extraction apparatus having the configuration shown in FIG. 11, the following problems may occur.
[0016]
(1) Since the frequency of the recovered clock changes instantaneously depending on the output of the error calculation circuit 21, there is a performance (hereinafter referred to as phase pull-in capability) that eliminates the phase shift of the recovered clock with respect to the recovered differential waveform signal. When the accumulated value of the output of the error calculation circuit 21 does not change, for example, when the output of the error calculation result of the error calculation circuit 21 is repeatedly output in positive and negative alternately, and the accumulated result is canceled, the error accumulation Since the output of the circuit 22 does not change, even when the recovered clock deviates from the target frequency, there is no performance to eliminate this (hereinafter referred to as frequency pulling ability), and accurate signal recovery cannot be performed.
[0017]
This phenomenon will be described in detail with reference to FIG.
FIG. 13 is a timing chart showing the relationship between the reproduction differential waveform signal, the error calculation result, and the reproduction clock (sampling clock). A single wave is used for the reproduction differential signal for simplicity of explanation.
[0018]
In FIG. 13, points a to p are sampling timings based on a reproduction clock in the A / D conversion circuit 11, that is, a sampling clock. Here, the values of digital data obtained by sampling are denoted by symbols “A” to “A”, respectively. “P”.
[0019]
FIG. 13A shows the characteristics when the reproduced differential waveform signal and the frequency of the reproduced clock match. Positive or negative values are detected at the timings “B”, “D”, “F”, “H”, “J”, “L”, “N”, and “P”. The difference component of the data is almost zero, and there is no increase or decrease in the error accumulation result. In addition, illustration of the phase error calculation result here is abbreviate | omitted.
[0020]
FIG. 13A shows the characteristics when the frequency of the reproduction clock is small with respect to the reproduction differential waveform signal. Positive or negative values are detected as “B”, “D”, “F”, “H”, “I”, “J”, “K”, “L”, “M”, “O”. FIG. 13C shows the phase error calculation results at each timing. As shown in the figure, at the timing of “B”, “D”, “F”, “H”, “J”, “L”, the phase error calculation result shows a positive value, “I”, “K”, The phase error calculation result at the timings “M” and “O” indicates a negative value. From “B” to “O”, the phase error calculation result gradually increases in the positive direction, and then negative values appear alternately, and then shows only negative values and gradually decreases. The error accumulating circuit 22 accumulates the error calculation result. However, if this relationship changes before the frequency of the reproduction clock matches the frequency of the reproduction differential signal, a phenomenon in which the increase / decrease in the error accumulation result is canceled can occur.
[0021]
FIG. 13C shows the characteristics when the frequency of the reproduction clock is larger than the reproduction differential waveform signal. A positive value or a negative value is detected at timings “B”, “D”, “F”, “H”, “J”, “K”, “L”, “M”, “O”. The phase error calculation results at each timing are shown in FIG. As shown in the figure, the phase error calculation results at the timings “B”, “D”, “F”, “H”, “J”, “L” indicate negative values, and “K”, “M”, The phase error calculation result at the timing “O” indicates a positive value. From “B” to “O”, the phase error calculation result gradually increases in the negative direction, and then positive values appear alternately, and then only positive values are shown and gradually decrease. The error accumulating circuit 22 accumulates the error calculation result. However, when such a relationship changes before the frequency of the reproduction clock matches the frequency of the reproduction differential signal, a phenomenon occurs in which the increase / decrease in the error accumulation result is offset. obtain.
[0022]
Thus, although the frequency of the reproduction clock is shifted with respect to the reproduction differential signal, there is a problem that the frequency pull-in range becomes narrow as a result without being reflected in the error accumulation result.
[0023]
Further, when considering a system that performs subsequent processing while performing adaptive equalization processing digitally after A / D conversion, a control loop from A / D conversion to clock generation due to a delay of adaptive equalization means As a result, the range of the frequency of the recovered clock can be reduced.
[0024]
(2) The frequency pull-in capability includes frequency response in addition to the frequency pull-in range, and when the gain of the loop is increased so that the generated clock is quickly pulled into the reproduced differential waveform signal, the reproduced differential waveform signal It reacts sensitively to frequency fluctuations, and stability cannot be achieved. Further, when the loop gain is lowered for the purpose of stability, the response to the frequency fluctuation of the reproduced differential waveform signal becomes slow, and the frequency tracking capability is lacking.
[0025]
FIG. 14 shows a configuration example of the error accumulating circuit 22, and FIG. 15 shows a relationship between the frequency error of the sampling clock with respect to the input signal and the time t in the configuration of the error accumulating circuit 22. In FIG. 15, the horizontal axis represents time, and the vertical axis represents the frequency error between the input signal and the sampling clock.
[0026]
In FIG. 14, the error accumulating circuit 22 adds the error calculation result from the error calculation circuit 21 to the output from the register 222 holding the addition result so far in the adder 221, and inputs it again to the register 222. This value is stored in the register 222. Further, the output of the adder 221 is configured to be multiplied by the gain of this loop by the coefficient unit 223 as an accumulated result and sent to the voltage controlled oscillation circuit 18 (FIG. 11). At this time, when the coefficient K of the coefficient unit 223 is large, as shown in FIG. 15A, the pull-in time to the target frequency is short, but the frequency variation is repeated until the target frequency converges. Even when the fluctuation occurs, it reacts sensitively and a frequency error occurs. Further, when the coefficient K of the coefficient unit 223 is small, as shown in FIG. 15 (a), the pull-in to the target frequency takes time until convergence, and after the pull-in, the reproduced differential waveform signal is instantaneous but is stable. When a dynamic frequency fluctuation occurs, the response is slow and the fluctuation frequency cannot be followed.
[0027]
Thus, the coefficient setting of the coefficient unit 223 of the error accumulating circuit 22 that determines the frequency response requires an optimal setting that satisfies these contradictory problems, which is a major problem in determining the system performance.
[0028]
The present invention solves the above-mentioned conventional problems (1) and (2), and provides a regenerative clock extraction apparatus having a wide frequency pull-in range and an optimum frequency response for the system. Objective.
[0029]
[Means for Solving the Problems]
In order to solve each of the above-described problems, the reproduction clock extracting apparatus of the present invention includes a quantization unit that quantizes an input signal with a sampling clock having a rate twice as high as a data rate, and a sampling output from the quantization unit. Even column sampling data every other sampling clock of the data , Ternary discrimination means for ternary discrimination of positive, zero, or negative values as reproduction data; and pattern detection means for detecting only a specific combination from a plurality of consecutive discrimination results output from the ternary discrimination means; , Using odd-sequence sampling data between two consecutive reproduction data in which the discrimination result of the ternary discrimination means changes Obtained by subtracting the sampling data output from the quantizing means and the data obtained by delaying the sampling data output from the quantizing means and multiplying the discrimination result by the ternary discriminating means. The error calculation means for calculating the sampling timing error and the odd column sampling data located between a plurality of reproduction data used for pattern detection are multiplied by the polarity of the detection pattern. product, Alternatively, the difference between multiple odd-column sampling data is multiplied by the polarity of the detection pattern product Is held based on the detection result of the pattern detecting means. , Take the difference from the past holding data , When generating an error transition extracting means for extracting only a difference result within a predetermined level range, an accumulating means for inputting and accumulating the extraction result of the error transition extracting means, and a sampling clock to be supplied to the quantizing means. , The calculation result of the error calculation means and the accumulation result of the accumulation means When Based on The Phase and frequency When A sampling clock generating means for adjusting the frequency and a recovered clock generating means for generating a recovered clock by dividing the sampling clock by two.
[0030]
Thereby, in addition to the phase pull-in capability, it is possible to have a wide frequency pull-in capability.
[0031]
The reproduction clock extracting apparatus of the present invention also includes a quantizing unit that quantizes an input signal with a sampling clock having a rate twice as high as a data rate, and one sampling clock among sampling data output by the quantizing unit. Even column sampling data , Ternary discrimination means for ternary discrimination of positive, zero, or negative values as reproduction data; and pattern detection means for detecting only a specific combination from a plurality of consecutive discrimination results output from the ternary discrimination means; , Using odd-sequence sampling data between two consecutive reproduction data in which the discrimination result of the ternary discrimination means changes Obtained by subtracting the sampling data output from the quantizing means and the data obtained by delaying the sampling data output from the quantizing means and multiplying the discrimination result by the ternary discriminating means. The error calculation means for calculating the sampling timing error and the odd column sampling data located between a plurality of reproduction data used for pattern detection are multiplied by the polarity of the detection pattern. product, Alternatively, the difference between multiple odd-column sampling data is multiplied by the polarity of the detection pattern product Is held based on the detection result of the pattern detecting means. , Take the difference from the past holding data , Error transition extraction means for extracting only a difference result within a predetermined level range, accumulation means for inputting and accumulating the calculation result of the error calculation means or the extraction result of the error transition extraction means, and sampling supplied to the quantization means When generating the clock , The calculation result of the error calculation means and the accumulation result of the accumulation means When Based on The Phase and frequency When A sampling clock generation means for adjusting the reproduction clock, a reproduction clock generation means for generating a reproduction clock by dividing the sampling clock by 2, and a reproduction data acquisition detection means for detecting whether or not the reproduced data can be acquired. A reproduction clock extraction device comprising: a reproduction data acquisition detection means; The The input of the accumulating means is the calculation result of the error calculation means and the extraction result of the error transition extraction means. When It is controlled to select one of these.
[0032]
As a result, it is possible to have a frequency pulling ability having both an optimum frequency pulling characteristic and a frequency followability.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
According to a first aspect of the present invention, there is provided a regenerative clock extracting apparatus comprising: a quantizing unit that quantizes an input signal with a sampling clock having a rate twice as high as a data rate; and one of sampling data output from the quantizing unit. Even-numbered sampling data every sampling clock , Ternary discrimination means for ternary discrimination of positive, zero, or negative values as reproduction data; and pattern detection means for detecting only a specific combination from a plurality of consecutive discrimination results output from the ternary discrimination means; , Using odd-sequence sampling data between two consecutive reproduction data in which the discrimination result of the ternary discrimination means changes Obtained by subtracting the sampling data output from the quantizing means and the data obtained by delaying the sampling data output from the quantizing means and multiplying the discrimination result by the ternary discriminating means. The error calculation means for calculating the sampling timing error and the odd column sampling data located between a plurality of reproduction data used for pattern detection are multiplied by the polarity of the detection pattern. product, Alternatively, the difference between multiple odd-column sampling data is multiplied by the polarity of the detection pattern product Is held based on the detection result of the pattern detecting means. , Take the difference from the past holding data , When generating an error transition extracting means for extracting only a difference result within a predetermined level range, an accumulating means for inputting and accumulating the extraction result of the error transition extracting means, and a sampling clock to be supplied to the quantizing means. , The calculation result of the error calculation means and the accumulation result of the accumulation means When Based on The Phase and frequency When A sampling clock generating means for adjusting the sampling clock and a recovered clock generating means for generating a recovered clock by dividing the sampling clock by two. According to these configurations, sampling of the A / D conversion is performed with data. When calculating the sampling timing error of A / D conversion using sampling data other than the reproduction data, using the sampling clock at a rate twice the rate, the accumulated value of the error transition extraction result using the error calculation result as the phase error Is used as a frequency error.
[0034]
According to a second aspect of the present invention, there is provided a reproduction clock extracting apparatus comprising: a quantizing unit that quantizes an input signal with a sampling clock having a rate twice as high as a data rate; and one sampling of sampling data output by the quantizing unit. Even column sampling data every clock , Ternary discrimination means for ternary discrimination of positive, zero, or negative values as reproduction data; and pattern detection means for detecting only a specific combination from a plurality of consecutive discrimination results output from the ternary discrimination means; , Using odd-sequence sampling data between two consecutive reproduction data in which the discrimination result of the ternary discrimination means changes Obtained by subtracting the sampling data output from the quantizing means and the data obtained by delaying the sampling data output from the quantizing means and multiplying the discrimination result by the ternary discriminating means. The error calculation means for calculating the sampling timing error and the odd column sampling data located between a plurality of reproduction data used for pattern detection are multiplied by the polarity of the detection pattern. product, Alternatively, the difference between multiple odd-column sampling data is multiplied by the polarity of the detection pattern product Is held based on the detection result of the pattern detecting means. , Take the difference from the past holding data , Error transition extraction means for extracting only a difference result within a predetermined level range, accumulation means for inputting and accumulating the calculation result of the error calculation means or the extraction result of the error transition extraction means, and sampling supplied to the quantization means When generating the clock , The calculation result of the error calculation means and the accumulation result of the accumulation means When Based on The Phase and frequency When A sampling clock generation means for adjusting the reproduction clock, a reproduction clock generation means for generating a reproduction clock by dividing the sampling clock by 2, and a reproduction data acquisition detection means for detecting whether or not the reproduced data can be acquired. A reproduction clock extraction device comprising: a reproduction data acquisition detection means; The The input of the accumulating means is the calculation result of the error calculation means and the extraction result of the error transition extraction means. When According to these configurations, when calculating the sampling timing error of the A / D conversion, the error calculation result is used as the phase error, and the acquisition of the reproduction data is detected. Until then, the accumulated value of the error transition extraction result is used as the frequency error by accumulating the error calculation result in the accumulated result until the acquisition of the reproduction data is detected.
[0035]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the recovered clock extraction apparatus according to the first embodiment of the present invention.
[0036]
In FIG. 1, reference numeral 11 denotes an A / D conversion circuit as a quantizing means, which samples an inputted reproduced differential waveform signal with a sampling clock having a rate twice the data rate and outputs it as digital data. This digital data is output as reproduction data via the DFF 101 and the DFF 102.
[0037]
Reference numeral 12 denotes a ternary discrimination circuit which is a ternary discriminating means, which performs ternary discrimination of the input digital data and outputs the discrimination result. That is, if the input digital data is larger than the positive threshold level (positive th in FIG. 1), it is determined as “1”, and if it is smaller than the negative threshold level (negative th in FIG. 1), “−1” is determined. ”And“ 0 ”otherwise.
[0038]
Reference numeral 13 denotes a pattern detection circuit which is a pattern detection means, which detects only a specific combination from a plurality of continuous discrimination results output from the ternary discrimination circuit 12. For example, only a specific pattern in which the current discrimination result of the discrimination result of the ternary discrimination circuit 12 is a positive value or a negative value and the discrimination result before and after that is zero is detected, and the detection result is sent to the error calculation circuit 14. Output.
[0039]
14 is an error calculation circuit, which is an error calculation means comprising one DFF 141, a subtractor 142, and a multiplier 143. The DFF 141 delays digital data from the DFF 103 by one clock, and the next subtractor 142 supplies the digital data. The digital data one clock before is subtracted from the data, and the result obtained by multiplying the subtraction result by the discrimination result by the ternary discrimination circuit 12 at the next multiplier 143 is output as the error calculation result indicating the sampling timing error.
[0040]
Note that the input data to the ternary discrimination circuit 12 is three DCKs 101 and 102 for three sampling clocks, and the input data to the (+) terminal of the subtractor 142 of the error calculation circuit 14 is two DFFs 103 and 141. Since the sampling clocks are delayed by 4 clocks, the ternary discrimination circuit 12 discriminates the data one clock before the data input to the (−) terminal of the subtractor 142 by the sampling clock. This is added to the multiplier 143. That is, the phase error is calculated from the data before and after one sampling clock of the reproduction data output as a discrimination result to the multiplier 143.
[0041]
Reference numeral 16 denotes an error transition extraction circuit, which is an error transition extraction means comprising two DFFs 161 and 162, a subtractor 163, and a level slice circuit 164. An error calculation result delayed by one reproduction clock by the DFF 104 is subjected to pattern detection. Based on the detection result of the circuit 13, the output is latched by the DFF 161. The output is similarly latched by the DFF 162 based on the detection result of the pattern detection circuit 13. The subtracter 163 subtracts the output of the DFF 162 from the output of the DFF 161. Further, the level slice circuit 164 compares the subtraction result with a predetermined slice level and outputs it as an error transition extraction result if it is within the predetermined slice level. That is, if the output of the subtracter 163 exceeds the positive slice level (positive sl in FIG. 1), or falls below the negative slice level (negative sl in FIG. 1), the output is set to “0”, otherwise Output as is.
[0042]
Since a delay of one reproduction clock occurs in the detection result of the pattern detection circuit 13, the input data to the error transition extraction circuit 16 is delayed by one reproduction clock via the DFF 104 to the output of the error calculation circuit 14. Here, as the input data of the error transition extraction circuit 16, only the result of the error calculation from the data around one sampling clock with respect to the current reproduction data of the detected pattern is input.
[0043]
Reference numeral 17 denotes an accumulating circuit as accumulating means, which includes an adder 171, a register 172, and a coefficient unit 173. The error transition extraction result is a register in which the adder 171 holds the addition result from the adder 171. The output of 172 is cumulatively added, and the addition result is again held in the register circuit 172 and multiplied by the coefficient K2 in the coefficient unit 173, and output as a cumulative result.
[0044]
Reference numeral 18 denotes a voltage-controlled oscillation circuit as a sampling clock generation means, and a sampling clock generated by adjusting the phase and frequency based on the accumulated value of the error calculation result and the error transition extraction result multiplied by the coefficient K1 by the coefficient unit 15. Output. That is, the frequency of the generated sampling clock is instantaneously increased if the input error calculation result is a positive value, and is instantaneously decreased if the input error calculation result is a negative value. Further, if the accumulated value of the input error transition result is a positive value, the frequency is large, and if it is a negative value, the frequency is small. The sampling clock is supplied to the A / D conversion circuit 11, the DFF 101, and the frequency dividing circuit 19, respectively.
[0045]
Reference numeral 19 denotes a frequency dividing circuit as a reproduction clock generating means, which generates and outputs a reproduction clock by dividing the sampling clock by two. The recovered clock is supplied to each DFF 102, 103, 104, 141, pattern detection circuit 13, and accumulation circuit 17.
[0046]
FIG. 2 is a block diagram showing a configuration example of the pattern detection circuit 13 in the regenerative clock extraction apparatus according to the present embodiment.
[0047]
The pattern detection circuit 13 of FIG. 2 includes two DFFs 131 and 132, two zero value determination circuits 1331 and 1333, a positive / negative value determination circuit 1332, and an AND circuit 134. The 3 From the value discrimination circuit 12 3 values The discrimination result is And input to the zero value discrimination circuit 1331, Delayed by one recovery clock in DFF131 The After being delayed by the DFF 131, it is input to the government discrimination circuit 1332 and , DFF132 further delays one reproduction clock . zero In the value discrimination circuits 1331 and 1333 Is When the ternary discrimination result is “0”, the output is “1”, otherwise, “0” is output. DFF13 After 1 In the positive / negative value discrimination circuit 1332 Is ternary When the determination result is “1” or “−1”, the output is “1”, otherwise “0” is output. The logical product circuit 134 calculates the logical product of the inputs from the positive / negative value discriminating circuit 1332 and the two zero value discriminating circuits 1331 and 1333, and outputs the result as a detection result. That is, 3 values A reproduction pattern having a discrimination result series of “0, 1, 0” or “0, −1, 0” is detected.
[0048]
FIG. 4 is a timing chart showing the relationship between the reproduced differential waveform signal, the sampling clock, and the recovered clock in the recovered clock extraction apparatus of the embodiment of FIG. 1 using the pattern detection circuit of FIG. In FIG. 4, points a to p represent timings at which reproduction data is fetched every other sampling timing in the A / D conversion circuit 11, and the values of the digital data to be reproduction data obtained by sampling are indicated. Symbols “A” to “P” are respectively represented, and digital data therebetween are respectively represented by symbols “A ′” to “O ′”.
[0049]
In the present embodiment, the reproduced differential waveform signal is sampled by the A / D conversion circuit 11 every time the sampling clock rises and latched by the next DFF 101, but the next DFF 102 is further output from the frequency divider circuit 16. Since the output of the DFF 101 in the previous stage is latched for each reproduction clock, the reproduction data becomes “A” to “P”, and “A ′” to “O ′” do not become reproduction data, and this data is used. The error calculation circuit 14 performs error calculation. In order to simplify the explanation, a single frequency is used for the reproduced differential waveform signal.
[0050]
FIG. 4A shows the characteristics when the reproduction clock frequency matches the reproduction differential waveform signal. In this case, it is determined that the reproduction data is “1” or “−1” as “B”, “D”, “F”, “H”, “J”, “L”, “N”, “N”. The error calculation result is calculated by taking the difference between the data before and after each. For example, “B” is “A′−B ′” (= {A′−B ′} × {1}), and “D” is “D′−C ′” (= {C′−D Error calculation is performed by '} × {−1}). Also, “0, 1, 0” or “0, −1, 0” reproduction patterns are detected as “A, B, C”, “C, D, E”, “E, F, G”. ”,“ G, H, I ”,“ I, J, K ”,“ K, L, M ”,“ M, N, O ”patterns, which are positive or negative values at the center of each pattern. An error transition extraction is performed by taking a difference between an error calculation result based on previous and subsequent sampling data and an error calculation result when a pattern is detected immediately before, and extracting only a difference result within a positive / negative slice level range from the result. For example, when “C, D, E” is detected as a pattern, an error calculation result “A′-B ′” of “A, B, C” previously detected from the error calculation result “D′−C ′” is detected. "(D'-C ')-(A'-B')" minus "" is compared with the positive slice level and the negative slice level, and only the result within the positive / negative slice level range becomes the error transition extraction result.
[0051]
Here, in the phase of FIG. 4A, the error calculation result at each timing is almost zero, the error transition extraction result is also almost zero, the accumulation result in the accumulating circuit 17 is not changed, and the voltage control oscillation is performed. The frequency of the sampling clock generated in the circuit 18 is maintained, and the phase and frequency of the reproduction clock remain as they are for the reproduction differential waveform signal.
[0052]
FIG. 4A shows characteristics when the frequency of the reproduction clock with respect to the reproduction differential waveform signal is small. In this case, it is determined that the reproduction data is “1” or “−1” as “B”, “D”, “F”, “H”, “J”, “M”, “O” data. The difference value based on the data before and after one sampling clock is the error calculation result. The error calculation results “A′−B ′”, “D′−C ′”, “E′−F ′”, “H′−G ′”, and “I′−J ′” are positive values, respectively. “−M” and “O′−N” ”are negative values. Moreover, the positive value gradually increases from “A′−B ′” to “I′−J ′”, suddenly reverses to a negative value at “L′−M ′”, and gradually decreases. When the relationship between the frequency of the reproduced differential waveform signal and the sampling clock changes as it is, the error calculation result shows that the positive value and the negative value increase and decrease alternately, and as a result, the total sum thereof becomes almost zero.
[0053]
On the other hand, “0, 1, 0” or “0, −1, 0” playback patterns are detected as “A, B, C”, “C, D, E”, “E, F, G”. ”,“ G, H, I ”,“ I, J, K ”,“ L, M, N ”,“ N, O, P ”, which are positive or negative values at the center of each pattern. An error transition extraction is performed by taking a difference between an error calculation result based on previous and subsequent sampling data and an error calculation result when a pattern is detected immediately before, and extracting only a difference result within a positive / negative slice level range from the result. For example, the difference between the error calculation result “D′−C ′” in the pattern “C, D, E” and the error calculation result “A′−B ′” of “A, B, C” of the pattern detected before that. The result “(D′−C ′) − (A′−B ′)” is a positive value. Similarly, the difference result in “E, F, G” is a positive value, and the difference result is a positive value until the timing of “I, J, K”. However, the difference result “(L′−M ′) − (I′−J ′)” at the timing of “L, M, N” is a large negative value, but at the timing of “N, O, P”. The difference result “(O′−N ′) − (L′−M ′)” becomes a positive value again. As described above, the difference result in the subtracter 163 changes so that a positive value appears continuously and then becomes a large negative value once again. These difference results are compared with the positive slice level and the negative slice level, and only the difference results within the positive and negative slice level range are accumulated as error transition extraction results.
[0054]
FIG. 5 shows the relationship between the error calculation result, the subtraction result by the subtractor 163, the accumulated result of the error transition extraction value, and the time t in the case of FIG.
[0055]
FIG. 5A shows an error calculation result, and positive values and negative values repeatedly appear so as to be point-symmetric at the zero point, and as a result, the sum of them becomes almost zero.
[0056]
FIG. 5 (a) shows the result of subtraction by the subtracter 163. When the error calculation result changes greatly from a positive value to a negative value, a large negative value appears. The level slice circuit 164 compares with the positive or negative slice level, excludes only negative values that appear large, and outputs other positive values as error transition extraction results.
[0057]
FIG. 5 (c) shows the accumulation result. By accumulating the error transition extraction result, the accumulation result becomes a positive value and represents the frequency deviation amount of the sampling clock from the reproduced differential waveform signal.
[0058]
As described above, in the phase of FIG. 4A, the error calculation result at each timing repeatedly outputs a positive value and a negative value, and the sum of them is almost zero, but the error transition extraction value in the accumulation circuit 17 As a result, the frequency of the sampling clock generated in the voltage controlled oscillation circuit 18 is increased, and the frequency of the reproduction clock is corrected to be higher with respect to the reproduction differential waveform signal, that is, in a direction matching the frequency. Is done.
[0059]
FIG. 4C shows the characteristics when the frequency of the reproduction clock with respect to the reproduction differential waveform signal is large. In this case, it is determined that the reproduction data is “1” or “−1” as “B”, “D”, “F”, “H”, “J”, “M”, “O” data. The difference value based on the data before and after one sampling clock is the error calculation result. The error calculation results “A′−B ′”, “D′−C ′”, “E′−F ′”, “H′−G ′”, and “I′−J ′” are negative values, respectively. '-L'"and"N'-O'"each have a positive value. Moreover, from “A′-B ′” to “I′-J ′”
Until “,” the negative value gradually decreases, and at “L′−M ′”, it is reversed to a positive value and gradually increases in the positive direction.
[0060]
When the relationship between the frequency of the reproduced differential waveform signal and the sampling clock remains unchanged, the error calculation results in repeated increases and decreases in positive and negative values as in FIG. Their sum is almost zero. On the other hand, “0, 1, 0” or “0, −1, 0” playback patterns are detected as “A, B, C”, “C, D, E”, “E, F, G”. ”,“ G, H, I ”,“ I, J, K ”,“ L, M, N ”,“ N, O, P ”, which are positive or negative values at the center of each pattern. An error transition extraction is performed by taking a difference between an error calculation result based on previous and subsequent sampling data and an error calculation result when a pattern is detected immediately before, and extracting only a difference result within a positive / negative slice level range from the result. For example, the difference between the error calculation result “D′−C ′” in the pattern “C, D, E” and the error calculation result “A′−B ′” of “A, B, C” of the pattern detected before that. The result “(D′−C ′) − (A′−B ′)” is a negative value. Similarly, the difference result in “E, F, G” is also a negative value, and the difference result is a negative value until the timing of “I, J, K”. However, the difference result “(L′−M ′) − (I′−J ′)” at the timing of “L, M, N” is a large positive value, but at the timing of “N, O, P”. The difference result “(O′−N ′) − (L′−M ′)” becomes a negative value again. In this way, the difference result in the subtracter 163 changes so that a negative value continuously appears and then once becomes a large positive value and a negative value appears again. These difference results are compared with the positive slice level and the negative slice level, and only the difference results within the positive and negative slice level range are accumulated as error transition extraction results.
[0061]
FIG. 6 shows the relationship between the error calculation result, the subtraction result by the subtractor 163, the cumulative result of the error transition extraction value, and the time t in the case of FIG.
[0062]
FIG. 6A shows the error calculation result. The positive value and the negative value repeatedly appear so as to be symmetric with respect to the zero point, and as a result, the sum thereof becomes almost zero.
[0063]
FIG. 6 (a) shows the result of subtraction by the subtractor 163. When the error calculation result changes greatly from a negative value to a positive value, a large positive value appears. Otherwise, the result becomes a negative value. The level slice circuit 164 compares only positive or negative slice levels, excludes only positive values that appear large, and outputs other negative values as error transition extraction results.
[0064]
FIG. 6 (c) shows the accumulation result. By accumulating the error transition extraction result, the accumulation result becomes a negative value and represents the frequency deviation amount of the sampling clock from the reproduced differential waveform signal.
[0065]
As described above, in the phase of FIG. 4C, the error calculation result at each timing repeatedly outputs a positive value and a negative value, and their sum is almost zero, but the error transition extraction result in the accumulation circuit 17 As a result, the frequency of the sampling clock generated in the voltage controlled oscillation circuit 18 is reduced, and the frequency of the recovered clock is corrected to be lower than that of the recovered differential waveform signal, that is, in a direction that matches the frequency. The
[0066]
Here, the reproduction pattern detected by the pattern detection circuit 13 performs pattern detection in the three states of the present, the past, and the future, but the same effect can be obtained by performing the detection in the two states of the present and the past. FIG. 3 is a block diagram showing the configuration of the pattern detection circuit in this case.
[0067]
The pattern detection circuit in FIG. 3 includes a DFF 131, two positive value determination circuits 1334 and 1337, two negative value determination circuits 1335 and 1336, two logical product circuits 136 and 137, and an OR circuit 138. The discrimination result from the value discrimination circuit 12 is delayed by one reproduction clock by the DFF 131. The discrimination result from the ternary discrimination circuit 12 and the output from the DFF 131 are “1” when the ternary discrimination result is “1” in the positive value discrimination circuits 1334 and 1337, and “0” otherwise. Is output. The negative value determination circuits 1335 and 1336 output “1” when the ternary determination result is “−1”, and output “0” otherwise. The AND circuit 136 sets the output to “1” when the outputs of the positive value determination circuit 1334 and the negative value determination circuit 1335 are both “1”, and sets it to “0” otherwise. Similarly, the AND circuit 137 sets the output to “1” when the outputs of the negative value determination circuit 1336 and the positive value determination circuit 1337 are both “1”, and sets it to “0” otherwise. The logical sum circuit 138 outputs “1” if any one of the logical product circuits 136 and 137 is “1”, and outputs “0” if both are “0” as a detection result. That is, the reproduction pattern “1, −1” or “−1, 1” is configured to be detected. When this pattern detection circuit is used, in the block diagram of FIG. 1, the input of the DFF 161 is input by multiplying the output of the DFF 141 by the output of the ternary discrimination circuit 12 (not shown). That is, the three-value discrimination result is multiplied by the data one sampling clock before the reproduction data to be discriminated and used as an input to the error transition extraction circuit.
[0068]
FIG. 7 is a timing chart showing the relationship between the reproduction differential waveform signal, the input of the error transition extraction circuit, the sampling clock, and the reproduction clock in the reproduction clock extraction apparatus of the present embodiment when using the pattern detection of FIG. Points a to p represent timings at which reproduced data is fetched every other sampling timing of the A / D conversion circuit 11, and the values of the digital data to be reproduced data obtained by sampling are represented by the symbols “A”. ”To“ P ”, and digital data in the meantime are represented by“ A ′ ”to“ P ′ ”, respectively.
[0069]
As in FIG. 4, the reproduced differential waveform signal is sampled by the A / D conversion circuit 11 every time the sampling clock rises and is latched by the next DFF 101, but the next DFF 102 is output from the frequency dividing circuit 16. Since the output of the DFF 101 in all stages is latched for each reproduction clock, the reproduction data is “A” to “P”, and “A ′” to “P ′” are not reproduction data, and this data is used. The error calculation circuit 14 performs error calculation. In order to simplify the explanation, a single frequency is used for the reproduced differential waveform signal.
[0070]
FIG. 7A shows a case where the frequency of the reproduction clock matches the reproduction differential waveform signal. In this case, the reproduction data is determined to be “1” or “−1” for all data “A” to “P”, and the error calculation result is the difference between the sampling data before and after each. If “B”, “A′−B ′” (= [A′−B ′] × [1]), and if “C”, “C′−B ′” (= [
Error calculation is performed by B′−C ′] × [−1]). Also, "1, -1" or
"-1, 1" is detected when "A, B", "B, C", "C, D", "D, E", "E, F", "F, G "," G, H "," H, I "," I, J "," J, K "," K, L "," L, M "," M, N "," N, O " , “O, P” patterns, which are obtained by multiplying the data between the current and past data of each pattern by the ternary discrimination result of the current data, as an input to the error transition extraction circuit 16. This is compared with the input when the pattern is detected previously, and error transition extraction is performed by extracting only the difference result within the positive / negative slice level range from the result. For example, when a pattern is detected for “B, C”, “−B ′” obtained by multiplying the data “B ′” in the meantime by the ternary discrimination result “−1” of “C”, the pattern detected before that “ “(−B′−A ′)” obtained by subtracting “A ′” obtained by multiplying the data “A ′” between “A” and “B” by the ternary discrimination result “1” of “B” is used as the difference result. The result is compared with the positive slice level and the negative slice level, and only the result within the positive / negative slice level range becomes the error transition extraction result.
[0071]
Here, in the phase of FIG. 7A, the error calculation result at each timing becomes almost zero, the error transition extraction result becomes almost zero, the accumulation result in the accumulation circuit 17 does not change, and the voltage controlled oscillation circuit 18 is changed. The frequency of the sampling clock generated in is maintained, and the phase of the recovered clock remains with respect to the recovered differential waveform signal.
[0072]
FIG. 7A shows characteristics when the frequency of the reproduction clock with respect to the reproduction differential waveform signal is small. In this case, the reproduction data is determined to be “1” or “−1” as “A”, “B”, “C”, “D”, “E”, “F”, “N”, “ The error calculation result, which is the difference value between the data before and after one sampling clock, is a positive value until the timing of “B” to “F”, and “N” to “P”. It becomes a negative value at the timing. In addition, the positive value gradually increases from the timing “B” to “F”, and is largely reversed to the negative value at the timing “N” and gradually decreases. When the relationship between the frequency of the reproduced differential waveform signal and the sampling clock changes as it is, the error calculation result shows that the positive value and the negative value increase and decrease alternately, and as a result, the total sum thereof becomes almost zero. On the other hand, the reproduction pattern “1, −1” or “−1, 1” is detected as “A, B”, “B, C”, “C, D”, “D, E”, “ E, F ”,“ N, O ”,“ O, P ”patterns, and the error transition extraction circuit includes three values of the current data in the data between the current and past data used for detecting each pattern. A product obtained by multiplying the discrimination result is input, and FIG. 7C shows the input of the error transition extraction circuit. Thus, “A ′”, “−B ′”, “C ′”, “−D ′”, “E ′” are positive values, and “−M ′”, “N ′”, “−O ′” , “P ′” is a negative value. The error transition extraction result is a positive value except for the timing when it changes from “E ′” to “−M ′”, and the negative value that appears greatly is excluded by the level slice circuit, so the accumulated result is a positive value.
[0073]
As described above, in the phase of FIG. 7A, the error calculation result at each timing repeatedly outputs a positive value and a negative value, and the sum of them is almost zero, but the error transition extraction result in the accumulation circuit 17 Is a positive value, the frequency of the sampling clock generated in the voltage controlled oscillation circuit 18 is increased, and the frequency of the recovered clock is increased with respect to the recovered differential waveform signal, that is, in the direction of matching the frequency. Will be corrected.
[0074]
FIG. 7D shows the case where the frequency of the reproduction clock with respect to the reproduction differential waveform signal is large. In this case, the reproduction data is determined to be “1” or “−1” as “A”, “B”, “C”, “D”, “E”, “F”, “G”, “ The error calculation result, which is the difference value between the data before and after one sampling clock, is a negative value until the timing of “B” to “H”, and the timing after “P”. Positive value. In addition, the negative value gradually increases from the timing “B” to “H”, and is largely reversed to a positive value at the timing “P” and gradually decreases. When the relationship between the frequency of the reproduced differential waveform signal and the sampling clock changes as it is, the error calculation result shows that the positive value and the negative value increase and decrease alternately, and as a result, the total sum thereof becomes almost zero. On the other hand, the reproduction pattern “1, −1” or “−1, 1” is detected as “A, B”, “B, C”, “C, D”, “D, E”, “ E, F ”,“ F, G ”,“ G, H ”patterns, and the error transition extraction circuit includes three values of the current data in the data between the current and past data used for detecting each pattern. A product obtained by multiplying the discrimination result is inputted, and FIG. 7 (o) shows an input of the error transition extraction circuit. Thus, “A ′”, “−B ′”, “C ′”, “−D ′”, “E ′”, “−F ′”, “G ′” are negative values, and “−O ′” Is positive. The error transition extraction result is a negative value except for the timing of changing from “G ′” to “−O ′”, and the positive value that appears greatly is excluded by the level slice circuit, so the accumulated result is a negative value.
[0075]
Thus, in the phase of FIG. 7D, the error calculation result at each timing repeatedly outputs a positive value and a negative value, and the sum of them is almost zero, but the error transition extraction result in the accumulation circuit 17 Result in a negative value, the frequency of the sampling clock generated in the voltage-controlled oscillation circuit 18 becomes smaller, and the frequency of the reproduced clock becomes lower with respect to the reproduced differential waveform signal, that is, in the direction in which the frequency matches. Will be corrected.
[0076]
The reproduction patterns detected by the pattern detection circuit are limited to “0, 1, 0” and “0, −1, 0”, or “1, −1” and “−1, 1”. By using a mixture, the frequency of error transition extraction increases and more effective sampling clock control can be performed.
[0077]
As described above, according to the present embodiment, sampling for A / D conversion is performed with a sampling clock having a rate twice the data rate, and the error calculation circuit 14 uses the sample data other than the reproduction data to perform A / D conversion. The phase error of the instantaneous sampling timing of the conversion is calculated, and the error transition extracting circuit 16 and the accumulating circuit 17 accumulate the instantaneous timing error transition based on the pattern detection, thereby reducing the frequency error of the sampling clock of the A / D conversion. In order to perform the calculation, in addition to the phase pull-in capability, it has a wide frequency pull-in capability.
[0078]
(Embodiment 2)
Embodiment 2 of the present invention will be described below with reference to the drawings.
[0079]
FIG. 8 is a block diagram of the reproduction clock extraction apparatus of the present embodiment. In addition to the configuration of FIG. 1 in the first embodiment, a reproduction processing circuit 50, a comparator 51, and a reproduction data acquisition detection means are further provided. The coefficient unit 30 and a switching circuit (hereinafter abbreviated as SW) 20 are provided, and detailed description other than the reproduction processing circuit 50, the coefficient unit 30, the comparator 51, and the SW 20 is omitted here.
[0080]
In FIG. 8, 50 is a reproduction processing circuit, which comprises a demodulation circuit 501, a sync detection circuit 502, and an error correction circuit 503, and the output of the DFF 102 is inputted as reproduction data. In the reproduction processing circuit 50, demodulation processing is performed by the demodulation circuit 501, and the sync detection circuit 502 detects sync data added every predetermined length of the input data and generates it for the data demodulated by the error correction circuit 503. The data error being corrected is corrected and demodulated data is output.
[0081]
Here, the error correction processing is indispensable for transmission of digital data, for example, recording / reproduction, and therefore, in general, an error correction code for error correction is added in addition to the original data to be recorded. Further, since the error correction processing is performed in units of data blocks for each predetermined length, it is also common that synchronization sync data for recognizing the start of the block unit for error correction is also added. FIG. 9 is a schematic diagram showing an example of a data block.
[0082]
9A shows the data block group described above, and FIG. 9A shows one data block unit constituting the data block group of FIG. 9A. In general, the data in the b section in FIG. 9 (a) is the original recorded data, the sync data is arranged in the preceding a section, and the error correction code is arranged in the c section after the original data. The configuration to take is taken.
[0083]
When such a series of input data is reproduced by the reproduction processing circuit 50, a sync pattern is detected first, a data block unit for error correction is recognized, and then error correction is performed. If the sync pattern cannot be detected, the data block to be corrected cannot be recognized even if the error correction is performed, so that all data errors occur. In error correction, the data error can be corrected and the number of data errors can be detected by verifying only the original data that is input or the result of calculation based on the sync data and the original data with the error correction code.
[0084]
Therefore, the acquisition of reproduced data is detected by comparing the sync detection result of the sync detection circuit 502 or the number of data errors of the error correction circuit 503 with a predetermined threshold value (th in FIG. 8) in the comparator 51. In the reproduction data acquisition detection result, the detection output is “0” until the number of detected syncs within a certain period becomes equal to or greater than a predetermined threshold value, and “1” when the number exceeds the predetermined value. Alternatively, the detection output is “0” until the number of data errors within a predetermined period becomes equal to or less than a predetermined threshold value, and when it becomes equal to or less than the predetermined value, “1” is output to the SW 20.
[0085]
The coefficient unit 30 multiplies the error calculation result output from the error calculation circuit 14 by the coefficient K3 and outputs the result.
[0086]
The SW 20 switches between the output of the coefficient unit 30 and the error transition extraction result of the error transition extraction circuit 16 based on the reproduction data acquisition detection result of the comparator 51 and outputs the result to the accumulation circuit 17. That is, when the reproduction data acquisition detection result is “0”, cumulative addition is performed according to the calculation result of the error transition extraction circuit 16, and when the reproduction data acquisition detection result is “1”, cumulative addition is performed based on the error calculation result. Frequency control in the control oscillation circuit 18 is performed.
[0087]
FIG. 10 shows the relationship between the frequency error of the sampling clock and the time t with respect to the input signal of the reproduction clock extraction apparatus of this embodiment. In FIG. 10, the horizontal axis represents time, and the vertical axis represents the frequency error between the input signal and the sampling clock.
[0088]
Since the frequency of the sampling clock has an error with respect to the input frequency so that reproduced data cannot be acquired in the period t1 in FIG. 10, the oscillation frequency of the voltage controlled oscillation circuit 18 is controlled in this period by the accumulated result of the error transition extraction result. . In the section t2, the frequency error is almost eliminated and the acquisition of the reproduction data is detected. The oscillation frequency of the voltage controlled oscillation circuit 18 is controlled by accumulating the result obtained by multiplying the error calculation result by the coefficient K3 with respect to the accumulated result so far. Is done. That is, the gain of the loop is increased by accumulating the error transition extraction results so that a quick frequency response can be made in the interval t1, and the error calculation result multiplied by a coefficient is accumulated so that a stable frequency response can be made in the interval t2. This reduces the loop gain.
[0089]
In this way, when reproduction data cannot be acquired, that is, when the frequency is not matched, a wide frequency pull-in range and quick frequency response can be provided by the cumulative addition value of the error transition extraction result. In addition, when reproduction data can be acquired, that is, when the frequency is almost the same, the accumulated addition value of the error transition until then is held, and the error calculation result is added to the result, thereby stabilizing A frequency response is obtained, and as a result, a quick frequency pull-in characteristic and a stable frequency follow-up characteristic are combined.
[0090]
In the above description of the first and second embodiments of the present invention, the voltage-controlled oscillation circuit 18 corrects the phase of the generated clock by changing the frequency instantaneously. For example, a delay device is used. It is also possible by other methods such as performing.
[0091]
In the description of the first and second embodiments, no equalization processing is performed on the reproduction signal, but the digital data output from the A / D conversion circuit 11 is digitally subjected to adaptive equalization processing. It is also possible to perform subsequent processing.
[0092]
In this case, the delay for the adaptive equalization processing increases the delay of the control loop from A / D conversion to clock recovery, and the conventional method will further reduce the clock pull-in range. In the first or second embodiment, the clock frequency pull-in capability is provided, and such a configuration can be dealt with. In other words, even if digital adaptive equalization processing and timing error calculation are performed at the same time in an unequalized state or a state where there is an equalization residue, both converge quickly, and adaptive equalization and sampling timing are optimal values. It becomes.
[0093]
【The invention's effect】
As described above, according to the present invention, when sampling of A / D conversion is performed with a sampling clock having a rate twice as high as the data rate, and the sampling timing error of A / D conversion is calculated, sampling data other than reproduction data is obtained. The error calculation means calculates the sampling timing phase error of the A / D conversion, and calculates the frequency error based on the accumulated value of the extraction result of the error transition extraction means based on the pattern detection result. For this reason, there is an excellent effect that the sampling clock has a phase pull-in capability and a wide frequency pull-in capability.
[0094]
In addition, a playback data acquisition detection means is provided to detect whether or not the data being played back has been acquired, and based on the playback data acquisition detection result, the input of the accumulation means is switched between the error transition extraction result and the error calculation result. Used to control the frequency of the sampling clock. Therefore, an excellent effect is achieved in that a quick frequency response and a stable frequency follow-up property can be provided together with a wide frequency pull-in range.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a recovered clock extraction apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of a pattern detection circuit of the recovered clock extraction apparatus according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing another configuration example of the pattern detection circuit of the recovered clock extraction apparatus according to the first embodiment of the present invention.
FIG. 4 is a timing chart of a recovered clock extraction device according to Embodiment 1 of the present invention.
FIG. 5 is a characteristic diagram of error transition extraction means of the recovered clock extraction apparatus according to Embodiment 1 of the present invention;
FIG. 6 is a characteristic diagram of error transition extraction means of the recovered clock extraction device according to the first embodiment of the present invention;
FIG. 7 is a timing chart of another configuration of the pattern detection circuit of the recovered clock extraction apparatus according to the first embodiment of the present invention;
FIG. 8 is a block diagram showing a configuration of a recovered clock extraction apparatus according to a second embodiment of the present invention.
FIG. 9 is a schematic diagram showing the principle of reproduction data acquisition detection means of the reproduction clock extraction apparatus according to the second embodiment of the present invention.
FIG. 10 is a characteristic diagram of a recovered clock extraction apparatus according to Embodiment 2 of the present invention;
FIG. 11 is a block diagram showing a configuration of a conventional recovered clock extraction device.
FIG. 12 is a timing chart of an error calculation circuit of a conventional reproduction clock extraction device.
FIG. 13 is a timing chart of an error calculation circuit of a conventional recovered clock extraction device.
FIG. 14 is a block diagram showing a configuration example of an error accumulating circuit of a conventional recovered clock extracting device.
FIG. 15 is a frequency drawing characteristic diagram of a conventional recovered clock extraction device.
[Explanation of symbols]
11 A / D conversion circuit
12 3-value discrimination circuit
13 Pattern detection circuit
14 Error calculation circuit
15 Coefficient unit
16 Error transition extraction circuit
17 Accumulation circuit
18 Voltage controlled oscillator circuit
19 Frequency divider
20 switching circuit
30 coefficient multiplier
50 Playback circuit
51 comparator

Claims (14)

Quantization means for quantizing an input signal with a sampling clock having a rate twice as high as a data rate;
The even columns sampling data of one sampling clock intervals of the sampling data output from the quantization means, a ternary discrimination means for performing the three values determined whether a positive value or zero value or negative value as reproduced data,
Pattern detection means for detecting only a specific combination from a plurality of successive determination results output by the ternary determination means;
Data obtained by delaying the sampling data output from the quantizing unit and the sampling data output from the quantizing unit using odd-numbered column sampling data between two consecutive reproduction data in which the determination result of the ternary determining unit changes And an error calculation means for calculating a sampling timing error obtained by multiplying the determination result by the ternary determination means ,
Wherein the product obtained by multiplying the polarity of the detection pattern in odd columns sampling data to the product obtained by multiplying the polarity of the detected pattern or a plurality of differences in the odd-numbered columns sampling data, located between the plurality of reproduction data to be used for pattern detection pattern detection and held on the basis of the detection result of means, taking the past retention data and the difference, an error transition extracting means for extracting only the difference result within a predetermined level range,
Accumulating means for inputting and accumulating the extraction result of the error transition extracting means;
Upon generation of the sampling clock to be supplied to said quantization means,-out based on the cumulative result of the operation result and the accumulation means of the error calculating unit, and a sampling clock generation means for adjusting the phase and frequency,
A reproduction clock extraction device comprising reproduction clock generation means for generating a reproduction clock by dividing the sampling clock by two. Quantization means for quantizing an input signal with a sampling clock having a rate twice as high as a data rate;
The even columns sampling data of one sampling clock intervals of the sampling data output from the quantization means, a ternary discrimination means for performing the three values determined whether a positive value or zero value or negative value as reproduced data,
Pattern detection means for detecting only a specific combination from a plurality of successive determination results output by the ternary determination means;
Data obtained by delaying the sampling data output from the quantizing unit and the sampling data output from the quantizing unit using odd-numbered column sampling data between two consecutive reproduction data in which the determination result of the ternary determining unit changes And an error calculation means for calculating a sampling timing error obtained by multiplying the determination result by the ternary determination means ,
Wherein the product obtained by multiplying the polarity of the detection pattern in odd columns sampling data to the product obtained by multiplying the polarity of the detected pattern or a plurality of differences in the odd-numbered columns sampling data, located between the plurality of reproduction data to be used for pattern detection pattern detection and held on the basis of the detection result of means, taking the past retention data and the difference, an error transition extracting means for extracting only the difference result within a predetermined level range,
Accumulating means for inputting and accumulating the calculation result of the error calculation means or the extraction result of the error transition extraction means;
Upon generation of the sampling clock to be supplied to said quantization means,-out based on the cumulative result of the operation result and the accumulation means of the error calculating unit, and a sampling clock generation means for adjusting the phase and frequency,
Regenerated clock generating means for generating a regenerated clock by dividing the sampling clock by two;
A reproduction clock extraction device comprising reproduction data acquisition detection means for detecting whether or not reproduced data has been acquired,
Ri by the detection result of the reproduction data acquisition detection means, and wherein the controlled is possible to input the accumulation means selects one of the extracted result of the operation result and the error transition extracting means of said error calculating means Regenerative clock extraction device. Said error calculating means, and the previous reproducing data determination result of the ternary determination means is the determination target, by multiplying the difference between the odd column sampling data immediately after the sampling timing error in the quantization means and clock recovery device according to claim 1 or 2, characterized in that so as to calculation. Said pattern detecting means, the current discrimination result output by said ternary determining means a positive or negative value, the determination result of the before and after that to detect the specific combination of a zero value and clock recovery device according to claim 1 or 2, characterized. Said error transition extracting means-out based on a detection result of the pattern detection means, the difference between the odd column sampling data before and after the reproduced data is the current discrimination result of the discrimination object used in the pattern detection, the current 5. The reproduction clock according to claim 4 , wherein a product obtained by multiplying a reproduction data ternary discrimination result is held, a difference from past holding data is taken, and only a difference result within a predetermined level range is extracted. Extraction device. Said pattern detecting means, characterized in that the current discrimination result output by the ternary discrimination means different from the determination result of the immediately preceding and to detect the particular combination not and zero values both determination results reproducing clock extracting apparatus according to any claim 1 or 2,. Said error transition extracting means-out based on a detection result of the pattern detection means, the odd column sampling data immediately before the reproduction data is the current discrimination result of the discrimination object used for the pattern detection, the current reproduction data 7. A regenerative clock extracting apparatus according to claim 6 , wherein a product obtained by multiplying the three-value discrimination result is held, a difference from past held data is taken, and only a difference result within a predetermined level range is extracted. . It said sampling clock generating means, a transmission frequency control by phase control of the output of the error calculating unit, and a transmission frequency control by frequency control of the output of the accumulation means so as to feedback control the quantization means The reproduction clock extraction apparatus according to claim 1 or 2 , wherein the reproduction clock extraction apparatus is a reproduction clock extraction apparatus. The reproduction data acquisition detection means composed of a sync detection means for detecting sync data added to each data block of a predetermined length, and comparing means for comparing the acquired number of sync data in said predetermined period with a predetermined value The reproduction clock extracting apparatus according to claim 2, wherein: The input of the cumulative means until tally of sync data in the predetermined period is equal to or greater than a predetermined value the select extraction result of the error transition extracting means, the calculation result of the error calculating unit if the predetermined value or more The reproduction clock extracting apparatus according to claim 9, wherein the reproduction clock extracting apparatus is controlled so as to select one of the two. The reproduced data acquisition detecting means comprises error correcting means for correcting an error by an error correcting code added to an input signal, and comparing means for comparing the number of code errors from the error correcting means with a predetermined value. The reproduction clock extracting apparatus according to claim 2, wherein: Said input of accumulation means, said code error number from the error correction means selects the extraction result of the error transition extracting means until a predetermined value or less, the calculation result of the error calculating unit if below the predetermined value 12. The reproduction clock extracting apparatus according to claim 11, wherein the reproduction clock extracting apparatus is controlled to select. And clock recovery device according to claim 1 or 2, characterized in that the signal input to the quantization means is a differential waveform. The sampling data output from the quantization means, and clock recovery device according to claim 1 or 2 performs subsequent processing while performing digitally adaptive equalizing process.

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