JP3902909B2 - Low power consumption dynamic random access memory - Google Patents

Low power consumption dynamic random access memory Download PDF

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Publication number
JP3902909B2
JP3902909B2 JP2000219279A JP2000219279A JP3902909B2 JP 3902909 B2 JP3902909 B2 JP 3902909B2 JP 2000219279 A JP2000219279 A JP 2000219279A JP 2000219279 A JP2000219279 A JP 2000219279A JP 3902909 B2 JP3902909 B2 JP 3902909B2
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power supply
circuit
output
internal power
random access
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JP2002042464A (en
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淳一 須山
亘 永井
彰宏 廣田
昇太 大坪
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to KR1020010043351A priority patent/KR100816403B1/en
Priority to TW090117634A priority patent/TW514919B/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Description

【０００１】
【発明が属する技術分野】
この発明は、消費電力を小さくしたダイナミックランダムアクセスメモリに関するもので、特に、携帯電話などに用いて好適な低消費電力型に関するものである。
【０００２】
【従来の技術】
ダイナミックランダムアクセスメモリ（以下DRAMという）はメモリセルをトランジスタとキャパシタで形成するため、高集積化が可能である。このため、他のランダムアクセスメモリ、特にスタティック型ランダムアクセスメモリ（以下SRAMという）と比較して容量あたりの価格が安い。
一方、SRAMは消費電流がDRAMと比較して小さく、特に、データの読み出し、書き込みを行わない待機時の消費電流はDRAMと比較すると格段に小さい。これは、DRAMが待機時にデータ保持のためのリフレッシュ動作を行っていることにも起因している。
DRAMは一般的に外部からの電源（外部電源）によって、駆動され、外部電源の供給が断たれると、DRAM内に保持したデータは消滅する。これは上述のリフレッシュ動作ができなくなり、記憶したデータが保持できないためである。
また、DRAMは外部電源を直接用いてその内部の回路を駆動するのではなく、内部電源発生回路によって外部電源を内部電源に変換して、この内部電源で各回路を駆動するのが一般的になっている。
上述のようなDRAMは、パーソナルコンピュータなどの常に外部電源から電源が供給されている機器においては有用であるが、携帯電話など低消費電流が要求される装置には不向きである。したがって、従来の携帯電話におけるメモリ構成は図２に示すように、データバス１０に共通にコントローラ２０、SRAM３０及びフラッシュメモリ４０が接続され、これらには常に電源５０が供給されている。
【０００３】
【発明が解決しようとする課題】
近年、携帯電話は音声のみでなく、文字情報や画像データなど多くのデータを送受信する傾向にある。DRAMは記憶容量が大きいものの、リフレッシュ動作により電流を消費するとともに、内部電位を発生する回路を有し、この発生回路は定常的に電流を消費する回路構成となっているのが一般的である。このため、携帯電話など低消費電流が要求される装置には不向きである。したがって、従来の携帯電話におけるメモリ構成は図２に示すように、データバス１０に共通にコントローラ２０、SRAM３０及びフラッシュメモリ４０が接続され、これらには常に電源５０が供給されている。
上述したようにDRAMは消費電流が大きいため、携帯電話に用いる場合は、消費電流を抑える必要がある。このため、携帯電話にDRAMを用いようとすれば、図３に示すような構成が考えられる。即ち、SRAM３０及びフラッシュメモリ４０と同様に、DRAM６０はデータバス１０に接続されるが、電源５０とDRAM６０との間にはスイッチ７０を設ける。コントローラ２０はDRAM６０の必要性を判断して、電源５０からの供給をスイッチ７０で立ちきることにより（スイッチ７０をオフさせる）DRAM６０での消費電流を抑えるようにする。
【０００４】
しかしながら、図３のような構成の場合、（１）スイッチ７０といった外部素子を必要とする、（２）DRAMへの電源供給を切った場合、データバス１０から寄生ダイオードを通して電流が流れ込み、DRAM６０が誤動作する可能性があるといった問題がある。このうち、（２）の問題点について図４を用いて詳しく説明する。
DRAM６０の出力回路の最終段がインバータの場合を例に取ると、図４に示すようにインバータ１００はNMOSトランジスタ１１０とPMOSトランジスタ１２０とから構成される。NMOSトランジスタ１１０とPMOSトランジスタ１２０のゲートは共通に入力ノード１５０に接続されている。出力回路の場合、入力ノード１５０はDRAM６０からの出力信号を受取る。PMOSトランジスタ１２０のソースSには電源電位が与えられる。PMOSトランジスタ１２０のドレインDはNMOSトランジスタ１１０のドレインと共通に出力ノード１４０に接続される。出力ノード１４０はDRAM６０の出力端子に接続されるもので、図３のようにDRAM６０が携帯電話などに搭載された場合はデータバス１０に接続される。なお、NMOS１１０のソースには接地電位が与えられる。
【０００５】
ここで、PMOSトランジスタ１２０にはそのドレインDからソースSに向けて順方向の寄生ダイオード１３０（実際にはドレイン−基板間に形成されたもの）が形成されている。電源が切れて、PMOSトランジスタのソースSに電源が供給されなくなってしまうと、PMOSトランジスタ１２０のソースSには電源電位は与えられない。一方、データバス１０にHレベルの信号が与えられると、DRAM６０がデータバスに接続されているため、PMOSトランジスタ１２０のドレインDにはこのHレベルの信号が与えられる。したがって、このHレベル信号が寄生ダイオード１３０を介してPMOSトランジスタ１２０のソースSに与えられる。PMOSトランジスタ１２０のソースSは電源線を介して他の回路に接続されているため、他の回路に電位を供給してしまうのである。また、データバス上のデータについても、Hレベル信号のレベルが低下してLレベルになってしまう可能性もある。
本発明の目的は、上述のような問題に鑑みてなされたものであり、外部の信号によりDRAMとしての消費電流を小さくして、かつこの低消費電流時に誤動作をしない低消費電力型ダイナミックランダムアクセスメモリを提供することにある。
【０００６】
【課題を解決するための手段】
この発明に係る低消費電力型ダイナミックランダムアクセスメモリは、外部電源によって駆動され、内部電源電位を発生する内部電源回路と、入力信号に応じた信号を出力する出力ノードを有する入力回路であって、前記出力ノードから電源電位が与えられる端子に向けて順方向に寄生ダイオードが形成されるトランジスタを有する入力回路と、データを保持するメモリアレイと、このメモリアレイを制御する周辺回路と、信号が出力される出力ノードを有する出力回路であって、前記出力ノードから電源電位が与えられる端子に向けて順方向に寄生ダイオードが形成されるトランジスタを有する出力回路とを有するダイナミックランダムアクセスメモリにおいて、前記入力回路及び出力回路は外部電源によって駆動され、前記メモリアレイ及び周辺回路は、前記内部電源回路によって生成された内部電源電位によって駆動され、外部から入力される制御信号に応答して、前記内部電源回路は不活性化され、かつ前記入力回路及び出力回路は外部電源が供給されたまま前記トランジスタがハイインピーダンス状態に制御される。
【０００７】
【発明の実施の形態】
図１は、この発明の実施例を説明するDRAMのブロック図である。DRAM２００は外部電源２１０によって駆動される。したがって、携帯電話のメモリ構成では図３のDRAM６０がスイッチ７０を介さず、直接電源５０に接続された状態になる。即ち、図３において、DRAM６０がSRAM３０及びフラッシュメモリ４０と同様に接続された状態になる。
外部電源２１０は、第１の内部電源回路群２２０に接続されると共に、出力回路２３０にも接続される。第１の内部電源回路群２２０は、外部電源２１０から受取った電位を変換して内部電源IVCとして入力回路２４０、周辺回路２５０、メモリアレイ２６０及び第２内部電源回路群２７０にこの内部電源IVCを供給する。例えば、外部電源２１０が３．３V、内部電源IVCは２．４Vである。
第１の内部電源回路群２２０は、制御端子２８０を介して電源制御信号CONTを受取る。この電源制御信号CONTは、第１の内部電源回路群２２０を不活性化させる。したがって、第１の内部電源回路群２２０は、入力回路２４０、周辺回路２５０、メモリアレイ２６０及び第２内部電源回路群２７０に内部電源IVCを供給しない。即ち、電源制御信号CONTによって第１の内部電源回路群２２０における消費電流は全くなくなるのである。
【０００８】
なお、第１の内部電源回路群２２０の消費電流をなくすのは、内部電源IVCの電位を０Vにする場合と、外部電源電位にあわせるという場合の２通りが考えられる。ここで、メモリアレイ２６０において、ビットラインとワードラインとがショートしており、この不良部分を冗長で置換えている場合がある。このような状態において、単に内部電源IVCを外部電源電位にあわせている場合だとショート部分に数マイクロAの電流が流れてしまう。したがって、内部電源IVCの電位は０V(接地電位)にするほうが望ましい。
【０００９】
第２の内部電源回路群２７０は、第１の内部電源回路群２２０から内部電源IVCを受けとり、この受取った内部電源IVCを変換して他の内部電源を入力回路２４０、周辺回路２５０及びメモリアレイ２６０に供給する。他の内部電源としては、基板電位、昇圧電位、１／２内部電源電位、レファレンス電位などがある。例えば内部電源が２．４Vのとき、これらの電位はそれぞれ、基板電位-１．０V、昇圧電位３．６V、１／２内部電源電位１．２V、レファレンス電位１．１Vである。
第２の内部電源回路群２７０は、制御端子２８０を介して電源制御信号CONTを受取る。電源制御信号CONTは、第２の内部電源回路群２７０を不活性化させる。このとき、第２の内部電源回路群２７０は第１の電源回路群２２０からの内部電源IVCを受取っていないため、不活性化された状態に近いが、電源制御信号CONTによって完全に不活性化される。したがって、第２の内部電源回路群２７０は、入力回路２４０、周辺回路２５０及びメモリアレイ２６０に内部電源を供給しない。即ち、電源制御信号CONTによって第２の内部電源回路群２７０における消費電流は全くなくなるのである。
【００１０】
入力回路２４０は、信号を受取るため一般的にはデータバスに接続される。即ち、携帯電話等にDRAMが搭載された場合、図３に示されるように、データバス１０と接続される。したがって、電源が供給されていれば外部からのデータ（例えばデータバス１０上のデータ）に応答して、周辺回路２５０へ信号を与える。
入力回路２４０の一般的な例として、図４に示されるようなインバータ１００が挙げられる。ここで、インバータ１００の入力ノード１５０はデータバスに接続され、出力ノード１４０が周辺回路２５０などに接続される。第１の内部電源回路群２２０が不活性化された結果、内部電源IVCが０Vとなった場合は、PMOS１２０のソースには電源電位が与えられなくなるため消費電流が全くなくなる。なお、入力ノード１５０にデータバスから信号が与えられるが、NMOSトランジスタ１１０及びPMOSトランジスタ１２０のソースには電位が与えられないため消費電流は発生せず、また、DRAM内部の回路への影響もない。
また、第１の内部電源回路群２２０が不活性化された結果、内部電源IVCが外部電源と同電位となったなった場合は、入力ノード１５０にデータバスから信号が与えられ、DRAMが動作を開始する可能性がある。そこで、入力回路２４０は、制御端子２８０を介して入力される電源制御信号CONTによって不活性化される方が望ましい。
【００１１】
周辺回路２５０は入力回路からデータを受取り、このデータをメモリアレイ２６０へ与えると共に、メモリアレイ２６０からデータを受取り、出力回路２３０へデータを与える。また、周辺回路２５０はメモリアレイ２６０などを制御するなど様々な回路を包含する。周辺回路２５０は直接DRAM外部とのデータのやり取りを行わないため、第１及び第２の内部電源回路群２２０、２７０及び入力回路２４０が不活性化されると、消費電流は発生させず不活性化状態になる。
なお、DRAM２００がシンクロナスDRAMやRambus系のDRAMの場合、その動作上必要であるCASレイテンシ−、バースト長、出力モードなどのデータがプログラマブルになっている。これらの情報は一般的に動作制御情報を記憶するモードレジスタ内に記憶される。このモードレジスタは、周辺回路内もしくはその近傍に設けられている。このようなDRAMにおいて、周辺回路などへの電源供給を止めてしまうと、格納されていたデータも消失してしまう。そこで、モードレジスタのみを外部電源で駆動するということも考えられる。
また、メモリアレイ２６０も直接DRAM外部とのデータのやり取りを行わないため、第１及び第２の内部電源回路群２２０、２７０及び周辺回路２５０が不活性化されると、消費電流は発生させず不活性化状態になる。
【００１２】
出力回路２３０は、メモリアレイからのデータを出力するため一般的にはデータバスに接続される。即ち、携帯電話等にDRAM２００が搭載された場合、図３に示されるように、データバス１０と接続される。したがって、DRAM２００内部からのデータ（周辺回路２５０から送られてきたデータ）に応答して、信号をデータバスに出力する。
出力回路２３０の一般的な例として、図５に示されるようなインバータ５００が挙げられる。インバータ５００はNMOSトランジスタ５１０、PMOSトランジスタ５２０、NAND回路５６０、NOR回路５７０、第１のインバータ回路５８０、第２のインバータ回路５９０及び第３のインバータ回路６００とから構成される。NMOSトランジスタ５１０のソースは接地電位に、ドレインは出力端子５４０に接続される。PMOSトランジスタ５２０のソースSは電源電位に、ドレインは出力端子５４０に接続される。インバータ５００の入力端子５５０は、NAND回路５６０の第１入力端子に接続されるともに、NOR回路５７０の第１入力端子にも接続される。
NAND回路５６０の第２入力端子には、インバータ５００の制御入力端子６１０から電源制御信号CONTが入力される。この電源制御信号CONTは第３のインバータ回路６００で反転されてNOR回路の第２入力端子にも入力される。NAND回路５６０の出力は第１のインバータ回路５８０を介してNMOSトランジスタ５１０のゲートに接続される。NOR回路５７０の出力は第２のインバータ回路５９０を介してPMOSトランジスタ５２０のゲートに接続される。
なお、出力回路２３０は外部電源で動作しているため、内部電源で動作している回路からの信号をレベルシフタで変換してから受取る必要がある。図示していないが、出力回路２３０の場合、入力端子５５０の手前にはレベルシフタ回路が接続されることになる。なお、ＤＲＡＭの電源が切れた場合にも出力回路２３０の出力をハイインピーダンスに保つ必要があるため、制御入力端子６１０へ供給される信号（図１における制御端子２８０に入力される信号）を供給する回路は、常に外部電源によって駆動されている必要がある。
【００１３】
次に図１及び図３も参照しながら、出力回路２３０の動作を説明する。
インバータ５００の入力端子５５０は、周辺回路２５０に接続され、出力端子５４０がDRAM２００の出力端子などを介してデータバス１０に接続される。ここで、出力回路２３０には外部電源２１０が与えられている。外部電源２１０は常にDRAM２００に与えれれている（携帯電話にDRAM２００が搭載された場合、携帯電話の電源がON状態ならば常に外部電源は与えられている）ため、このインバータ５００のPMOSトランジスタ５２０のソースSには電源電位が、NMOSトランジスタ５１０のソースには接地電位が与えられている。
なお、Lレベルの電源制御信号CONTが入力された場合、NAND回路５６０はその第１入力端子の信号レベルに係らずHレベルの出力信号を、NOR回路５７０はその第１入力端子の信号レベルに係らずLレベルの出力信号を出力する。これらの信号はそれぞれ第１及び第２のインバータ回路５８０、５９０で反転され、NMOSトランジスタ５１０のゲートにはLレベルの信号が、PMOSトランジスタ５２０のゲートにはHレベルの信号が与えられる。したがって、インバータ５００（出力回路２３０）は出力状態がハイインピーダンスになるよう設定される。
【００１４】
このような状態でデータバス１０にHレベルまたはLレベルの信号が転送されても、NMOSトランジスタ５１０及びPMOSトランジスタ５２０においては寄生トランジスタ５３０による電流が流れず、DRAM内部の回路への影響もない。また、NMOSトランジスタ５１０のゲートにはLレベルの信号がPMOSトランジスタ５２０のゲートにはHレベルの信号が与えられているため、NMOSトランジスタ５１０及びPMOSトランジスタ５２０はOFF状態を保ち、消費電流は発生しない。
なお、上述した実施例においては、入力回路はトランジスタのゲートでデータを受取る例で説明したが、入力保護トランジスタなどがあり、出力回路の例で説明したような寄生ダイオードによる電流が考えられる場合は、入力回路においても出力回路同様に外部電源を供給してトランジスタがONしないよう制御すれば良い。
【００１５】
【発明の効果】
以上説明したように、この発明によれば、外部からの制御信号によって内部電源回路、入力回路、メモリアレイ及び周辺回路は不活性とする一方、出力回路へは常に外部電源が与えられるようにしたため、DRAMとしての消費電流を小さくして、かつこの低消費電流時に誤動作をしない低消費電力型ダイナミックランダムアクセスメモリを提供することができる。
【図面の簡単な説明】
【図１】この発明の実施例を示すDRAMのブロック図である。
【図２】携帯電話におけるメモリ構成を示す図である。
【図３】携帯電話においてDRAMを用いようとした場合のメモリ構成を示す図である。
【図４】入力回路及び出力回路において代表的なインバータを示す回路図である。
【図５】出力回路において代表的なインバータを示す回路図である。
【符号の説明】
２００ DRAM
２１０ 外部電源
２２０ 第１の内部電源回路群
２３０ 出力回路
２４０ 入力回路
２５０ 周辺回路
２６０ メモリアレイ
２７０ 第２の内部電源回路群[0001]
[Technical field to which the invention belongs]
The present invention relates to a dynamic random access memory with reduced power consumption, and particularly to a low power consumption type suitable for use in a mobile phone or the like.
[0002]
[Prior art]
A dynamic random access memory (hereinafter referred to as DRAM) can be highly integrated because a memory cell is formed of a transistor and a capacitor. For this reason, the price per capacity is lower than that of other random access memories, particularly static random access memories (hereinafter referred to as SRAM).
On the other hand, the current consumption of the SRAM is smaller than that of the DRAM, and in particular, the current consumption during standby in which data is not read or written is much smaller than that of the DRAM. This is due to the fact that the DRAM performs a refresh operation for holding data during standby.
DRAM is generally driven by an external power supply (external power supply), and when the external power supply is cut off, the data held in the DRAM disappears. This is because the refresh operation described above cannot be performed and stored data cannot be retained.
In addition, DRAM does not drive external circuits directly by using an external power supply, but generally converts an external power supply to an internal power supply by an internal power generation circuit and drives each circuit with this internal power supply. It has become.
The DRAM as described above is useful in a device such as a personal computer that is constantly supplied with power from an external power source, but is not suitable for a device such as a cellular phone that requires low current consumption. Therefore, as shown in FIG. 2, the conventional mobile phone has a memory configuration in which a controller 20, SRAM 30, and flash memory 40 are connected in common to the data bus 10, and a power supply 50 is always supplied to them.
[0003]
[Problems to be solved by the invention]
In recent years, mobile phones tend to transmit and receive not only voice but also a lot of data such as character information and image data. Although DRAM has a large storage capacity, it has a circuit that consumes current by a refresh operation and generates an internal potential, and this generating circuit generally has a circuit configuration that constantly consumes current. . For this reason, it is not suitable for a device such as a cellular phone that requires low current consumption. Therefore, as shown in FIG. 2, the conventional mobile phone has a memory configuration in which a controller 20, SRAM 30, and flash memory 40 are connected in common to the data bus 10, and a power supply 50 is always supplied to them.
As described above, since the DRAM consumes a large amount of current, it is necessary to suppress the consumption current when used in a mobile phone. Therefore, if a DRAM is used in a mobile phone, a configuration as shown in FIG. 3 can be considered. That is, like the SRAM 30 and the flash memory 40, the DRAM 60 is connected to the data bus 10, but a switch 70 is provided between the power supply 50 and the DRAM 60. The controller 20 determines the necessity of the DRAM 60 and suppresses current consumption in the DRAM 60 by turning off the supply from the power supply 50 by the switch 70 (turning off the switch 70).
[0004]
However, in the case of the configuration as shown in FIG. 3, (1) an external element such as a switch 70 is required. (2) When power supply to the DRAM is turned off, current flows from the data bus 10 through the parasitic diode, and the DRAM 60 There is a problem that it may malfunction. Of these, the problem (2) will be described in detail with reference to FIG.
Taking the case where the final stage of the output circuit of the DRAM 60 is an inverter as an example, the inverter 100 includes an NMOS transistor 110 and a PMOS transistor 120 as shown in FIG. The gates of the NMOS transistor 110 and the PMOS transistor 120 are connected to the input node 150 in common. In the case of an output circuit, the input node 150 receives an output signal from the DRAM 60. A power supply potential is applied to the source S of the PMOS transistor 120. The drain D of the PMOS transistor 120 is connected to the output node 140 in common with the drain of the NMOS transistor 110. The output node 140 is connected to the output terminal of the DRAM 60, and is connected to the data bus 10 when the DRAM 60 is mounted on a mobile phone or the like as shown in FIG. A ground potential is applied to the source of the NMOS 110.
[0005]
Here, a forward parasitic diode 130 (actually formed between the drain and the substrate) is formed in the PMOS transistor 120 from the drain D to the source S. If the power is cut off and no power is supplied to the source S of the PMOS transistor, the power source potential is not applied to the source S of the PMOS transistor 120. On the other hand, when an H level signal is applied to the data bus 10, since the DRAM 60 is connected to the data bus, the H level signal is applied to the drain D of the PMOS transistor 120. Therefore, this H level signal is applied to the source S of the PMOS transistor 120 via the parasitic diode 130. Since the source S of the PMOS transistor 120 is connected to another circuit via the power supply line, the potential is supplied to the other circuit. In addition, for data on the data bus, the level of the H level signal may be lowered to the L level.
The object of the present invention has been made in view of the above-mentioned problems, and is a low power consumption type dynamic random access in which the consumption current as a DRAM is reduced by an external signal and no malfunction occurs at the low consumption current. To provide memory.
[0006]
[Means for Solving the Problems]
A low power consumption type dynamic random access memory according to the present invention is an input circuit having an internal power supply circuit that is driven by an external power supply and generates an internal power supply potential, and an output node that outputs a signal corresponding to the input signal , An input circuit having a transistor in which a parasitic diode is formed in a forward direction from the output node to a terminal to which a power supply potential is applied, a memory array that holds data, a peripheral circuit that controls the memory array, and a signal output In the dynamic random access memory, the output circuit includes a transistor in which a parasitic diode is formed in a forward direction from the output node toward a terminal to which a power supply potential is applied. The circuit and the output circuit are driven by an external power source, and the memory array And the peripheral circuit are driven by the internal power supply potential generated by the internal power supply circuit, the internal power supply circuit is inactivated in response to a control signal input from the outside, and the input circuit and the output circuit are The transistor is controlled to a high impedance state while the external power supply is supplied.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram of a DRAM for explaining an embodiment of the present invention. DRAM 200 is driven by an external power supply 210. Therefore, in the memory configuration of the mobile phone, the DRAM 60 of FIG. 3 is directly connected to the power supply 50 without passing through the switch 70. That is, in FIG. 3, the DRAM 60 is connected in the same manner as the SRAM 30 and the flash memory 40.
The external power supply 210 is connected to the first internal power supply circuit group 220 and also to the output circuit 230. The first internal power supply circuit group 220 converts the potential received from the external power supply 210 and supplies the internal power supply IVC to the input circuit 240, peripheral circuit 250, memory array 260, and second internal power supply circuit group 270 as the internal power supply IVC. Supply. For example, the external power supply 210 is 3.3V, and the internal power supply IVC is 2.4V.
The first internal power supply circuit group 220 receives the power supply control signal CONT via the control terminal 280. This power control signal CONT inactivates the first internal power supply circuit group 220. Therefore, the first internal power supply circuit group 220 does not supply the internal power supply IVC to the input circuit 240, the peripheral circuit 250, the memory array 260, and the second internal power supply circuit group 270. That is, no current is consumed in the first internal power supply circuit group 220 by the power supply control signal CONT.
[0008]
The current consumption of the first internal power supply circuit group 220 can be eliminated in two ways: when the potential of the internal power supply IVC is set to 0V, and when the potential is adjusted to the external power supply potential. Here, in the memory array 260, the bit line and the word line are short-circuited, and this defective portion may be replaced with redundancy. In such a state, if the internal power supply IVC is simply set to the external power supply potential, a current of several micro A flows through the shorted portion. Therefore, it is desirable to set the potential of the internal power supply IVC to 0 V (ground potential).
[0009]
The second internal power supply circuit group 270 receives the internal power supply IVC from the first internal power supply circuit group 220, converts the received internal power supply IVC, and sends other internal power supplies to the input circuit 240, the peripheral circuit 250, and the memory array. 260. Other internal power supplies include a substrate potential, a boosted potential, a ½ internal power supply potential, a reference potential, and the like. For example, when the internal power supply is 2.4 V, these potentials are the substrate potential −1.0 V, the boosted potential 3.6 V, the 1/2 internal power supply potential 1.2 V, and the reference potential 1.1 V, respectively.
The second internal power supply circuit group 270 receives the power supply control signal CONT via the control terminal 280. The power supply control signal CONT inactivates the second internal power supply circuit group 270. At this time, since the second internal power supply circuit group 270 has not received the internal power supply IVC from the first power supply circuit group 220, the second internal power supply circuit group 270 is almost inactivated but is completely inactivated by the power supply control signal CONT. Is done. Therefore, the second internal power supply circuit group 270 does not supply internal power to the input circuit 240, the peripheral circuit 250, and the memory array 260. That is, the current consumption in the second internal power supply circuit group 270 is completely eliminated by the power supply control signal CONT.
[0010]
Input circuit 240 is typically connected to a data bus for receiving signals. That is, when a DRAM is mounted on a mobile phone or the like, it is connected to the data bus 10 as shown in FIG. Therefore, if power is supplied, a signal is given to the peripheral circuit 250 in response to external data (for example, data on the data bus 10).
A general example of the input circuit 240 is an inverter 100 as shown in FIG. Here, the input node 150 of the inverter 100 is connected to the data bus, and the output node 140 is connected to the peripheral circuit 250 and the like. As a result of the inactivation of the first internal power supply circuit group 220, when the internal power supply IVC becomes 0V, the power supply potential is not applied to the source of the PMOS 120, so that no current is consumed. Although a signal is applied to the input node 150 from the data bus, no current is generated because no potential is applied to the sources of the NMOS transistor 110 and the PMOS transistor 120, and there is no influence on the internal circuit of the DRAM. .
When the internal power supply IVC becomes the same potential as the external power supply as a result of the inactivation of the first internal power supply circuit group 220, a signal is applied to the input node 150 from the data bus, and the DRAM operates. There is a possibility to start. Therefore, the input circuit 240 is preferably deactivated by the power supply control signal CONT input via the control terminal 280.
[0011]
Peripheral circuit 250 receives data from the input circuit and provides this data to memory array 260, and also receives data from memory array 260 and provides data to output circuit 230. The peripheral circuit 250 includes various circuits such as controlling the memory array 260 and the like. Since the peripheral circuit 250 does not directly exchange data with the outside of the DRAM, when the first and second internal power supply circuit groups 220 and 270 and the input circuit 240 are inactivated, no current consumption is generated and inactive. It will be in the state.
When the DRAM 200 is a synchronous DRAM or a Rambus DRAM, data such as CAS latency, burst length, and output mode necessary for its operation are programmable. These pieces of information are generally stored in a mode register that stores operation control information. This mode register is provided in or near the peripheral circuit. In such a DRAM, if power supply to peripheral circuits and the like is stopped, stored data is also lost. Therefore, it can be considered that only the mode register is driven by an external power source.
In addition, since the memory array 260 does not directly exchange data with the outside of the DRAM, no current consumption occurs when the first and second internal power supply circuit groups 220 and 270 and the peripheral circuit 250 are deactivated. It becomes inactivated.
[0012]
Output circuit 230 is typically connected to a data bus to output data from the memory array. That is, when the DRAM 200 is mounted on a mobile phone or the like, it is connected to the data bus 10 as shown in FIG. Therefore, in response to data from the DRAM 200 (data sent from the peripheral circuit 250), a signal is output to the data bus.
A general example of the output circuit 230 is an inverter 500 as shown in FIG. The inverter 500 includes an NMOS transistor 510, a PMOS transistor 520, a NAND circuit 560, a NOR circuit 570, a first inverter circuit 580, a second inverter circuit 590, and a third inverter circuit 600. The source of the NMOS transistor 510 is connected to the ground potential, and the drain is connected to the output terminal 540. The source S of the PMOS transistor 520 is connected to the power supply potential, and the drain is connected to the output terminal 540. The input terminal 550 of the inverter 500 is connected to the first input terminal of the NAND circuit 560 and is also connected to the first input terminal of the NOR circuit 570.
A power supply control signal CONT is input from the control input terminal 610 of the inverter 500 to the second input terminal of the NAND circuit 560. This power control signal CONT is inverted by the third inverter circuit 600 and also input to the second input terminal of the NOR circuit. The output of the NAND circuit 560 is connected to the gate of the NMOS transistor 510 via the first inverter circuit 580. The output of the NOR circuit 570 is connected to the gate of the PMOS transistor 520 through the second inverter circuit 590.
Since the output circuit 230 operates with an external power supply, it is necessary to receive a signal from a circuit operating with the internal power supply after conversion by a level shifter. Although not shown, in the case of the output circuit 230, a level shifter circuit is connected in front of the input terminal 550. Even when the power of the DRAM is turned off, the output of the output circuit 230 needs to be kept at a high impedance, so that a signal supplied to the control input terminal 610 (a signal input to the control terminal 280 in FIG. 1) is supplied. The circuit to be operated must always be driven by an external power source.
[0013]
Next, the operation of the output circuit 230 will be described with reference to FIGS.
The input terminal 550 of the inverter 500 is connected to the peripheral circuit 250, and the output terminal 540 is connected to the data bus 10 via the output terminal of the DRAM 200 or the like. Here, an external power source 210 is supplied to the output circuit 230. Since the external power supply 210 is always supplied to the DRAM 200 (when the DRAM 200 is mounted on the mobile phone, the external power supply is always supplied if the power supply of the mobile phone is on), the PMOS transistor 520 of the inverter 500 A source potential is applied to the source S, and a ground potential is applied to the source of the NMOS transistor 510.
When the L level power control signal CONT is input, the NAND circuit 560 sets the H level output signal regardless of the signal level of the first input terminal, and the NOR circuit 570 sets the signal level of the first input terminal. Regardless, L level output signal is output. These signals are inverted by the first and second inverter circuits 580 and 590, respectively, and an L level signal is applied to the gate of the NMOS transistor 510 and an H level signal is applied to the gate of the PMOS transistor 520. Therefore, the inverter 500 (output circuit 230) is set so that the output state becomes high impedance.
[0014]
Even if an H-level or L-level signal is transferred to the data bus 10 in such a state, no current flows through the parasitic transistor 530 in the NMOS transistor 510 and the PMOS transistor 520, and there is no influence on the circuit in the DRAM. Further, since the L level signal is applied to the gate of the NMOS transistor 510 and the H level signal is applied to the gate of the PMOS transistor 520, the NMOS transistor 510 and the PMOS transistor 520 are kept in the OFF state and no current consumption occurs. .
In the above-described embodiments, the input circuit has been described as receiving data at the gate of the transistor, but there is an input protection transistor or the like, and when the current due to the parasitic diode as described in the example of the output circuit is considered. As in the output circuit, the input circuit may be controlled so that an external power supply is supplied and the transistor is not turned on.
[0015]
【The invention's effect】
As described above, according to the present invention, the internal power supply circuit, the input circuit, the memory array, and the peripheral circuit are inactivated by an external control signal, while the external power is always supplied to the output circuit. Therefore, it is possible to provide a low power consumption type dynamic random access memory that reduces the current consumption as a DRAM and does not malfunction when the current consumption is low.
[Brief description of the drawings]
FIG. 1 is a block diagram of a DRAM showing an embodiment of the present invention.
FIG. 2 is a diagram showing a memory configuration in a mobile phone.
FIG. 3 is a diagram showing a memory configuration when DRAM is used in a mobile phone.
FIG. 4 is a circuit diagram showing a typical inverter in an input circuit and an output circuit.
FIG. 5 is a circuit diagram showing a typical inverter in the output circuit.
[Explanation of symbols]
200 DRAM
210 External power supply 220 First internal power supply circuit group 230 Output circuit 240 Input circuit 250 Peripheral circuit 260 Memory array 270 Second internal power supply circuit group

Claims (5)

外部電源によって駆動され、内部電源電位を発生する内部電
源回路と、
入力信号に応じた信号を出力する出力ノードを有する入力回路であって、前記出力ノードから電源電位が与えられる端子に向けて順方向に寄生ダイオードが形成されるトランジスタを有する入力回路と、
データを保持するメモリアレイと、
このメモリアレイを制御する周辺回路と、
信号が出力される出力ノードを有する出力回路であって、前記出力ノードから電源電位が与えられる端子に向けて順方向に寄生ダイオードが形成されるトランジスタを有する出力回路とを有するダイナミックランダムアクセスメモリにおいて、
前記入力回路及び出力回路は外部電源によって駆動され、
前記メモリアレイ及び周辺回路は、前記内部電源回路によって生成された内部電源電位によって駆動され、
外部から入力される制御信号に応答して、前記内部電源回路は不活性化され、かつ前記入力回路及び出力回路は外部電源が供給されたまま前記トランジスタがハイインピーダンス状態に制御される低消費電力型ダイナミックランダムアクセスメモリ。An internal power supply circuit driven by an external power supply and generating an internal power supply potential;
An input circuit having an output node that outputs a signal according to an input signal, the input circuit having a transistor in which a parasitic diode is formed in a forward direction from the output node toward a terminal to which a power supply potential is applied;
A memory array for holding data;
Peripheral circuits for controlling the memory array;
An output circuit having an output node from which a signal is output, and an output circuit having a transistor in which a parasitic diode is formed in a forward direction from the output node toward a terminal to which a power supply potential is applied ,
The input circuit and the output circuit are driven by an external power source,
The memory array and the peripheral circuit are driven by an internal power supply potential generated by the internal power supply circuit,
In response to a control signal input from the outside, the internal power supply circuit is inactivated, and the input circuit and the output circuit are controlled to be in a high impedance state while the external power supply is supplied. Type dynamic random access memory. 請求項１記載の低消費電力型ダイナミックランダムアクセスメモリをメモリコアとして用いたシステムLSI。  A system LSI using the low power consumption type dynamic random access memory according to claim 1 as a memory core. 前記入力回路も前記内部電源回路と同様に不活性化される請求項１記載のダイナミックランダムアクセスメモリまたは請求項２記載のシステムLSI。  3. The dynamic random access memory according to claim 1, or the system LSI according to claim 2, wherein the input circuit is also deactivated similarly to the internal power supply circuit. 前記低消費電力型ダイナミックランダムアクセスメモリの動作制御情報を記憶するモードレジスタを更に有し、このモードレジスタは外部電源により駆動される請求項１記載のダイナミックランダムアクセスメモリ、または請求項２記載のシステムLSI。  3. The dynamic random access memory according to claim 1, further comprising a mode register for storing operation control information of the low power consumption type dynamic random access memory, and the mode register is driven by an external power source. LSI. 前記動作制御情報は、シンクロナス動作の出力タイミングを決めるレイテンシー、バーストレングス及び出力モードの少なくとも一つを含む請求項４記載のダイナミックランダムアクセスメモリ、またはシステムLSI。  5. The dynamic random access memory or system LSI according to claim 4, wherein the operation control information includes at least one of a latency, a burst length, and an output mode that determine an output timing of a synchronous operation.
JP2000219279A 2000-07-19 2000-07-19 Low power consumption dynamic random access memory Expired - Fee Related JP3902909B2 (en)

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JP2000219279A JP3902909B2 (en) 2000-07-19 2000-07-19 Low power consumption dynamic random access memory
US09/907,449 US6438061B1 (en) 2000-07-19 2001-07-18 Dynamic random access memory with low power consumption
KR1020010043351A KR100816403B1 (en) 2000-07-19 2001-07-19 Dynamic random access memory with low power consumption
TW090117634A TW514919B (en) 2000-07-19 2001-07-19 Low power consumption DRAM
US10/175,859 US6574150B2 (en) 2000-07-19 2002-06-21 Dynamic random access memory with low power consumption

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JP2004060106A Division JP3981092B2 (en) 2004-03-04 2004-03-04 Low power consumption type semiconductor integrated circuit device

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