JP3890919B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
This invention relates to a method for manufacturing a semiconductor equipment, to form a coating film on the surface a step is formed to an improvement of the technique for etching the wiring or the like.
[0002]
[Prior art]
The technique of etching the coating film is mainly used as a planarization technique for reducing a wiring step when a multilayer wiring is formed in the manufacture of a semiconductor integrated circuit. For example, a first layer wiring is formed on a semiconductor substrate on which elements are formed, an interlayer insulating film is deposited thereon, and then SOG (Spin On Glass) or the like is used to eliminate the unevenness transferred to the interlayer insulating film. The glass film is applied, and the entire surface is etched (etched back) by a dry etching method. In this way, the second layer wiring is formed on the flattened substrate (for example, Japanese Patent Publication No. 5-87146).
[0003]
In the planarization technique for etching such a coating film, it is necessary to optimally control the etching amount of the coating film. As a method for that,
(1) A method of measuring the etching rate of the coating film in advance and determining the suitability of the etching amount according to the etching time,
(2) When etching the coating film in plasma, a method for determining the remaining film thickness of the coating film from the change in the intensity of the emission spectrum;
(3) There is a method of measuring the remaining film thickness of the coating film on the flat part by measuring the optical film thickness using an ellipsometer or the like.
[0004]
[Problems to be solved by the invention]
Since the methods (1) and (2) both use an indirect film thickness measurement method, it is difficult to control the etching amount with high accuracy. The method of (3) is effective as long as the etching amount is within the range of the coating film thickness in the flat part, but the residual film thickness cannot be measured when cutting more than the coating film thickness in the flat part. Not applicable.
[0005]
After etching back is complete, a method of evaluating the suitability of the etching amount by cross-sectional inspection using an electron microscope or the like is also conceivable, but this is a post-completion inspection, resulting in a destructive inspection that delays feedback to actual processing This is not preferable, and it is difficult to increase the number of observation points, and it is difficult to evaluate variation.
[0006]
The present invention has been made in consideration of the above situation, the purpose is to provide a method for manufacturing a semiconductor equipment using a technique which enables the propriety determination of easy etching amount by an optical non-destructive testing Yes.
[0007]
[Means for Solving the Problems]
The present invention provides a method for manufacturing a semiconductor device including a step of forming a coating film on a stepped surface on a semiconductor substrate on which a desired element is formed, and etching the coating film. An inspection pattern having a planar shape including a pair of protrusions separated from each other and the width of the space formed by the pair of protrusions intermittently changing prior to the formation of the coating film. Forming and detecting a boundary position between the coating film and the substrate in a space portion in the inspection pattern in the etching process of the coating film, and based on correlation data between the boundary position measured in advance and the etching amount It is characterized by determining the suitability of the etching amount.
[0008]
The present invention also provides a method for manufacturing a semiconductor device, comprising: forming a coating film after depositing an insulating film on a stepped surface on a semiconductor substrate on which a desired element is formed; and etching the coating film. Prior to the deposition of the insulating film, the width of the space portion formed by the pair of protrusions is intermittently changed on the stepped surface of the semiconductor substrate, including a pair of protrusions separated from each other. A test pattern having a planar shape is formed, and a boundary position between the coating film and the insulating film is detected in a space portion in the test pattern in the etching process of the coating film, and the boundary position and etching measured in advance are detected. It is characterized in that the suitability of the etching amount is determined based on the amount correlation data.
[0009]
In the present invention, in order to determine whether or not the etching amount of the coating film is appropriate, the ratio of the line width to the space width (hereinafter simply referred to as the line / space ratio) is different at a plurality of locations within the surface. A convex inspection pattern having a curved line portion and a space portion is used. When such a test pattern is formed on a flat surface in advance and a coating film is formed, and this coating film is etched back, the etching amount of the coating film differs at different line / space ratios, and the etching amount depends on the etching amount. As a result, the boundary position between the coating film and the base changes. The boundary position between the coating film and the base can be easily detected by an optical microscope or the like.
[0010]
Therefore, if the correlation data of the boundary position between the coating film and the base in the inspection pattern and the etching amount is obtained in advance by, for example, a plurality of repeated measurements, the above-described boundary position is optically detected in the actual planarization process. Accordingly, it is possible to determine the suitability of the etching amount based on the correlation data.
According to the present invention, fracture observation is not required, multipoint measurement is easy, and accurate etching amount control without variation is possible.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an inspection pattern used in one embodiment of the present invention. This inspection pattern is formed simultaneously with the first layer wiring on the surface of the substrate on which the step is formed by the first layer wiring, for example, (a) is a plan view, and (b), (c) ), (D), and (e) are cross-sectional views at positions AA ', BB', CC ', and DD' in (a), respectively.
[0012]
As shown in the figure, the inspection pattern of this embodiment is composed of a pair of convex portions 11 and 12 having a predetermined thickness. The convex portions 11 and 12 are formed within the range of the width l of the flat surface of the predetermined substrate 10, and in the range of the width l, there are line portions having a width of L1 on both sides at the position AA ′, and S1 is inside thereof. There is a space part of width. At the BB ′ position, the width of the line portion is as large as L2, and the width of the space portion is as small as S2. At the CC ′ position, the width of the line portion is L3 and the width of the space portion is S3, and at the DD ′ position, the width of the line portion is L4 and the width of the space portion is S4. That is, this inspection pattern is formed so as to have a plurality of locations with different line / space ratios.
[0013]
In this invention, such an inspection pattern is formed in advance on a flat surface to form a coating film, and when this coating film is etched back, the etching amount of the coating film is different at different line / space ratios. In addition, the fact that the boundary position of the coating film with the base changes according to the etching amount is utilized. In order to obtain the correlation between the etching amount and the boundary position, the following preliminary measurement is performed.
[0014]
FIG. 2 shows a state in which the coating film 13 such as SOG is formed on the substrate having the inspection pattern shown in FIG. 1 and a state of the remaining film 14 after a predetermined time when this is etched back. -B ', CC' and DD 'are shown in cross-sectional views at respective positions. As shown in the drawing, the state of etching in the space portion inside the inspection pattern varies depending on the width of the space portion. When the state of the remaining film 14 is seen in a plan view, it becomes as shown in FIG. 3, and the boundary position e between the remaining film 14 and the base at the center of the space portion moves with the progress of etching. FIG. 4 shows how the boundary position changes as e1, e2, e3... As the etching progresses. It can be observed with an optical microscope or the like which position of the boundary position e is AA ′, BB ′, CC ′, DD ′ on the inspection pattern.
[0015]
From the above measurement, the relationship between the etch back amount (that is, the coating film cutting amount) and the boundary position e, specifically, the etch back amount and the maximum width (critical interval) of the space where the remaining film 14 exists at that time. Relationship is required. By repeating the above steps, correlation data between the etch back amount and the critical interval as shown in FIG. 5 is obtained. If this data is prepared in advance, the critical interval is within the range A from FIG. 5 by forming a similar inspection pattern and detecting the critical interval in the actual planarization process of the semiconductor element. In other words, it can be determined that the etchback amount is in the range of B.
[0016]
Explaining a specific embodiment in which the present invention is applied as a planarization technique for reducing a wiring step, as shown in FIG. 6, a surface covered with an insulating film 22 of a silicon substrate 21 on which a desired element is formed. First layer Al wiring 23 is formed. Simultaneously with this Al wiring process, the inspection pattern 24 described in FIG. 1 is formed on the flat surface of the substrate. Then, for example, an SOG film 25 is applied as a planarizing film for eliminating a step due to the first layer Al wiring 23. When the SOG film 25 is etched back and planarized, it is possible to determine whether or not the etch back amount is appropriate by using optical observation and the data shown in FIG.
After flattening by performing such an etch back amount control, an interlayer insulating film is further deposited if necessary to form a second layer Al wiring.
[0017]
As described above, according to this embodiment, the correlation data between the boundary position between the coating film and the base in the inspection pattern and the etching amount is obtained in advance by a plurality of repeated measurements. In addition, by performing the above-described boundary position detection, it is possible to determine the suitability of the etching amount based on the above correlation data. According to this embodiment, it is easy to perform multipoint measurement without observing destruction, and flattening by precise etching amount control without variation is possible.
[0018]
FIG. 7 shows a case where the planarizing SOG film 25 is formed after the first layer wiring 23 is formed and the insulating film 26 such as a SiO ₂ film is deposited. When the insulating film 26 is a CVD film or the like with good step coverage, the inspection pattern 24 is transferred to the insulating film 26. Therefore, the detection determination of the etchback amount can be performed in the same manner based on the inspection pattern transferred to the insulating film 26 instead of directly on the inspection pattern 24. However, in this case, the same film structure as that in FIG. 7 is used when obtaining the correlation data shown in FIG.
[0019]
The inspection pattern used for this invention is not restricted to the said Example, The inspection pattern represented by various plane patterns as shown in FIGS. 8-13 can be used. In FIG. 8, a plurality of line portions (convex portions) 81, 82, 83, and 84 having a constant width are arranged with different space widths, and the line / space ratio gradually decreases in the direction of arrow a in the figure. When the coating film is formed and etched back as in the previous embodiment, the boundary position between the remaining film of the coating film and the base varies as e1, e2, and e3 depending on each space portion. Therefore, correlation data between the remaining position of the coating film and the boundary position between the base and the etch back amount can be obtained from this.
[0020]
The inspection pattern of FIG. 9 is composed of a pair of convex portions 91 and 92, and the width is continuously changed so that the inner space portion is V-shaped, and the line / space ratio gradually increases in the direction of arrow b in the figure. The increase is the same as in the embodiment of FIG. The inspection pattern shown in FIG. 10 is also composed of a pair of convex portions 101 and 102, but the width of the space portion is constant and the width of the line portion is varied depending on the position. This also increases the line / space ratio in the direction of arrow b as in FIG. As a property of the coating film, even if the space is constant, the coating film is formed thicker as the width of the line portion sandwiching the space is wider. That is, the film thickness of the coating film is different at a position where the line / space ratio is different. Accordingly, the etch back amount can be detected from the boundary position e when the coating film is etched back.
[0021]
The inspection pattern shown in FIG. 11 includes a pair of convex portions 111 and 112, but the line portion width and the space portion width are changed more complicatedly.
It is not always necessary that the two convex portions of the inspection pattern exemplified above are separated. For example, the inspection pattern of FIG. 12 is obtained by integrating the inspection pattern of the embodiment of FIG. 1 into one convex portion. FIG. 13 shows an example in which the inspection pattern of the embodiment of FIG. Since these also have a plurality of locations having different line / space ratios, correlation data between the boundary position e of the coating film and the etch back amount can be obtained.
[0022]
【The invention's effect】
As described above, according to the present invention, in order to determine the suitability of the etching amount of the coating film, the line portion has a predetermined thickness and the ratio of the line width to the space width is different at a plurality of locations in the plane. And a convex inspection pattern with a space part. When such a test pattern is formed on a flat surface in advance and a coating film is formed, and this coating film is etched back, the etching amount of the coating film differs at different line / space ratios, and the etching amount depends on the etching amount. Since the boundary position between the coating film and the substrate changes, the correlation data between the coating film and substrate boundary position in the inspection pattern and the etching amount are obtained in advance by repeated measurement. In addition, by performing the above-described boundary position detection, it is possible to determine the suitability of the etching amount based on the correlation data, and it is possible to accurately control the etching amount without variation.
[Brief description of the drawings]
FIG. 1 shows an inspection pattern in one embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the relationship between the inspection pattern and the remaining film thickness of a coating film.
FIG. 3 is a plan view showing the relationship between the inspection pattern and the remaining film.
FIG. 4 is a plan view showing a change in a boundary position between a remaining film and a base due to etching of a coating film.
FIG. 5 is data showing a correlation between an etch back amount and a critical interval in which a coating film remains.
FIG. 6 shows a planarization step of the same embodiment.
FIG. 7 shows a planarization process of another embodiment.
FIG. 8 shows an inspection pattern of another embodiment.
FIG. 9 shows an inspection pattern of another embodiment.
FIG. 10 shows an inspection pattern of another embodiment.
FIG. 11 shows an inspection pattern of another embodiment.
FIG. 12 shows an inspection pattern of another embodiment.
FIG. 13 shows an inspection pattern of another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 11, 12 ... Convex part, 13 ... Coating film, 14 ... Residual film, 21 ... Silicon substrate, 22 ... Insulating film, 23 ... 1st layer Al wiring, 24 ... Inspection pattern, 26 ... Insulating film, e ... boundary position.

Claims (2)

In a manufacturing method of a semiconductor device including a step of forming a coating film on a stepped surface on a semiconductor substrate on which a desired element is formed, and etching the coating film,
Prior to the formation of the coating film, the semiconductor substrate includes a pair of protrusions separated from each other and the width of the space formed by the pair of protrusions is intermittently changed prior to the formation of the coating film. Forming an inspection pattern having a planar shape,
In the etching process of the coating film, the boundary position between the coating film and the substrate in the space portion in the inspection pattern is detected, and the etching amount is determined based on the correlation data between the boundary position and the etching amount measured in advance. A method of manufacturing a semiconductor device, comprising performing a suitability determination. In a method for manufacturing a semiconductor device, the method includes forming a coating film after depositing an insulating film on a stepped surface on a semiconductor substrate on which a desired element is formed, and etching the coating film.
Prior to the deposition of the insulating film on the stepped surface of the semiconductor substrate, the width of the space portion formed by the pair of protrusions and the pair of protrusions separated from each other is intermittently changed. Forming an inspection pattern having a planar shape,
In the etching process of the coating film, the boundary position between the coating film and the insulating film in the space portion in the inspection pattern is detected, and the etching amount based on the correlation data between the boundary position and the etching amount measured in advance A method for manufacturing a semiconductor device, comprising: determining whether the semiconductor device is suitable.

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