JP3880942B2 - Processor, computer and priority determination method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data flow type processor, and more particularly to a processor provided with buffer memories in an input stage and an output stage, and a method for selecting an execution thread in the processor.
[0002]
[Prior art]
When a processor such as a computer processes data, multi-thread processing that executes a plurality of tasks in a time-sharing manner is generally employed in order to efficiently perform more data processing (for example, see Patent Document 1). reference).
[0003]
Several methods for realizing multithreading for data processing have been proposed. Among them, there is data flow type multi-thread processing that determines the execution order of threads according to the data flow. Such a processor has a mechanism for executing processes required in the process of data to be processed in accordance with the processing order. In this way, a thread that does not correspond to a process is not executed, and it is possible to efficiently assign processor capacity to a process required at that time.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-029984
[Problems to be solved by the invention]
However, the conventional data flow type that selects the next execution thread depending on the output result after processing of each processing unit has a problem in the following cases.
[0006]
For example, a processing target that requires real-time processing often requires processing that does not conform to the processing flow (data flow). Processing that deviates from the data flow requires overhead such as separate interrupt processing and work state save processing. In addition, such interrupt processing causes a disturbance in the data flow and reduces processing efficiency.
[0007]
The present invention has been made in view of such a problem, and provides a data flow type processor capable of minimizing the loss of real-time property, a computer using this processor, and a priority determination method. Objective.
[0008]
[Means for Solving the Problems]
According to the present invention,
A plurality of storage means for storing process data to be processed by one or more execution units, which corresponds to one of the processes obtained by time-sharing a certain data process into at least one or more;
Data to be processed by the execution unit is received from at least one of the plurality of storage means assigned to a certain execution unit, and the execution result of the execution unit is stored in one of the plurality of storage means assigned to the execution unit. Data processing means,
Information about the amount of processing data stored in each storage unit is received from each of the storage units, and the execution status of an execution unit that accesses the storage unit is obtained from the amount of processing data stored in a storage unit. Priority determining means for determining a priority indicating the order of execution of the execution unit;
There is provided a processor characterized by comprising:
[0009]
And a computer comprising the processor.
[0010]
Also,
With respect to an execution unit corresponding to one of the processes obtained by time-sharing a certain data process into at least one or more, data to be processed by the execution unit is received from at least one of a plurality of storage devices allocated to the execution unit.
Storing the execution result of the execution unit in one of the plurality of storage devices allocated to the execution unit;
Information on the amount of processing data stored in each storage device is received from each of the storage devices, and the execution status of an execution unit that accesses the storage device is determined from the amount of processing data stored in a storage device, A priority determination method is provided, wherein a priority indicating the order of execution of the execution unit is determined.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0012]
(First embodiment)
FIG. 1 is an example of a block diagram of a processor according to the first embodiment. FIG. 1 shows a plurality of FIFOs (First-In First-Out) 101, a selection unit 102, an execution control unit 103, a cache 104, a switching unit 105, a plurality of register sets 106, a memory bus 107, A storage unit 108 and an arithmetic processing unit 109 are shown.
[0013]
The FIFO 101 is composed of a memory, and is a storage device that can be read first from what has been previously stored. Each FIFO 101 includes a plurality of 1 to n (n is arbitrary). The storage capacities of the FIFOs 101 are not necessarily the same, but the same configuration is preferable in order to process a plurality of threads equally.
[0014]
As used herein, a thread refers to a processing unit or execution of a processing unit after a process to be executed by a processor is divided and assigned to a plurality of time intervals. The thread is realized by controlling each unit performed by the execution control unit 103 and executing a predetermined program code given in advance by the arithmetic processing unit 109 under this control. Since the processor of the present embodiment is a data flow type, one process is completed by sequentially processing a plurality of divided threads for one process data. The threads are processed in parallel, and data flow type processing of a plurality of processing data can be performed asynchronously. Threading one process in this way is mainly performed to realize multi-thread processing using a real-time OS.
[0015]
The selection unit 102 has a function of selecting a FIFO designated by the execution control unit 103 from among a plurality of FIFOs 101 provided. The FIFO 101 selected here is read and written by the arithmetic processing unit 109.
[0016]
The execution control unit 103 has a function of controlling overall processing performed by the processor of the present embodiment. This also includes a table that holds a priority indicating which thread is preferentially executed. The execution control unit 103 has a function of setting this table based on information such as the FIFO 101 and instructing each unit to execute which thread of which processing data is processed according to the contents of the table.
[0017]
The cache 104 is provided in order to prevent the arithmetic processing unit 109 from sequentially accessing a storage device having a low read / write speed when the program code corresponding to the thread is executed. In general, the access speed of a mass storage device such as a main memory or a magnetic disk device is slower than the processing speed of the arithmetic processing unit 109. Although the cache 104 does not have the storage capacity of the large capacity storage device, a storage device with a high access speed is used. Data and program codes that are frequently accessed are temporarily stored in the cache 104 so that the arithmetic processing unit 109 does not wait for reading and writing, and is used to increase the processing amount of the arithmetic processing unit 109 as much as possible.
[0018]
The switching unit 105 selects one or more register sets necessary for processing from among a plurality of register sets 106 so as to be accessible. The arithmetic processing unit 109 accesses a register set in which data necessary for processing is stored via the switching unit 105.
[0019]
The register set 106 is a collection of various registers (temporary storage devices) necessary for the execution control unit 103 to execute the program code. The register set 106 includes, for example, a calculation register, an addressing register, and a stack pointer. In the present embodiment, a plurality of register sets 106 having 1 to m (m is arbitrary) are provided. Each register set 106 does not necessarily have the same configuration, but is preferably the same configuration so that each thread can process whatever register set is used.
[0020]
The memory bus 107 is provided so that data can be exchanged between the cache 104, the plurality of register sets 107, and the storage unit 108. The data stored in each can be moved through the memory bus 107. The execution control unit 103 performs data movement.
[0021]
The storage unit 108 stores program code executed for processing by the processor of the present embodiment and processing data to be processed. In some cases, it is used as a temporary save location for data stored in the cache 104 and the register set 107. .
[0022]
The arithmetic processing unit 109 has a function of executing the program code stored in the storage unit 108 or the cache 104. When executing the program code, which FIFO 101 and which register set 106 are used and which thread is to be processed are determined by an instruction from the execution control unit 103.
[0023]
FIG. 2 shows an overview of the thread processing of the processor in this embodiment.
Since the processor of the present embodiment is a data flow type, the processing data is provided in the form of input, and an output is basically obtained through one path (flow). The input processing data undergoes processing (each thread 201) that is sequentially executed by the arithmetic processing unit 109 according to the program code stored in the storage unit 108 in advance, and is output as an output result. When there is a next stage process, the output result that is output is the next stage input data.
[0024]
When processing data that is input data is input, the FIFO 101-A, which is one of a plurality of FIFOs 101 instructed by the execution control unit 103, stores this. The FIFO 101-A notifies the execution control unit 103 of the FIFO accumulation amount in the FIFO 101-A as a status report 202-A in response to a request from the execution control unit 103 or the like.
[0025]
When the arithmetic processing unit 109 executes the thread 201-1 according to an instruction from the execution control unit 103, processing using the data in the FIFO 101-A as input data is started. At this time, data in the FIFO 101-A is read in order from the previously stored data. The processing result performed by this thread is stored in the FIFO 101-B according to an instruction from the execution control unit 103. Similarly to the FIFO 101-A, the FIFO 101-B also notifies the execution control unit 103 of the status report 202-B including the FIFO accumulation amount.
[0026]
When the above processing ends from the thread 201-2 to the thread 201-x (x is arbitrary), the processing result is output as an output.
[0027]
The execution control unit 103 instructs the execution processing unit 103 which thread is to be executed by the arithmetic processing unit 109. The execution control unit 103 sets priorities in the execution priority table provided by itself based on the information of the status reports 202-A to 202-n notified from the FIFO 101-A to the FIFO 101-n. The execution instruction 203 is determined from the above. When the execution instruction 203 is determined, the priority determined by using only a part of the plurality of status reports 202 may be used, or the highest priority thread 201 may be determined from the priority determined in consideration of all the status reports 202. May be determined. Preferably, the execution order of each thread 201 is determined from all the status reports 202 to improve the efficiency of the entire process.
[0028]
Hereinafter, a method for the execution control unit 103 to determine the execution order of the threads will be described.
[0029]
FIG. 3 shows an example of a method in which the execution control unit 103 of the processor according to the present embodiment determines the thread execution priority with respect to the input-side FIFO accumulation amount for a certain thread. Since the FIFO accumulation amount corresponding to the vertical axis shown in FIG. 3 is the input-side FIFO, for example, the FIFO 101-A for the thread 201-1 and the FIFO 101-B for the thread 201-2 shown in FIG.
[0030]
A large amount of processing-waiting data stored in the input-side FIFO of a thread means that the processing of that thread is delayed. Therefore, it is necessary to increase the priority of the thread and process the data waiting for processing promptly. For this reason, as shown in FIG. 3, the setting is made such that execution becomes easier (priority becomes higher) as the FIFO accumulation amount increases. As indicated by the intersection 302, a higher priority is set in the table indicating the priority of each thread held by the execution control unit 103 as the FIFO accumulation amount increases.
[0031]
In the example shown in FIG. 3, the relationship between the FIFO accumulation amount and the thread execution priority is indicated by a proportional straight line 301, but it is not necessarily a straight line. For example, the proportional curve 303 may be such that the priority increases as the FIFO storage amount approaches the upper limit. In this case, it is possible to effectively prevent the FIFO from overflowing. Further, the priority may be increased stepwise or stepwise so that the implementation is simple in the design of the processor regardless of the curve or straight line. As an example, an operation may be performed in which a threshold value is set in the FIFO accumulation amount, and the thread is not executed until the threshold value is exceeded, or the execution is continued until the threshold value is cut.
[0032]
FIG. 4 shows an example of a thread priority determination method for the output-side FIFO accumulation amount for a certain thread of the processor according to this embodiment. Since the FIFO accumulation amount corresponding to the vertical axis shown in FIG. 4 is the output side FIFO, for example, the FIFO 101-B for the thread 201-1 and the FIFO 101-C for the thread 201-2 shown in FIG.
[0033]
The fact that a large amount of processing waiting data is accumulated in the output FIFO of a certain thread means that the processing of the subsequent thread is delayed. If the thread is executed as it is, the FIFO on the output side may overflow. Therefore, it is necessary to lower the priority of the thread and suppress the processing so that the FIFO on the output side does not overflow. For this reason, as shown in FIG. 4, the setting is made such that execution becomes difficult (priority becomes low) as the FIFO accumulation amount on the output side increases. As indicated by the intersection 402, a lower priority is set in the table indicating the priority of each thread held by the execution control unit 103 as the FIFO accumulation amount increases.
[0034]
In the example shown in FIG. 4, the relationship between the FIFO accumulation amount and the thread execution priority is indicated by a proportional line 401, but it is not necessarily a straight line. For example, the proportional curve 403 may be used in which the priority decreases as the FIFO accumulation amount on the output side approaches the upper limit. In this case, it is possible to effectively prevent the output side FIFO from overflowing. Further, the priority may be lowered stepwise or stepwise so that the implementation is simple in the design of the processor regardless of a curve or a straight line. As an example, an operation may be performed in which a threshold value is set in the FIFO accumulation amount, and the thread is not executed until the threshold value is cut, or the execution is continued until the threshold value is exceeded.
[0035]
As described above, the execution control unit 103 determines the priority of the thread according to the priority obtained by combining both the priority obtained from the input-side FIFO and the priority obtained from the output-side FIFO, or the priority based on the input-side FIFO. To decide.
[0036]
At this time, there may be a case where the priority obtained from the input-side FIFO accumulation amount and the priority obtained from the output-side FIFO accumulation amount indicate a conflicting priority. For example, it is conceivable that both the input side and the output side are close to the upper limit of the accumulation amount. In this case, based on the amount of FIFO storage on the input side, provided that there is enough space in the output FIFO storage space to store the output results after processing the processing data stored in the input FIFO. Prioritize priority. Except for this case, priority is given to the priority based on the output-side FIFO accumulation amount or the execution of this thread is temporarily prohibited in order to prevent the output-side FIFO from overflowing.
[0037]
FIG. 5 shows an example of a flow for determining a thread to be executed next in the processor according to this embodiment.
[0038]
First, the accumulated amount of all FIFOs is acquired (S1). As for the acquisition method, each FIFO may be inquired or may be voluntarily reported from each FIFO. The acquisition method is not limited.
[0039]
Next, it is checked whether or not there is a FIFO that is likely to exceed the upper limit accumulation amount for each FIFO (S2). If there is a FIFO that is likely to be exceeded as a result of the inspection, an emergency process is performed for the thread related to the FIFO (S3).
[0040]
Examples of emergency processing include the following processing. One is to process a thread having the corresponding FIFO on the input side with the highest priority by an interrupt. Interrupt means means for forcibly changing the order of normal processing. By processing with priority over other threads, the amount of FIFO storage can be reduced. The other is to temporarily prohibit execution of threads that have the corresponding FIFO on the output side. By prohibiting the execution of the thread, the data added to the FIFO is stopped, so that the accumulated amount can be afforded.
[0041]
The contents of the emergency processing should be determined flexibly according to the processing status and the characteristics of the processing data, and are not limited to the above examples.
[0042]
If there is no FIFO that is likely to overflow, it is next determined whether the priority of all threads has been obtained (S4).
[0043]
If none of the threads for which priority has been obtained is selected, one of the threads being processed or waiting is selected (S5). Then, the priority of the thread is determined by the method described above from the accumulated amounts of the input side and output side FIFOs used by the selected thread (S6). After the determination, it is determined whether the priority of all threads has been obtained again (S4).
[0044]
If it is determined that the priority has been obtained for all the threads, the thread having the highest priority is selected from the threads for which the priorities have been obtained (S7).
[0045]
As described above, the thread to be executed next can be selected from the threads being processed or waiting.
[0046]
With the configuration as described above, it is possible to select a thread to be executed according to the FIFO accumulation amount on the input side and the output side, while being allocated to the processing that efficiently requires the processing capability of the data flow type processor. .
[0047]
It is also possible to use a computer that carries the data flow type processing and includes the processor according to the present embodiment.
[0048]
(Second Embodiment)
A diagram showing an example of a block diagram of a processor in the second embodiment and a diagram showing an overview of thread processing are the same as those in FIGS. 1 and 2 in the first embodiment.
[0049]
FIG. 6 shows an example of a thread priority determination method for the input-side FIFO accumulation amount for a certain thread in the processor according to the present embodiment. Since the FIFO accumulation amount corresponding to the vertical axis shown in FIG. 6 is the input-side FIFO, for example, the FIFO 101-A for the thread 201-1 and the FIFO 101-B for the thread 201-2 shown in FIG.
[0050]
A large amount of processing-waiting data stored in the input-side FIFO of a thread means that the processing of that thread is delayed. Therefore, it is necessary to increase the priority of the thread and process the data waiting for processing promptly. For this reason, as shown in FIG. 6, the setting is made such that execution becomes easier (priority becomes higher) as the FIFO accumulation amount increases.
[0051]
The difference from the first embodiment is that different thread execution priorities are set when the FIFO accumulation amount increases and decreases. Even when looking at the same FIFO accumulation amount, for example, the priority corresponding to the intersection 601 when the FIFO accumulation amount increases is lower than the priority corresponding to the intersection 602 when the FIFO accumulation amount decreases.
[0052]
When the relationship between the accumulated amount of the input-side FIFO and the thread processing is seen, the accumulated amount of the input-side FIFO decreases if the thread is executed, and conversely increases if the thread is not executed. Considering the time when the FIFO accumulation amount at the intersection 602 is reduced at this time, even if the accumulation amount of the input-side FIFO is reduced, the method of decreasing the priority of the thread is gentle. Conversely, when considering the increase in the FIFO accumulation amount at the intersection 601, even if the input FIFO accumulation amount is increased, the thread priority is moderately increased. That is, even if the accumulation amount of the input-side FIFO changes, the thread that has once started processing is likely to be continuously executed because the priority is maintained at a high level. Conversely, a thread whose priority is low and difficult to execute means that it is difficult to execute unless the accumulation amount of the input-side FIFO becomes higher.
[0053]
The cache 104 shown in FIG. 1 is provided so that processing data required for thread processing can be accessed at high speed with a small storage capacity as described above. Since the storage capacity is small, there is a high possibility that the processing data of one thread once read is overwritten and disappears when another thread is executed. The lost processing data must be read into the cache 104 again from a storage device with a slow access speed. If the thread to be executed is frequently changed due to the fluctuation of the input FIFO amount, the amount and number of data that must be read from the other storage device to the cache 104 inevitably increase.
[0054]
Similarly, in the case of the register set 106 illustrated in FIG. 1, if the number of executing and waiting threads exceeds the number of register sets 106, it is necessary to temporarily save to another storage device. This is because in order to execute a thread that was not assigned to the register set 106 at a certain point in time, the register set 106 occupied by another thread needs to be released for this thread. Since the contents of the register set 106 must be moved between storage devices, frequent thread switching causes overhead, as does the cache 104.
[0055]
The processor according to the present embodiment realizes a state in which a thread is likely to be executed frequently, and reduces the overhead of reading data into the cache 104. Therefore, the processing capability of the processor can be allocated to the original data processing.
[0056]
In the example shown in FIG. 6, the relationship between the FIFO accumulation amount and the thread priority is indicated by an ellipse, but it is not always necessary to be an ellipse. For example, the priority may be increased stepwise or stepwise so that the implementation is simple in the design of the processor.
[0057]
FIG. 7 shows an example of a thread priority determination method for the output-side FIFO accumulation amount for a certain thread of the processor according to this embodiment. Since the FIFO accumulation amount corresponding to the vertical axis shown in FIG. 7 is the output-side FIFO, for example, the FIFO 101-B for the thread 201-1 and the FIFO 101-C for the thread 201-2 shown in FIG.
[0058]
The fact that a large amount of processing waiting data is accumulated in the output FIFO of a certain thread means that the processing of the subsequent thread is delayed. If the thread is executed as it is, the FIFO on the output side may overflow. Therefore, it is necessary to lower the priority of the thread and suppress the processing so that the FIFO on the output side does not overflow. For this reason, as shown in FIG. 7, the setting is made such that execution becomes difficult (priority becomes lower) as the FIFO accumulation amount on the output side increases.
[0059]
The difference from the first embodiment is that different thread execution priorities are set when the FIFO accumulation amount increases and decreases. Looking at the same FIFO accumulation amount, for example, the priority corresponding to the intersection 702 when the FIFO accumulation amount increases is higher than the priority corresponding to the intersection 701 when the FIFO accumulation amount decreases.
[0060]
When looking at the relationship between the accumulated amount of the output side FIFO and thread processing, the accumulated amount of the output side FIFO tends to increase if the thread is executed, and conversely decreases if not executed. At this time, considering the increase in the FIFO accumulation amount at the intersection point 702, even if the accumulation amount of the output-side FIFO is increased, the method of decreasing the priority of the thread is gentle. Conversely, when considering a decrease in the FIFO accumulation amount at the intersection point 701, even if the accumulation amount of the output-side FIFO decreases, the priority of the thread increases slowly. That is, even if the accumulation amount of the output-side FIFO changes, the thread that has once started processing is likely to be continuously executed because the priority remains high. Conversely, a thread whose priority is low and difficult to execute means that it is difficult to execute unless the accumulation amount of the output-side FIFO becomes lower.
[0061]
For this effect, refer to the description of FIG. 6 described above.
[0062]
In the example shown in FIG. 7, the relationship between the FIFO accumulation amount and the thread execution priority is indicated by an ellipse, but it is not necessarily required to be an ellipse. For example, the priority may be increased stepwise or stepwise so that the implementation is simple in the design of the processor.
[0063]
As described above, the execution control unit 103 determines the priority of the thread according to the priority obtained by combining both the priority obtained from the input-side FIFO and the priority obtained from the output-side FIFO, or the priority based on the input-side FIFO. To decide.
[0064]
At this time, there may be a case where the priority obtained from the input-side FIFO accumulation amount and the priority obtained from the output-side FIFO accumulation amount indicate a conflicting priority. For example, when processing data is not accumulated in both the input side FIFO and the output side FIFO. In this case, it is not necessary to preferentially execute the thread, so priority is given to the priority based on the input-side FIFO accumulation amount.
[0065]
On the other hand, there may be a case where both the input side and the output side are close to the upper limit of the accumulation amount. In this case, based on the amount of FIFO storage on the input side, provided that there is enough space in the output FIFO storage space to store the output results after processing the processing data stored in the input FIFO. Prioritize priority. Except for this case, priority is given to the priority based on the output-side FIFO accumulation amount or the execution of this thread is temporarily prohibited in order to prevent the output-side FIFO from overflowing.
[0066]
A diagram illustrating an example of a flow for determining a thread to be executed next in the processor according to the present embodiment is the same as FIG. 5 according to the first embodiment.
[0067]
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.
[0068]
【The invention's effect】
According to the present invention, it is possible to provide a data flow type processor capable of minimizing the loss of real-time property, a computer using the processor, and a priority determination method.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a block configuration of a processor according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an overview of thread processing of the processor according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of a thread activation priority determination method for an input-side FIFO accumulation amount for a thread having a processor according to the first embodiment of the present invention;
FIG. 4 is a diagram showing an example of a thread activation priority determination method for an output-side FIFO accumulation amount for a thread with a processor according to the first embodiment of the present invention;
FIG. 5 is a diagram illustrating an example of a flow for determining a thread to be started next after the processor according to the first embodiment of the present invention;
FIG. 6 is a diagram illustrating an example of a thread activation priority determination method for an input-side FIFO accumulation amount for a thread having a processor according to the second embodiment of the present invention;
FIG. 7 is a diagram illustrating an example of a thread activation priority determination method for an output-side FIFO accumulation amount for a thread having a processor according to the second embodiment of the present invention;
[Explanation of symbols]
101 FIFO (First-In First-Out)
102 selection unit 103 execution control unit 104 cache 105 switching unit 106 register set 107 memory bus 108 storage unit 109 operation processing unit 202 status report 203 execution instruction

Claims (4)

A plurality of storage means for storing process data to be processed by one or more execution units, which corresponds to one of the processes obtained by time-sharing a certain data process into at least one or more;
Data to be processed by the execution unit is received from at least one of the plurality of storage means assigned to a certain execution unit, and the execution result of the execution unit is stored in one of the plurality of storage means assigned to the execution unit. Data processing means,
Receiving information about the amount of processing data stored by each storage means from each of the storage means;
As the amount of processing data stored in a storage unit is larger, the priority indicating the order of execution of the execution unit after the execution unit that receives data to be processed from the storage unit is determined as a higher priority. ,
The smaller the amount of processing data stored in a storage means, the lower the priority indicating the order of execution of the execution unit to be executed after that for the execution unit receiving data to be processed from the storage means. ,
When the amount of processing data stored in some of the storage means is equal, the increase / decrease tendency of the amount of processing data stored in the storage means for each execution unit that receives data to be processed from the storage means And a priority determining means for determining a higher priority in descending order of decreasing tendency .   When the priority determining unit determines that the amount of processing data stored in a certain storage unit exceeds the upper limit of the storage capacity of the storage unit, the priority determining unit is the highest in the execution unit that receives data to be processed from the storage unit. The processor according to claim 1, wherein the priority is determined. Computer including a processor according to any one of claims 1 to 2. With respect to an execution unit corresponding to one of the processes obtained by time-sharing a certain data process into at least one or more, data to be processed by the execution unit is received from at least one of a plurality of storage devices allocated to the execution unit.
Storing the execution result of the execution unit in one of the plurality of storage devices allocated to the execution unit;
Receiving information about the amount of processing data that each storage device stores from each of the storage devices;
As the amount of processing data stored in a certain storage device is larger, the priority indicating the order of execution of the execution unit to be executed thereafter is determined as a higher priority for the execution unit that receives data to be processed from the storage device. ,
The smaller the amount of processing data stored in a storage device, the lower the priority indicating the order of execution of the execution unit to be executed after that for the execution unit that receives data to be processed from the storage device. ,
When the amount of processing data stored in some of the storage devices is the same, the increasing / decreasing tendency of the amount of processing data stored in the storage devices for each execution unit that receives data to be processed from the storage means A priority determination method characterized by determining a higher priority in descending order of decreasing tendency .

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