JP3864248B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a logic circuit designed for low power consumption. In particular, a semiconductor device in which the power consumption for maintaining the state is completely cut off and the return from the standby mode is extremely quick while maintaining the state of the latch or register circuit (hereinafter simply referred to as a latch circuit) in the standby mode. Applicable to provision.
[0002]
[Prior art]
A C-MOSFET (Complimentary Metal Oxide Semiconductor Field Effect Transistor) circuit using a transistor having a plurality of threshold voltages is known as means for reducing the power consumption of the circuit while realizing high-speed operation of the circuit. A multi-threshold voltage (MT) CMOSFET circuit is hereinafter abbreviated as an MTCMOS circuit. FIG. 10 is a circuit diagram showing an example of an MTCMOS circuit. The MTCOMS circuit has virtual power supply lines v-Vdd and v-Vss in addition to the power supply lines Vdd and Vss. Vdd and v-Vdd are connected by a high threshold voltage transistor Hvt-Tr1, and Vss and v-Vss are connected by a high threshold voltage transistor Hvt-Tr2. The logic circuit is composed of a low threshold voltage transistor to form a LowVt circuit. The LowVt circuit is an example, and an arbitrary logic circuit that realizes a predetermined function is configured. Here, in order to operate the logic circuit (LowVt circuit) normally, it is necessary to apply the power supply voltage, and the power supply voltage to the LowVt circuit is supplied from v-Vdd and v-Vss. Since the response speed of the logic circuit is preferably as high as possible, the logic circuit is configured by transistors having a low threshold voltage. This is because if the threshold voltage is low, the turn-on time can be shortened to achieve a high operating speed. On the other hand, a transistor having a low threshold voltage is not preferable from the viewpoint of saving power consumption. That is, a transistor having a low threshold voltage has a large off-leakage current, and this off-leakage current cannot be ignored when a large number of gates are connected. In particular, when the circuit is in a non-operating state or in a standby mode (hereinafter simply referred to as a standby state), an off-leakage current flows even though the circuit is not operating, and wasteful power is consumed.
[0003]
Therefore, when the circuit enters the standby state, the virtual power supply lines v-Vdd and v-Vss are disconnected from the actual power supply lines Vdd and Vss, and measures are taken to prevent leakage current from flowing in the logic circuit. High threshold voltage transistors Hvt-Tr1 and Hvt-Tr2 are used to disconnect the virtual power line and the real power line. Since Hvt-Tr1 and Hvt-Tr2 have a high threshold voltage, there is little off-leakage current, and current consumption when the virtual power supply line is cut can be reduced. On the other hand, since Hvt-Tr1 and Hvt-Tr2 are not involved in the logic operation, the low switching speed does not affect the operation of the circuit.
[0004]
That is, the high speed operation of the logic circuit is realized by a transistor having a low threshold voltage, and the disadvantage of the power consumption by using the transistor having the low threshold voltage is that the high threshold transistor (Hvt-Tr1 and Cover by disconnecting from the actual power line with Hvt-Tr2). In this way, a semiconductor device having the advantages of both high speed operation and low power consumption can be realized. Here, an example is described in which the above functions are realized by both virtual power lines of v-Vdd and v-Vss. A similar function can be realized by using only one of the virtual power lines of v-Vdd and v-Vss. That is, the same MTCMOS circuit can be configured by Vdd and v-Vss or v-Vdd and Vss.
[0005]
However, the logic circuit has a large number of registers or latches, and these latch circuits need to be maintained until the state returns from the standby state to the normal operation state. Conventionally, the following means are known as the latch state holding means in the standby state.
[0006]
FIG. 11 is a circuit diagram for explaining an example of latch state holding means in the prior art. In the example shown in FIG. 11, a level holder circuit is provided at the output stage of the LowVt circuit. The level holder circuit is composed of a high-threshold transistor, and the voltage is supplied from the actual power supply lines (Vdd and Vss) regardless of whether or not the standby state is established (that is, whether Hvt-Tr1 and Hvt-Tr2 are on or off). Supply. By providing such a level holder circuit where it is necessary to hold the level in the standby state, it becomes possible to hold the necessary latch state. Further, the current consumption during standby can be suppressed by configuring the level holder circuit with a transistor having a high threshold voltage.
[0007]
FIG. 12 is a diagram for explaining another example of latch state holding means in the prior art. In the example shown in FIG. 12, an operation of periodically refreshing is performed so that the potentials of the virtual power supply lines v-Vdd and v-Vss maintain the data retention voltage at a minimum. Here, the data retention voltage is a minimum voltage necessary to maintain the latch state in the logic circuit. In addition, the refresh is an operation of charging v-Vdd and v-Vss so that the voltages of the virtual power supply lines v-Vdd and v-Vss become substantially the same potential as the actual power supply lines Vdd and Vss. That is, when the standby state is entered, Hvt-Tr1 and Hvt-Tr2 are turned off in order to save power consumption, but the charges accumulated in v-Vdd and v-Vss are discharged from the time of turning off and gradually decrease ( v-Vss rises). At this time, if the voltage between v-Vdd and v-Vss falls below the data retention voltage, the latch state disappears. Therefore, in this example, before the voltage between v-Vdd and v-Vss falls below the data retention voltage, the operation of turning on Hvt-Tr1 and Hvt-Tr2 or other means is used to charge the v-Vdd and v-Vss lines. Perform the operation. The cycle of this operation is the refresh interval. By such an operation, the latch state in the logic circuit in the standby state can be maintained.
[0008]
FIG. 13 is a diagram for explaining still another example of latch state holding means in the prior art. In the example shown in FIG. 13, diodes D1 and D2 are inserted between Vdd and v-Vdd and between Vss and v-Vss, respectively. Since the silicon junction diode does not turn on unless forward bias of about 0.7V is applied, the diode is off unless a potential difference of 0.7V or more occurs between Vdd and v-Vdd or between Vss and v-Vss. State. When the standby state is entered and Hvt-Tr1 and Hvt-Tr2 are turned off and the charges of v-Vdd and v-Vss are discharged, the potential drops (v-Vss rises), and diodes D1 and D2 are turned on. become. Therefore, after the diode is turned on, v-Vdd and v-Vss are maintained at the potential, and the potential between v-Vdd and v-Vss is maintained at the data retention voltage or higher. As a result, the latch state of the logic circuit is maintained.
[0009]
[Problems to be solved by the invention]
However, the example shown in FIGS. 11 to 13 has the following problems. That is, in the example shown in FIG. 11, the power is continuously supplied to the level holder circuit even in the standby state, and it is not possible to realize complete suppression of power consumption. In addition, it is necessary to add a function for automatically inserting a level holder circuit to the circuit design tool. If the level holder circuit is inserted manually at the design stage, the design efficiency cannot be improved, and it seems that there are many insertion points. Therefore, a design tool that does not have an automatic insertion function has a large human load. This is because it is expected to take.
[0010]
In the example shown in FIG. 12, current consumption due to charging / discharging of the virtual power supply line is increased, and the power consumption reduction effect to be realized by employing the MTCOMS circuit is diminished.
[0011]
Further, in the example shown in FIG. 13, the supply of the DC current through the diode continues to be performed even in the standby state, and complete suppression of the consumption current is not realized as in the case of FIG.
[0012]
That is, although the MTCMOS circuit is originally intended to simultaneously realize the high speed operation and low power consumption of the logic circuit, the power consumption of the MTCMOS circuit in order to maintain the latch state in the logic circuit. It is necessary to diminish the suppression effect. That is, the original and ultimate purpose of the logic circuit to which the MTCMOS circuit is applied is to simultaneously realize the latch state retention and zero power consumption in the standby state, but the method or technique has not yet been presented. Is the current situation.
[0013]
An object of the present invention is to maintain a latch state in a logic circuit in a standby state without impairing its original characteristics in a logic circuit that realizes high-speed operation and low power consumption using an MTCMOS circuit. It is another object of the present invention to maintain the latch state in the standby state without impairing the high speed of the logic operation during normal operation. Another object is to realize a logic circuit that realizes quick transition from a normal operation state to a standby state and quick return from a standby state to a normal operation state. It is another object of the present invention to provide a semiconductor device manufacturing technique that hardly increases the process load and costs by adding a few additional steps to the conventional manufacturing process.
[0014]
[Means for Solving the Problems]
The outline of the present invention will be described as follows. The semiconductor device of the present invention includes a first power supply line to which a first voltage is supplied, a second power supply line to which a second voltage is supplied, and a first transistor having a first level threshold voltage. Either a third power supply line connected to the first power supply line or a fourth power supply line connected to the second power supply line via the second transistor having the first level threshold voltage A circuit composed of a transistor having a second level threshold voltage and driven by a potential difference between the first power supply line and the fourth power supply line or between the third power supply line and the second power supply line; And a nonvolatile latch circuit connected to an arbitrary node of the circuit. Alternatively, in the semiconductor device of the present invention, a potential difference between the first power line, the second power line, both the third power line and the fourth power line, and the third power line and the fourth power line. And a nonvolatile latch circuit connected to an arbitrary node of the circuit. That is, the present invention includes a non-volatile latch circuit that retains its state even when the power supply is cut off, in the logic circuit portion in the MTCOMS circuit.
[0015]
With such a nonvolatile latch circuit, a necessary latch state can be recorded in a nonvolatile manner, and that state can be maintained even if the virtual power supply line falls below the data retention voltage. The nonvolatile latch circuit of the present invention is connected to an arbitrary node of the logic portion. In other words, a memory array area is provided separately from the logic circuit, and the state required when transitioning from the normal operation state to the standby state is recorded in the memory array area, and when returning from the standby state to the normal operation state, the memory array area is recorded. There is no need to load data. For this reason, it is not necessary to decode the word line or the bit line, and no special operation for transition to the standby state or return from the standby state is required.
[0016]
Note that the nonvolatile latch circuit can replace a volatile latch circuit that has been widely used in conventional logic circuits. The nonvolatile latch circuit of the present embodiment operates in the same manner as a conventional volatile latch circuit, and it is necessary to insert a nonvolatile latch circuit that simply provides a nonvolatile function that is not necessary for circuit design. Absent. Therefore, a conventional design system can be used as it is simply by adding a nonvolatile latch circuit to the library of the logic circuit design system. That is, when designing the semiconductor device of the present invention, it is not necessary to change the logic circuit design system in a methodological manner.
[0017]
The nonvolatile latch circuit includes a pair of resistor elements in which at least one resistor element is a spin valve element, and the latch state of the nonvolatile latch circuit is stored as a resistance value magnitude relationship of the resistor element pair. Can do. That is, in the present invention, the latch state is recorded as the resistance value of the spin valve element. An example of the spin valve element is a tunnel magnetoresistive element. The recording of the latch state in the nonvolatile latch circuit can be exemplified by one performed every operation cycle of the circuit or one performed only immediately before the first transistor and the second transistor are turned off.
[0018]
The spin valve element is a memory element using a magnetoresistive effect in which a resistance value changes depending on the direction of magnetization. Examples of the magnetoresistive effect include an anisotropic magnetoresistive effect (AMR), a giant magnetoresistive effect (GMR), and a tunnel magnetoresistive effect (TMR) that obtains a magnetoresistive effect using a tunnel current. A spin valve element using TMR has a three-layer structure of at least a ferromagnetic layer (pinned layer), an insulating layer (tunnel layer), and a ferromagnetic layer (free layer), and is called an MTJ (Magnetic Tunnel Junction) element. It is. When the magnetization direction of the free layer matches the magnetization direction of the pinned layer, a large amount of tunnel current flows through the insulating layer, and when the magnetization direction of the free layer is opposite to the magnetization direction of the pinned layer, the current flowing through the insulating layer matches. Less than the tunnel current of the case. That is, information can be recorded according to the magnetization direction (electron spin direction) of the free layer.
[0019]
In the present invention, the above MTJ element can be used. The information recorded on the MTJ element is non-volatile, and is a static element that does not cause destruction of the recorded content due to reading of information. Reading of information only detects a resistance change of the MTJ element. Also, an operation for changing the direction of spin, that is, a write operation can be performed in nanosecond order or less. Therefore, the read and write speeds are high, and the nonvolatile latch circuit can be operated without affecting the operation speed of a normal logic circuit.
[0020]
In addition, since the MTJ element constituting the nonvolatile latch circuit according to the present invention is formed of a film such as a ferromagnetic material as described above, it can be formed at a temperature that does not deteriorate the performance of the already formed transistor. is there. That is, the influence of forming the MTJ element on the performance of the transistor already formed on the silicon surface is small. That is, the load on the manufacturing process for forming the MTJ element is small. Further, the MTJ element can be manufactured by adding a few masks and a photolithography process to the conventional logic circuit forming process (transistor forming process). The disadvantages of manufacturing the semiconductor device of the present invention, that is, a semiconductor device including a nonvolatile latch circuit including a spin valve element such as an MTJ element, are small compared to a conventional manufacturing process. Furthermore, the MTJ element of the present invention can be formed in a wiring layer above a transistor constituting a logic circuit. That is, the MTJ element does not affect the area where the transistor is formed on the silicon substrate. Therefore, the formation of the MTJ element does not occupy the area of the silicon substrate, there is no demerit for miniaturization, and the miniaturization can be advantageously promoted.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different modes and should not be interpreted as being limited to the description of the present embodiment. In addition, the same code | symbol shall be attached | subjected to the same element or member throughout the whole embodiment.
[0022]
FIG. 1 is a circuit diagram illustrating an outline of a semiconductor device according to an embodiment of the present invention. The semiconductor device of the present embodiment includes power supply lines Vdd and Vss, virtual power supply lines v-Vdd and v-Vss, high threshold voltage MOSFETs Hvt-Tr1 and Hvt-Tr2, combinational logic circuit 1, and nonvolatile latch circuit NVL1. , NVL2,..., NVLn.
[0023]
The power supply lines Vdd and Vss are power supply lines that supply a power supply voltage that is actually supplied to the semiconductor device. When the power supply to the semiconductor device is interrupted, for example, power is not supplied to Vdd and Vss in the power-off state, but power supply to Vdd and Vss is continued in the standby state. For example, the potential of Vdd can be exemplified by 1.8 V, and the potential of Vss can be exemplified by the ground potential.
[0024]
Virtual power supply lines v-Vdd and v-Vss are power supply lines for driving combinational logic circuit 1 and nonvolatile latch circuits NVL1 to NVL1. Virtual power supply lines v-Vdd and v-Vss are connected to Vdd and Vss via Hvt-Tr1 and Hvt-Tr2, respectively. When the semiconductor device is in a normal operation, Hvt-Tr1 and Hvt-Tr2 are turned on, and the potentials of v-Vdd and v-Vss substantially match Vdd and Vss, respectively. When the semiconductor device is in a standby state, Hvt-Tr1 and Hvt-Tr2 are turned off, and power supply from Vdd to v-Vdd and power supply from Vss to v-Vss are cut off. As a result, power consumption in the standby state can be reduced.
[0025]
The high threshold voltage MOSFETs Hvt-Tr1 and Hvt-Tr2 are MOSFETs having a threshold voltage higher than the threshold voltage of the MOSFETs constituting the combinational logic circuit 1. As described above, Hvt-Tr1 and Hvt-Tr2 have a function of blocking the connection between Vdd and v-Vdd and Vss and v-Vss, respectively. Since Hvt-Tr1 and Hvt-Tr2 are high threshold voltage transistors, the off-state current is small, and thus the effect of suppressing power consumption is large. On / off control of Hvt-Tr1 and Hvt-Tr2 is performed by control signals SIG1, SIG2 input to the gates.
[0026]
The combinational logic circuit 1 is an arbitrary logic circuit, and is arbitrarily designed so as to realize a predetermined function. The combinational logic circuit 1 is composed of a low threshold voltage MOSFET as described above. The operation speed can be increased by configuring the MOSFET with a low threshold voltage.
[0027]
The nonvolatile latch circuits NVL1 to NVL1 are latch circuits that record the latch state in a nonvolatile manner. In this specification, a 1-bit register is also included in the latch circuit. The non-volatile latch circuits NVL1 to NVLn are connected to arbitrary nodes in the combinational logic circuit 1. That is, the nonvolatile latch circuit can be inserted into an output unit or the like that needs to record the state in the combinational logic circuit 1 when entering the standby state. Alternatively, all or part of the state recording circuits such as latches, flip-flops, and registers necessary for realizing the original logic function can be replaced with the nonvolatile latch circuit.
[0028]
As a result, even if the circuit enters a standby state and the voltage between the virtual power supply lines is lower than the data retention voltage, data in a portion that needs to be recorded is not lost. In the semiconductor device of this embodiment, since the nonvolatile latch circuit is individually connected to an arbitrary node, it is necessary to record or read necessary data in a memory area provided separately from a logic circuit or the like such as a memory array. There is no. This eliminates the need for a special operation for saving or restoring data when entering the standby state. Of course, there is no need to provide a memory array area for recording the state in the logic circuit.
[0029]
In addition, since the conventional volatile latch circuit can be replaced with a nonvolatile latch circuit, the conventional design system can be used as it is simply by adding elements of the nonvolatile latch circuit to the conventional logic circuit design system. It is. In order to design the semiconductor device according to the present embodiment, no significant change such as a methodological change of the conventional design system is required.
[0030]
FIG. 2 is a circuit diagram showing an example of a nonvolatile latch circuit. The same nonvolatile latch circuit can be applied to each of NVL1 to NVL. Therefore, FIG. 2 illustrates one of the nonvolatile latch circuits. The nonvolatile latch circuit includes a sense / latch circuit unit C1 and a write current generation circuit C2. The nonvolatile latch circuit receives the input signals IN and IN bar and outputs the output signals OUT and OUT bar. In addition, control signals REFRESHN and DATAGET are input to the nonvolatile latch circuit. The operation of these control signals will be described later. The signals S and S are in a complementary relationship. When S is at “High level”, the S bar is at “Low level”, and when S is at “Low level”, the S bar is at “High level”. "It is in. In the figure, bars are shown as horizontal lines on the symbols. Although an example in which both the input signals IN and IN bar are input is shown here, only the input signal IN may be input and the input signal IN bar may be generated by an appropriate inverter. Similarly, only the output signal OUT may be taken out and the OUT bar generated by an appropriate inverter. In the logic circuit connected to the subsequent stage of the nonvolatile latch circuit of this embodiment, when only the output signal OUT or OUT bar is necessary, only one of them may be output.
[0031]
The sense / latch circuit unit C1 includes inverter circuits INV1 and INV2. INV1 includes a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Tr1 and an n-channel MOSFET Tr2. The input of INV1 is a common gate of Tr1 and Tr2, and is connected to the output node n2 of INV2. The source of Tr1 is connected to the power supply voltage Vdd, and the drain of Tr1 is connected to the drain of Tr2. The source of Tr2 is connected to one end of a tunnel magnetoresistive element MTJ0 described later. The connection point between the drain of Tr1 and the drain of Tr2 is the output node n1 of INV1. The output node n1 outputs the output signal OUT bar.
[0032]
INV2 includes a p-channel MOSFET Tr3 and an n-channel MOSFET Tr4. The input of INV2 is a common gate of Tr3 and Tr4, and is connected to the output node n1 of INV1. The source of Tr3 is connected to the power supply voltage Vdd, and the drain of Tr3 is connected to the drain of Tr4. The source of Tr4 is connected to one end of a tunnel magnetoresistive element MTJ1 described later. The connection point between the drain of Tr3 and the drain of Tr4 is the output node n2 of INV2. The output node n2 outputs an output signal OUT.
[0033]
Here, the MOSFET is exemplified as the transistor constituting the nonvolatile latch circuit, but the gate insulating film may be a MISFET (Metal Insulator Semiconductor FET) made of silicon nitride or another insulating film, or a bipolar transistor. There may be. The same applies to MOSFETs described below. Furthermore, Tr1 and Tr3 may be replaced with appropriate load elements such as resistance elements.
[0034]
The sense / latch circuit unit C1 further includes tunnel magnetoresistive elements MTJ0 and MTJ1. MTJ0 and MTJ1 have at least three layers of a pinned layer, an insulating film, and a free layer. MTJ0 and MTJ1 are resistance elements in which the resistance value of the path from the pinned layer to the free layer is high when the magnetization directions of the pinned layer and the free layer are different, and the resistance value is low when the magnetization directions match. In the present embodiment, when MTJ0 exhibits a low resistance value (that is, when the magnetization directions of the free layer and the pinned layer match), MTJ1 exhibits a high resistance value (that is, the magnetization direction of the free layer is equal to that of the pinned layer). Different from the magnetization direction). Such a configuration can be realized by arranging the write data line DWL as follows. For example, for a current passing through a certain direction to DWL, for example, a magnetic field in the same direction as the pinned layer is generated for MTJ0, and a magnetic field is generated for MTJ1 in a direction different from the pinned layer. Place. As a result, the magnetization direction of the free layer of either MTJ0 or MTJ1 always coincides with the magnetization direction of the pinned layer, and the magnetization direction of the other free layer matches the magnetization direction of the pinned layer due to the DWL passing current in a certain direction. It becomes different. That is, one of the resistance value of MTJ0 and the resistance value of MTJ1 is large and the other is small. By reversing the direction of the passing current to DWL, the magnitude relationship between the resistance values of MTJ0 and MTJ1 can be reversed. The arrangement of MTJ0, MTJ1 and DWL will be described later.
[0035]
Here, MTJ0 and MTJ1 are shown as examples of spin valve elements, but can be replaced with spin valve elements using magnetoresistance effects (GMR, AMR) other than the tunnel magnetoresistance effect (TMR). In addition, although the resistance elements of MTJ0 and MTJ are tunnel magnetoresistive elements here, either one may be a pure resistance having a fixed resistance value. In this case, if the resistance of the MTJ changes in the range of Rh to Rl, it is necessary to have a relationship of Rh>R> Rl (where R is the resistance value of the pure resistance).
[0036]
The sense latch circuit C1 further includes p-channel MOSFETs Tr5 and Tr6 and an n-channel MOSFET Tr7. The sources of Tr5 and Tr6 are connected to Vdd, the drain of Tr5 is connected to n1, and the drain of Tr6 is connected to n2. The drain of Tr7 is connected to a connection point SET connecting the other ends of MTJ0 and MTJ1, and the source of Tr7 is grounded. A control signal REFRESHN is input to each gate of Tr5, Tr6, and Tr7. The operation of Tr5, Tr6, Tr7 will be described later. Note that Tr7 may be omitted when the driving force of Tr5 and Tr6 is sufficiently larger than that of Tr2 and Tr4. Here, the driving force can be typically represented by a small on-resistance.
[0037]
The write current generation circuit C2 includes n-channel type MOSFETs Tr8, Tr9, Tr10, Tr11, Tr12. The drains of Tr8 and Tr9 are connected to Vdd. The sources of Tr8 and Tr9 are connected to the drains of Tr10 and Tr11, respectively, and the sources of Tr10 and Tr11 are connected to each other and connected to the drain of Tr12. The source of Tr12 is grounded. An input signal IN is input to the gates of Tr8 and Tr11, and an input signal IN bar is input to the gates of Tr9 and Tr10. The connection between the source of Tr8 and the drain of Tr10 is the output node n3 of the data write line DWL, and the connection between the source of Tr9 and the drain of Tr11 is the output node n4 of DWL. For example, when the input signal IN is at a high level, Tr8 is in an on state and n3 is connected to a power source of a potential Vdd (since IN bar is at a low level, Tr10 is in an off state). On the other hand, since Tr11 is on, n4 is connected to the ground potential when Tr12 is on. That is, in this state, a current i (i> 0) flows through the DWL in the positive direction of the arrow. Conversely, when the input signal IN is at a low level, a current i flows through the DWL in the direction opposite to the arrow. A control signal DATAGET is input to the gate of Tr12. The write current flows through the DWL only during the period when the High level is applied as DATAGET.
[0038]
Here, the configuration as described above is illustrated as the write current generation circuit C2, but as long as the circuit can control the direction of the current flowing through the write data line DWL in response to the input signal IN or IN bar, It can be replaced with a configuration.
[0039]
FIG. 3A is a plan view illustrating a part of the nonvolatile latch circuit of the present embodiment, and FIG. 3B is a cross-sectional view thereof. FIG. 3 does not show the entire nonvolatile latch circuit. Further, a part of the illustrated nonvolatile latch circuit constitutes a part of a logic circuit formed on a single semiconductor substrate (chip). Note that the cross-sectional view of FIG. 3B shows a cross section taken along the line bb in the plan view of FIG.
[0040]
An element isolation region 2 is formed on the semiconductor substrate 1s, and a MOSFET constituting a nonvolatile latch circuit is formed in an active region 3 surrounded by the element isolation region 2. The MOSFET is the aforementioned Tr1 or the like.
[0041]
The semiconductor substrate 1s is made of, for example, single crystal silicon. When the MOSFET is an n-channel type, the semiconductor substrate 1s itself is p-type or a p-type well region is formed in the semiconductor substrate 1s. When the MOSFET is a p-channel type, the semiconductor substrate 1s itself is n-type or an n-type well region is formed in the semiconductor substrate 1s.
[0042]
The element isolation region 2 is made of, for example, silicon oxide. The element isolation region 2 is formed, for example, by forming a groove on the surface of the semiconductor substrate 1s, and then forming a silicon oxide film by a CVD (Chemical Vapor Deposition) method or the like, and using a CMP (Chemical Mechanical Polishing) method, It is formed by removing the film. The active region 3 is a region surrounded by the element isolation region 2.
[0043]
A MOSFET gate insulating film 4 is formed on the active region 3, and a MOSFET gate electrode 5 is further formed thereon. In the vicinity of the surface of the active region 3 on both sides of the gate electrode 5, a semiconductor region 6 serving as a source or drain of the MOSFET is formed. Gate electrode 5 is formed of, for example, a low-resistance polycrystalline silicon film. In order to reduce the resistance, for example, boron or phosphorus is doped at a high concentration. In order to reduce the resistance of the polycrystalline silicon film, the surface may be formed into a metal silicide, or a metal such as tungsten may be formed on the surface through an intermediate layer. The gate insulating film 4 is a silicon oxide film formed by, for example, a thermal oxidation method or a thermal CVD method. When the MOSFET is an n-channel type, the semiconductor region 6 is doped with an n-type impurity such as phosphorus. When the MOSFET is a p-channel type, a p-type impurity such as boron is doped. The surface of the semiconductor region 6 may be formed into a metal silicide in order to reduce the resistance or reduce the contact resistance. The semiconductor region 6 is formed by self-alignment using the gate electrode as a mask.
[0044]
A first layer metal wiring M1 (8) is formed above the semiconductor region 6 via a plug 7. A damascene process can be used to form the plug 7 and the wiring M1. That is, after depositing an interlayer insulating film made of a silicon oxide film or the like, the surface thereof is flattened by, for example, a CMP method, and connection holes or wiring grooves are formed by, for example, a dry etching method. Thereafter, a conductive material (eg, tungsten, copper, aluminum, etc.) is deposited, and excess conductive material on the surface of the interlayer insulating film in regions other than the connection holes and wiring grooves is removed by, eg, CMP. These damascene processes can also be applied to the formation of wirings, plugs and the like which will be described later. In the following description, the description of the damascene process is omitted.
[0045]
Over the first layer metal wiring M1, a second layer metal wiring M2 (10, 11) is formed via a plug 9. M2 includes a data write line DWL. The data write line DWL is patterned in a U shape as shown in the plan view of FIG. In general, the magnetization direction of the MTJ pinned layer is made uniform by raising and lowering the temperature with an external magnetic field applied. That is, once the temperature is raised above the Neel temperature, which is the magnetic transition temperature of the antiferromagnet to the paramagnetic state, and the temperature is lowered while applying an external magnetic field from the temperature above the Neel temperature, the magnetization direction is changed. Align. In the case of FIG. 3A, the magnetization direction of the pinned layer is formed so as to be aligned with the x direction or its negative direction. Under such circumstances, if a current is passed in a certain direction of DWL, the magnetization direction of the free layer becomes opposite to MTJ0 and MTJ1 due to the magnetic field. That is, as described above, the magnitude relationship between the resistance values of MTJ0 and MTJ1 can be generated, and the magnitude relationship can be inverted depending on the direction of the passing current of DWL.
[0046]
A local wiring 12 is formed on the second layer metal wiring M2 via an insulating film, and magnetoresistive elements MTJ0 and MTJ1 are formed on the local wiring 12. Further, a third layer metal wiring M3 is formed above MTJ0 and MTJ1.
[0047]
The film thickness of the insulating film between M2 and the local wiring 12 is as thin as 50 to 100 m, for example. By making the film thickness sufficiently thin, the magnetic field generated by the DWL reaches the free layers of MTJ0 and MTJ1 with a sufficient magnitude. Further, by making the film thickness sufficiently thin, it is not necessary to form a connection member such as a plug (stud) in the contact hole for connecting to the local wiring 12.
[0048]
As shown in the figure, MTJ0 and MTJ1 are formed on the top of the DWL. That is, it is formed at a position that is affected by the magnetic field generated by the DWL. The MTJ0 and MTJ1 include the ferromagnetic free layer 13, the insulating layer 14, the ferromagnetic pinned layer 15, and the diamagnetic layer 16, as described above. An appropriate intermediate layer may be provided in each of these layers or upper and lower end layers thereof. For example, a cobalt (Co) film can be used for the free layer 13 and the pinned layer 15, and an FeMn film can be used for the diamagnetic layer 16, for example. Further, the insulating layer 14 includes a silicon oxide film or alumina (Al ₂ O ₃ ) A membrane can be used. These thin films can be formed by sputtering or CVD. A metal layer such as titanium may be formed between the free layer 13 and the local wiring 12 and on the diamagnetic layer 16.
[0049]
Further, as shown in the figure, MTJ0 and MTJ1 are formed in an interlayer insulating film between the second layer metal wiring M2 and the third layer metal wiring. For this reason, the plane area of the device occupied only by the MTJ is substantially zero, and there is almost no area demerit by forming the MTJ. In addition, a photomask necessary for forming the MTJ includes a mask for forming a contact hole for connecting the local wiring 12 and the second layer metal wiring 10, a mask for patterning the local wiring 12, There are at most three masks together with a mask for patterning each layer of the MTJ. From the ratio of all the manufacturing processes, the addition of the photolithography process corresponding to these three masks is sufficiently small, and the nonvolatile latch circuit of the present embodiment is compared with the manufacturing process of the conventional logic circuit. It can be said that the increase in process load in the manufacturing process is small. Moreover, the process after the MOSFET is manufactured is a low-temperature process of 400 ° C. or lower such as CVD and sputtering, and there is no concern about the deterioration of the MOSFET due to the formation of the MTJ.
[0050]
With the device configuration as described above, the nonvolatile latch circuit shown in FIG. 2 can be realized. However, the device configuration shown in FIG. 3 is merely an example, and the circuit of FIG. 2 can be realized by another configuration.
[0051]
The operation of the nonvolatile latch circuit described above is as follows. FIG. 4 is a diagram illustrating an example of timing for explaining the operation of the nonvolatile latch circuit. First, the data write operation will be described.
[0052]
It is assumed that the input signals IN and IN bar are input at time t1, and that IN is maintained at a high level and IN bar is maintained at a low level as illustrated in the figure from time t1 to t4. During times t1 to t4, Tr8 and Tr11 shown in FIG. 2 are in an on state, and Tr9 and Tr10 are in an off state. Between times t1 and t2, the potential of the node n3 is Vdd−Vth (where Vth is the threshold voltage of a transistor such as Tr8), but since Tr12 is in an off state, the potential of the node n4 is also Vdd−. Vth, and no current flows through the data write line DWL.
[0053]
When the control signal DATAGET changes to High level at time t2, Tr12 is turned on. At this time, the potential of n4 decreases toward the ground potential, and a data write current starts to flow through DWL. The direction of the current is the direction of the arrow. A magnetic field is generated around the DWL by passing a current through the DWL, and the magnetization directions of the free layers of the tunnel magnetoresistive elements MTJ0 and MTJ1 are changed or maintained. The magnetization direction of the pinned layer is determined in advance so as to have a magnetization direction relationship between the free layer and the pinned layer so that the resistance value of MTJ0 is smaller than that of MTJ1 in the above-described IN and IN bar states. Suppose that
[0054]
The data write current is maintained until DATAGET becomes Low level at time t3. Since the current needs to flow for at least the minimum time necessary for the magnetization directions of the free layers of MTJ0 and MTJ1 to change, a time that can secure such minimum time is set at time t3. The time required for magnetization reversal (minimum time t3-t2) is 1 ns or less. For example, published in February 2001, by Hidehide Matsuyama, “Current Status and Issues of Magnetic Random Access Memory”, Journal of Applied Magnetics Society of Japan, Vol. 25, no. 2, pp. As described in 51-58, it is known that the time required for magnetization reversal can be reduced to 1 ns or less.
[0055]
In this way, the input signal state is reflected in MTJ0 and MTJ1, and the data write operation is completed. Note that the input signal is maintained until time t4 in order to secure a predetermined data hold time after time t3. Time (t3-t1) is a data setup time, and time (t4-t3) is a data hold time.
[0056]
In the write operation of the present embodiment, no current flows through DWL only by inputting an input signal, and current application to DWL is controlled only by control signal DATAGET. Therefore, the timing specifications required for the input signal only ensure a predetermined data setup time and data hold time, and it is not necessary to completely match the timings of IN and IN bar. Further, the time during which the DATAGET signal is at the high level may be equal to or longer than the switching time of the MTJ, and the time can be controlled to a minimum by the Tr12. As a result, current consumption for data writing can be minimized. Note that Tr12 is not particularly necessary unless the current consumption and the timing of the input signal are taken into consideration.
[0057]
Next, an operation for reading information from the MTJ will be described. Consider a case where the control signal REFRESHN changes from High level to Low level at time t5 and returns to High level at time t7.
[0058]
Prior to time t5, Tr5 and Tr6 are in the off state and Tr7 is in the on state, so the previous state is maintained regardless of the writing to the MTJ. Even if Tr7 is in the ON state, Tr1 and Tr2, Tr3 and Tr4 have a C-MOS structure, so that no current flows and current consumption is saved.
[0059]
When REFRESHN changes to low level at time t5, Tr5 and Tr6 change to an on state and Tr7 changes to an off state. Since Tr5 and Tr6 are in the on state and Tr7 is in the off state, the potentials of the nodes n1 and n2 become Vdd, and as a result, Tr2 and Tr4 are in the on state. Therefore, SET is precharged to Vdd-Vth through Tr2 and MTJ0 and through Tr4 and MTJ1. At the same time, Tr7 is turned off, so that no steady current flows due to this precharge. Therefore, current consumption during refresh (data reading) can be minimized.
[0060]
Assuming that the potentials of n2 and n1 (output signals OUT and OUT bar) before precharging are low level and high level, respectively, as shown in FIG. 4, OUT (node n2) changes to high level by precharging. In FIG. 4, the time required for precharging is t6-t5.
[0061]
When REFRESHN changes to high level at time t7, Tr5 and Tr6 change to an off state and Tr7 changes to an on state. In this state, Tr1 and Tr2, Tr3 and Tr4 start operation as inverters, and either node n1 or node n2 operates to be at a high level and the other to be at a low level. Initially in this transient state, both n1 and n2 are at high level, so both Tr2 and Tr4 are on, and Tr7 is also on, so the potentials of n1 and n2 are in accordance with the circuit time constant. The operation to transition to the ground potential is entered. One of n1 and n2 having a lower potential first turns off Tr2 or Tr4 and enters a steady state. When Tr2 first enters the off state, the steady state is in which n1 is at a high level and n2 is at a low level. When Tr4 enters the OFF state first, it becomes a steady state where n1 is low level and n2 is high level. That is, the circuit composed of Tr1 and Tr2, Tr3 and Tr4 serves as a sense circuit that amplifies the potential difference between the nodes n1 and n2 to a logic level. Note that in this circuit, current flows only during the state transition period, and no current flows during a period in which the state is stabilized, so power consumption is extremely small.
[0062]
Which node has the potential decreasing first is determined by the time constant of the circuit as described above. The time constant of n1 is mainly determined by the resistance value of MTJ0, the ON resistance of Tr2 and Tr7, and the stray capacitance. The time constant of n2 is mainly determined by the resistance value of MTJ1 and the ON resistance of Tr4 and Tr7. , Determined by stray capacitance. The stray capacitance of the circuit is not so large, and if the circuit is made symmetrical, the stray capacitance on the n1 side and the n2 side will be almost the same, so the difference in time constant is determined by the resistance value of the MTJ. In the state described above, since the resistance value of MTJ0 is smaller, the potential of n1 decreases first, and Tr4 is turned off first. That is, n2 (OUT) is steady at High level and n1 (OUT bar) is steady at Low level. In FIG. 4, this transition time is t8-t7.
[0063]
As described above, the state recorded in the MTJ is read and output as the output signals OUT and OUT bar. This read operation is performed in response to the REFRESHN signal. However, it is also possible to perform the read operation in response to power-on, for example. In the precharge operation described above, the potentials of the nodes n1 and n2 do not necessarily match. That is, even during the precharge operation, it is sufficient that the potentials of n1 and n2 rise so that the latch circuit composed of the inverter pair reflects the difference in resistance value of MTJ after precharge. For example, Tr7 can be replaced with a current limiting element such as a resistance element as long as a sufficient potential to turn on can be realized. If the driving force of Tr5 and Tr6 can be sufficiently increased, the SET node can be directly connected to the ground potential.
[0064]
Note that the high state of the control signal DATAGET and the low state of REFRESHN can be temporally superimposed. As a superposition condition, it is necessary that the MTJ state be determined before the rising edge of REFRESHN.
[0065]
Further, the high state of DATAGET and the low state of REFRESHN can be arbitrarily separated in time. That is, it is possible to arbitrarily set the input data capture timing and the output data validation timing. As a result, this circuit can be operated like a master-slave type flip-flop.
[0066]
FIG. 5 is a diagram showing the result of simulating the operation when the power supply voltage Vdd (v−Vdd) is cut off. The vertical axis is voltage, and the horizontal axis is time. The power supply voltage is cut off at about 21 ns, and Vdd is completely 0 V at about 30 ns. Thereafter, the power supply voltage starts to be restored at about 40 ns, and Vdd is almost completely restored at about 50 ns. It can be seen that the output OUT bar and the output OUT automatically return to the state before the power supply is cut off following the return of the power supply. The refresh operation (data reading) is performed at about 49 ns when the power supply voltage is almost restored, and the refresh operation is completed at about 51 ns. Even if the data is not automatically restored with the restoration of the power supply voltage, the latching state is restored to the state before the power is shut off by the refresh operation. FIG. 6 is an enlarged view of the refresh operation. The vertical axis is voltage, and the horizontal axis is time. However, the absolute value of the time axis does not correspond to FIG. At a time of 9.0 ns, the REFRESHN signal starts to become a low level, and at about 9.5 ns, the REFRESHN signal almost reaches a low level. OUT (n2 potential) and OUT bar (n1 potential) change with a delay of about 0.2 ns from the REFRESHN signal, and the precharge is completed at about 9.7 ns. The SET potential almost follows this operation. When the REFRESHN signal starts to be high level at time 11.0 ns, OUT (n2 potential) and OUT bar (n1 potential) begin to decrease with a delay of about 0.2 ns, and OUT bar (n1 potential) starts at about 11.3 ns. Is divided into high level and OUT (n2 potential) is divided into low level, and a steady state is reached at 11.7 ns. In this simulation, the rise time and fall time of REFRESHN are set to 0.5 ns, but the circuit operation can be further speeded up by reducing them.
[0067]
As described above, the nonvolatile latch circuit according to the present embodiment can secure an operation speed with a high ns order as the operation speed. For this reason, it is possible to record or read the state (data) from / to the nonvolatile latch circuits NVL1 to NVL every operation cycle (clock) of the logic circuit. Even if data is written to the nonvolatile latch circuit every operation cycle, the operation speed of the logic circuit is not impaired. This is a great advantage compared to the case where an EEPROM (Electrical Erasable Programmable Read Only Memory) or a flash EEPROM is used as the nonvolatile memory element. That is, in an EEPROM or the like, the write / erase time is slower than the logic period, and it is impossible to perform the write / erase operation in synchronization with the operation of the logic circuit. In addition, an EEPROM or the like requires a high voltage for writing / erasing, but a high voltage is not necessary for the nonvolatile latch circuit of this embodiment. This point can also be cited as an advantage of the semiconductor device of this embodiment.
[0068]
Note that the nonvolatile latch circuit of this embodiment can be formed by adding an MTJ element to a wiring layer after forming a transistor included in a logic circuit. The MTJ can be formed only by adding at most three masks (two depending on process selection) and a photolithography process. In other words, the nonvolatile latch circuit of this embodiment can be formed with a small number of additional steps compared to the entire semiconductor device formation step. It can be seen that the advantages of such a process are significant when compared with the case of a floating gate type nonvolatile recording element such as an EEPROM. In other words, the EEPROM requires a complicated process different from a normal MOSFET forming process for forming a logic circuit in order to form a floating gate. On the other hand, the nonvolatile latch circuit of the present embodiment can be formed by adding a relatively simple process as described above to a normal logic circuit MOSFET formation process. Compared with the formation process of the EEPROM, the formation process of the nonvolatile latch circuit of this embodiment is simple, and its superiority is clear from the viewpoint of process load and cost reduction.
[0069]
Further, since the state (data) is recorded every logic cycle, the data is recorded even when a sudden power interruption occurs, and a quick recovery can be realized.
[0070]
Note that writing data to the nonvolatile latch circuit is not necessarily performed every logic cycle. Data may be recorded only when the standby mode is entered, that is, only immediately before Hvt-Tr1 and Hvt-Tr2 are turned off. In this case, it is necessary to detect the trigger for entering the standby mode and perform a necessary recording operation.
[0071]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Is possible.
[0072]
For example, the nonvolatile latch circuit exemplified in this embodiment is merely an example. For example, a nonvolatile latch circuit as shown in FIG. 7 can be used. FIG. 7 is a circuit diagram showing another example of a nonvolatile latch circuit applicable to the present invention. The nonvolatile latch circuit shown in FIG. 7 has MTJ1 and MTJ2, and at the time of data writing, the write current to MTJ1 and MTJ2 flows by setting the data write control signal DW to the high level. The write current flows in either the direction of the arrow indicated by MTJ1 or the direction of the arrow indicated by MTJ2 according to the output of the register 20. Thereby, the output state of the register 20 can be recorded. To read data, the data restore control signal DRS is set to a low level, the magnitude relationship between the resistance values of MTJ1 and MTJ2 is detected by the amplifier / latch circuit 21, and this is amplified to a logic level and latched. The output of the amplifier / latch circuit 21 is fed back to the register 20, and the register value is set to that value.
[0073]
In the above-described embodiment, an example in which both virtual power supply lines v-Vdd and v-Vss are described has been described. However, as shown in FIG. 8, there is no v-Vdd and Hvt-Tr1, and power is supplied directly from Vdd. A configuration in which a potential is supplied may be used. In this case, it goes without saying that the standby state is realized by blocking Hvt-Tr2. Conversely, as shown in FIG. 9, there may be a configuration in which there is no v-Vss and Hvt-Tr2, and a power supply potential (ground potential) is directly supplied from Vss. In this case, of course, the standby state is realized by cutting off Hvt-Tr1.
[0074]
Further, the number of data write lines DWL is not necessarily one, and may be constituted by a plurality. In this case, the MTJ free layer can be magnetized by the combined magnetic field formed by a plurality of data write lines, and the write current can be reduced.
[0075]
Further, when the nonvolatile latch circuits are provided in all the nodes that need to be recorded, the high threshold voltage transistors Hvt-Tr1, 2 and virtual power supply lines v-Vdd, v-Vss can be omitted. is there. In this case, voltage supply to Vdd and Vss is cut off in the standby state.
[0076]
The latch circuit of the node that does not require recording need not be the above-described nonvolatile latch circuit. That is, a volatile latch circuit and a nonvolatile latch circuit can be mixed in the logic circuit of the semiconductor device.
[0077]
In addition, a scan chain is configured by connecting the above-described nonvolatile latch circuits in series, a buffer is provided in the signal output unit, a signal output may be only one of OUT or OUT bar, an input signal IN or The other input signal can be generated from one of the IN bars using an inverter, the p-channel MOSFET and the n-channel MOSFET are replaced with a slight change in wiring, or a p-channel MOSFET is used instead of the n-channel MOSFET. Needless to say, other changes are possible.
[0078]
In the above-described embodiment, the example in which the data write line DWL is arranged in an electrically insulated state from the MTJ has been described. However, the data write line DWL may be formed in contact with the MTJ. Wiring may be used.
[0079]
Also, the MTJ storage state is exemplified by a binary value of “0” or “1”. An intermediate value may be given to the state of magnetization. However, the magnitude relationship between the resistance values of MTJ0 and MTJ1 is clearly maintained.
[0080]
The material of each member in the above-described embodiment is merely an example. Other materials can be used as long as the predetermined performance can be achieved. For example, the semiconductor material is not limited to silicon, and a compound semiconductor can also be used.
[0081]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones are as follows. That is, in a logic circuit that achieves high-speed operation and low power consumption using an MTCMOS circuit, the latched state in the logic circuit in the standby state can be maintained without deteriorating its original characteristics. Further, the latch state can be maintained in the standby state without impairing the high speed of the logic operation during normal operation. Further, it is possible to realize a logic circuit that realizes quick transition from the normal operation state to the standby state and quick return from the standby state to the normal operation state. Further, by adding a few additional steps to the conventional manufacturing process for these logic circuits, it is possible to provide a manufacturing technique for a semiconductor device that does not substantially increase the process load and increase the cost.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an outline of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a circuit diagram showing an example of a nonvolatile latch circuit.
FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a part of a nonvolatile latch circuit according to an embodiment of the present invention; FIGS.
FIG. 4 is a diagram showing an example of timing for explaining the operation of the nonvolatile latch circuit.
FIG. 5 is a diagram illustrating a result of simulating an operation when a power supply voltage Vdd (v−Vdd) is cut off.
FIG. 6 is an enlarged view of a refresh operation part.
FIG. 7 is a circuit diagram showing another example of a nonvolatile latch circuit applicable to the present invention.
FIG. 8 is a circuit diagram showing an outline of another example of the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a circuit diagram showing an outline of still another example of the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a circuit diagram showing an example of an MTCMOS circuit.
FIG. 11 is a circuit diagram illustrating an example of latch state holding means in the prior art.
FIG. 12 is a diagram illustrating another example of latch state holding means in the prior art.
FIG. 13 is a diagram for explaining still another example of latch state holding means in the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Combination logic circuit, 1s ... Semiconductor substrate, 2 ... Element isolation region, 3 ... Active region, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Semiconductor region, 7, 9 ... Plug, 10 ... Second layer metal Wiring, 12 ... Local wiring, 13 ... Free layer, 14 ... Insulating layer, 15 ... Pin layer, 16 ... Diamagnetic layer, 20 ... Register, 21 ... Amplifier / latch circuit, C1 ... Sense / latch circuit, C2 ... Current generation circuit, D1 ... diode, DATAGET ... control signal, DRS ... data restore control signal, DW ... data write control signal, DWL ... data write line, Hvt-Tr1, Hvt-Tr2 ... high threshold voltage MOSFET (transistor ), IN, IN bar: input signal, INV1, INV2: inverter circuit, M1: first layer metal wiring, M2: second layer metal wiring, M3: third layer metal wiring, M J0, MTJ1 ... tunnel magnetoresistive element, NVL1 to n ... non-volatile latch circuit, OUT, OUT bar ... output, REFRESHN ... control signal, SIG1 ... control signal, Vdd, Vss ... power supply line, v-Vdd, v-Vss ... Virtual power line.

Claims (6)

A first power supply line to which a first voltage is supplied;
A second power supply line to which a second voltage is supplied;
A third power supply line connected to the first power supply line via a first transistor having a first level threshold voltage or a second power supply connected to the first power supply line via a second transistor having a first level threshold voltage. A fourth power line connected to the two power lines;
A circuit configured by a transistor having a second level threshold voltage and driven by a potential difference between the first power supply line and the fourth power supply line or between the third power supply line and the second power supply line;
A non-volatile latch circuit connected to an arbitrary node of the circuit,
The nonvolatile latch circuit includes a first inverter and a second inverter composed of transistors formed on a semiconductor substrate , a first spin valve element, and a second spin valve element or a resistance element. An input of one inverter and an output of the second inverter are connected, an output of the first inverter and an input of the second inverter are connected, and the first inverter is connected between a power supply node and a power supply line. 1 spin valve element is disposed, and the second spin valve element or resistance element is disposed between a power supply node and a power line of the second inverter,
The spin valve element is formed between a plurality of wiring layers formed in an upper layer of the transistor on the semiconductor substrate.
Semiconductor device. A first power supply line to which a first voltage is supplied;
A second power supply line to which a second voltage is supplied;
A third power supply line connected to the first power supply line via a first transistor having a first level threshold voltage;
A fourth power line connected to the second power line via a second transistor having the first level threshold voltage;
A circuit configured by a transistor having a second level threshold voltage and driven by a potential difference between the third power supply line and the fourth power supply line;
A non-volatile latch circuit connected to an arbitrary node of the circuit,
The nonvolatile latch circuit includes a first inverter and a second inverter composed of transistors formed on a semiconductor substrate , a first spin valve element, and a second spin valve element or a resistance element. An input of one inverter and an output of the second inverter are connected, an output of the first inverter and an input of the second inverter are connected, and the first inverter is connected between a power supply node and a power supply line. 1 spin valve element is disposed, and the second spin valve element or resistance element is disposed between a power supply node and a power line of the second inverter,
The spin valve element is formed between a plurality of wiring layers formed in an upper layer of the transistor on the semiconductor substrate.
Semiconductor device. The nonvolatile latch circuit includes a pair of resistance elements in which at least one resistance element is the spin valve element,
3. The semiconductor device according to claim 1, wherein a latch state of the nonvolatile latch circuit is stored as a resistance value magnitude relationship of the resistance element pair.   The semiconductor device according to claim 3, wherein the spin valve element is a tunnel magnetoresistive element.   The semiconductor device according to claim 1, wherein the latch state is recorded in the nonvolatile latch circuit every operation cycle of the circuit.   3. The semiconductor device according to claim 1, wherein recording of the latch state in the nonvolatile latch circuit is performed only immediately before the first transistor and the second transistor are turned off.

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