JP3860022B2 - Binary signal decoding circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for demodulating a digital modulation signal (a binary signal such as an FSK modulation signal).
[0002]
[Prior art]
Conventionally, as shown in FIG. 4, a demodulating circuit for a digital modulation signal has, as shown in FIG. 4, a detection circuit 101 for detecting a modulation signal and extracting a baseband signal, and transmission information from the extracted baseband signal. And a decoding circuit 102 that determines the code of “0” or “1” and decodes the original signal.
[0003]
The decoding circuit 102 is usually configured to compare the extracted baseband signal with a predetermined threshold value V and determine as a code of “0” or “1” depending on whether or not the threshold value is exceeded. .
[0004]
[Problems to be solved by the invention]
However, in the decoding circuit as described above, since the threshold value V is a value fixed to the intermediate value of the pulse amplitude of the baseband signal, the extracted baseband signal is distorted or contains noise. In some cases, a problem that the original signal cannot be correctly decoded due to erroneous determination is likely to occur.
[0005]
For example, in the example of FIG. 4, even if the original signal has a waveform as shown in FIG. 5A, the baseband signal extracted by the detection circuit 101 is like the example shown in FIG. When the waveform is distorted or contains noise or the like, as shown in FIG. 5C, the waveforms N ₁ , N ₂ , N ₃ ,... It is decoded into a signal different from the original signal of (a).
[0006]
Therefore, the present invention provides decoding that is unlikely to cause erroneous determination even when the baseband signal is distorted as in the example shown in FIG. 5B or when the waveform including noise is distorted. It was made for the purpose of providing technology.
[0007]
[Means for Solving the Problems]
A binary signal decoding circuit according to claim 1 of the present invention includes:
An inverting circuit for inverting the polarity of the signal to be decoded;
One of the signal to be decoded or the inverted signal is input, the peak value in the positive or negative direction of the input signal is held, and there is a predetermined difference in the polarity direction opposite to the held peak value A peak holding circuit for inverting the polarity direction for holding the peak value when a signal is input;
Code for determining the sign of the signal to be decoded by comparing the signal to be decoded or the other signal of the inverted signal not input to the peak holding circuit with the peak value held by the peak holding circuit The measure of providing a judgment circuit was taken.
[0008]
Claim 2
The peak hold circuit
Two diodes connected in parallel so as to have opposite conduction directions between the input and output of the peak holding circuit,
And a capacitor connected in parallel to the output unit.
[0009]
[Action]
In the binary signal decoding circuit according to claim 1 of the present invention,
An inverting circuit that inverts the polarity of the signal to be decoded and one of the signal to be decoded or the inverted signal is input, and the positive or negative peak value of the input signal is held and held. A peak holding circuit for inverting the polarity direction for holding the peak value when a signal having a predetermined difference in the polarity direction opposite to the peak value is input, and the peak of the signal to be decoded or the inverted signal Since the other signal not input to the holding circuit is compared with the peak value held by the peak holding circuit, the code determining circuit determines the code of the signal to be decoded. Since the code is always determined with a peak value having a reverse polarity as a threshold value, even if some distortion or noise is included in the waveform of the signal to be decoded, the code is not erroneously determined.
[0010]
In the binary signal decoding circuit according to claim 2,
The peak holding circuit includes two diodes connected in parallel so as to be in opposite conduction directions between an input unit and an output unit of the peak holding circuit, and a capacitor connected in parallel to the output unit. As a result, the function of reversing the polarity direction for holding the peak value when a signal having a predetermined difference is input using the forward voltage drop of the diode is realized.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a binary signal decoding circuit according to the present invention will be described in detail with reference to the drawings showing embodiments thereof.
[0012]
FIG. 1 is a block diagram of a binary signal decoding circuit as the above embodiment, and FIG. 2 is an example of an original signal and a part of signal waveforms.
[0013]
In the figure, reference numeral 1 denotes a detection circuit that detects a received signal S ₁ and extracts a baseband signal S ₂ .
Reference numeral 2 denotes an inverting circuit that inverts the polarity of the baseband signal S ₂ and outputs an inverted signal S ₃ .
[0014]
A peak holding circuit ₃ holds a peak value in the positive or negative direction of the inverted signal S ₃ and outputs the peak value as the peak value signal S ₄ .
[0015]
4 with the base band signal S ₂ and the peak value signal S ₄ is inputted, whether the baseband signal S _2, compares the peak value signal S ₄ as a threshold, it exceeds the peak value signal S ₄ a code decision circuit for outputting positive and negative pulse as decoded signal S ₅ by or.
[0016]
In FIG. 2, signal S ₀ is an original signal before modulation, signal S ₂ is a baseband signal, signal S ₃ is an inverted signal, signal S ₄ is a peak value signal, and signal S ₅ is a decoded signal.
[0017]
In the peak holding circuit 3, when a value having a predetermined difference in the reverse polarity direction with respect to the held peak value is input, the polarity direction for holding the peak value is reversed. For example, when the predetermined difference is set to 6 V, if a value of −2 V or less is input when +4 V is held as the positive peak value, the negative peak value is held from that point. Then, the value at that time is held as the peak value in the negative direction. After that, when a value less than the peak value is input, the negative peak value is updated as needed. When a value greater than the predetermined difference by 6 V or more is input, the polarity is maintained again. The direction is reversed and the peak value in the positive direction is held.
[0018]
In other words, the peak value in the same polarity direction is continuously maintained unless there is a large input change such as when the sign of the baseband signal is inverted, so even if some distortion or noise occurs in the baseband signal. The polarity direction holding the peak value is not reversed. When the sign of the baseband signal is inverted (when a pulse having a reverse polarity direction is input), the polarity direction for holding the peak is inverted.
[0019]
Therefore, the peak holding circuit 3 outputs the peak value in the direction opposite to the baseband signal to the code determination circuit 4 for each pulse of the baseband signal as a threshold value.
[0020]
In the code determination circuit 4, the peak value in the reverse polarity direction is input as a threshold value for each pulse of the baseband signal from the peak holding circuit 3, so that the baseband signal includes some distortion and noise. Even if it is, there is little possibility of misjudgment. In addition, since the amplitude change range in which the code can be determined is widened compared to a method in which the intermediate value of the pulse amplitude is set as a threshold, demodulation with high function is possible.
[0021]
In the above description, an example in which a signal obtained by inverting the baseband signal is input to the peak holding circuit is shown. Conversely, the baseband signal is input to the peak holding circuit as it is, and the sign determination circuit is input. Then, a signal obtained by inverting the baseband signal may be compared with a threshold value output from the peak holding circuit.
[0022]
Next, one embodiment of a binary signal decoding circuit according to the present invention will be described with reference to the circuit diagram.
[0023]
In FIG.
A baseband signal S ₆ output from a detection circuit (not shown) or the like is input to the inverting input terminal of the first operational amplifier circuit 51 after the DC component is removed by the differentiation function by the RC series circuit.
[0024]
The baseband signal S ₆ is inverted from the first operational amplifier circuit 51 and output as the inverted signal S ₇ .
[0025]
The inverted signal S ₇ is input to the inverting input terminal of the second operational amplifier circuit 52, inverted again, and output as the re-inverted signal S ₈ .
[0026]
The reinversion signal S ₈ is input to the input terminal 53 in of the peak holding circuit 53.
[0027]
Between the input terminal 53 _in and the output terminal 53 _out of the peak holding circuit 53, two small-signal silicon diodes D ₁ and D ₂ are connected in parallel with the conduction direction being reversed. The capacitor C is connected between the output terminal 53 _out and the ground G.
[0028]
In the peak holding circuit 53, the forward voltage drop voltage (about 0.6 V) of the silicon diodes D ₁ and D ₂ is used. The forward voltage drop voltage is caused by a junction voltage between a p-type semiconductor and an n-type semiconductor constituting the diode.
[0029]
For example, when the +4 V re-inversion signal S ₈ is input from the second operational amplifier circuit 52 to the input terminal 53 _in of the peak holding circuit 53 in a discharged state where the capacitor C is not charged, becomes the silicon diode D ₁ is conducting state of the forward, the the capacitor C the forward voltage drop voltage (approximately 0.6V) is pulled voltage from the + 4V (+ 3.4 V) is charged is applied.
[0030]
That is, the terminal voltage of the capacitor C is charged, so that 0.6V voltage lower than the re-inverted signal S ₈ is held as the peak value.
[0031]
At this time, since no series resistance is interposed in the capacitor C, the time constant becomes substantially zero (since it does not have an integration function), and charging is completed instantaneously.
[0032]
After that, for example, when the re-inversion signal S ₈ of + 4.5V is input to the input terminal 53 _in of the peak holding circuit 53, the capacitor C is charged with + 3.9V (= + 4.5V−0.6V). The In this way, the peak value is updated.
[0033]
However, for example, + 3.5 V there is no change in the charging voltage of the capacitor C be re-inverted signal S ₈ is input. That is, the order state to the capacitor C + 3.4 V is charged (as re-inverted signal S ₈ to + 4V) discharged from is started, the forward direction of the silicon diode as seen from the capacitor C becomes conductive Therefore, the re-inversion signal S ₈ needs to be +2.8 V (+3.4 V−0.6 V) or less. That is, if the re-inversion signal S ₈ does not become smaller than 1.2 V (0.6 V from the voltage actually charged in the capacitor C) from the held peak value, the peak value is held as it is. It will be.
[0034]
In this way, the peak holding circuit 53 holds the peak value in the positive or negative direction of the input signal, and a signal having a predetermined difference in the polarity direction opposite to the held peak value is input. when the functionality of inverting the polarity direction for holding the peak value is realized, is a peak value signal S ₉ that is held is outputted.
[0035]
The inverted signal S ₇ inverted by the first operational amplifier circuit 51 is input to the inverting input terminal of the third operational amplifier circuit 54 constituting the sign determination circuit, and the non-inverting input terminal of the third operational amplifier circuit 54 is input. The peak value signal S ₉ held by the peak holding circuit 53 is inputted. Therefore, the third operational amplifier circuit 54 determines the sign of the inverted signal S _{7 using} the peak value signal S ₉ as a threshold and outputs the determination signal S ₁₀ .
[0036]
For example, when the inverted signal S ₇ has a positive value and the peak value signal S ₉ has a negative value, the output terminal of the third operational amplifier 54 becomes negative, and the inverted signal S ₇ has a negative value and has a peak. when the value signal S ₉ is a positive value output terminal of the third operational amplifier 54 is the positive.
[0037]
When the determination signal S ₁₀ is input to the inverter circuit 55, when the determination signal S ₁₀ is negative, the digital signal S ₁₁ output from the inverter circuit 55 becomes the low level, the determination signal S ₁₀ is positive In this case, the digital signal S ₁₁ output from the inverter circuit 55 is at a high level, and the digital signal S ₁₁ corresponding to the determined code is obtained.
[0038]
The digital signal S ₁₁ is output as a decoded signal based on the baseband signal S ₆ .
[0039]
The NAND circuit 56 is supplied with a digital signal S ₁₁ as a decoded signal and a control signal S _12, and the control signal S ₁₂ controls whether the digital signal S ₁₁ can be output. It is configured.
[0040]
In the example of FIG. 3, a signal obtained by inverting the baseband signal S ₆ once is input to the third operational amplifier circuit 54 constituting the sign determining circuit, and the signal obtained by inverting the baseband signal S ₆ twice. That is, although a signal in the same state as the original baseband signal is input to the peak holding circuit 53, the inverted signal output from the first operational amplifier circuit 51 may be interpreted as a baseband signal. In this case, the baseband signal is input to the third operational amplifier circuit 54 constituting the sign determination circuit, the inverted signal of the baseband signal is input to the peak holding circuit 53, and the peak value is input to the third operational amplifier. This is input to the circuit 54.
Further, a germanium diode, a Schottky barrier diode, a light emitting diode or the like having a forward voltage drop characteristic different from that of a silicon diode may be used.
[0041]
【The invention's effect】
As described above, according to the binary signal decoding circuit of claim 1,
An inversion circuit, a peak holding circuit, and a sign determination circuit are provided. In the sign determination circuit, a sign is always determined with a peak value having a reverse polarity as a threshold value, so that a waveform of a signal to be decoded has some distortion and noise. Since the code is not misjudged even if it is included, an accurate decoding circuit can be realized.
[0042]
According to the binary signal decoding circuit of claim 2,
The function of inverting the polarity direction for holding the peak value when a signal having a predetermined difference is input by a peak holding circuit including two diodes and a capacitor is realized. A decoding circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a configuration of an embodiment of a binary signal decoding circuit according to the present invention.
FIG. 2 is a diagram showing signal waveforms at various parts of the binary signal decoding circuit;
FIG. 3 is a circuit diagram of an embodiment of a binary signal decoding circuit according to the present invention.
FIG. 4 is a configuration diagram of a conventional binary signal decoding circuit.
FIG. 5 is an explanatory diagram illustrating an example of erroneous determination by a binary signal decoding circuit of a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Detection circuit 2 Inversion circuit 3 Peak holding circuit 4 Sign determination circuit 51 1st operational amplifier circuit (inversion circuit)
52 Second operational amplifier circuit (inverting circuit)
53 Peak holding circuit 54 Third operational amplifier circuit (sign determination circuit)

Claims (2)

An inverting circuit for inverting the polarity of the signal to be decoded;
One of the signal to be decoded or the inverted signal is input, the peak value in the positive or negative direction of the input signal is held, and there is a predetermined difference in the polarity direction opposite to the held peak value A peak holding circuit for inverting the polarity direction for holding the peak value when a signal is input;
Code for determining the sign of the signal to be decoded by comparing the signal to be decoded or the other signal of the inverted signal not input to the peak holding circuit with the peak value held by the peak holding circuit A binary signal decoding circuit comprising: a determination circuit. The peak hold circuit
Two diodes connected in parallel so as to have opposite conduction directions between the input and output of the peak holding circuit,
The binary signal decoding circuit according to claim 1, further comprising a capacitor connected in parallel to the output unit.

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