JP3824624B2 - Liquid crystal display control circuit that compensates drive for high-speed response - Google Patents

Description

  The present invention relates to a control circuit for a liquid crystal display device, and more particularly to a liquid crystal display device which enables high-speed response by adding a correction value to a cell drive voltage to compensate for the drive and further simplifying the circuit configuration for drive compensation. It is to provide a control circuit.

  Liquid crystal display devices are widely used as energy-saving and space-saving display devices. In recent years, the use of a computer as a display device for displaying moving images has been proposed as a display device for televisions for displaying moving images.

  The liquid crystal display panel has a source electrode to which a display driving voltage in accordance with display data is applied, a gate electrode driven at a scanning timing, and a cell transistor and a pixel electrode arranged at the intersecting position thereof. Thus, a desired image display is performed by applying a display driving voltage to the liquid crystal layer between the pixel electrodes to change the transmittance of the liquid crystal.

  When a liquid crystal display panel is used as a display device for a television, for example, it is necessary to display an image of 60 frames per second. For this purpose, the transmittance of the liquid crystal layer within one frame period of about 16 msec is required. The change needs to be completed. Although it is relatively easy to apply the display drive voltage to the source electrode and apply the same voltage between the pixel electrodes within one frame period, the optical characteristics (for example, transmission) of the liquid crystal layer can be achieved within one frame period. It may be difficult to completely change the rate depending on the display image. For example, it takes a relatively long time to change from the state of black display with zero transmittance to the state of intermediate color display with 25% transmittance.

  Depending on the response characteristics of the liquid crystal material, if a liquid crystal material with poor response characteristics is used, it may be difficult to change from a state of zero transmittance to a state of 25% transmittance within one frame period. . Also, depending on the liquid crystal material, the response time for changing from a state of zero transmittance to a certain degree of transmittance may be longer than the response time for changing from a state of 25% transmittance to a higher transmittance. is there. Alternatively, the same problem occurs when the transmittance changes in the opposite direction.

A compensation driving method has been proposed as a method for compensating for the slow response of such a liquid crystal material. In this driving method, the optimum driving level at which the liquid crystal layer can complete the change in transmittance within one frame period is calculated in consideration of the state after driving in the previous frame and the driving level in the current frame. A drive level voltage is applied to the pixel electrode. For example, when the transmittance is changed to 50% in the current frame when the transmittance is zero in the previous frame period, the pixel electrode is not driven with a driving level voltage corresponding to the transmittance of 50%. The pixel electrode is driven with a higher drive level voltage. As a result, even if the response characteristic of the liquid crystal layer is slow, the response of the liquid crystal layer becomes faster with respect to a higher drive voltage, and the target transmittance state can be changed within one frame period. The same applies when changing from a high transmittance to a low transmittance.
Japanese Patent Laid-Open No. 11-125050

  In order to perform the above drive compensation, it is necessary to provide a display drive data generation circuit for converting input image data into display drive data in the control circuit of the liquid crystal display device. The display drive data generation circuit generates compensated display drive data by calculation from the input image data of the current frame and the state data after driving of the previous frame. Such an operation is complicated, and an attempt to execute it with a special logic circuit complicates the operation circuit, resulting in an increase in the cost of the liquid crystal display device.

  Therefore, it is conceivable to provide a conversion table in the display drive data generation circuit that can directly obtain the display drive data. However, such a conversion table requires a relatively expensive circuit such as an SRAM that can be accessed at a high speed, and the conversion table itself causes an increase in the cost of the liquid crystal display device.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a control circuit for a liquid crystal display device that performs drive compensation at a reduced cost.

  Furthermore, another object of the present invention is to provide a control circuit for a liquid crystal display device that can further simplify a display drive data generation circuit for drive compensation.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a display drive data generation for generating display drive data from image data of a current frame and image data of a previous frame in a control circuit of a liquid crystal display device. The display drive data generation unit has a conversion table storing display drive data or correction values corresponding to combinations of image data of the current frame and image data of the previous frame. Further, the conversion table stores the display drive data or the correction value corresponding to the combination of the upper bits of the current frame image data and the upper bits of the previous frame image data, thereby reducing the size of the conversion table. . Further, the display drive data generation unit interpolates the corresponding lower bits by interpolation from a plurality of adjacent display drive data read from the conversion table or its correction value according to the lower bits of the current frame image data. And an interpolation calculation unit for obtaining display drive data or a correction value thereof. When the interpolation calculation unit determines the correction value, the interpolation calculation unit includes a drive level calculation unit that corrects the current frame image data according to the calculated correction value and generates display drive data. Display drive data is supplied to the source driver, and a drive voltage corresponding to the display drive data is applied to the pixel electrode via the source electrode and the cell transistor.

  According to the above control circuit, the conversion table stores the display drive data or its correction value corresponding to the combination of the upper bits of the current frame image data and the upper bits of the previous frame image data. The capacity of the high-speed memory circuit that stores the conversion table can be reduced. As the capacity of the conversion table is reduced, the accuracy of the display drive data or its correction value decreases, so an interpolation circuit is provided to generate display drive data or its correction value with higher accuracy by interpolation. The input image data is corrected accordingly to obtain display drive data.

  Further, in order to achieve the above object, according to the second aspect of the present invention, in the control circuit of the liquid crystal display device, display drive data is obtained from the image data of the current frame and the post-drive state data of the previous frame. A display drive data generation unit that generates display drive data or a correction value for the display drive data corresponding to the combination of the image data of the current frame and the post-drive state data of the previous frame. 1 conversion table. The display drive data generation unit further includes a post-drive state data generation unit that generates post-drive state data of the current frame from the image data of the current frame and the post-drive state data of the previous frame. Then, the post-drive state data generation unit stores a second conversion table storing the post-drive state data of the current frame or the difference value corresponding to the combination of the image data of the current frame and the post-drive state data of the previous frame. Have. Further, the second conversion table stores the post-drive state data of the current frame or a difference value thereof corresponding to the combination of the high-order bits of the current frame image data and the high-order bits of the post-frame drive state data, and the conversion The table size is reduced. Accordingly, in accordance with the lower bits of the current frame image data, a plurality of adjacent post-drive state data read from the second conversion table or the difference values thereof are interpolated after the drive corresponding to the lower bits by interpolation calculation. A first interpolation calculation unit for obtaining state data or a difference value thereof is included. When the first interpolation calculation unit obtains the difference value, the first interpolation calculation unit includes a post-drive level calculation unit that corrects the current frame image data according to the obtained difference value and generates post-drive state data of the current frame. . The post-drive state data is temporarily stored in a frame memory having a storage area corresponding to a pixel in order to obtain a display drive level in the next frame.

  In the second aspect of the present invention, more preferably, as in the first aspect, the first conversion table is a combination of the upper bits of the current frame image data and the upper bits of the post-drive status data of the previous frame. Correspondingly, display drive data or its correction value is stored to reduce the size of the conversion table. Accordingly, the display drive data generation unit converts the plurality of adjacent display drive data read from the first conversion table or its correction value into the lower bits by interpolation calculation according to the lower bits of the current frame image data. A second interpolation calculation unit that obtains the corresponding interpolated display drive data or its correction value is provided. When the second interpolation calculation unit obtains the correction value, the second interpolation calculation unit has a drive level calculation unit that corrects the current frame image data according to the obtained correction value and generates display drive data.

  According to a third aspect of the present invention, there is provided a charge reset driving type liquid crystal display device that applies a driving voltage to a pixel electrode in the first half of a frame period and applies a driving voltage corresponding to a gradation value of zero in the second half of the frame period. The control circuit includes a display drive data generation unit that generates display drive data from the image data of the current frame and the image data of the previous frame, and the display drive data generation unit includes the current frame image data and the previous frame image data. The first conversion table storing the display drive data or its correction value is provided corresponding to the combination. Then, the drive voltage is determined according to the display drive data read from the conversion table or its correction value.

  According to a fourth aspect of the present invention, there is provided a charge reset driving type liquid crystal display device that applies a driving voltage to a pixel electrode in the first half of a frame period and applies a driving voltage corresponding to a gradation value of zero in the second half of the frame period. The control circuit includes a display drive data generation unit for generating display drive data, and the display drive data generation unit corresponds to the combination of the current frame image data and the previous frame drive state data or the display drive data or A first conversion table storing the correction value, and a second conversion table storing post-drive state data of the current frame corresponding to a combination of image data of the current frame and post-drive state data. Then, the drive voltage is determined according to the display drive data read from the first conversion table or its correction value. Further, the post-drive state data of the current frame read from the second conversion table is temporarily stored in the frame memory and used for obtaining data of the next frame.

  In the above third and fourth aspects, in a preferred embodiment, a conversion table in which the capacity size of the first and second aspects of the present invention is reduced can be applied.

  In the third and fourth aspects described above, in a preferred embodiment, when current frame image data having the same gradation is supplied to adjacent pixels, current frame drive data generated for the adjacent pixels is provided. The gradation value is made different by a predetermined gradation value between adjacent pixels.

  In the third and fourth aspects described above, in a preferred embodiment, when current frame image data having a different gradation level is supplied to an adjacent pixel, the gradation level of the current frame image data for the adjacent pixel. An edge filter for emphasizing the edge portion is provided by increasing / decreasing or decreasing / increasing the frequency.

  Embodiments of the present invention will be described below with reference to the drawings. However, the protection scope of the present invention is not limited to the following embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is an overall configuration diagram of a liquid crystal display device according to the present embodiment. The liquid crystal display device shown in FIG. 1 includes a source driver 16 that drives a source electrode with a display drive voltage Vd and a gate driver 18 that drives a gate electrode connected to the gate of a cell transistor. Have Input image data Fi corresponding to a pixel and having a gradation value is supplied from the host computer in synchronization with the dot clock DCLK, and the display drive data generation unit 12 uses the input image data Fi to obtain a gradation value necessary for display drive. Display drive data Fo having The display drive data Fo is obtained in consideration of a drive compensation method described later. The display drive data Fo is supplied to the timing controller 14, serial-parallel converted, and the display drive data Fo for one line is supplied to the source driver 16 at a predetermined timing. This is the digital data processing circuit.

  Further, the source driver 16 has a digital / analog conversion circuit, converts the display drive data Fo of the digital signal into an analog signal, and generates a display drive signal Vd corresponding to the liquid crystal characteristics.

  Further, the liquid crystal display device includes a conversion table ROM 22 that stores conversion table data to be downloaded to a conversion table built in the display drive data generation unit 12, a temperature sensor 24, a frame memory 20 that stores image data of the previous frame, and the like. Have

  FIG. 2 is a diagram for explaining the principle of drive compensation. In FIG. 2A, the horizontal axis indicates the frame period, the vertical axis indicates the transmittance T (64 gradations), which is the optical characteristic of the pixel liquid crystal layer, x in the figure indicates the input image data Fi, and ○ indicates the liquid crystal layer. The state after driving is shown. In FIG. 2B, the horizontal axis indicates the frame period, and the vertical axis indicates the display drive voltage Fo (64 gradations).

  In the example of FIG. 2, the input image data Fi has a gradation value = 0 at frame 0F, a gradation value = 32 at the next frame 1F, a gradation value = 63 at the next frame 2F, and a gradation at the next frame 3F. The value = 0, and the gradation value = 32 in the next frame 4F. In this case, in the frame 1F, the input image data Fi = 32, but considering that the response characteristic of the liquid crystal layer is slow, the display drive data Fo is a gradation value obtained by adding the correction value Δo to the input image data Fi. Set. By adding this correction value Δo, it becomes possible to reach the target value of transmittance T = 32 from the state of transmittance = 0 of the previous frame as close as possible within the period of frame 1F. This is drive compensation.

  In frame 2F, the input image data as the target value is Fi = 63, which is the maximum gradation level. Therefore, the display drive data Fo is set to the drive voltage level “63” of the maximum gradation. As shown in FIG. 2A, in the frame 1F, the transmittance T of the liquid crystal layer does not reach the gradation value of the target input image data, and reaches the transmittance T that is lower by the difference Δp. Further, even in the frame 2F, the transmittance T reaches a lower value by the difference Δp without reaching the target value.

  Next, in the frame 3F, the input image data as the target value is Fi = 0 and the minimum gradation level. Also in this case, a correction value cannot be added to the display drive data Fo, and the minimum gradation drive voltage = 0 is set. As a result, within the period of the frame 3F, the transmittance of the liquid crystal layer does not reach the minimum gradation, but only becomes a level higher than the minimum gradation level by the difference Δp.

  Next, in frame 4F, the input image data that is the target value is Fi = 32. In this case, the display drive level Fo is set higher by the correction value Δo than the level of the input image data Fi. However, unlike the case of the frame 1F where the liquid crystal layer state (transmittance T = 0) in the previous frame changes to the transmittance T = 32, in the frame 4F, the transmittance T = 16 to the transmittance = Change to 32 and little change. Accordingly, the correction value Δo in the frame 4F is set smaller than the correction value Δo in the frame 1F.

  As described above, according to the drive compensation method, the display drive data Fo corresponding to the liquid crystal drive voltage is set according to the relationship between the input image data Fi of the previous frame and the input image data Fi of the current frame. If the difference between the two is large, the correction value Δo is correspondingly added to the input image data Fi of the current frame.

  Further, in the case of a liquid crystal layer having a slow response characteristic, there is a case where the level of the input image data Fi of the target value is not reached within one frame period even if the correction value is added to the drive level as described above. In that case, instead of the input image data Fi of the previous frame, the data Fp of the liquid crystal state (transmittance T) after driving the previous frame is used. That is, the display drive data Fo in the current frame is set according to the post-drive state data Fp of the previous frame and the input image data Fi of the current frame, and a drive voltage is generated accordingly.

  In order to execute such a method, it is necessary to temporarily store the post-drive state data Fp in the memory in order to calculate the display drive data Fo for the next frame. It is necessary to obtain post-drive state data Fp in the frame. This calculation is performed by the display drive data generation unit 12 of FIG. The display drive data generation unit 12 has a correction value conversion table and a difference value conversion table as reference tables in order to perform calculations at high speed. The display drive data generation unit 12 stores the table data in the conversion table ROM 22 in two conversion tables. Download table data. In that case, the optimum table data is selected and downloaded according to the detected temperature from the temperature sensor 24 or the frequency of the vertical synchronization signal, if necessary.

  FIG. 3 is a configuration diagram of the display drive data generation unit 12 in the present embodiment. In the figure, the input image data of the current frame (nth) is nFi, the display image data of the current frame is nFo, the post-drive status data of the current frame is nFp, and each data of the previous frame (n-1) Are (n-1) Fi, (n-1) Fo, and (n-1) Fp. The display drive data generation unit 12 includes a drive level correction value conversion table 42 and a post-drive level difference value conversion table 32 for drive compensation. These tables 42 and 32 have correction values and difference values corresponding to combinations of input image data nFi of the current frame and post-drive state data (n−1) Fp of the previous frame.

  FIG. 4 is a diagram illustrating an example of the correction value conversion table. As shown in the figure, the correction value conversion table stores the drive level correction value Δo for the combination of the post-drive state data (n−1) Fp of the previous frame and the input image data nFi of the current frame. In this example, the post-drive state data (n−1) Fp of the previous frame and the input image data nFi of the current frame are both 64-gradation (6 bits) data.

  For example, the post-drive state data (n-1) Fp of the previous frame is 0/63 (63 gradation levels 0), while the input image data nFi of the current frame is 8/63 (63 gradation levels 8). If so, the correction value Δo = 11. Therefore, the level obtained by adding the correction value Δo to the input image data nFi is the display drive data nFo = 19/63. Similarly, if the image data nFi of the current frame is 32/63, the correction value Δo = 20 and the display drive data nFo = nFi + Δo = 32 + 20 = 52/63.

  Conversely, when the post-drive status data (n-1) Fp of the previous frame is the highest level of 63/63, the correction value Δo is negative, and the display drive data nFo is corrected more than the input image data nFi. The level becomes higher by the value Δo. If the post-drive status data (n-1) Fp of the previous frame is 32/63, the correction value Δo is negative if the current frame image data nFi is lower than 32/63, and positive if it is higher than 32/63. It has become.

  When the image data Fi of the current frame is at the minimum and maximum levels of 0/63 and 63/63, correction values cannot be added respectively, and the display drive data nFo remains at the level of the input image data nFi. .

  FIG. 5 is a diagram illustrating an example of the difference value conversion table. This table stores the drive level difference value Δp for the combination of the post-drive state data (n−1) Fp of the previous frame and the input image data nFi of the current frame. Also in this example, the post-drive state data (n−1) Fp of the previous frame and the input image data nFi of the current frame are both 64-gradation (6 bits) data.

  As shown in this figure, when the image data nFi of the current frame is 0/63, the difference value Δp increases as the level of the post-drive state data (n-1) Fp of the previous frame increases, and the current frame drive The level of the rear state is a level that does not reach the target value. That is, it is in a state where the frame 2F has shifted to 3F in FIG. On the contrary, when the image data nFi of the current frame is 63/63, the lower the level of the post-drive state data (n-1) Fp of the previous frame, the larger the difference value Δp becomes. The level is less than the target value.

  FIG. 6 is a graph showing a correction value conversion table. This graph shows correction values for nine types of post-drive data (n−1) Fp of the previous frame, with the correction value Δo of the correction value conversion table of FIG. 4 as the vertical axis and the image data nFi of the current frame as the horizontal axis. It is a plot. This graph makes it easy to understand the correction value settings.

  7 to 9 are diagrams showing display drive data nFo obtained by adding the correction value of FIG. 6 to the image data nFi of the current frame. That is, the broken lines in FIGS. 7 to 9 indicate the image data nFi of the current frame, and the solid lines indicate the display drive data nFo of the current frame. As shown in FIG. 7A, in order to display the current frame image data nFi from the 0/63 level of the previous frame, the display drive data generation unit 12 sets the drive level nFo as shown by the solid line. Generated. In this case, the correction value Δo is always positive. Conversely, as shown in FIG. 9 (I), in order to display the current frame image data nFi from the 63/63 level of the previous frame, the drive level nFo as shown by the solid line is generated.

  Returning to FIG. 3, the configuration of the display drive data generation unit 12 will be further described. The display drive data generation unit 12 receives the input image data nFi and the dot clock CCLK, and generates a combined signal S1 of the post-drive state data of the previous frame and the image data of the current frame for referring to the conversion tables 32 and 42. An input image data conversion unit 30 is included. Further, the display drive data generation unit 12 uses the correction value conversion table 42, the difference value conversion table 32, and the correction value Δo and the difference value Δp read from these conversion tables to obtain a high-precision correction value Δo by interpolation. Interpolation calculation units 34 and 44 for obtaining the difference value Δp, and calculation units 36 and 46 for adding the correction value Δo and the difference value Δp to the current frame image data nFi. Then, the DRAM controller 38 supplies read and write commands and addresses to the two frame memories 20A and 20B, and the data switching unit 40 switches between the two frame memories 20A and 20B.

  The frame memories 20A and 20B store the post-drive state data (n−1) Fp of the previous frame on one side and the post-drive state data nFp of the current frame on the other side. When generating the display drive data, the memory controller 38 reads the post-drive state data (n−1) Fp of the previous frame from one frame memory and supplies it to the input image data conversion unit 30. The post-drive state data nFp of the current frame obtained by the calculation unit 36 is written in the other frame memory.

  In the present embodiment, in order to reduce the capacity of the SRAM in which the correction value conversion table 42 and the difference value conversion table 32 are stored, the reference combination data S1 is the post-drive data (n−1) of the previous frame. Each is a combination of upper bits of Fp and current frame image data nFi. For example, if each data (n-1) Fp, nFi is 6 bits (64 gradations), in this example, the combination of the upper 3 bits is the reference data. In that case, as shown in FIG. 4, the correction conversion table 42 stores 8 × 8 = 64 correction values Δo. Similarly, the difference value conversion table 32 also stores 8 × 8 = 64 difference values Δp as shown in FIG. Therefore, the case of the combination of the post-drive data (n-1) Fp of the previous frame of 64 gradations and the current frame image data nFi (= 64 × 64 = 4096) and the SRAM used for the conversion tables 32 and 42 The capacity can be reduced to 1/64.

  As described above, as the capacities of the conversion tables 42 and 32 are reduced, the accuracy of the correction value Δo and the difference value Δp read from the respective conversion tables is reduced. Therefore, the display drive data generation unit 12 includes a correction value interpolation calculation unit 44 that performs interpolation calculation according to a combination of lower bits of the post-drive data (n-1) Fp of the previous frame and the current frame image data nFi, and a difference value correction. And an arithmetic unit 34. The interpolation calculation units 34 and 44 are supplied from the input image data conversion unit 30 with the combination S2 of the lower 3 bits of the post-drive data (n-1) Fp of the previous frame and the current frame image data nFi, respectively. A correction value and a difference value for data between 32 and 42 grid points are obtained by linear interpolation.

  And it has the drive level calculating part 46 and the post-drive data calculating part 36 which add correction value (DELTA) o and difference value (DELTA) p calculated | required by the interpolation calculating parts 44 and 34 to the present frame image data nFi. The drive level calculator 46 obtains the display drive data nFo of the current frame by the calculation formula shown in the figure and outputs it to the liquid crystal panel side. Further, the post-drive level calculation unit 36 obtains the post-drive data nFp of the current frame by the calculation formula shown in the figure, and writes it into the one frame memory 20B via the data switching unit 40. The written post-drive data nFp is read as post-drive data of the previous frame in the next (n + 1) th frame, supplied to the input image data conversion unit 30, and the (n + 1) th frame. This is used to generate display drive data and post-drive data.

  Only the upper bits of the post-drive data nFp may be written in one frame memory 20B. In this case, the upper bits of the post-drive data are included in the upper bit combination signal S1 to the conversion tables 32 and 42, but are not included in the lower bit combination signal S2 to the interpolation calculation units 34 and 44. Accordingly, in this case, the interpolation calculation units 34 and 44 perform the interpolation calculation according to only the lower bits of the image data nFi of the current frame.

  If the state after driving in the previous frame (n-1) F is a state of transparency T = 0/63, and the input image data nFi is 20/63 in the next frame 1F, the display driving data generation unit 12 The operation of will be described.

  As an initial state, the first frame memory 20A stores 6-bit post-drive data (n-1) Fp = 0/63 of the previous frame. Therefore, 6-bit input image data nFi = 20/63 is input. The DRAM controller 38 reads the post-drive data (n-1) Fp = 0/63 of the previous frame from the first frame memory 20A, and the data is sent to the input image data conversion unit 30 via the data switching unit 40. Supplied. The input image data converter 30 generates upper bit combination data S1 for referring to the conversion tables 32 and 42 from the image data nFi of the current frame and the post-drive data (n-1) Fp of the previous frame. In this case, as shown in the conversion table of FIG. 4, for nFi = 20/63, (n−1) Fp = 0/63, the correction value is given to the lattice point on the conversion table corresponding to these combinations, Since there is no difference value data, it is necessary to read out data of a plurality of grid points adjacent to the grid point, for example, four points. Therefore, for nFi = 20/63 and (n−1) Fp = 0/63, the input image data conversion unit 30 as (n−1) Fp & nFi = ( 00,16), (00,24), (08,16), (08,24) are generated. The upper bit combination data is represented by data of 64 gradations for convenience of explanation, but in actuality, data of 3 bits (8 gradations) is combined.

The next correction value Δo and difference value Δp are read from the correction value conversion table 42 and the difference value conversion table 32 in correspondence with the upper bit combination data S1.
Δo: (00,16) = 22, (00,24) = 23, (08,16) = 12, (08,24) = 16 Δp: (00,16) = − 4, (00,24) = − 3, (08,16) = − 1, (08,24) = 0 Next, the interpolation calculation units 44 and 34 calculate nFi = 20/63, (n− 1) A highly accurate correction value and difference value corresponding to Fp = 0/63 are obtained by interpolation calculation. For this purpose, the input image data conversion unit 30 generates the lower bit combination data S2 of nFi = 20/63, (n−1) Fp = 0/63, and supplies it to the interpolation calculation units 44 and 34. That is, the lower-order bit combination data S2 is (n-1) Fp & nFi = (0, 4) as shown in the figure. As a result, the correction value interpolation calculation unit 44 calculates Δo = [[{22 × (8-4) + 23 × 4} / 8] × (8-0) + [{12 × (8-4) + 16 × 4} /8]×0]÷8=22.5≒23Δp=[[{(-4)×(8-4)+(-3)×4}/8]×(8-0)+[{(-1) × (8-4) + 0 × 4} / 8] × 0] ÷ 8 = −3.5 ≒ −4 is calculated. This interpolation calculation is performed by linear interpolation calculation.

  Next, the drive level calculator 46 adds the correction value Δo = 23/63 and the image data nFi = 20/63 of the current frame to calculate display drive data nFo = 43/63. Similarly, the post-drive level calculation unit 36 adds the difference value Δp = −4 / 63 and the image data nFi = 20/63 of the current frame to obtain post-drive state data (n−1) Fp = 16/63. calculate. The display drive data nFo is supplied to the timing controller 14 in FIG. 1 and converted into a drive voltage by the source driver 16. The post-drive state data (n−1) Fp is written into the second frame memory 20B.

  As described above, since the capacity of the conversion table 42 for converting the input image data into the display drive data in order to adopt the drive compensation method is reduced by lowering the bit of the reference data, the interpolation calculation unit is correspondingly provided. 44 is provided to prevent a decrease in accuracy.

  Further, the data stored in the conversion table 42 is not the display drive data itself but the correction value Δo for the input image data. If it is a correction value, as shown in FIG. 4R> 4, the required number of gradations is reduced, so that the number of bits of data stored in the conversion table can also be reduced. Thereby, the SRAM capacity of the conversion table can be further reduced. Of course, the data in the conversion table 42 can be used as display drive data (data obtained by adding a correction value to the input image data). In that case, the drive level calculation part 46 becomes unnecessary. Whether the data in the conversion table 42 is to be a correction value or display drive data is determined by comparing the effect of reducing the SRAM capacity of the conversion table with the effect of providing the drive level calculation unit.

  If the response characteristic of the liquid crystal layer is slow, as described above, the target transparency may not be reached within the frame period even if drive compensation is performed. In that case, it is necessary to consider the state of transparency after driving the liquid crystal layer. Therefore, in this embodiment, the difference value conversion table 32 is provided, and the interpolation calculation unit 34 is provided. The difference value conversion table 32 also reduces the number of bits of reference data to reduce the table capacity. Further, when the data in the difference value conversion table 32 is not the difference value but the post-drive state data nFp itself is stored, the post-drive level calculation unit 36 becomes unnecessary.

  Also for the conversion table 32, post-drive state data can be stored instead of the difference value. In this case, the post-drive level calculation unit 36 is not necessary.

  In the preferred embodiment, the display drive data generator 12 is composed of an ASIC. By reducing the capacity of the SRAM constituting the conversion tables 42 and 32, the number of peripheral circuit gates required for the SRAM can be greatly reduced, and the number of SRAM gates can be saved.

  FIG. 10 is a diagram illustrating a configuration example of the input image data conversion unit 30. A decoder 302 is provided in the input image data conversion unit 30, and the decoder 302 uses the input image data nFi and the post-drive data (n-1) Fp of the previous frame as an address of the conversion table 42 to be referred to. , Combined data S1 ((n-1) Fp & nFi) is generated.

  FIG. 11 is a diagram illustrating another configuration example of the input image data conversion unit 30. In this example, the decoder 304 generates an 8-bit (256 gradations) output from 6-bit input image data nFi and 6-bit post-drive data (n−1) Fp. Furthermore, an OR gate 306 is provided for bundling a plurality of outputs in a region where the fluctuation of the correction value Δo and the difference value Δp is small among the 256 outputs S1-0 to S1-255. That is, in an area where the change in the conversion table data is large, the data is stored with a high resolution, and in an area where the change is small, the data is stored with a thinned resolution. Thereby, the capacity of the conversion table can be reduced, and the accuracy of the generated correction value and difference value can be increased.

[Second Embodiment]
As a driving method of a liquid crystal display device, CR driving has been proposed in order to improve moving image characteristics of images. In CR (Charge and Reset) driving, a driving voltage is applied to the pixel electrode in the first half of the frame period, and the driving voltage is set to zero in the second half, thereby displaying a certain portion of the frame period in black. As a result, it has been reported that the motion of the video looks smooth. In general, the duty ratio is set to be 50% or less. Therefore, in order to perform CR driving, the liquid crystal layer must be capable of high-speed response. When the frame period is 16 ms, a response speed of less than 8 ms is required, and the applied liquid crystal layer material is limited.

  In the second embodiment, a drive compensation method is adopted for CR driving so that this CR driving can be applied to a medium-speed liquid crystal layer having a response speed of about 20 ms. That is, the display drive data of the current frame is obtained from the post-drive data of the previous frame and the image data of the current frame and supplied to the panel driver, and the current frame is calculated from the drive data of the previous frame and the image data of the current frame. Is obtained and stored in the frame memory. Each calculation is speeded up by referring to the conversion table. More preferably, the data for referring to the conversion table is reduced in bit to reduce the capacity of the conversion table.

  FIG. 12 is a diagram for explaining CR driving in the present embodiment. FIG. 12A is a diagram showing a change in CR drive waveform (broken line) and liquid crystal transmittance when a high-speed response liquid crystal layer is used. In this example, for the sake of simplicity, display image data of five gradations is used. It is assumed that the display image data is 0 in the first frame 0F, and the display image data is changed to 3, 5, and 3 in the subsequent frames 1F, 2F, and 3F. The driving pulse corresponding to the display image data “3” is applied to the first half of the frame 1F, and the driving voltage is reset to zero in the second half. Accordingly, the transmittance of the liquid crystal layer reaches the target transmittance in the first half and returns to zero (black) in the second half. The same applies to frames 2F and 3F. Since it has a high-speed response characteristic, the target transmittance can be reached in half the frame period, and the transmittance can be returned to zero in the other half.

  FIG. 12B shows changes in the CR drive waveform and the liquid crystal transmittance when a liquid crystal layer having a medium speed response characteristic is used. Also in this example, the input image data changes to 0, 3, 5, and 3 in frames 0F, 1F, 2F, and 3F. In frame 1F, the liquid crystal layer cannot sufficiently complete the response with the drive pulse in the first half of the frame period, resulting in insufficient response B1, and the liquid crystal layer is sufficiently reset even with the reset pulse in the second half of the frame period. Insufficient response B2 occurs without being completed. In frame 2F, since the drive level is the maximum “5”, a large remaining response B3 occurs at the time of reset. If a drive pulse corresponding to the image data “3” is applied from the post-drive state B3 in the next frame 3F, this causes an excessive response B4.

  In this way, the CR drive system has a drive voltage application period and a discharge period that achieve the target transmittance within a period of one frame, and the liquid crystal layer with medium speed response characteristics causes insufficient response or excessive response. To do.

  Therefore, in the present embodiment, as shown in FIG. 12C, the drive level is driven in the current frame from the liquid crystal state after reset of the previous frame (post-drive data) and the image data of the current frame. The level and the post-drive data indicating the liquid crystal state after reset are generated. In the example shown in the figure, when the input image data is “3” in the frame 1F, the display drive level is set to “4”. As a result, the transmittance of the liquid crystal reaches the target value by the end of the drive pulse (C1 in the figure). However, at the end of resetting, a residual response occurs (C2 in the figure), and it is not completely black. Then, due to the remaining response (C4 in the figure) at the end of the reset of the frame 3F, the drive level in the frame 4F is set lower than the target value even though the input image data is “3”. As a result, no excessive response occurs at the end of the drive pulse (C5 in the figure).

  In the second embodiment, the display drive data generation unit 12 shown in FIG. 3 is provided to perform CR drive. In the display drive data generation unit 12, in the case of CR drive, the correction value conversion table 42, the correction value interpolation calculation unit 44, and the drive level calculation unit 46 are the same as those in the first embodiment. In the second embodiment, the difference value conversion table 32 stores the remaining response data at the end of reset and outputs the remaining response data. Then, highly accurate response remaining data is generated by the interpolation calculation unit 34. This remaining response data is a kind of post-drive state data Fp.

  In the second embodiment, the post-drive level calculation unit 36 is unnecessary, and the remaining response data (post-drive state data) obtained by the interpolation calculation unit 34 is one of the frame memories 20A and 20B. And is used to obtain display drive data for the next frame.

  As shown in FIG. 12, when the drive compensation method is adopted in the CR drive method, even in the case of the same display image data “3”, the drive pulses are different in the frames 1F and 3F, and the transmittance of the liquid crystal layer responding thereto is The changes are also different. FIG. 13 is a waveform diagram showing in detail the optical response of the liquid crystal layer when the same display image data is driven. In the figure, the solid line represents the optical response waveform of the frame 1F in FIG. 12C, and the broken line represents the optical response waveform of the frame 3F.

  Thus, even with the same display image data, the optical response waveform of the liquid crystal layer varies depending on the history of the pixels. Such a phenomenon causes a pseudo contour when the image data of the same gradation level is supplied to adjacent pixels, because the transmittance differs from pixel to pixel.

  FIG. 14 is a diagram for explaining the pseudo contour and the diffusion processing. FIG. 14A shows a pixel region of 4 rows and 3 columns. The upper six pixels are displayed with the solid line optical response (a) in FIG. 13, and the lower six pixels are displayed with the broken line optical response (b). In this case, a pseudo contour is generated at the boundary between the two groups of pixel regions due to the difference in optical response. Such a pseudo contour causes a reduction in image quality.

  Therefore, in the present embodiment, as shown in FIG. 14B, diffusion processing is performed to increase or decrease the gradation level by a certain minute value between adjacent pixels even for the same input image data. In particular, this diffusion process is preferably performed at the boundary portion where the optical response is different. In order to perform the diffusion processing, the input image levels of adjacent pixels are compared, and if they are the same, the display drive data level is subjected to plus / minus processing by a minute value at random or under a certain rule. Thereby, it is possible to prevent the pseudo contour from appearing clearly.

  As this diffusion process is performed, it is expected that the outline of the image to be displayed will be blurred. Therefore, in a preferred embodiment, an edge filter is provided corresponding to performing the diffusion processing, and processing for enhancing the edge of the contour portion of the image is performed.

  FIG. 15 is a control circuit diagram provided with an edge filter and a diffusion processing unit. FIG. 15A shows the entire control circuit, FIG. 15B shows the edge filter, and FIG. 15C shows the diffusion processing unit. FIG. 16 is a diagram illustrating data processed by the edge filter and the diffusion processing unit. The edge filter and the diffusion process will be described with reference to both drawings.

  The edge filter 50 is provided in the previous stage of the display drive data generation unit 12, and detects a significant change in the gradation level of the input image data Fi and performs a process of emphasizing the level before and after the change. The diffusion processing unit 52 is provided in the subsequent stage of the display drive data generation unit 12 and detects adjacent pixels having the same level of the input image data Fi from the generated drive data Fo, and detects them. Increase or decrease the display drive level Fo of the pixel by a minute value.

  The edge filter circuit of FIG. 15B includes delay flip-flops 54 and 56 that shift input image data Fi, an edge detection circuit 58 that compares the outputs of both flip-flops, and an addition / subtraction command bit S58 from the edge detection circuit. There are provided delay flip-flops 60 and 62 for shifting, and an addition / subtraction circuit 64 for adding / subtracting the enhancement level to / from the input image data Fi by the edge detection signal S59 and the addition / subtraction command bit S58 from the edge detection circuit.

  As an example, it is assumed that the input image data changes to gradation levels “10”, “20”, and “10” as shown in FIG. Since the gradation levels are greatly different between the edges E1 and E2, the edge detection circuit 58 detects that this timing is the edge of the image. When the level of the input image data is changed from the low level to the high level, the edge detection circuit 58 sets the edge detection signal S59 to the activation level, and the addition / subtraction command bit S58 is sequentially set to minus “0” in synchronization with the activation. , Plus “1”. These addition / subtraction command bits S58 are shifted by the delay flip-flops 60, 62 and supplied to the addition / subtraction circuit 64.

  The adder / subtractor circuit 64 subtracts a predetermined value “5” from the input image data “10” immediately before the edge, adds a predetermined value “5” to the input image data “20” immediately after the edge, and performs edge-enhanced image data. Output Fie.

  Similarly, at the timing of edge E2, since the gradation level changes from a high level to a low level, the edge detection circuit 58 sequentially sets the addition / subtraction command bit S58 to plus “1” and minus “0”. As a result, the addition / subtraction circuit 64 adds the predetermined value “5” from the input image data “20” immediately before the edge, and subtracts the predetermined value “5” from the input image data “10” immediately after the edge, thereby enhancing the edge. Output image data Fie.

  Next, the diffusion processing circuit in FIG. 15C will be described with reference to the waveform diagram in FIG. The diffusion processing circuit includes delay flip-flops 74 and 76 that shift the input image data Fie, a comparator 78 that compares the outputs and detects whether or not they have the same gradation level, and outputs in synchronization with the dot clock DCLK. T-type flip-flop 80 that toggles “0” and “1”, and an exclusive OR circuit that inverts the output S80 of the flip-flop 80 in synchronization with the horizontal synchronization signal Hsync and outputs the addition / subtraction command bit S82 to the adder / subtractor 82 and an adder / subtractor 84 for adding / subtracting a minute value to / from the drive data Fo in accordance with the addition / subtraction command bit S82 in synchronization with the detection signal S78 from the comparator 78.

  As shown in FIG. 16B, when the gradation level of the input image data is constant at “10”, the comparator 78 detects it, and the adder / subtractor 84 adds a minute value “1” for each pixel.・ Decrease. In the next display line, the addition / subtraction command bit S82 is inverted to the reverse pattern. Therefore, the adder / subtractor 84 increments or decrements the minute value “1” for each pixel. As a result, the drive data Fod subjected to the diffusion processing has a level in which the gradation level is diffused as shown in FIG.

  Returning to FIG. 1, the control circuit of the liquid crystal display device of the present embodiment has a temperature sensor 24. The temperature sensor 24 is used for detecting the temperature in use and downloading an optimal conversion table from the conversion table ROM. The display drive data generation unit 12 counts the vertical synchronization signal, downloads an optimum conversion table corresponding to the temperature information from the temperature sensor at regular intervals from the ROM, and expands it in the built-in SRAM. . As a result, the drive compensated drive data nFo is obtained from an optimum conversion table that takes into account the response characteristics of the liquid crystal material due to changes in the surrounding environment.

  Specifically, the higher the detected temperature, the faster the response speed of the liquid crystal layer, so the absolute value of the correction value in the correction value conversion table is at a relatively low level. Also, the lower the detection temperature, the slower the response speed of the liquid crystal layer, so that the absolute value of the correction value in the correction value conversion table becomes a relatively high level.

  Further, the display drive data generation unit 12 monitors the frequency f of the vertical synchronization signal Vsync. Then, an optimal conversion table is downloaded from the ROM according to the detected frequency and expanded in the built-in SRAM. For example, when the frequency f is high, the frame period is shortened, so that the absolute value of the correction value in the conversion table is relatively high. On the other hand, when the frequency f is low, the frame period becomes long, so that the absolute value of the correction value in the conversion table becomes relatively short.

  The exemplary embodiments are summarized as follows.

  (Supplementary Note 1) The control circuit of the liquid crystal display device includes a display drive data generation unit that generates display drive data from the image data of the current frame and the image data of the previous frame, and the display drive data generation unit A conversion table storing display drive data or a correction value corresponding to a combination of image data of the current frame and image data of the previous frame, and the conversion table includes upper bits of the current frame image data and the previous frame The display drive data or the correction value thereof is stored corresponding to the combination of the upper bits of the image data, and the display drive data generation unit converts the correction value according to the lower bits of the current frame image data. From the adjacent display drive data read from the table or its correction value, the lower bits are interpolated by interpolation. The control circuit of the liquid crystal display device characterized by having an interpolation calculation unit which respond to determine an interpolated display drive data or correction values thereof.

  (Supplementary note 2) In Supplementary note 1, the conversion table is grouped in a predetermined range with respect to a combination of the high-order bits of the current frame image data and the high-order bits of the previous frame image data, and corresponds to the grouped unit. A control circuit for a liquid crystal display device, wherein the display drive data or its correction value is stored.

  (Supplementary Note 3) The control circuit of the liquid crystal display device includes a display drive data generation unit that generates display drive data from the image data of the current frame and the post-drive state data of the previous frame, and the display drive data generation unit , A first conversion table storing display drive data or a correction value thereof corresponding to a combination of the image data of the current frame and the post-drive state data of the previous frame, and the display drive data generation unit , A post-drive state data generation unit that generates post-drive state data of the current frame from the image data of the current frame and the post-drive state data of the previous frame, and the post-drive state data generation unit Corresponding to the combination of the upper bit of the image data and the upper bit of the post-drive status data of the previous frame, the post-drive status data of the current frame or its difference value In accordance with the stored second conversion table and the lower bits of the current frame image data, a plurality of adjacent post-drive state data read from the second conversion table or the difference values thereof are converted into the lower bits by interpolation. A first interpolating operation unit that obtains corresponding interpolated post-drive state data or a difference value thereof, and the post-drive state data corresponds to a pixel in order to obtain a display drive level in the next frame. A control circuit for a liquid crystal display device, wherein the control circuit is temporarily stored in a frame memory having a storage area.

  (Supplementary note 4) In Supplementary note 3, the first conversion table corresponds to a combination of the high-order bits of the current frame image data and the high-order bits of the post-drive state data of the previous frame, or the display drive data or its A correction value is stored, and the display drive data generation unit further interpolates from a plurality of adjacent display drive data or correction values read from the first conversion table according to the lower bits of the current frame image data. A control circuit for a liquid crystal display device, comprising: a second interpolation calculation unit that obtains an interpolated display drive data or correction value corresponding to the lower bit by calculation.

  (Additional remark 5) In additional remark 3, said 1st conversion table is grouped in the predetermined range about the combination of the upper bit of the said present frame image data, and the upper bit of previous frame image data, The said grouped unit The control circuit for the liquid crystal display device, wherein the display drive data or the difference value thereof is stored corresponding to the above.

  (Supplementary Note 6) In the supplementary note 1 or 3, the display drive data generation unit further includes a conversion table memory for storing a plurality of sets of the first and / or second conversion tables, and a temperature detection unit. A control circuit for a liquid crystal display device, wherein a conversion table is downloaded from the conversion table memory in accordance with the temperature detected by the temperature detecting means for each period.

  (Additional remark 7) In additional remark 1 or 3, the said display drive data generation part downloads a conversion table from the said conversion table memory according to the frequency of a horizontal synchronizing signal or a vertical synchronizing signal for every predetermined period, It is characterized by the above-mentioned. A control circuit for a liquid crystal display device.

  (Supplementary Note 8) Control of a liquid crystal display device of charge reset driving method in which a driving voltage is applied to the pixel electrode in the first half of the frame period and a driving voltage corresponding to a gradation value of zero is applied to the pixel electrode in the second half of the frame period The circuit has a display drive data generation unit that generates display drive data from the image data of the current frame and the image data of the previous frame, and the display drive data generation unit includes the current frame image data and the previous frame image data. Corresponding to the combination, the first conversion table storing the display drive data or the correction value thereof, and according to the display drive data read from the first conversion table or the correction value thereof, A control circuit for a liquid crystal display device, characterized in that the driving voltage is required.

  (Supplementary Note 9) Control of a charge reset driving type liquid crystal display device in which a driving voltage is applied to the pixel electrode in the first half of the frame period and a driving voltage corresponding to a gradation value of zero is applied to the pixel electrode in the second half of the frame period The circuit includes a display drive data generation unit that generates display drive data, the display drive data generation unit corresponding to the combination of the current frame image data and the previous frame drive state data. A first conversion table storing the correction value, and a second conversion table storing post-drive state data of the current frame corresponding to a combination of the image data of the current frame and the post-drive state data. Then, the drive voltage is determined according to the display drive data read from the first conversion table or its correction value, and the second change is determined. The control circuit of the liquid crystal display device, characterized in that the post driving status data read from the table is temporarily stored in the frame memory.

  (Supplementary note 10) In addition, the current frame display drive generated for the adjacent pixel when the current frame image data having the same gradation is supplied to the adjacent pixel. A control circuit for a liquid crystal display device, comprising: a dispersion processing unit that changes data gradation values by a predetermined gradation value between the adjacent pixels.

  (Supplementary note 11) In addition, when the current frame image data having different gradation levels is supplied to an adjacent pixel, the gradation level of the current frame image data for the adjacent pixel is increased. A control circuit for a liquid crystal display device, wherein an edge filter that decreases or decreases / increases is provided in a stage preceding the display drive data generation unit.

  (Additional remark 12) In Additional remark 8 or 9, said 1st conversion table is grouped in the predetermined range about the combination of the upper bit of said current frame image data, and the upper bit of previous frame image data, and the said grouping is carried out. A control circuit for a liquid crystal display device, wherein the display drive data or a difference value thereof is stored corresponding to each unit.

  (Supplementary note 13) In the supplementary note 8 or 9, the display drive data generation unit further includes a conversion table memory for storing a plurality of sets of the first and / or second conversion tables, and a temperature detection unit. A control circuit for a liquid crystal display device, wherein a conversion table is downloaded from the conversion table memory in accordance with the temperature detected by the temperature detecting means for each period.

  (Additional remark 14) In additional remark 8 or 9, the said display drive data generation part downloads a conversion table from the said conversion table memory according to the frequency of a horizontal synchronizing signal or a vertical synchronizing signal for every predetermined period, It is characterized by the above-mentioned. A control circuit for a liquid crystal display device.

  (Supplementary note 15) A liquid crystal display device comprising: the control circuit according to any one of supplementary notes 1, 3, 8, or 9; and a liquid crystal display panel whose display is controlled by the control circuit.

  As described above, according to the present invention, the response characteristics of the liquid crystal display device can be improved and the image quality in moving image display can be improved.

1 is an overall configuration diagram of a liquid crystal display device according to an embodiment. It is a figure for demonstrating the principle of drive compensation. It is a block diagram of the display drive data generation part 12 in the example of this embodiment. It is a figure which shows an example of a correction value conversion table. It is a figure which shows an example of a difference value conversion table. It is a figure which shows the graph of a correction value conversion table. It is a figure which shows the display drive data nFo calculated | required by adding the correction value of FIG. 6 to the image data nFi of the present frame. It is a figure which shows the display drive data nFo calculated | required by adding the correction value of FIG. 6 to the image data nFi of the present frame. It is a figure which shows the display drive data nFo calculated | required by adding the correction value of FIG. 6 to the image data nFi of the present frame. 3 is a diagram illustrating a configuration example of an input image data conversion unit 30. FIG. 6 is a diagram illustrating another configuration example of the input image data conversion unit 30. FIG. It is a figure for demonstrating CR drive in the example of this Embodiment. It is a wave form diagram which shows in detail the optical response of the liquid crystal layer when the same display image data is driven. It is a figure for demonstrating a pseudo contour and a spreading | diffusion process. FIG. 3 is a control circuit diagram provided with an edge filter and a diffusion processing unit. It is a figure which shows the data processed by the edge filter and the spreading | diffusion process part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Liquid crystal display panel 12 Display drive data generation part 20 Frame memory 42 1st conversion table, correction value conversion table 44 2nd interpolation calculating part, correction value interpolation calculating part 32 2nd conversion table, difference value conversion table 34 1st 1 interpolation calculation unit, difference value interpolation calculation unit

Claims (4)

In a control circuit of a liquid crystal display device of charge reset driving method in which a driving voltage is applied to the pixel electrode in the first half of the frame period and a driving voltage corresponding to a gradation value of zero is applied to the pixel electrode in the second half of the frame period.
A display drive data generation unit for generating display drive data;
The display drive data generation unit includes a first conversion table storing the display drive data or a correction value corresponding to a combination of current frame image data and previous frame drive state data, and image data of the current frame. And a second conversion table storing post-drive state data of the current frame corresponding to the combination of post-drive state data after the previous frame,
The drive voltage is determined according to the display drive data read from the first conversion table or its correction value, and the post-drive state data read from the second conversion table is temporarily stored in the frame memory. A control circuit for a liquid crystal display device, wherein the control circuit is stored. In claim 1 ,
Further, when current frame image data having the same gradation is supplied to an adjacent pixel, the gradation value of the display drive data for the current frame generated for the adjacent pixel is set to the adjacent pixel. A control circuit for a liquid crystal display device, comprising a dispersion processing unit that varies a predetermined gradation value between pixels. In claim 1 ,
Further, when current frame image data having different gradation levels is supplied to an adjacent pixel, an edge filter that increases / decreases or decreases / increases the gradation level of the current frame image data for the adjacent pixel, respectively. A control circuit for a liquid crystal display device, which is provided before the display drive data generation unit. A control circuit according to claim 1 ;
A liquid crystal display device comprising: a liquid crystal display panel whose display is controlled by the control circuit.

Images