JP3800929B2 - Semiconductor package, manufacturing method thereof, and insulating tape substrate for semiconductor package - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a novel technique in which a plurality of electrodes formed on a semiconductor chip and a metal wiring formed on an insulating tape substrate are superposed under heating, pressed with a bonding tool, and subjected to ultrasonic vibration to be metallurgically connected. The present invention relates to a semiconductor package, a manufacturing method thereof, and an insulating tape substrate for a semiconductor package.
[0002]
[Prior art]
Insulating tape substrate with wiring that is electrically connected to the electrodes formed on the semiconductor chip, for example, Tape Automated Bonding (TAB) Bump free to directly connect the inner lead of the tape carrier and the Al electrode formed on the semiconductor element A bonded semiconductor package is disclosed in Japanese Patent Laid-Open No. 5-160202. According to this, as shown in FIG. 17, 21 is a semiconductor element made of silicon, 22 is an electrode made of aluminum, 23 is a protective film, and 24 is a metal inner lead. 25 is a bonding tool, and 26 is a horn.
[0003]
After the inner lead 24 and the bonding tool 25 are arranged above the center portion of the Al electrode 22 formed on the semiconductor element 21, a load is applied to the bonding tool 25 and pressed onto the inner lead 24, and then pressed onto the Al electrode 22 as it is. At this time, the contact portion of the inner lead 24 with the bonding tool 25 is plastically deformed by a pressing force from the bonding tool 25 due to a load applied to the bonding tool 25, and becomes a shape depending on the tip shape of the bonding tool. In this state, ultrasonic vibration is applied, and the inner lead 24 and the Al electrode 22 can be metallurgically joined. The applied ultrasonic frequency is 60 kHz or around 60 kHz. The semiconductor element is heated to about 200 to 250 ° C. on the heating stage because the bonding can be performed satisfactorily.
Japanese Laid-Open Patent Publication No. 10-41357 discloses a tape carrier for a semiconductor device made of soft copper having a Vickers hardness of 130 or less and having an inner lead portion plated with Au.
[0004]
[Problems to be solved by the invention]
The phenomenon of metal-to-metal bonding as described above will be briefly described. After the load is applied, the surface layer of the contact portion of each material is subjected to shear stress and plastically deformed by applying ultrasonic waves. At this time, there is a region where metals having new surfaces with no oxide film or contaminants on the surface are in direct contact with each other, that is, a region where there is no obstacle to interdiffusion of each metal. Since the semiconductor element is heated, the thermal energy and the frictional heat generated by the frictional sliding generated at the contact portion serve as a driving force for atomic diffusion, and the atoms diffuse each other. At this time, an intermetallic compound having a certain thickness grows at the contact portion, and bonding is completed. The larger the intermetallic compound generation region, the better the bonding strength, which is a key factor for improving the reliability of semiconductor components. In order to increase the intermetallic compound generation region, the new surface region may be increased. The key point is the plastic deformation of the inner lead.
[0005]
Conventionally, copper used for the inner lead is hard to be plastically deformed with a Vickers hardness of 100 or more, so the damage to the underlying semiconductor chip increases, and as a result, cracks in the chip, that is, bonding damage may occur, This was one of the factors that lowered production yield. As a countermeasure against this, it has been common to deal with this by increasing the thickness of the gold plating applied to the inner lead surface to about 1.0 to 2.0 μm. This is because gold becomes a cushioning material because it is softer than copper. However, thicker gold plating significantly increases the cost of TAB tape and is not a good idea. On the other hand, when the thin gold plating is used, the bonding strength between the inner lead and the electrode pad is unstable, that is, the variation in strength becomes large, and there is a risk that the bonding reliability cannot be ensured. When the thickness of Au, which is softer than the core copper, is small, the deformation of the lead, particularly the gold-plated portion, when applying ultrasonic vibration is smaller than when the thickness is thick. For this reason, the bonding region formed in the process of deforming the lead is reduced, and the bonding strength may be reduced. Furthermore, the cause of bonding damage depends on the state of the intermetallic compound formed at the joint.
FIG. 18 shows a state in which an intermetallic compound is formed at the interface between the electrode pad and the inner lead. As can be seen from FIG. 18, the intermetallic compound layer is formed preferentially from the outer peripheral portion of the crimping portion. The crimping part is a contact mark of the inner lead formed on the electrode pad formed when the inner lead is bonded to the electrode pad.
FIG. 19 shows a state when bonding damage occurs. The damage is caused from the outer peripheral portion of the pressure-bonding portion, that is, the region where the intermetallic compound is preferentially formed, and it is considered that the intermetallic compound forming region is the starting point. After the formation of the intermetallic compound, when vibration is still applied to the interface of the joint, the intermetallic compound layer pulls the electrode pad in the direction of ultrasonic vibration. For this reason, it is considered that when the ultrasonic vibration is excessively applied, interface peeling easily occurs in the intermetallic compound formation region. Further, when a large amplitude is applied, cracks are likely to occur in the semiconductor material under the intermetallic compound formation region, and damage is caused when it is vibrated excessively.
[0006]
The various problems related to bonding are caused by the fact that copper or copper alloy of the core material of the inner lead is hard and the formation state of the intermetallic compound is local.
Japanese Patent Laid-Open No. 10-41357 discloses that the rolled copper foil of the core material of the inner lead is soft with a Vickers hardness of 130 or less, but does not show that the hardness is 100 or less.
[0007]
An object of the present invention is to solve the above-described problems, a plurality of electrodes formed on a semiconductor chip and a plurality of metal wirings formed on an insulating tape substrate can be bonded damage-free and have high bonding strength. An object of the present invention is to provide a semiconductor package having the same, a manufacturing method thereof, and an insulating tape substrate for semiconductor package.
[0008]
[Means for Solving the Problems]
The present invention includes a plurality of electrodes formed on a semiconductor chip and a plurality of metal wirings formed on an insulating tape substrate mounted on the semiconductor chip. , Frequency 100 kHz or more and amplitude 1.5 μm or less Ultrasonic vibration By crimping by In a directly connected semiconductor package, the metal wiring is made of copper or copper alloy plated with gold, and the copper or copper alloy has its Vickers hardness. 6 0-100, and the thickness of the gold plating is Is 0 . 01-0.8μm Good Preferably, it is 0.1 to 0.5 μm, and at least the connection portion of the connection interface between the metal wiring and the electrode Of the crimped part of The outer periphery and center of Whole Further, an intermetallic compound of a metal constituting the metal wiring and a metal constituting the electrode is formed.
The present invention relates to ultrasonic vibration between a plurality of electrodes formed on a semiconductor chip and a plurality of metal wirings formed on an insulating tape substrate mounted on the semiconductor chip. By crimping by In the method of manufacturing a directly connected semiconductor package, the metal wiring is made of copper or copper alloy plated with gold, and the thickness of the gold plating is 0.01-0.8 μ m And the metal wiring is made of copper or copper alloy plated with gold, and the copper or copper alloy has Vickers hardness. 6 0-10 0 Yes ,load While adding weight, the frequency is 100 kHz or more, preferably 100 to 200 kHz and its amplitude is 1.5 μm or less, preferably 1 μm or more at 100 kHz, 0.5 μm or more at 150 kHz, 0.2 μm or more at 200 kHz, Than Preferably, the interface between the metal wiring and the electrode by the ultrasonic vibration in the lateral direction is 1 to 1.5 μm at 100 kHz, 0.5 to 1.0 μm at 150 kHz and 0.2 to 0.6 μm at 200 kHz. The entire outer peripheral part and central part of the crimped part An intermetallic compound of a metal constituting the metal wiring and a metal constituting the electrode is formed.
[0009]
As a more specific preferable configuration, a plurality of electrodes formed on the functional surface side of the semiconductor chip and a plurality of metal wirings formed on the insulating tape substrate mounted on the functional surface side of the semiconductor chip are used in combination with ultrasonic vibration. In the semiconductor package to be directly connected, the plurality of metal wirings formed on the insulating tape substrate are made of copper or copper alloy plated with gold, and the surface of the plurality of metal wirings formed on the insulating tape substrate The function of the semiconductor chip in a region in which the thickness of the applied gold plating is 0.01 to 0.8 μm and the metal wiring formed on the insulating tape substrate and the electrode formed on the functional surface side of the semiconductor chip are directly connected Intermetalization composed of the metal constituting the metal wiring and the metal constituting the electrode formed on the semiconductor chip at the outer peripheral portion of the electrode formed on the surface side and the central portion of the region. This can be achieved by forming a compound.
[0010]
The semiconductor package of the present invention is formed in the inner lead bonding part even when the Vickers hardness of the copper or copper alloy of the core material of the inner lead is 60 to 100 and the thickness of the gold plating formed on the inner lead surface is 0.01 to 0.8 μm. The intermetallic compound region can be widened and bonding damage can be eliminated. Conventionally, since hard electrolytic copper having a Vickers hardness of about 150 has been used for the inner lead, it differs from the package configuration in which the thickness of the gold plating is 1.0 μm or more in order to reduce bonding damage.
[0011]
In the semiconductor package in which the electrode formed on the semiconductor element and the metal wiring formed on the TAB tape are directly connected together using ultrasonic vibration, the configuration of the metal wiring formed on the TAB tape is gold-plated. Made of copper or copper alloy, and the Vickers hardness of copper or copper alloy of the core portion of the metal wiring formed on the TAB tape is set to 60 to 100, and applied to the surface of the metal wiring formed on the TAB tape. Thickness of gold plating 0.01 ~ 0.8μm Is .
Furthermore, the present invention provides A frequency of 100 kHz or more and an amplitude of 1.5 μm or less Ultrasonic vibration Crimping with In the insulating tape substrate for a semiconductor package in which a metal wiring layer directly connected to an electrode formed in the semiconductor package is formed, the metal wiring is made of gold-plated copper or copper alloy, and the copper or copper Vickers hardness of alloy 60 ~ 100, gold plating is its thickness Is 0 . 01-0.8μm Good Preferably, it is 0.1 to 0.5 μm.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(Example 1)
FIG. 1 is a view showing one configuration of an embodiment of a semiconductor package according to the present invention, and FIG. 2 is a cross-sectional view taken along the line AB in FIG. In the semiconductor chip 1, a plurality of electrode pads 2 are formed on the functional surface side, and a protective film 3 is applied to a region excluding a portion where the electrode pads 2 are formed. A stress buffer layer 4 is formed on the tape substrate 7 on which the inner lead 5 and the wiring are formed. The stress buffer layer 4 on the insulating tape substrate 7 and the protective film 3 provided on the semiconductor chip 1 are bonded, and the inner lead 5 is bonded to the electrode pad 2. The inner lead bonding part 9 has a structure covered with a resin sealant 8 (shown in FIG. 2). The solder ball 6 connected to the wiring that becomes the other end of the inner lead 5 is mounted on a bump land 10 formed on the surface opposite to the surface on which the stress buffer layer 4 of the tape substrate 7 is mounted, and is reflowed. As a result, a cylindrical portion is formed on the ball as shown in the figure, and the bump land 10 is filled with the solder.
[0013]
A wiring pattern (including inner leads 5) is formed by etching using a substrate in which a copper foil having a Vickers hardness of 100 is bonded to an insulating tape made of a polyimide resin film with a resin adhesive, and then joined to the inner leads 5 An insulating tape substrate with 1.5 μm gold plating was prepared. Thereafter, a stress buffer layer using an epoxy resin having an adhesive ability was formed on the tape substrate, and the stress buffer layer and the semiconductor chip were attached and bonded. In this attaching process, the inner leads on the tape substrate side are arranged on the electrode pads of the semiconductor chip. Next, the inner lead on the tape substrate and the electrode pad on the semiconductor chip were joined by inner lead bonding so as to be electrically conductive. The electrode pad 2 is made of Al or Al alloy (Al-based alloy containing a small amount of Si, Si-Cu, Cu). Gold plating is formed on the wiring on the joint side of the inner lead 5 and the surface on the same side.
[0014]
The semiconductor package according to the present invention can be formed for one chip such as a main logic IC, a memory, a logic IC, etc., and a multichip module on which these are mounted. The multichip module is mounted on a ceramic or resin multilayer substrate. According to the present embodiment, it can be made smaller than the conventional one.
[0015]
FIG. 3 is a perspective view showing an inner lead bonding method. FIG. 3 shows only a bonding tool, a horn that holds the bonding tool, and transmits ultrasonic vibrations to the bonding tool, an inner lead, and an electrode portion of a semiconductor chip. 11 is a semiconductor chip, 12 is an electrode pad, 13 is a protective film, 14 is an inner lead, 15 is a bonding tool, and 16 is a horn. In this inner lead bonding process, the inner lead 14 is deformed into an S-shape as shown in the cross section of FIG. 2 by the bonding tool 15 and is dropped onto the electrode pad 12 on the semiconductor chip 11 to use ultrasonic vibration with a frequency of 60 kHz. The inner lead 14 and the electrode pad 12 were connected by the thermocompression bonding method. The protective film 13 is made of PIQ (polyimide) and is cured by heat treatment after coating. Bonding is performed by heating to about 200 to 250 ° C.
[0016]
In order to investigate the influence of the gold plating thickness on the bonding reliability of the inner lead bonding part, the following samples were prepared and examined.
[0017]
A stress buffer layer was attached to the tape substrate in the same manner as above except that an insulating tape substrate having wiring (including inner leads) with a gold plating film thickness of 0.01, 0.1, 0.3, 0.7, 1.0, and 2.0 μm was used. After that, a semiconductor chip was attached. Thereafter, inner lead bonding was performed in the same manner as described above to produce a package having the same structure. For these packages, the bonding strength of the inner lead bonding portion, the frequency of occurrence of bonding damage, and the state of intermetallic compound formation at the bonding portion were investigated.
[0018]
Here, a method for investigating the state of intermetallic compound formation at the joint will be described. First, a sample for which inner lead bonding has been completed is immersed in a molten Sn—Pb eutectic alloy. At this time, the wiring formed on the tape substrate, that is, gold and copper, immediately diffuses into the molten Sn—Pb eutectic alloy, leaving only the intermetallic compound formed on the electrode pad. Since the intermetallic compound remains in the state of being formed at the joint, the formation state can be observed.
[0019]
Figure 4 shows the ultrasonic frequency is 60 kHz, and the thickness of the gold plating film is 0.01, 0.1, 0.3, 0.5, 0.7, 1.0, 1.5,
It is the figure which showed the joint strength change when changing to 2.0 micrometer. However, the ultrasonic frequency applied at the time of inner lead bonding is the same as that of the conventional 60 kHz. It can be seen that when the thickness of the gold plating film is about 0.7 μm to 1.0 μm or more, the strength value is saturated and good bonding is achieved. On the other hand, it can be confirmed that the strength is lowered when the gold plating film is thin (0.5 μm or less). As a result, it can be said that a gold plating film thickness of 0.7 μm or more is necessary to achieve good inner lead bonding at 60 kHz oscillation. In other words, with 60 kHz oscillation, good bonding cannot be achieved with a gold plating film thickness of 0.5 μm or less.
[0020]
FIG. 5 shows the state of intermetallic compound formation at the joint interface of the package having various gold plating thicknesses shown in FIG. It can be seen that the inside of the frame surrounded by the black line is the crimping portion, and the intermetallic compound is preferentially formed from the outer periphery. The blackened area indicates that an alloy layer made of an intermetallic compound was formed. The white part is an unjoined area. As described above, this local intermetallic compound formation easily causes bonding damage. Moreover, it turns out that the intermetallic compound formed in the crimping | compression-bonding part is so rough that gold plating film thickness is thin. If gold (Hv 40-50) softer than copper is thick, the plastic deformation of the plating film at the interface is further promoted, and the intermetallic compound layer is densely formed. However, when the gold plating film is thin, the deformation amount of the gold plating film is small and the intermetallic compound formation state becomes rough as shown in FIG. 5 and the bonding strength is reduced.
[0021]
FIG. 6 shows the compound formation area ratio of the intermetallic compound formed at the joint interface in FIG. As shown in FIG. 7, the compound formation area ratio is obtained by dividing the area S of the compound formation region by the area SA of the crimping part. According to FIG. 6, it can be seen that when the gold plating film thickness is 1.0 μm or more, the area ratio is saturated at about 60%. When the inner lead bonding is performed at 60 kHz, the bonding strength is drastically lowered when the area ratio is less than 60%. Therefore, an area ratio of about 60% is required to achieve good inner lead bonding. From FIG. 4, when the gold plating film thickness is 0.7 μm or more, sufficient bonding strength can be obtained, so that the compound formation area ratio is preferably 50% or more, more preferably 55% or more.
[0022]
Next, the following samples were prepared and examined in order to investigate the effect of ultrasonic vibration applied during inner lead bonding on bondability.
[0023]
After forming a wiring pattern (including inner leads) on copper tape made of polyimide with a Vickers hardness of 100, gold plated with a thickness of 0.01, 0.1, 0.3, 0.7, 1.0, 1.5 and 2.0 μm A substrate was prepared. Gold plating films thinner than 0.01 μm cannot be produced with current technology. Thereafter, a stress buffer layer having an adhesion capability was formed on the tape substrate, and the stress buffer layer and the semiconductor chip were attached and bonded. In this attaching process, the inner leads on the tape substrate side are arranged on the electrode pads of the semiconductor chip. Next, the inner lead on the tape substrate and the electrode pad on the semiconductor chip were joined by inner lead bonding so as to be electrically conductive. Inner lead bonding was performed by the same method as above except that the ultrasonic frequencies were 100 kHz and 170 kHz.
[0024]
FIG. 8 shows the change in bonding strength with respect to the gold plating film thickness of the inner lead when the ultrasonic frequency is 100 kHz and 170 kHz. For comparison, the bonding strength change at 60kHz oscillation is also shown. At ultrasonic frequencies of 100 kHz and 170 kHz, the bonding strength is close to saturation even when the gold plating film thickness is 0.01 μm, which is equivalent to that when the gold plating film thickness is 0.7 μm or more at 60 kHz oscillation. It can be seen that when the ultrasonic frequency is 100 kHz or more, good bonding is possible with a thinner gold plating film thickness than that at 60 kHz oscillation. When the gold plating film thickness is thin, it can be confirmed that the effect of improving the bonding strength at the ultrasonic frequencies of 100 kHz and 170 kHz is very large. Therefore, in order to form a compound formation area ratio of 50% or more, when the gold plating film and the ultrasonic frequency are expressed on an integer scale, the values at 0.7 μm at 60 kHz and 0.01 μm at 100 kHz are plotted. If the value is equal to or greater than the value obtained by connecting the lines with a straight line, good bonding is obtained.
[0025]
FIG. 9 shows the state of intermetallic compound formation at the interface of the joint when the ultrasonic frequency is 100 kHz and 170 kHz. It can be seen that the intermetallic compound was formed on the outer periphery of the crimping part at 60 kHz, whereas the intermetallic compound was densely formed over the entire crimping part at 100 kHz and 170 kHz oscillation. When the frequency is increased, the lead can be deformed with an amplitude smaller than that of the lower frequency. Further, if the oscillation time is the same, the number of vibrations (sliding times) increases. For this reason, it is presumed that the intermetallic compound could be formed densely over the entire crimped part at a higher frequency. As a result, it is considered that good bonding was achieved.
[0026]
FIG. 10 shows the compound formation area ratio of the intermetallic compound formed at the joint interface in FIG. FIG. 10 shows that the area ratio (about 50%) is close to saturation even when the gold plating film thickness is about 0.01 μm. It can be confirmed that this tendency corresponds to the tendency of the bonding strength shown in FIG. In addition, in FIG. 8, even when the gold plating film thickness is 0.01 μm, the bonding strength is close to the saturation strength, so when ultrasonic vibration of 100 kHz or higher is applied, good inner lead bonding can be achieved if the area ratio is about 50%. .
[0027]
According to the examination results shown in the present example, even if the thickness of the gold plating film applied to the inner lead surface is made thinner than before, no bonding damage occurs and good bonding can be achieved. It can be seen that a significant improvement in production yield can be realized by improving the bonding reliability of the parts, and that the cost of the semiconductor package can be reduced.
[0028]
(Example 2)
A study performed to confirm the effect of the present embodiment will be described.
[0029]
In order to investigate the influence of the hardness of the inner lead on the bonding reliability of the inner lead bonding part, the following samples were prepared and examined.
[0030]
Except for using copper foils with Vickers hardness of 60, 80, and 120, as in Example 1, produced a tape substrate with a gold plating thickness of 1.5μm (including inner leads) and buffered the stress. After pasting the layer, the semiconductor chip was pasted. Thereafter, inner lead bonding was performed to produce a package having the same structure. The ultrasonic frequency during inner lead bonding is 60 kHz. The frequency of occurrence of bonding damage in the inner lead bonding portion was investigated for these packages.
[0031]
Note that a copper foil having a Vickers hardness of less than 60 cannot be produced with the current technology.
[0032]
Here, a method for investigating bonding damage will be described. With respect to the sample for which the inner lead bonding has been completed, the bonding portion is observed using an infrared microscope from the back surface of the semiconductor chip, that is, the surface on which the inner lead bonding is not performed. When the bonding damage shown in FIG. 18 exists, this portion is imaged black, so that the presence or absence of damage can be confirmed.
[0033]
FIG. 11 shows the frequency of occurrence of bonding damage with respect to the hardness of the core copper of the inner lead. For comparison, the frequency of bonding damage in a conventional package with a Vickers hardness of 150 for the inner lead and a gold plating thickness of 1.5 μm is also shown. According to FIG. 11, the occurrence frequency of damage is low and constant when the Vickers hardness of the core copper is 100 or less, and it can be seen that even if the gold plating film thickness is the same, it is significantly reduced compared to the conventional package. If the Vickers hardness of the core copper is 100 or less, a package with high bonding reliability can be realized, and the production yield can be greatly improved.
[0034]
FIG. 12 shows the cross-sectional structure of the Vickers hardness 100 copper inner lead 5 used in this example and the cross-sectional structure of the copper inner lead used in the conventional semiconductor package. The structure of the copper inner lead of the semiconductor package of this example is composed of coarse crystal grains as compared with the structure of the conventional inner lead. For this reason, the Vickers hardness is softer than the conventional (Hv150). The copper inner lead of the package of this embodiment is intended to make crystal grains coarse, that is, soft, by removing the impurities from the electrolytic solution by treating the electrolytic solution with activated carbon and increasing the purity of the produced copper.
[0035]
(Example 3)
After a wiring pattern (including inner leads) was formed on a polyimide tape with a Vickers 100 copper foil, a tape substrate with a 0.5 μm gold plating was prepared. Thereafter, a stress buffer layer having an adhesion capability was formed on the tape substrate, and the stress buffer layer and the semiconductor chip were attached and bonded. In this attaching process, the inner leads on the tape substrate side are arranged on the electrode pads of the semiconductor chip. Next, the inner lead on the tape substrate and the electrode pad on the semiconductor chip were joined by inner lead bonding so as to be electrically conductive. Inner lead bonding was performed in the same manner as in Example 1 except that the ultrasonic frequency was 100 kHz.
[0036]
In order to investigate the effect of ultrasonic frequency on the bonding reliability of the inner lead bonding part, the following samples were prepared and examined.
[0037]
A tape substrate on which wiring (including inner leads) with a gold plating thickness of 0.5 μm was formed and a stress buffer layer was attached, and then a semiconductor chip was attached. Thereafter, inner lead bonding was performed in the same manner as described above except that ultrasonic frequencies of 60, 80, 120, 140, 160, and 170 kHz were added, and a package having the same structure was produced. For these packages, the bonding strength of the inner lead bonding portion and the frequency of occurrence of bonding damage were investigated.
[0038]
Here, a method for evaluating the bonding strength of the inner lead bonding portion will be described. As shown in FIG. 13, first, the sample is tilted and fixed at 45 °, and then the tip of the L-shaped tensile test probe is hooked on the center portion of the inner lead and pulled in the vertical direction. Then, the maximum load until lead breakage was measured and determined as the joint strength.
[0039]
FIG. 14 shows the bonding strength of the inner lead bonding portion at ultrasonic frequencies of 60 kHz, 100 kHz, and 170 kHz, and shows the change in bonding strength with respect to the vibration amplitude at the tip of the bonding tool. The vibration amplitude at the tip of the bonding tool was a laser Doppler vibrometer. This vibrometer is a device that irradiates a measurement spot with laser light and measures the vibration velocity component of the irradiation spot from the Doppler effect of the reflected wave. The output speed component is output to the oscilloscope as a voltage waveform. The vibration amplitude is calculated from the peak value. The measurement spot diameter of the laser Doppler vibrometer is 35 μm (when the work distance is 20 mm).
[0040]
According to FIG. 14, it can be confirmed that the junction can be made with a smaller amplitude as the frequency becomes higher than 1.0 μm at 100 kHz and 0.4 μm or more at 170 kHz compared with 60 kHz. Furthermore, from FIG. 14, the amplitude is 1 μm or more at 100 kHz, 0.5 μm or more at 150 kHz, 0.2 μm or more at 200 kHz, preferably 1 to 1.5 μm at 100 kHz, 0.5 to 1.0 μm at 150 kHz, and 0.2 to 0.6 μm at 200 kHz. An intermetallic compound of the metal constituting the metal wiring and the metal constituting the electrode is formed at the connection interface between the metal wiring and the electrode by the ultrasonic vibration in the direction.
[0041]
FIG. 15 shows the frequency of occurrence of bonding damage with respect to the ultrasonic frequency. According to FIG. 15, occurrence of bonding damage is recognized when the frequency is lower than 100 kHz. However, it can be confirmed that the damage occurrence frequency can be completely suppressed when the ultrasonic frequency is 100 kHz or more. For inner lead bonding where no bonding damage occurs, an ultrasonic frequency of 100 kHz or higher may be applied.
[0042]
As the lead progresses, the lead frictionally slides with respect to the electrode pad, so that a new surface of the electrode pad (a clean surface from which all the surface contamination films such as oxide films and organic substances have been removed) is exposed. When this new electrode pad surface and gold (plated film on the lead surface) come into contact, an intermetallic compound is immediately formed at the interface of the contact portion. Since the soft lead is easily plastically deformed by ultrasonic vibration, the exposure amount of the new surface of the electrode pad is larger than that of the conventional hard lead. Further, since it is easily deformed, it is considered that the impact of ultrasonic vibration can be absorbed and the influence of bonding damage to the underlying semiconductor chip is small. Furthermore, since a high ultrasonic frequency can be bonded with a small amplitude, it is considered that the effect of suppressing the occurrence of bonding damage is high. Therefore, highly reliable inner lead bonding can be achieved.
[0043]
(Example 4)
After forming a wiring pattern (including inner leads) on a polyimide tape with a Vickers hardness 80 copper foil, a tape substrate with 0.1 μm gold plating was prepared. Thereafter, a stress buffer layer having an adhesion capability was formed on the tape substrate, and the stress buffer layer and the semiconductor chip were attached and bonded. In this attaching process, the inner leads on the tape substrate side are arranged on the electrode pads of the semiconductor chip. Next, the inner lead on the tape substrate and the electrode pad on the semiconductor chip were joined by inner lead bonding so as to be electrically conductive. Inner lead bonding was performed in the same manner as in Example 1 except that the ultrasonic frequency was set to 170 kHz. With respect to this package, the bonding strength of the inner lead bonding portion, the compound formation area ratio, and the frequency of occurrence of bonding damage were investigated.
[0044]
FIG. 16 shows the results of investigating bonding strength, compound formation area ratio, and bonding damage occurrence frequency. For comparison, the bonding strength, compound formation area ratio, and bonding damage occurrence frequency in the conventional packages investigated at the same time were each set as 10. According to Fig. 16, it is confirmed that even if the thickness of the gold plating is reduced by more than 1/10 from the conventional 1.5μm to 0.1μm, the bonding strength is increased by 10% and the compound formation area ratio is increased by 50%. It can be seen that it is well joined. Furthermore, no bonding damage has occurred.
[0045]
According to the present embodiment, no bonding damage occurs and good bonding can be achieved, so that a significant increase in production yield can be realized by improving the bonding reliability of the inner lead bonding portion. Furthermore, since the thickness of the gold plating film applied to the inner lead surface is about 1/10 thinner than before, the cost of the semiconductor package can be significantly reduced.
[0046]
【The invention's effect】
According to the present invention, in the semiconductor package structure, the thickness of the gold plating applied to the wiring formed on the insulating tape substrate can be reduced to 0.01 to 0.5 μm, thereby greatly reducing the production process in the package manufacturing. Furthermore, the core material of the metal wiring in the connection between the metal wiring formed on the insulating tape substrate and the electrode pad formed on the semiconductor chip is set to 60 to 100 in Vickers hardness so that the connection portion between the connection wiring and the electrode pad Reliability is improved and yield can be improved significantly.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor package according to the present invention.
FIG. 2 is a side view of FIG.
FIG. 3 is a perspective view showing an inner lead bonding method.
FIG. 4 is a diagram showing the relationship between the thickness of the gold plating film and the bonding strength.
FIG. 5 is a diagram showing a state in which an intermetallic compound is formed at a joint interface.
FIG. 6 is a diagram showing a relationship between a compound formation area ratio of an intermetallic compound formed at a joint interface and a thickness of a gold plating film.
FIG. 7 is a view showing a method for calculating a compound formation area ratio.
FIG. 8 is a diagram showing the relationship between gold plating film thickness and bonding strength when the ultrasonic frequency is 100 and 170 kHz.
FIG. 9 is a diagram showing a state of formation of an intermetallic compound at the joint interface when the ultrasonic frequency is 100 and 170 kHz.
FIG. 10 is a diagram showing a relationship between a compound formation area ratio of an intermetallic compound formed at a joint interface and a gold plating film thickness.
FIG. 11 is a diagram showing the relationship between the hardness of the core copper of the inner lead and the frequency of occurrence of bonding damage.
FIG. 12 is a diagram showing a cross-sectional structure of an inner lead using a conventional electrolytic copper foil and a cross-sectional structure of a copper inner lead of a semiconductor package of the present invention.
FIG. 13 is a cross-sectional view showing a method for evaluating bonding strength.
FIG. 14 is a diagram showing the relationship between bonding strength and amplitude when the ultrasonic frequency is 60, 100, and 170 kHz.
FIG. 15 is a diagram showing the relationship between the rate of occurrence of bonding damage and the ultrasonic frequency.
FIG. 16 is a diagram showing the results of investigating bonding strength, compound formation area ratio, and bonding damage occurrence frequency.
FIG. 17 is a perspective view showing a conventional inner lead bonding method.
FIG. 18 is a diagram showing the results of investigating the formation states of intermetallic compounds formed at the interface between the electrode pad and the inner lead.
FIG. 19 is a diagram when bonding damage occurs.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Electrode pad, 3 ... Protective film, 4 ... Stress buffer layer, 5 ... Inner lead, 6 ... Solder ball, 7 ... Tape substrate, 8 ... Sealing material, 9 ... Inner lead bonding part, 10 ... bump land, 11 ... semiconductor chip, 12 ... electrode pad, 13 ... protective film, 14 ... inner lead, 15 ... bonding tool, 16 ... horn.

Claims (3)

The plurality of electrodes formed on the semiconductor chip and the plurality of metal wirings formed on the insulating tape substrate on which the semiconductor chip is mounted are directly connected by pressure bonding by ultrasonic vibration having a frequency of 100 kHz or more and an amplitude of 1.5 μm or less. In the semiconductor package, the metal wiring is made of copper or copper alloy plated with gold, the copper or copper alloy has a Vickers hardness of 60 to 100, and the gold plating has a thickness of 0. The metal that constitutes the electrode and the metal that constitutes the metal wiring and the whole of the outer peripheral portion and the central portion of the crimped portion of at least the connection portion of the connection interface between the metal wiring and the electrode that is 01 to 0.8 μm A semiconductor package characterized in that an intermetallic compound is formed.   In a manufacturing method of a semiconductor package in which a plurality of electrodes formed on a semiconductor chip and a plurality of metal wirings formed on an insulating tape substrate on which the semiconductor chip is mounted are directly connected by pressure bonding by ultrasonic vibration, the metal wiring is It is made of copper or copper alloy having a Vickers hardness of 60 to 100 with gold plating, and the thickness of the gold plating is 0.01 to 0.8 μm, and the frequency is 100 kHz or more while applying a load. The ultrasonic wave having an amplitude of 1.5 μm or less constitutes the metal and the electrode constituting the metal wiring in the entire outer peripheral portion and central portion of the crimped portion of the connection interface between the metal wiring and the electrode. A method of manufacturing a semiconductor package, comprising forming an intermetallic compound with a metal to be processed.   In an insulating tape substrate for a semiconductor package having a metal wiring layer directly connected to an electrode formed on a semiconductor package by pressure bonding by ultrasonic vibration having a frequency of 100 kHz or more and an amplitude of 1.5 μm or less, the metal wiring is subjected to gold plating. A semiconductor package, wherein the copper or copper alloy has a Vickers hardness of 60 to 100 and the gold plating has a thickness of 0.01 to 0.8 μm. Insulating tape substrate.

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