JP3799146B2 - 1-bit signal processor - Google Patents

Description

【００２８】
ＤＳＭの伝達関数は、Ｙ(ｚ)／Ｘ(ｚ)であり、下記式４に示すように、ｚの級数で表される。この式４の右辺の１行目は、式３に基づいて２行目に示すように表すことができる。
【００２９】
【数２】

【００３０】
式４において、所望の伝達関数を満足するように係数α_ｎ，β_ｎを決め、係数α_０〜α_５から係数ｆ〜ａを、係数β_０〜β_５から係数Ｅ〜Ａを導く。
【００３１】
右辺の２行目の分子におけるｚ^０の項はｆだけであり、したがって、ｆ＝α_０である。
【００３２】
次に、右辺の１行目の分子からα_０(１−ｚ^−１)^５を引くと、α_０＋α_１ｚ^−１・・・＋・・・α_５ｚ^−５−α_０(１−ｚ^−１)^５が得られる。
【００３３】
同様に、右辺の２行目の分子からｆ(１−ｚ^−１)^５を引く。このとき、ｚ^−１の項はｅだけであり、このｅは、右辺の１行目の対応したα_１と等しい。
【００３４】
以上の処理を、式４の分子の全ての項に対して繰り返して、係数ｄ〜ａを求める。また、この処理を式４の分母の全ての項に対して繰り返して、係数Ｅ〜Ａを求める。
【００３５】
【発明が解決しようとする課題】
ＤＳＭ間で信号をフィルタリングし、またＤＳＭ間で１ビット信号のストリームを維持することが望ましい。このフィルタリングが必要な理由は、例えば縦続接続されたＤＳＭにおいて望ましくない量子化雑音が蓄積されるのを防止するためである。しかしながら、適切なディジタルフィルタは、少なくとも、ビットストリームの各ビットを加算して多ビットの信号を生成し、及び／又はビットストリームにｐ（≧１）ビットの係数を乗算する。そして、このようなフィルタに縦続したＤＳＭの全ての係数乗算器は、ｐビット信号が供給されるｐビットの乗算器でなければならず、非常に不経済である。
【００３６】
本発明は、上述したような実情に鑑みてなされたものであり、本発明の目的は、１ビット信号を処理する直列又は縦続接続された複数のデルタ−シグマ変調器を備える１ビット信号処理装置を提供することである。なお、上述した論文には、このような提案については、何ら記載も示唆もされていない。
【００３７】
【課題を解決するための手段】
本発明に係る１ビット信号処理装置は、ｎ（≧３）次のデルタ−シグマ変調手段を備える。このｎ次のデルタ−シグマ変調手段は、第１の１ビット信号が入力される第１の入力手段と、第２の１ビット信号が入力される第２の入力手段と、ｐビット信号を１ビット信号に再量子化して、当該１ビット信号処理装置の出力信号として出力する量子化手段と、複数の信号混合手段とを有する。これらの複数の信号混合手段は、入力される第１の１ビット信号と第１の係数の積と、入力される第２の１ビット信号と第２の係数の積と、出力信号と第３の係数の積との加算値の積分値を求める第１段目の信号混合手段と、入力される第１の１ビット信号と第１の係数の積と、入力される第２の１ビットと第２の係数の積と、上記出力信号と第３の係数の積と、前段の積分値との加算値の積分値を求める少なくとも１つの中間段の信号混合手段と、入力される１ビット信号と第１の係数の積と、入力される第２の１ビット信号と第２の係数と、前段の積分値との加算値を求めて、量子化手段で１ビット信号に再量子化されるｐビット信号を生成する最終段の信号混合手段とからなる。
【００３８】
第１の１ビット信号と第２の１ビット信号は、第１の係数と第２の係数の比率で混合される。また、第３の係数は、雑音除去のために固定の値とされる。更に、第１の係数及び又は第２の係数は、可変である。
【００３９】
この１ビット信号処理装置は、制御信号に基づいて、上記可変の第１及び第２の係数を発生し、上記複数の信号混合手段に供給する係数発生手段を更に備える。また、係数発生手段は、第１及び第２の係数を予め記憶したメモリからなり、制御信号をアドレス信号として、第１及び第２の係数を読み出す。
【００４０】
また、１ビット信号処理装置は、複数の混合手段を同期させて動作させるためのクロックを発生するクロック発生手段と、入力される第１及び第２の１ビット信号をクロック発生手段からのクロックに同期させる同期手段とを更に備える。
【００４１】
【発明の実施の形態】
以下、本発明に係る１ビット信号処理装置について、図面を参照しながら説明する。
【００４２】
本発明に係る１ビット信号処理装置は、本発明を適用したデルタ−シグマ変調器（以下、ＤＳＭという。）を備える。このＤＳＭは、図１に示すように、５次のＤＳＭであり、５つの積分部と、最終段とを備えている。このＤＳＭは、１ビット信号が供給される入力端子１１と、信号処理を施した１ビット信号を出力する出力端子１７とを備える。
【００４３】
最終段の量子化器１５には、例えば正と負の両方の数を表す２の補数形式のｐビットの信号が供給される。量子化器１５は、例えば閾値が０の比較器からなり、ｐビットの信号を、正の信号が＋１に、負の信号が−１となるように量子化して、出力信号を生成する。
【００４４】
１段目の積分部は、入力端子１１に接続された１ビット係数乗算器１２_１と、出力端子１７に接続された１ビット係数乗算器１６_１と、１ビット係数乗算器１２_１及び１ビット係数乗算器１６_１の出力を加算する加算器１３_１と、加算器１３_１の出力を積分する積分器１４_１とを備える。１ビット係数乗算器１２_１，１６_１は、１ビット信号に、ｐビットからなる係数Ａ_１，Ｃ_１をそれぞれ乗算する。加算器１３_１は、１ビット係数乗算器１２_１，１６_１の各出力を加算して、積分器１４_１に供給する。
【００４５】
中間段の４つの積分部は、それぞれ、入力端子１１に接続された１ビット係数乗算器１２_２，１２_３，１２_４，１２_５と、出力端子１７に接続された１ビット係数乗算器１６_２，１６_３，１６_４，１６_５と、加算器１３_２，１３_３，１３_４，１３_５と、積分器１４_２，１４_３，１４_４，１４_５とを備える。１ビット係数乗算器１２_２〜１２_５，１６_２〜１６_５は、１ビット信号にｐビットからなる係数Ａ_２〜Ａ_５，Ｃ_２〜Ｃ_５をそれぞれ乗算する。加算器１３_２〜１３_５は、対応する段の１ビット係数乗算器１２_２〜１２_５，１６_２〜１６_５の各出力と、前段の積分器１４_１〜１４_４の出力とがそれぞれ供給され、それらを加算して積分器１４_２〜１４_５に供給する。
【００４６】
積分器１４_１〜１４_５は、例えば図２に示すように、加算器２１と、この加算器２１に直列に接続された遅延回路２２とをそれぞれ備える。遅延回路２２の出力は加算器２１にフィードバックされており、加算器２１は、１ビット係数乗算器１２_１〜１２_５，１６_１〜１６_５の各出力を加算した加算器１３_１〜１３_５の出力を累積する。図２に示す加算器２１での加算を、１ビット係数乗算器１２_１〜１２_５，１６_１〜１６_５の各出力を加算するその段の加算器１３_１〜１３_５で行うようにしてもよい。したがって、１ビット係数乗算器用の加算器１３_１〜１３_５と積分器用の加算器２１を必ずしも独立して設ける必要はない。
【００４７】
最終段は、入力端子１１に接続された１ビット係数乗算器１２_６と、加算器１３_６とを備える。加算器１３_６は、１ビット係数乗算器１２_６の出力と前段の積分器１４_５の出力を加算して、加算値を量子化器１５に供給する。
【００４８】
図１に示すように、係数Ａ_１〜Ａ_５，Ｃ_１〜Ｃ_５が固定値であり、積分器１４_１〜１４_５の中に独立した加算器２１を設けている場合、１ビット係数乗算器１２_１〜１２_５の各出力と１ビット係数乗算器１６_１〜１６_５の各出力をそれぞれ加算する加算器１３_１〜１３_５を、ルックアップテーブルで置き換えるようにしてもよい。具体的には、１ビット信号に係数Ａ_１，Ｃ_１を乗算すると、出力は、＋Ａ_１、−Ａ_１、＋Ｃ_１、−Ｃ_１となる。そこで、ルックアップテーブルに、＋Ａ_１、−Ａ_１と＋Ｃ_１、−Ｃ_１との全ての組み合わせを記憶しておく。そして、１ビット信号をアドレスとしてルックアップテーブルからその組み合わせを読み出すようにする。
【００４９】
上述したように、係数Ａ_１〜Ａ_５，Ｃ_１〜Ｃ_５は、上述の論文に記述されている方法によって定められる。勿論、係数は、回路の安定度が得られるように定められる。ところで、本発明では、更に、係数を、図３Ａに示すように、実線２５で示す雑音除去特性が得られるように設定する。それによって、入力信号の帯域における雑音（帯域内雑音）は減少する。
【００５０】
図１，３Ｃを参照し、本発明の実施例について説明する。これらの係数を、更に、図３Ｂに示すように、入力信号及び雑音を全帯域で例えば６ｄＢ減衰させ、帯域外の雑音を減衰させたままで、入力信号（及び帯域内雑音）を例えば６ｄＢ増幅して補償する図３Ｃの実線２７に示すようなローパスフィルタ特性が得られるように、設定する。
【００５１】
図３Ｃに示すように、ローパスフィルタ特性２７のロールオフ周波数において、帯域外の雑音の一部は、上述した補償のための増幅により、増幅されるが、全体の雑音は低減される。図３Ａ〜３Ｃは、２次のローパスフィルタを３次のＤＳＭに組み込んだ設計原理に基づいたものである。２次と３次を組み合わせた結果の５次のＤＳＭでは、係数は、ＤＳＭ全体の中に分散されている。
【００５２】
本発明に係る１ビット信号処理装置は、上述のようにして係数が設定されたＤＳＭを複数縦続接続したものであり、例えば図４に示すように、縦続接続された３つのＤＳＭ３１，３２，３３を備える。ＤＳＭの安定度は、帯域外であろうと帯域内であろうと、過大な雑音によって損なわれる。ところで、本発明では、上述したようなローパスフィルタ特性によって、少なくとも入力１ビット信号の周波数帯域外の雑音を減少させることにより、複数のＤＳＭを、例えば図４に示すように３つのＤＳＭ３１，３２，３３を縦続接続することができる。
【００５３】
図５及び関連出願（英国出願番号９６２４６７１．５）に記述されているように、ＤＳＭを、入力端子１１ａを介して供給される１ビット信号に係数Ａ_ｎを乗算する１ビット係数乗算器１２_ｎと、入力端子１１ｂを介して供給される１ビット信号に係数Ｂ_ｎを乗算する１ビット係数乗算器１８_ｎと、１ビット係数乗算器１２_ｎ，１８_ｎの各出力を加算する加算器１３_ｎとを備えた信号ミキサとして構成するようにしてもよい。なお、この図５は、１段の積分部の構成を示すブロック図である。
【００５４】
関連出願（英国出願番号９６２４６７１．５）に記載されているＤＳＭでは、図６に示すように、各積分部は、３つの入力を有する加算器４５_１，４５_２，４５_３と、加算器４５_１〜４５_３の各出力端子にそれぞれ接続された積分器４６_１，４６_２，４６_３と、加算器４５_１〜４５_３の第１の入力端子に接続され、第１の１ビット信号に係数Ａ_１，Ａ_２，Ａ_３を乗算する第１の係数乗算器４３_１、４３_２，４３_３と、加算器４５_１〜４５_３の第２の入力端子に接続され、第２の１ビット信号に係数Ｂ_１，Ｂ_２，Ｂ_３を乗算する第２の係数乗算器４４_１、４４_２，４４_３と、加算器４５_１〜４５_３の第３の入力端子に接続され、このＤＳＭの出力信号に係数Ｃ_１，Ｃ_２，Ｃ_３を乗算する第３の係数乗算器４８_１、４８_２，４８_３とを備える。
【００５５】
ＤＳＭの最終段は、３つの入力を有する加算器４５_４と、加算器４５_４の第１の入力端子に接続され、第１の１ビット信号に第１の係数Ａ_４を乗算する第１の係数乗算器４３_４と、加算器４５_４の第２の入力端子に接続され、第２の１ビット信号に第２の係数Ｂ_４を乗算する第２の係数乗算器４４_４とを備え、前段の積分器４６_３の出力端子に接続されている。加算器４５_４の出力端子は、量子化器４７に接続されている。
【００５６】
中間段の加算器４５_２，４５_３は、それぞれ第４の入力端子を有し、この入力端子を介して前段の積分器４６_１，４６_２からの出力が供給される。
【００５７】
係数乗算器４３_１〜４３_４，４４_１〜４４_４，４８_１〜４８_３は、全て１ビットの乗数器であり、供給される１ビット信号にｐビットからなる係数を乗算して、ｐビットの乗算値を生成する。
【００５８】
加算器４５_１〜４５_４及び積分器４６_１〜４６_３は、ｐビットで動作する。
【００５９】
ｐビットの信号は、例えば正数と負数を表す２の補数表現となっている。
【００６０】
量子化器４７は、閾値が０の比較器を備え、負の入力を−１（論理０）に、正の入力を＋１（論理１）にエンコードして、１ビットの出力信号を出力端子４９を介して出力する。
【００６１】
同期回路４２は、入力端子４１ａ，４１ｂを介して第１の１ビット信号と第２の１ビット信号が供給され、これらの第１及び第２の１ビット信号を、クロック発生回路１から供給される局部クロックに同期させる。この同期回路４２は、２つの入力１ビット信号を、別々に同期させる場合もある。クロック発生回路１は、ＤＳＭのクロッキング制御も行う。
【００６２】
係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４，Ｃ_１〜Ｃ_３は、上述の論文に述べられた方法を用いて、下記条件を満足するように決定される。
【００６３】
ａ）回路安定度、ｂ）雑音除去、ｃ）入力１ビット信号の帯域内で所定ゲインを有し、帯域外でこの所定ゲインよりも小さなゲインを有する。
【００６４】
係数Ｃ_１〜Ｃ_３は、雑音除去のために固定の値とされる。
【００６５】
係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４は、入力１ビット信号の伝達関数の零点を定義しており、したがって入力１ビット信号のゲインを制御するものである。
【００６６】
そして、例えば、係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４は、係数の値で決定される固定の比率で第１の１ビット信号と第２の１ビット信号を加算する係数である。したがって、係数Ａ_１〜Ａ_４と係数Ｂ_１〜Ｂ_４は異なる値としてもよいし、それぞれが等しい値としてもよい。
【００６７】
また、例えば、係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４は、第１の１ビット信号と第２の１ビット信号の混合比を変えることができるように、可変とする。これらの可変係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４は、係数発生器２から供給される。例えば、係数発生器２は、係数の組を予め記憶した係数メモリからなり、制御信号ＣＳに応じた種々なアドレスによって係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４を読み出して、係数乗算器１３_１〜１３_４，１４_１〜１４_４に供給する。
【００６８】
あるいは、係数発生器２を、制御信号ＣＳに対応した係数を発生するマイクロコンピュータで構成するようにしてもよい。
【００６９】
本発明では、このように構成されるＤＳＭにおいても、ＤＳＭの係数を、入力１ビット信号の帯域内で所定ゲインを有し、帯域外でこの所定ゲインよりも小さなゲインを有するように設定する。
【００７０】
また、本発明に係る１ビット信号処理装置を、例えば関連出願（英国出願番号９６２４６７１．５）に記述されているように、構成してもよい。すなわち、本発明に係る１ビット信号処理装置は、図７に示すように、２つの入力信号を混合する混合器５１，５２，５３，５４を備え、これらの混合器５１〜５４は、可変係数を発生する係数発生器２を有する図６に示すＤＳＭからなる。混合器５１，５２の出力対は、加算器５５に供給され、混合器５３，５４の出力対は加算器５６に供給される。これらの加算器５５，５６は、固定の係数Ａ_１〜Ａ_４，Ｂ_１〜Ｂ_４を有する図６のＤＳＭからなる。最終の加算器５７は、加算器５５，５６と同様に、固定の係数を有するＤＳＭからなる。
【００７１】
ここで、図８に他のフィルタ特性を示す。このフィルタ特性は、例えば入力１ビット信号の帯域において一定ゲインであり、音声帯域外においてそれよりも小さな一定ゲインである。図１に示す５次のＤＳＭの係数を、図８の周波数特性を満たすように設定する。
【００７２】
【発明の効果】
本発明に係る１ビット信号処理装置は、ｎ（≧３）次のデルタ−シグマ変調手段を備える。このデルタ−シグマ変調手段は、１ビット信号が入力される入力手段と、ｐビット信号を１ビット信号に再量子化して、当該１ビット信号処理装置の出力信号として出力する量子化手段と、複数の信号混合手段とを有する。複数の信号混合手段は、入力１ビット信号と係数の積と、出力信号と係数の積との加算値の積分値を求める第１段目の信号混合手段と、入力１ビット信号と係数の積と、出力信号と係数の積と、前段の積分値との加算値の積分値を求める少なくとも２つの中間段の信号混合手段と、入力１ビット信号と係数の積と、前段の積分値との加算値を求めて、量子化手段で１ビット信号に再量子化されるｐビット信号を生成する最終段の信号混合手段とからなる。そして、係数を、入力１ビット信号の帯域内で所定ゲインを有し、帯域外で所定ゲインよりも小さなゲインを有するように設定することにより、入力信号帯域の外の量子化雑音を低減することができる。量子化雑音を低減することにより、回路の安定度を高めることができ、また安定度を低下させる大きな雑音の蓄積を防ぐことにより、複数のデルタ−シグマ変調器を縦続接続することができる。
【図面の簡単な説明】
【図１】本発明を適用したデルタ−シグマ変調器の具体的な構成を示すブロック図である。
【図２】図１に示すデルタ−シグマ変調器の積分器の具体的な構成を示すブロック図である。
【図３】図１に示すデルタ−シグマ変調器の入力１ビット信号に対するフィルタ特性を説明するための図である。
【図４】図１に示すデルタ−シグマ変調器を複数縦続接続したときの具体的な構成を示すブロック図である。
【図５】図１に示すデルタ−シグマ変調器を変更したデルタ−シグマ変調器の具体的な構成を示すブロック図である。
【図６】本発明を適用したデルタ−シグマ変調器の具体的な構成を示すブロック図である。
【図７】図６に示すデルタ−シグマ変調器を用いた信号ミキサの具体的な構成を示すブロック図である。
【図８】他のフィルタ特性を示す図である。
【図９】従来のデルタ−シグマ変調器の構成を示すブロック図である。
【図１０】ｎ次のフィルタとして構成されたデルタ−シグマ変調器の構成を示すブロック図である。
【図１１】雑音除去特性を示す図である。
【図１２】５次のデルタ−シグマ変調器の構成を示すブロック図である。
【符号の説明】
１２_１〜１２_６，１６_１〜１６_５ １ビット係数乗算器、１３_１〜１３_６ 加算器、１４_１〜１４_５ 積分器、１５ 量子化器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a 1-bit signal processing apparatus, and more particularly to a 1-bit signal processing apparatus including an n (≧ 3) order delta-sigma modulator having a filter. In the embodiments of the present invention, the audio signal processing apparatus is described. However, the present invention is not limited to the audio signal processing apparatus.
[0002]
[Prior art]
It is known to convert an analog signal into a digital signal by sampling the analog signal at a frequency equal to or higher than the Nyquist frequency and quantizing the amplitude of the obtained sample with m bits. For example, when m = 8, the sample value is quantized with an accuracy of 8 bits. In general, m is 1 or more.
[0003]
An analog / digital converter (hereinafter referred to as an A / D converter) that quantizes an analog signal into a 1-bit digital signal is referred to as a “sigma-delta A / D converter” or “delta-sigma A / D converter”. "It has been known. Here, the term “delta-sigma” is used. Such delta-sigma A / D converters are described, for example, by Craig Marven, Gillian Ewers, 1993, Texas Instruments, “Texas Instruments for Digital Signal Processing. It is described in “A Simple Approach to Digital Signal Processing” (ISBN 0-904.047-00-8).
[0004]
In the delta-sigma A / D converter, as shown in FIG. 9, the difference (delta) between the analog input signal and the integrated value (sigma) of the 1-bit output signal is obtained by the adder 101, and the 1-bit quantum is obtained. Is supplied to the generator 102. The output signal is composed of bits of logic 0 and logic 1, and logic 0 and logic 1 represent -1 and +1 as actual values, respectively. The integrator 103 accumulates the 1-bit output signal and outputs a cumulative value that follows the value of the analog input signal. The 1-bit quantizer 102 increases (+1) or decreases (−1) the accumulated value for each bit to be generated. The sampling frequency of the delta-sigma A / D converter is set to a high frequency so that an output bit stream whose accumulated value follows the analog input signal can be generated.
[0005]
The term “1 bit” signal as used in the claims and in the following description means a signal generated, for example, by a delta-sigma A / D converter and quantized with an accuracy of 1 digital bit.
[0006]
The delta-sigma modulator (hereinafter referred to as DSM) is configured as an n-th order filter that directly processes a 1-bit signal, and this n-th order filter is the first performed on October 7-10, 1993. Paper published in the 95th AES (Audio Engineering Society) conference by NM Casey and James AS Angus “One Bit Digital Processing Signal Processing: Audio Research Group, Electrical Department, University of York, Heslington, York Y01 5DD UK (Signal Processing: Audio Research Group, The Electronics Department, The University of York, Heslington, York YO1 5DD England) It has been proposed. FIG. 10 is a block diagram showing the configuration of the filter part of the 3rd order (n = 3) of the DSM.
[0007]
As shown in FIG. 10, the DSM includes an input terminal 111 to which a 1-bit signal is input and an output terminal 117 that outputs the processed 1-bit signal. Each bit of the 1-bit signal is processed in synchronization with a predetermined clock (not shown) in the entire DSM. The output bit signal is generated by a 1-bit quantizer 115 including a comparator having a threshold value of 0, for example. The DSM is a 1-bit multiplier 112 connected to the input terminal 111. ₁ , 112 ₂ , 112 ₃ And a 1-bit multiplier 116 connected to the output terminal 117 ₁ , 116 ₂ , 116 ₃ And the adder 113 ₁ , 113 ₂ , 113 ₃ And integrator 114 ₁ , 114 ₂ , 114 ₃ And.
[0008]
1-bit multiplier 112 ₁ ~ 112 ₃ Is a coefficient A composed of p bits in a 1-bit signal supplied via the input terminal 111. ₁ ~ A ₃ And the resulting p-bit multiplication value is added to the adder 113. ₁ ~ 113 ₃ 1-bit multiplier 116 ₁ ~ 116 ₃ Is a p-bit coefficient C in the output signal ₁ ~ C ₃ And the resulting p-bit multiplication value is added to the adder 113. ₁ ~ 113 ₃ To supply each. Adder 113 ₁ ~ 113 ₃ Respectively adds those multiplication values, and adds the obtained addition values to the integrator 114. ₁ ~ 114 ₃ To supply. Further, an intermediate stage adder 113 is used. ₂ , 113 ₃ Is the previous integrator 114 ₁ , 114 ₂ Are also added. The final stage is a 1-bit multiplier 112 connected to the input terminal 111. ₄ And the adder 113 ₄ 1-bit multiplier 112 ₄ Is a p-bit coefficient A to the input 1-bit signal. ₄ And the adder 113 ₄ Is obtained by adding the preceding integrator 114 to the multiplication value. ₃ Add the outputs of. The obtained addition value is supplied to the 1-bit quantizer 115.
[0009]
In DSM, two's complement calculation is used to represent positive and negative p-bit numbers. When a positive value is input, the 1-bit quantizer 115 quantizes it to +1 (logic 1), and when a negative value is input, it quantizes it to -1 (logic 0) and outputs it. To do.
[0010]
In a paper written by Casey and Angus, “The 1-bit processor produces a 1-bit output signal that includes an unacceptably unclear audio signal due to noise. There must be a description. " Noise that obscure the audio signal is quantization noise generated by the 1-bit quantizer 115.
[0011]
The 1-bit quantizer 115 has a first input terminal to which an audio signal is supplied, and a second input terminal to which a random bit stream (quantization noise) substantially uncorrelated with the audio signal is supplied. It can be regarded as an adder. In this model, an audio signal input via the input terminal 111 is converted into a 1-bit multiplier 112. ₁ ~ 112 ₄ Is fed forward to output terminal 117 and 1-bit multiplier 116. ₁ ~ 116 ₃ Is fed back by. Therefore, the coefficient A in the feedforward path ₁ ~ A ₄ Defines the zero point in the z-transform of the transfer function of the audio signal, and the coefficient C in the feedback path ₁ ~ C ₃ Defines the poles in the z-transform of the transfer function.
[0012]
On the other hand, the noise signal is converted from the 1-bit quantizer 115 to the 1-bit multiplier 116. ₁ ~ 116 ₃ And the coefficient C ₁ ~ C ₃ Defines the pole of the transfer function of the noise signal. The transfer function of the noise signal is different from the transfer function of the input signal.
[0013]
Factor A ₁ ~ A ₄ , C ₁ ~ C ₃ Is defined so that circuit stability is obtained among other desired characteristics.
[0014]
Coefficient C ₁ ~ C ₃ For example, as indicated by a solid line 120 in FIG. 11, quantization noise in the voice band is removed and minimized.
[0015]
Factor A ₁ ~ A ₄ , C ₁ ~ C ₃ Is also determined so that desired audio signal characteristics can be obtained.
[0016]
Factor A ₁ ~ A ₄ , C ₁ ~ C ₃ Can be determined as follows.
[0017]
a) For example, H (z) is obtained by z-transforming a transfer function of a desired filter characteristic having a noise removal function.
[0018]
b) Convert H (z) into a coefficient.
[0019]
This is “Theory and Practical Implementation of a Fifth Order Sigma-Delta A / D Converter”, Audio Engineering Society Journal, Vol. 39, No. . 7/8, 1991, July / August, by Earl Double Adams et al. (Journal of Audio Engineering Society, Volume 39, no. 7/8, 1991 July / August by RW Adamset al.) This can be done using the method described in Casey's above mentioned paper.
[0020]
Here, a specific method for determining the coefficient will be described.
[0021]
An outline of the process of analyzing the fifth-order DSM and the process of calculating the coefficient for obtaining a desired filter characteristic will be described.
[0022]
As shown in FIG. 12, the fifth-order DSM is a multiplier 121 having coefficients a to f. ₁ ~ 121 ₆ And the adder 122 ₁ ~ 122 ₅ And integrator 123 ₁ ~ 123 ₅ And a multiplier 125 of coefficients A to E ₁ ~ 125 ₅ And. Integrator 123 ₁ ~ 123 ₅ Each have a unit delay time. Integrator 123 ₁ ~ 123 ₅ Respectively output signals s [n], t [n], u [n], v [n], and w [n]. A signal x [n] is input to the DSM. Here, [n] represents one sample in consecutive samples synchronized with the clock. The quantizer 124 outputs a signal y [n], and this signal y [n] is also an output signal of the DSM. The quantizer 124 is analyzed based on a model that is considered to operate as a simple adder that adds random noise to the signal. Therefore, the quantizer 124 is ignored in this analysis.
[0023]
The output signal y [n] in the sample [n] multiplies the input signal x [n] by the coefficient f, and the integrator 123 in the previous stage. ₅ Output signal w [n] is added, for example, y [n] = fx [n] + w [n].
[0024]
The same principle with integrator 123 ₁ ~ 123 ₄ When applied to each output signal, the following equation 1 is obtained.
[0025]
y [n] = fx [n] + w [n]
w [n] = w [n-1] + ex [n-1] + Ey [n-1] + v [n-1]
v [n] = v [n-1] + dx [n-1] + Dy [n-1] + u [n-1]
u [n] = u [n-1] + cx [n-1] + Cy [n-1] + t [n-1]
t [n] = t [n-1] + bx [n-1] + By [n-1] + s [n-1]
s [n] = s [n-1] + ax [n-1] + Ay [n-1]
... Formula 1
When these equations 1 are z-transformed, the following equation 2 is obtained.
[0026]
Y (z) = fX (z) + W (z)
W (z) (1-z ^-1 ) = Z ^-1 (eX (z) + EY (z) + V (z))
V (z) (1-z ^-1 ) = Z ^-1 (dX (z) + DY (z) + U (z))
U (z) (1-z ^-1 ) = Z ^-1 (cX (z) + CY (z) + T (z))
T (z) (1-z ^-1 ) = Z ^-1 (bX (z) + BY (z) + S (z))
S (z) (1-z ^-1 ) = Z ^-1 (aX (z) + AY (z))
... Formula 2
In the z conversion equation 2, when Y (z) is solved as a single function of X (z), the following equation 3 is obtained.
[0027]
[Expression 1]

[0028]
The transfer function of DSM is Y (z) / X (z), and is represented by a series of z as shown in the following formula 4. The first line on the right side of Expression 4 can be expressed as shown in the second line based on Expression 3.
[0029]
[Expression 2]

[0030]
In Equation 4, the coefficient α so as to satisfy the desired transfer function _n , Β _n The coefficient α ₀ ~ Α ₅ To the coefficient f to a, the coefficient β ₀ ~ Β ₅ The coefficients EA are derived from
[0031]
Z in the second row of molecules on the right ⁰ Is only f, so f = α ₀ It is.
[0032]
Next, from the first row of molecules on the right side, α ₀ (1-z ^-1 ) ⁵ Subtracting α ₀ + Α ₁ z ^-1 ... + ... α ₅ z ^-5 -Α ₀ (1-z ^-1 ) ⁵ Is obtained.
[0033]
Similarly, from the numerator in the second row on the right side, f (1-z ^-1 ) ⁵ pull. At this time, z ^-1 Is only e, and this e is the α corresponding to the first line on the right side. ₁ Is equal to
[0034]
The above processing is repeated for all the terms of the numerator of Equation 4 to obtain the coefficients d to a. Further, this process is repeated for all the terms in the denominator of Equation 4 to obtain the coefficients E to A.
[0035]
[Problems to be solved by the invention]
It is desirable to filter signals between DSMs and maintain a stream of 1-bit signals between DSMs. The reason for this filtering is to prevent unwanted quantization noise from accumulating in cascaded DSMs, for example. However, a suitable digital filter at least adds each bit of the bitstream to generate a multi-bit signal and / or multiplies the bitstream by a p (≧ 1) bit coefficient. All the coefficient multipliers of the DSM cascaded to such a filter must be p-bit multipliers to which a p-bit signal is supplied, which is very uneconomical.
[0036]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a 1-bit signal processing device including a plurality of serial or cascaded delta-sigma modulators for processing a 1-bit signal. Is to provide. The above-mentioned paper does not describe or suggest any such proposal.
[0037]
[Means for Solving the Problems]
The 1-bit signal processing apparatus according to the present invention includes n (≧ 3) -order delta-sigma modulation means. The n-th order delta-sigma modulation means includes a first input means to which a first 1-bit signal is input, a second input means to which a second 1-bit signal is input, and a p-bit signal as 1 A quantization unit that re-quantizes the bit signal and outputs the signal as an output signal of the 1-bit signal processing apparatus; and a plurality of signal mixing units. The plurality of signal mixing means include a product of the input first 1-bit signal and the first coefficient, a product of the input second 1-bit signal and the second coefficient, an output signal, and a third A first-stage signal mixing means for obtaining an integral value of an addition value of the product of the coefficients of the first, a product of the input first 1-bit signal and the first coefficient, and an input second 1-bit At least one intermediate stage signal mixing means for obtaining an integral value of the sum of the product of the second coefficient, the product of the output signal and the third coefficient, and the integral value of the previous stage, and an input 1-bit signal And the first coefficient, the input second 1-bit signal, the second coefficient, and the integrated value of the previous stage are obtained and re-quantized by the quantization means into a 1-bit signal. It comprises signal mixing means at the final stage for generating a p-bit signal.
[0038]
The first 1-bit signal and the second 1-bit signal are mixed at a ratio of the first coefficient and the second coefficient. The third coefficient is a fixed value for noise removal. Furthermore, the first coefficient and / or the second coefficient are variable.
[0039]
The 1-bit signal processing apparatus further includes coefficient generating means for generating the variable first and second coefficients based on the control signal and supplying the first and second coefficients to the plurality of signal mixing means. The coefficient generating means is composed of a memory in which the first and second coefficients are stored in advance, and reads the first and second coefficients using the control signal as an address signal.
[0040]
In addition, the 1-bit signal processing device includes a clock generation unit that generates a clock for operating a plurality of mixing units in synchronization, and the first and second 1-bit signals that are input are clocks from the clock generation unit. Synchronization means for synchronizing.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
A 1-bit signal processing apparatus according to the present invention will be described below with reference to the drawings.
[0042]
A 1-bit signal processing apparatus according to the present invention includes a delta-sigma modulator (hereinafter referred to as DSM) to which the present invention is applied. As shown in FIG. 1, this DSM is a fifth-order DSM, and includes five integration units and a final stage. The DSM includes an input terminal 11 to which a 1-bit signal is supplied and an output terminal 17 that outputs a 1-bit signal subjected to signal processing.
[0043]
The final-stage quantizer 15 is supplied with a p-bit signal in two's complement format representing both positive and negative numbers, for example. The quantizer 15 includes a comparator having a threshold value of 0, for example, and quantizes a p-bit signal so that a positive signal becomes +1 and a negative signal becomes −1 to generate an output signal.
[0044]
The first stage integration unit includes a 1-bit coefficient multiplier 12 connected to the input terminal 11. ₁ And a 1-bit coefficient multiplier 16 connected to the output terminal 17 ₁ And a 1-bit coefficient multiplier 12 ₁ And 1-bit coefficient multiplier 16 ₁ Adder 13 for adding the outputs of ₁ And the adder 13 ₁ Integrator 14 for integrating the output of ₁ With. 1-bit coefficient multiplier 12 ₁ , 16 ₁ Is a coefficient A consisting of p bits in a 1-bit signal. ₁ , C ₁ Respectively. Adder 13 ₁ Is a 1-bit coefficient multiplier 12 ₁ , 16 ₁ Are added to obtain an integrator 14. ₁ To supply.
[0045]
The four integration units in the intermediate stage are each a 1-bit coefficient multiplier 12 connected to the input terminal 11. ₂ , 12 ₃ , 12 ₄ , 12 ₅ And a 1-bit coefficient multiplier 16 connected to the output terminal 17 ₂ , 16 ₃ , 16 ₄ , 16 ₅ And the adder 13 ₂ , 13 ₃ , 13 ₄ , 13 ₅ And integrator 14 ₂ , 14 ₃ , 14 ₄ , 14 ₅ With. 1-bit coefficient multiplier 12 ₂ ~ 12 ₅ , 16 ₂ ~ 16 ₅ Is a coefficient A consisting of 1 bit signal and p bits. ₂ ~ A ₅ , C ₂ ~ C ₅ Respectively. Adder 13 ₂ ~ 13 ₅ Is the corresponding 1-bit coefficient multiplier 12 ₂ ~ 12 ₅ , 16 ₂ ~ 16 ₅ And the integrator 14 in the previous stage ₁ ~ 14 ₄ Are added to each other and added to the integrator 14. ₂ ~ 14 ₅ To supply.
[0046]
Integrator 14 ₁ ~ 14 ₅ For example, as shown in FIG. 2, each includes an adder 21 and a delay circuit 22 connected in series to the adder 21. The output of the delay circuit 22 is fed back to the adder 21, which adds the 1-bit coefficient multiplier 12. ₁ ~ 12 ₅ , 16 ₁ ~ 16 ₅ Adder 13 adding the outputs of ₁ ~ 13 ₅ Accumulate the output of. The addition by the adder 21 shown in FIG. ₁ ~ 12 ₅ , 16 ₁ ~ 16 ₅ The adder 13 at that stage for adding the outputs of ₁ ~ 13 ₅ You may make it carry out. Therefore, an adder 13 for a 1-bit coefficient multiplier ₁ ~ 13 ₅ And the adder 21 for the integrator are not necessarily provided independently.
[0047]
The final stage is a 1-bit coefficient multiplier 12 connected to the input terminal 11. ₆ And the adder 13 ₆ With. Adder 13 ₆ Is a 1-bit coefficient multiplier 12 ₆ Output and the previous integrator 14 ₅ Are added, and the added value is supplied to the quantizer 15.
[0048]
As shown in FIG. ₁ ~ A ₅ , C ₁ ~ C ₅ Is a fixed value and integrator 14 ₁ ~ 14 ₅ 1 is provided with an independent adder 21, a 1-bit coefficient multiplier 12 ₁ ~ 12 ₅ 1-bit coefficient multiplier 16 ₁ ~ 16 ₅ Adders 13 for adding the outputs of ₁ ~ 13 ₅ May be replaced with a lookup table. Specifically, the coefficient A is added to the 1-bit signal. ₁ , C ₁ Multiply the output by + A ₁ , -A ₁ , + C ₁ , -C ₁ It becomes. So, in the lookup table, + A ₁ , -A ₁ And + C ₁ , -C ₁ Remember all the combinations. Then, the combination is read from the lookup table using the 1-bit signal as an address.
[0049]
As mentioned above, the coefficient A ₁ ~ A ₅ , C ₁ ~ C ₅ Is determined by the method described in the above paper. Of course, the coefficient is determined so that the stability of the circuit can be obtained. By the way, in the present invention, the coefficient is further set so as to obtain the noise removal characteristic indicated by the solid line 25 as shown in FIG. 3A. Thereby, noise in the band of the input signal (in-band noise) is reduced.
[0050]
An embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 3B, these coefficients are further amplified by, for example, 6 dB while the input signal and noise are attenuated by, for example, 6 dB over the entire band, and the noise outside the band is attenuated by, for example, 6 dB. The low-pass filter characteristic as shown by the solid line 27 in FIG. 3C to be compensated is set.
[0051]
As shown in FIG. 3C, at the roll-off frequency of the low-pass filter characteristic 27, a part of the out-of-band noise is amplified by the above-described compensation amplification, but the entire noise is reduced. 3A to 3C are based on a design principle in which a second-order low-pass filter is incorporated in a third-order DSM. In the fifth order DSM resulting from the combination of the second order and the third order, the coefficients are distributed throughout the DSM.
[0052]
The 1-bit signal processing apparatus according to the present invention is obtained by cascading a plurality of DSMs having coefficients set as described above. For example, as shown in FIG. 4, three cascading DSMs 31, 32, 33 are connected. Is provided. DSM stability, whether out of band or in band, is compromised by excessive noise. By the way, in the present invention, by reducing the noise outside the frequency band of at least the input 1-bit signal by the low-pass filter characteristics as described above, a plurality of DSMs, for example, as shown in FIG. 33 can be connected in cascade.
[0053]
As described in FIG. 5 and the related application (UK Application No. 9624671.5), the DSM is applied to the 1-bit signal supplied via the input terminal 11a by the factor A. _n 1-bit coefficient multiplier 12 _n And a coefficient B for the 1-bit signal supplied via the input terminal 11b. _n 1-bit coefficient multiplier 18 _n And a 1-bit coefficient multiplier 12 _n , 18 _n Adder 13 for adding the outputs of _n It may be configured as a signal mixer provided with. FIG. 5 is a block diagram showing a configuration of a one-stage integrating unit.
[0054]
In the DSM described in the related application (UK Application No. 9624671.5), each integrator is an adder 45 having three inputs as shown in FIG. ₁ , 45 ₂ , 45 ₃ And the adder 45 ₁ ~ 45 ₃ Integrators 46 connected to the respective output terminals of the ₁ , 46 ₂ , 46 ₃ And the adder 45 ₁ ~ 45 ₃ Connected to the first input terminal of the first A-bit signal, the coefficient A ₁ , A ₂ , A ₃ The first coefficient multiplier 43 that multiplies ₁ 43 ₂ , 43 ₃ And the adder 45 ₁ ~ 45 ₃ Is connected to the second input terminal, and the second 1-bit signal has a coefficient B ₁ , B ₂ , B ₃ The second coefficient multiplier 44 that multiplies ₁ 44 ₂ 44 ₃ And the adder 45 ₁ ~ 45 ₃ Is connected to the third input terminal, and the output signal of the DSM ₁ , C ₂ , C ₃ A third coefficient multiplier 48 ₁ 48 ₂ , 48 ₃ With.
[0055]
The final stage of the DSM is an adder 45 with three inputs. ₄ And the adder 45 ₄ Connected to the first input terminal of the first coefficient A to the first 1-bit signal. ₄ The first coefficient multiplier 43 that multiplies ₄ And the adder 45 ₄ To the second input terminal of the second one-bit signal to the second coefficient B ₄ The second coefficient multiplier 44 that multiplies ₄ The integrator 46 in the previous stage ₃ Is connected to the output terminal. Adder 45 ₄ The output terminal is connected to the quantizer 47.
[0056]
Intermediate stage adder 45 ₂ , 45 ₃ Each have a fourth input terminal through which the integrator 46 of the previous stage is connected. ₁ , 46 ₂ The output from is supplied.
[0057]
Coefficient multiplier 43 ₁ ~ 43 ₄ 44 ₁ ~ 44 ₄ , 48 ₁ ~ 48 ₃ Are all 1-bit multipliers, and multiply the supplied 1-bit signal by a coefficient consisting of p bits to generate a p-bit multiplied value.
[0058]
Adder 45 ₁ ~ 45 ₄ And integrator 46 ₁ ~ 46 ₃ Operates on p bits.
[0059]
The p-bit signal has a two's complement representation representing, for example, a positive number and a negative number.
[0060]
The quantizer 47 includes a comparator having a threshold value of 0, encodes a negative input to -1 (logic 0) and a positive input to +1 (logic 1), and outputs a 1-bit output signal to an output terminal 49. Output via.
[0061]
The synchronization circuit 42 is supplied with the first 1-bit signal and the second 1-bit signal via the input terminals 41 a and 41 b, and these first and second 1-bit signals are supplied from the clock generation circuit 1. Synchronize with the local clock. The synchronizing circuit 42 may synchronize two input 1-bit signals separately. The clock generation circuit 1 also performs DSM clocking control.
[0062]
Factor A ₁ ~ A ₄ , B ₁ ~ B ₄ , C ₁ ~ C ₃ Is determined to satisfy the following conditions using the method described in the above paper.
[0063]
a) circuit stability, b) noise removal, c) a predetermined gain within the band of the input 1-bit signal, and a gain smaller than the predetermined gain outside the band.
[0064]
Coefficient C ₁ ~ C ₃ Is a fixed value for noise removal.
[0065]
Factor A ₁ ~ A ₄ , B ₁ ~ B ₄ Defines the zero of the transfer function of the input 1-bit signal, and therefore controls the gain of the input 1-bit signal.
[0066]
For example, the coefficient A ₁ ~ A ₄ , B ₁ ~ B ₄ Is a coefficient that adds the first 1-bit signal and the second 1-bit signal at a fixed ratio determined by the value of the coefficient. Therefore, the coefficient A ₁ ~ A ₄ And coefficient B ₁ ~ B ₄ May be different values, or may be equal to each other.
[0067]
For example, the coefficient A ₁ ~ A ₄ , B ₁ ~ B ₄ Is variable so that the mixing ratio of the first 1-bit signal and the second 1-bit signal can be changed. These variable coefficients A ₁ ~ A ₄ , B ₁ ~ B ₄ Is supplied from the coefficient generator 2. For example, the coefficient generator 2 includes a coefficient memory in which a set of coefficients is stored in advance. ₁ ~ A ₄ , B ₁ ~ B ₄ And the coefficient multiplier 13 ₁ ~ 13 ₄ , 14 ₁ ~ 14 ₄ To supply.
[0068]
Alternatively, the coefficient generator 2 may be configured by a microcomputer that generates a coefficient corresponding to the control signal CS.
[0069]
In the present invention, even in the DSM configured as described above, the coefficient of the DSM is set so as to have a predetermined gain within the band of the input 1-bit signal and to have a gain smaller than the predetermined gain outside the band.
[0070]
The 1-bit signal processing apparatus according to the present invention may be configured as described in a related application (UK application number 9624671.5), for example. That is, the 1-bit signal processing apparatus according to the present invention includes mixers 51, 52, 53, and 54 for mixing two input signals as shown in FIG. 7, and these mixers 51 to 54 have variable coefficients. The DSM shown in FIG. 6 has a coefficient generator 2 for generating. The output pair of the mixers 51 and 52 is supplied to the adder 55, and the output pair of the mixers 53 and 54 is supplied to the adder 56. These adders 55 and 56 have a fixed coefficient A ₁ ~ A ₄ , B ₁ ~ B ₄ The DSM of FIG. Similar to the adders 55 and 56, the final adder 57 is composed of a DSM having a fixed coefficient.
[0071]
Here, another filter characteristic is shown in FIG. This filter characteristic is, for example, a constant gain in the input 1-bit signal band, and a constant gain smaller than that outside the audio band. The coefficients of the fifth-order DSM shown in FIG. 1 are set so as to satisfy the frequency characteristics of FIG.
[0072]
【The invention's effect】
The 1-bit signal processing apparatus according to the present invention includes n (≧ 3) -order delta-sigma modulation means. The delta-sigma modulation means includes an input means for inputting a 1-bit signal, a quantization means for requantizing the p-bit signal into a 1-bit signal and outputting it as an output signal of the 1-bit signal processing device, Signal mixing means. The plurality of signal mixing means includes a first stage signal mixing means for obtaining an integral value of the sum of the product of the input 1-bit signal and the coefficient and the product of the output signal and the coefficient, and the product of the input 1-bit signal and the coefficient. And at least two intermediate stage signal mixing means for obtaining an integral value of the product of the output signal and the coefficient and the integrated value of the preceding stage, the product of the input 1-bit signal and the coefficient, and the integrated value of the preceding stage The final stage signal mixing means for obtaining the added value and generating a p-bit signal re-quantized to a 1-bit signal by the quantization means. The quantization noise outside the input signal band is reduced by setting the coefficient to have a predetermined gain within the band of the input 1-bit signal and to have a gain smaller than the predetermined gain outside the band. Can do. By reducing the quantization noise, the stability of the circuit can be increased, and by preventing the accumulation of a large noise that lowers the stability, a plurality of delta-sigma modulators can be cascaded.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a specific configuration of a delta-sigma modulator to which the present invention is applied.
2 is a block diagram showing a specific configuration of an integrator of the delta-sigma modulator shown in FIG. 1. FIG.
3 is a diagram for explaining filter characteristics for an input 1-bit signal of the delta-sigma modulator shown in FIG. 1; FIG.
4 is a block diagram showing a specific configuration when a plurality of delta-sigma modulators shown in FIG. 1 are connected in cascade. FIG.
5 is a block diagram showing a specific configuration of a delta-sigma modulator obtained by changing the delta-sigma modulator shown in FIG. 1. FIG.
FIG. 6 is a block diagram showing a specific configuration of a delta-sigma modulator to which the present invention is applied.
7 is a block diagram showing a specific configuration of a signal mixer using the delta-sigma modulator shown in FIG. 6. FIG.
FIG. 8 is a diagram illustrating another filter characteristic.
FIG. 9 is a block diagram showing a configuration of a conventional delta-sigma modulator.
FIG. 10 is a block diagram showing a configuration of a delta-sigma modulator configured as an n-th order filter.
FIG. 11 is a diagram illustrating noise removal characteristics.
FIG. 12 is a block diagram showing a configuration of a fifth-order delta-sigma modulator.
[Explanation of symbols]
12 ₁ ~ 12 ₆ , 16 ₁ ~ 16 ₅ 1-bit coefficient multiplier, 13 ₁ ~ 13 ₆ Adder, 14 ₁ ~ 14 ₅ Integrator, 15 quantizer

Claims (9)

n (≧ 3) order delta-sigma modulation means,
The n-th order delta-sigma modulation means is:
First input means for receiving a first 1-bit signal ;
Second input means for receiving a second 1-bit signal ;
quantization means for re-quantizing the p-bit signal into a 1-bit signal and outputting it as an output signal of the 1-bit signal processing device;
A plurality of signal mixing means,
The plurality of signal mixing means include:
The product of the input first 1-bit signal and the first coefficient , the product of the input second 1-bit signal and the second coefficient, and the product of the output signal and the third coefficient A first stage signal mixing means for obtaining an integral value of the added value;
The product of the input first 1-bit signal and the first coefficient , the product of the input second 1-bit and the second coefficient, the product of the output signal and the third coefficient , At least one intermediate stage signal mixing means for obtaining an integral value of the addition value of the integral value of
An addition value of the product of the input 1-bit signal and the first coefficient , the input second 1-bit signal, the second coefficient, and the previous integration value is obtained, and the quantization means A 1-bit signal processing apparatus comprising a final-stage signal mixing means for generating the p-bit signal re-quantized to a 1-bit signal. 2. The 1- bit signal processing apparatus according to claim 1, wherein the first 1-bit signal and the second 1-bit signal are mixed at a ratio of the first coefficient to the second coefficient . 2. The 1-bit signal processing apparatus according to claim 1 , wherein the third coefficient is a fixed value for noise removal . The first factor is 1-bit signal processing device of any one of claims 1 to 3, characterized in that a variable. 5. The 1-bit signal processing apparatus according to claim 1 , wherein the second coefficient is variable . 6. 6. The 1-bit signal processing apparatus according to claim 4, further comprising coefficient generating means for generating the variable first and second coefficients based on a control signal and supplying the variable first and second coefficients to the plurality of signal mixing means . 7. The coefficient generation means comprises a memory in which the first and second coefficients are stored in advance, and reads the first and second coefficients using the control signal as an address signal. 1-bit signal processing device. Clock generating means for generating a clock for operating the plurality of mixing means in synchronization;
  8. The 1-bit signal processing apparatus according to claim 1, further comprising synchronization means for synchronizing the inputted first and second 1-bit signals with a clock from the clock generation means. 9. 9. The 1- bit signal processing apparatus according to claim 1, wherein the first and second 1-bit signals are audio signals .

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