JP3791561B2 - Calculation method and calculation device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arithmetic method and an arithmetic device, and more particularly to an arithmetic method and an arithmetic device that perform butterfly operation on data of a predetermined number of bits and perform bit shift processing or clip processing on the operation result of the butterfly operation. .
[0002]
[Prior art]
Recently, digitalization is also spreading in broadcasting technology. FIG. 5 shows a configuration example of a DAB (Digital Audio Broadcasting) receiving apparatus that is one of digital radio broadcasts that digitize and broadcast audio signals.
[0003]
The tuner 92 selects a signal of a predetermined broadcasting station (channel) from signals received via the antenna 91 and outputs the signal to the A / D converter 93. The A / D converter 93 A / D converts the supplied signal and outputs the converted digital data to an FFT (Fast Fourier Transform) circuit 94.
[0004]
The FFT circuit 94 performs FFT operation and converts the data transmitted in the OFDM (Orthogonal Frequency Division Multiplexing) method by converting the supplied data on the time axis into data on the frequency axes of a plurality of subcarriers. Demodulate. The FFT circuit 94 includes a symbol after a guard interval component provided between adjacent symbols on the time axis (a modulation signal of a predetermined period including a predetermined amount of data) is removed. Ingredients are supplied.
[0005]
The deinterleave circuit and error correction circuit 95 performs deinterleave processing on the data supplied from the FFT circuit 94 and also performs error correction processing. A part of the signal processed by the deinterleave circuit and error correction circuit 95 is supplied to the decoding circuit 96. The decoding circuit 96 decodes the audio signal of the supplied signals, converts the decoded data into an analog audio signal, and then converts the left channel audio signal and the right channel audio signal into the speakers 97, 98 to output audio corresponding to those signals.
[0006]
The additional data output circuit 99 separates and outputs additional data such as program contents and traffic information from the signal supplied from the deinterleave circuit and error correction circuit 95.
[0007]
FIG. 6 shows an example of a signal flow in the FFT circuit 94 in the case of performing an 8-point FFT operation. The FFT circuit 94 preliminarily rearranges the data f (0), f (4), f (2), f (6), f (1), f (5), f (3), f (7) is supplied.
[0008]
The built-in butterfly computing unit performs butterfly computation on two of the data, and stores the two computation results in the built-in memory.
[0009]
In the first stage butterfly computation, the 0th data f (0) and the first data f (4), the second data f (2) and the third data f (6), The butterfly operation is performed on the fourth data f (1) and the fifth data f (5), and the sixth data f (3) and the seventh data f (7). Are stored in the memory as the 0th data R1 (0) to the 7th data R1 (7).
[0010]
Next, in the second stage butterfly operation, the 0th data R1 (0), the second data R1 (2), the first data R1 (1), and the third data R1 ( 3) The butterfly operation is performed on the fourth data R1 (4) and the sixth data R1 (6), and the fifth data R1 (5) and the seventh data R1 (7). The calculation results are stored in the memory as the 0th data R2 (0) and the 7th data R2 (7).
[0011]
In the third stage butterfly operation, the 0th data R2 (0), the 4th data R2 (4), the 1st data R2 (1), and the 5th data R2 (5 ), Butterfly operation is performed on the second data R2 (2), the sixth data R2 (6), and the third data R2 (3) and the seventh data R2 (7). These calculation results are stored in the memory as the 0th data F (0) and the 7th data F (7).
[0012]
Next, the data (FFT-calculated data) F (0) to F (7) calculated in this way are output to the deinterleave circuit and error correction circuit 95.
[0013]
In this way, 4 (8/2) times of butterfly calculations are performed on eight data in one stage using the input data or the calculation result of the previous butterfly calculation as data, for a total of 3 (= log₂(8)) Stage butterfly computation is performed.
[0014]
When performing an FFT operation on N pieces of data (that is, N points), the input data or the result of the previous butterfly operation is used as data in one stage (N points). / 2) butterfly operations are performed, and the total M (= log₂(N)) stage butterfly computation is performed.
[0015]
When a time-decimation type algorithm is used for the FFT operation, in the butterfly operation, a predetermined complex number (rotation operator) W is applied to one data B (complex number) of the two data A and B.^k _N(= (Exp (−j2πk / N)), where N is an integer), and then the sum of the operation result and the other data A (complex number) (the operation result of the butterfly operation R = A + W^kB) is calculated.
[0016]
At this time, the dynamic range of the real part (range of values that the real part can take) and the dynamic range of the imaginary part of the computation result R of the first stage butterfly computation are the dynamic range and imaginary number of the real part of the data before computation. Of dynamic range (1 + 2^1/2) Times (described later).
[0017]
Further, the dynamic range of the real part and the dynamic range of the imaginary part of the data after the i-th stage butterfly computation (that is, the computation result of the i-th stage butterfly computation) are the data input to the first stage. 2 of the dynamic range of the real part and imaginary part of^i-1(1 + 2^1/2) Times (described later).
[0018]
Therefore, when the M-stage butterfly calculation is performed, the dynamic range of the real part and the imaginary part of the calculation result is 2 of the dynamic range of the real part and the dynamic range of the imaginary part of the input data.^M-1(1 + 2^1/2) Doubled.
[0019]
In order to be able to hold data in the entire dynamic range, the number of bits is K (log) rather than the number of bits of input data.₂(2^M-1(1 + 2^1/2)) Above, the smallest integer) memory needs to be used.
[0020]
For example, when performing an FFT operation of 2,048 points, 11 (M = 11 = log₂(2048)) stage butterfly computation is required. For example, if the input data is 8 bits, 20 (≧ 19.3 = 8 + log) per one data (real part or imaginary part)₂(2^11-1(1 + 2^1/2))) Bit memory is required.
[0021]
[Problems to be solved by the invention]
However, when a memory having a number of bits K more than the number of bits of input data is used, the dynamic range of data in the first few stages is much narrower than the dynamic range of data that can be stored in the memory. There is a problem that the utilization efficiency of the memory is lowered.
[0022]
Note that the number of bits of data stored in the memory is set to a small value in advance, and at each stage, the calculation result is bit-shifted to the LSB (Least Significant Bit) side in accordance with the occurrence of overflow of the calculation result of the butterfly calculation. Although it may be possible to reduce the number of bits required for the memory and increase the memory utilization efficiency by clipping to a predetermined value, a circuit for monitoring the overflow of the operation result is necessary. As a result, the circuit configuration becomes complicated and the cost increases.
[0023]
The present invention has been made in view of the situation as described above, and does not require a circuit for monitoring overflow by performing bit shift processing on the operation result of a preset stage butterfly operation, This reduces the cost of the device.
[0024]
[Means for Solving the Problems]
  An arithmetic device according to a first aspect of the present invention is an arithmetic device that performs a predetermined number of FFT operations on an input signal modulated by a predetermined modulation method using the OFDM method, A butterfly operation circuit that performs a butterfly operation of the number of stages corresponding to the number of points, and a clip processing circuit that performs a clip process on the result of the butterfly operation at each stage, and the butterfly operation circuit is preset based on the modulation method Perform bit shifts at specified stagesIt is characterized by that.
  An arithmetic device according to a second aspect of the present invention is an arithmetic device that performs an IFFT operation on an input signal having a predetermined number of points modulated by a predetermined modulation method using an OFDM method, and A butterfly operation circuit that performs butterfly operation of the number of stages corresponding to the number of points, and a clip processing circuit that performs clip processing on the result of the butterfly operation at each stage, and the butterfly operation circuit is preset based on the modulation method It is characterized in that a bit shift is performed in each stage.
[0025]
  A calculation method according to a first aspect of the present invention is a calculation method for performing FFT calculation of a predetermined number of points on an input signal modulated by a predetermined modulation method using the OFDM method, and for the input signal, A butterfly computation step for performing a butterfly computation of the number of stages corresponding to the number of points, and a clip processing step for performing a clip process on the result of the butterfly computation at each stage, wherein the butterfly computation step is based on the modulation method in advance. Perform bit shift at the set stageIt is characterized by that.
  An arithmetic method according to a second aspect of the present invention is an arithmetic method for performing an IFFT operation on an input signal having a predetermined number of points modulated by a predetermined modulation method using the OFDM method. A butterfly computation step for performing butterfly computation of the number of stages corresponding to the number of points, and a clip processing step for performing clip processing on the result of the butterfly computation at each stage, wherein the butterfly computation step is preset based on the modulation method A bit shift is performed in each stage.
[0026]
  In the arithmetic device according to the first aspect of the present invention, when an FFT operation with a predetermined number of points is performed on an input signal modulated by a predetermined modulation method using the OFDM method, the input signal corresponds to the number of points. The number of stages of butterfly computation is performed, the result of the butterfly computation of each stage is clipped, and bit shift is performed at a preset stage based on the modulation method.
  In the arithmetic device according to the second aspect of the present invention, when an IFFT operation is performed on an input signal having a predetermined number of points modulated by a predetermined modulation method using the OFDM method, the input signal corresponds to the number of points. The butterfly operation of the number of stages is performed, clip processing is performed on the result of the butterfly operation at each stage, and bit shift is performed at a stage set in advance based on the modulation method.
[0027]
  In the calculation method according to the first aspect of the present invention, when an FFT calculation of a predetermined score is performed on an input signal modulated by a predetermined modulation method using the OFDM method, the input signal corresponds to the score. The butterfly operation is performed for the number of stages, clip processing is performed on the result of the butterfly operation at each stage, and bit shift is performed at a stage set in advance based on the modulation method.
  In the calculation method according to the second aspect of the present invention, when IFFT calculation is performed on an input signal having a predetermined number of points modulated by a predetermined modulation method using the OFDM method, the input signal corresponds to the number of points. The number of stages of butterfly computation is performed, clip processing is performed on the result of the butterfly computation at each stage, and bit shift is performed at a stage set in advance based on the modulation method.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the configuration of an embodiment of the arithmetic unit of the present invention. This embodiment is, for example, an FFT arithmetic unit used in place of the FFT circuit 94 in the receiving apparatus of FIG.
[0029]
In this embodiment, 11 stages of butterfly operations are performed on 2,048 points of 8-bit input data using a 10-bit memory (storage area) per data.
[0030]
The input buffer 1 temporarily stores data supplied from a predetermined circuit (for example, the A / D converter 93 in FIG. 5) (data that has been rearranged in the reverse bit order in advance). For example, the input buffer 1 receives and stores data that is QPSK modulated or QAM (Quadrature Amplitude Modulation) modulated by the OFDM method.
[0031]
The selector 2 reads out two data A and B from the input buffer 1 and outputs them to the arithmetic circuit 3.
[0032]
The selector 2 reads out the real part and imaginary part of the two data A and B from the memory 4 (storage means) and outputs the data to the arithmetic circuit 3.
[0033]
The memory 4 stores data being processed (a 10-bit real part (that is, a value in the interval [−512, 511]) and a 10-bit imaginary part).
[0034]
The butterfly operation unit 21 (first operation means) of the operation circuit 3 is supplied with data A and B from the selector 2 with a bit width of 10 bits, and the rotation operator data W stored in the built-in ROM.^k(W^k _N= Exp (−j2πk / N)) is read as appropriate, and its data W^k, Butterfly operation (A + W) for two data A and B^kB), and the operation result is output to the bit shift processing unit 22 (second operation means) with a bit width of 12 bits.
[0035]
The bit shift processing unit 22 of the arithmetic circuit 3 is a low-order 11 other than the sign bit of the calculation result (12 bits) of the fifth butterfly calculation, the seventh butterfly calculation, and the tenth butterfly calculation. After the bit is shifted by one bit to the LSB side, the processed calculation result is output to the clip processing unit 23 (third calculation means).
[0036]
Note that the bit shift processing unit 22 calculates the LSB value after the bit shift process by performing operations such as rounding, rounding down, and rounding up in decimal numbers according to the fractional value of the calculation result before the process. May be.
[0037]
The clip processing unit 23 of the arithmetic circuit 3 determines that the supplied 12-bit arithmetic result value is 512 (= 2).^Ten/ 2) If the value is greater than or equal to 511, the value is changed to 511. If the value is smaller than -512, the value is changed to -512.
[0038]
The selector 5 is configured to store the two data (calculation results) calculated by the arithmetic circuit 3 at the addresses of the memory 4 in which the two data before the calculation are stored.
[0039]
The selector 5 outputs the calculation result of the eleventh butterfly calculation supplied from the calculation circuit 3 to the output buffer 6.
[0040]
The output buffer 6 temporarily stores the data (operation result) supplied from the selector 5 and outputs it to a predetermined circuit (for example, the deinterleave circuit and error correction circuit 95 in FIG. 5). The output buffer 6 can output the data supplied from the selector 5 after, for example, shifting the data by 3 bits to the MSB (Most Significant Bit) side in accordance with the signal level in the subsequent circuit.
[0041]
Next, the operation of this embodiment will be described with reference to the flowchart of FIG.
[0042]
First, in step S1, the input buffer 1 receives 2,048 pieces of data that have been DQPSK modulated by, for example, the OFDM method from a predetermined circuit (for example, the A / D converter 93 in FIG. 5).
[0043]
In step S2, the selector 2 receives 2,048 pieces of data from the input buffer 1 (in the case of the first stage butterfly calculation) or the memory 4 (in the case of the second to eleventh stage butterfly calculations). Two predetermined data items are read out, and the data items are output to the butterfly operation unit 21 of the operation circuit 3.
[0044]
In step S3, the butterfly computation unit 21 performs a butterfly computation (A + W) on the two supplied data A and B.^kB), and outputs two calculation results to the bit shift processing unit 22.
[0045]
At this time, as shown in FIG. 3, the dynamic range of the real part and the dynamic range of the imaginary part of the two supplied data A and B are the interval [-a, a] (that is, data A and B (complex numbers)). The dynamic range of) is a square area having a side of 2a with the origin of the complex plane as the center.^kIs an operator that rotates the position by a predetermined angle around the origin, so that the rotation operator W in the butterfly calculation^kResult of multiplication of B and B^kThe dynamic range of the real part and the dynamic range of the imaginary part of B are the interval [-2^1/2a, 2^1/2a].
[0046]
In addition, W^kThe sum of B and A, that is, the dynamic range of the real part and the dynamic range of the imaginary part of the result of the butterfly operation, is calculated by the interval [− (1 + 2^1/2) A, (1 + 2^1/2) A].
[0047]
For example, the values of the data A and B are A = a + j · a, B = a + j · a, and the rotation operator W^kBut W^k= 2^-1/2-J ・ 2^-1/2W^k・ B is 2^1/2a + j · 0, and A + W^kB is (1 + 2^1/2) A + j · a. Thus, the calculation result A + W in this case^kReal part of B (1 + 2^1/2) A is the dynamic range [− (1 + 2^1/2) A, (1 + 2^1/2) A] upper limit value.
[0048]
When performing a predetermined n-stage (n> 1) butterfly operation on data in which the dynamic range of the real part and the imaginary part is in the interval [−a, a], the first to (n−) th stages are used. 1) In the stage, the rotation operator W whose value is 1^k(The dynamic range of the real part and the imaginary part of the (n−1) -th stage operation result is the interval [−2].^n-1a, 2^n-1a]), in the nth stage, for example, the value is 2^-1/2-J ・ 2^-1/2Rotation operator W^kWhen the butterfly operation is performed with the upper limit value of the dynamic range of the real part and the imaginary part (2^n-1(1 + 2^1/2A) and lower limit (-2)^n-1(1 + 2^1/2A) occurs.
[0049]
That is, when the n-th stage butterfly operation is performed on data whose dynamic range of the real part and the imaginary part is the interval [−a, a], the real part and the imaginary part of the operation result of the n-th butterfly operation The dynamic range of the section [-2^n-1(1 + 2^1/2A, 2^n-1(1 + 2^1/2) A].
[0050]
Next, in step S4, the bit shift processing unit 22 determines whether or not the number of stages of the current butterfly operation is any one of the fifth stage, the seventh stage, and the tenth stage. If it is determined that the number of operation stages is any one of the fifth, seventh, and tenth stages, the process proceeds to step S5 to perform bit shift processing.
[0051]
In step S5, the bit shift processing unit 22 bit-shifts the calculation result supplied from the butterfly calculation unit 21 by 1 bit to the LSB side, and decreases the absolute value of the calculation result. Then, the bit shift processing unit 22 outputs the calculation result to the clip processing unit 23.
[0052]
On the other hand, if it is determined in step S4 that the number of stages of the current butterfly operation is not any of the fifth, seventh, and tenth stages, step S5 is skipped, and the bit shift processing unit 22 Without doing anything, the calculation result supplied from the butterfly calculation unit 21 is output to the clip processing unit 23.
[0053]
That is, as shown in FIG. 4, the bit shift processing unit 22 applies all the calculation results of the fifth stage, the seventh stage, and the tenth stage of the butterfly calculations of all 11 stages. Bit shift is performed on the data to compress the dynamic range of the data to ½.
[0054]
Actual data (real part or imaginary part) in this embodiment (data subjected to QPSK modulation in the OFDM system assuming that the amplitude distribution is a Gaussian distribution (standard deviation is 1/8 of the dynamic range)) According to the result of previously simulating the distribution of the values of the values, the value distribution width is expanded by about 1.5 times by the first stage butterfly calculation, and by the first and second stage butterfly calculations. About 2.2 times. Furthermore, the width in which the values are distributed is expanded by about 3.2 times by the first to third butterfly operations, and is about 4.5 times by the first to fourth butterfly operations. To spread. Then, by the 11-stage butterfly operation, the width in which the values are distributed is expanded by about 13.7 times.
[0055]
Thus, the actual data value distribution width is narrower than the dynamic range. However, the width of the actual distribution of the values of the real part and the imaginary part of the input data (data before performing the butterfly operation) varies depending on the data modulation method.
[0056]
Based on the result of this simulation, in the apparatus of the present embodiment, the calculation result of the fifth stage butterfly calculation in which the value of the real part or the imaginary part of the data becomes greater than 512 or −513 is increased. On the other hand, the first bit shift processing is performed, the dynamic range of the data is compressed to ½, and then the probability that the value of the real part or the imaginary part of the data is 512 or more or −513 or less increases. A second bit shift process is performed on the calculation result of the butterfly calculation at the stage, and a third bit shift process is performed on the calculation result of the butterfly calculation at the tenth stage. The dynamic range is compressed to ½.
[0057]
Next, in step S6, the clip processing unit 23 determines whether the value of the calculation result supplied from the bit shift processing unit 22 is 512 or more, and whether the value of the calculation result is smaller than −512. If it is determined that the value of the calculation result is 512 or more, or if it is determined that the value of the calculation result is smaller than −512, the process proceeds to step S7.
[0058]
In step S7, when the value of the calculation result is 512 or more, the clip processing unit 23 changes the value of the calculation result to 511. When the value of the calculation result is smaller than −512, the clip processing unit 23 sets the value of the calculation result to − After changing to 512, the calculation results are output to the selector 5.
[0059]
On the other hand, if it is determined in step S6 that the value of the calculation result is smaller than 512 and equal to or greater than −512, step S7 is skipped, and the clip processing unit 23 does not do anything and sends the calculation result to the selector 5. Output.
[0060]
Note that the clip processing unit 23 converts the 12-bit operation result to 10 bits (the lower 9 bits of the 12-bit data are used as the lower 9 bits of the 10-bit data, After the value of the sign bit of the data is set to the value of the sign data of 10-bit data), it is output to the selector 5.
[0061]
Further, according to the result of the simulation described above, in the present embodiment, in the butterfly calculation other than the fifth stage, the seventh stage, and the tenth stage, the calculation result is 512 or more or −513 or less. Since the probability is small, only the clipping process is performed on the data (real part or imaginary part) that is 512 or more or −513 or less, and all the data is set to the value of the interval [−512, 511].
[0062]
Note that a truncation error occurs when the above bit shift process is performed, and a distortion error occurs when the clip process is performed, but according to the results of the above simulation, the calculation accuracy required for practical use is ensured. Therefore, no particular problem occurs.
[0063]
Next, in step S8, the selector 5 uses the calculation result supplied from the clip processing unit 23 of the calculation circuit 3 as the address (first to tenth stages) of the memory 4 where the selector 2 reads the data. (In the case of butterfly calculation) or stored in the output buffer 6 (in the case of the 11th stage butterfly calculation).
[0064]
In step S9, the arithmetic circuit 3 determines whether or not the butterfly operation has been performed on all the data in the current stage. If there is still data that has not been subjected to the butterfly operation, step S2 The butterfly operation is performed on these data.
[0065]
On the other hand, if the butterfly operation is performed on all the data in the current stage, the process proceeds to step S10.
[0066]
In step S10, the arithmetic circuit 3 determines whether or not the eleventh butterfly operation has been completed (that is, whether or not all eleventh butterfly operations have been completed), and the eleventh butterfly operation. If it is determined that the calculation has not ended, the process returns to step S2 to perform the next stage butterfly calculation.
[0067]
On the other hand, if it is determined that the 11th stage butterfly computation has been completed, the process proceeds to step S11, and the output buffer 6 uses the data (calculation result) after performing the 11th stage butterfly computation to a predetermined circuit (for example, The data is output to the deinterleave circuit and error correction circuit 95) of FIG.
[0068]
As described above, among the 11 stages of butterfly computations, the bit shift process is performed on the computation results of the 5th stage, the 7th stage, and the 10th stage butterfly computation, thereby obtaining one data (real part). Alternatively, an FFT operation is performed on 2,048 points of 8-bit input data in a 10-bit memory (storage area) per imaginary part).
[0069]
In this embodiment, 2,048 points of FFT calculation are performed. However, the number of data is not limited to 2,048 points. By changing the configuration of the apparatus, the number of data can be changed. An FFT operation can be performed. In this case, the stage for performing the bit shift process can be easily calculated by the above-described simulation.
[0070]
Moreover, in the said Example, although FFT calculation is performed, IFFT (Inverse FFT) calculation can be performed by changing the order of the rotation operator to be used. A device that performs such an IFFT operation can be used when a predetermined signal is modulated by the OFDM method in a transmitting device that transmits a modulated signal to the above-described receiving device.
[0071]
【The invention's effect】
  As above,According to the first aspect of the present invention, when an FFT operation with a predetermined number of points is performed on an input signal modulated by a predetermined modulation method using the OFDM method, the number of stages corresponding to the number of points for the input signal The butterfly calculation is performed, the clipping process is performed on the result of the butterfly calculation at each stage, and the bit shift is performed at a stage set in advance based on the modulation method.
  According to the second aspect of the present invention, when an IFFT operation is performed on an input signal having a predetermined number of points modulated by a predetermined modulation method using the OFDM method, the input signal corresponds to the number of points. The butterfly operation of the number of stages is performed, clip processing is performed on the result of the butterfly operation of each stage, and bit shift is performed at a stage set in advance based on the modulation method.
  In any case, as a result,Without providing a circuit or the like for monitoring overflow, the number of bits per data can be reduced and the FFT operation can be performed, and the cost of the apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of an arithmetic unit according to the present invention.
FIG. 2 is a flowchart for explaining the operation of the embodiment of FIG. 1;
FIG. 3 is a diagram illustrating an example of a dynamic range of a result of multiplication in a butterfly operation.
FIG. 4 is a diagram for explaining the signal flow of the embodiment of FIG. 1;
FIG. 5 is a block diagram illustrating a configuration example of a DAB receiving apparatus.
FIG. 6 is a diagram for explaining an example of an FFT signal flow;
[Explanation of symbols]
1 input buffer, 2 selector, 3 operation circuit, 4 memory, 5 selector, 6 output buffer, 21 butterfly operation unit, 22 bit shift processing unit, 23 clip processing unit, 91 antenna, 92 tuner, 93 A / D converter, 94 FFT circuit, 95 deinterleave circuit and error correction circuit, 96 decoding circuit, 97, 98 speaker, 99 additional data output circuit

Claims (8)

An arithmetic device that performs a predetermined number of FFT operations on an input signal modulated by a predetermined modulation method using an OFDM system,
A butterfly operation circuit for performing a butterfly operation of the number of stages corresponding to the number of points for the input signal;
A clip processing circuit that performs clip processing on the result of the butterfly computation at each stage;
The butterfly operation circuit performs bit shift at a preset stage based on the modulation method.
An arithmetic device characterized by that. When the predetermined modulation method is QPSK modulation and the predetermined number of points is 2048 , bit shift is performed in the fifth, seventh, and tenth stages of the butterfly computation . The arithmetic device according to claim 1. 3. The arithmetic device according to claim 2 , wherein the clip processing circuit performs a clipping process on an operation result at a stage where no bit shift is performed in the butterfly arithmetic circuit . The computing device according to claim 1 , wherein a stage for performing bit shift in the butterfly computation is determined by simulating a distribution of values in the modulation method . The input signal is a signal broadcast and received in the DAB format.
The arithmetic unit according to claim 1. An arithmetic device that performs an IFFT operation on a predetermined number of input signals modulated by a predetermined modulation method using an OFDM method,
A butterfly operation circuit for performing a butterfly operation of the number of stages corresponding to the number of points for the input signal;
A clip processing circuit that performs clip processing on the result of the butterfly computation at each stage;
The butterfly operation circuit performs bit shift at a preset stage based on the modulation method.
An arithmetic device characterized by that. An arithmetic method for performing a predetermined number of FFT operations on an input signal modulated by a predetermined modulation method using the OFDM method,
A butterfly calculation step for performing butterfly calculation of the number of stages corresponding to the number of points for the input signal;
A clip processing step for performing clip processing on the result of the butterfly computation at each stage,
In the butterfly calculation step, bit shift is performed at a preset stage based on the modulation method.
An arithmetic method characterized by the above. An arithmetic method for performing an IFFT operation on a predetermined number of input signals modulated by a predetermined modulation method using an OFDM method,
A butterfly calculation step for performing butterfly calculation of the number of stages corresponding to the number of points for the input signal;
A clip processing step for performing clip processing on the result of the butterfly computation at each stage,
In the butterfly calculation step, bit shift is performed at a preset stage based on the modulation method.
An arithmetic method characterized by the above.

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