JP3790514B2 - Pseudo random sequence generation system - Google Patents

Description

  The present invention generally relates to wireless communication systems. More specifically, the present invention relates to a TDD (time division duplex) system and an FDD (frequency division duplex) system that spread data for transmission using an OVSF (orthogonal variable spreading factor) code and a Hadamard code. Includes an improved system for generating OVSF and Hadamard code.

  Many types of communication systems, such as FDD communication systems and TDD communication systems, use one or more pseudo-random code sequences to spread data for transmission. Such codes are used in various places throughout the system on both the sending and receiving sides. Commonly used code sequences include OVSF codes and Hadamard codes.

FIG. 1 illustrates a code tree of an OVSF code that maintains orthogonality between different channels. The OVSF code can be defined using the code tree of FIG. 1, and the channelization code is uniquely described as C _{ch, SF, k} . Here, SF is a code spreading coefficient, k is a code number, and k ≦ SF−1. Each level of the code tree defines a channelization code of length SF corresponding to the spreading factor of SF of FIG.

  The channelization code generation method is defined as follows.

  The rightmost value of each channelization codeword corresponds to the first transmitted chip in time. The OVSF code used depends on the spreading factor, the number of channels used and the channel type.

  One method for generating the OVSF code is to use the mathematical description described above. However, operating such a matrix is computationally expensive and requires extremely fast and expensive hardware to perform. In addition, for such purposes, if the computing device is fixed in hardware, it is usually not possible to use it for other purposes. This complicates the system, resulting in an unnecessarily complex and expensive overall system design.

  Therefore, there is a need for convenient means for generating OVSF codes quickly and efficiently. Such means are also preferably adaptable to the generation of other types of code such as Hadamard sequences.

  The present invention includes a system and method for quickly and efficiently generating OVSF code using a register that holds the identification information of a code tree branch of the desired code and a counter that orders the branches. The system of the present invention generates code on demand and requires very few hardware resources.

  Furthermore, the system and method of the present invention can be adapted to generate Hadamard sequences.

  A presently preferred embodiment will be described with reference to the drawings. In the figures, similar elements are indicated with similar reference numbers. In addition, a preferred embodiment of the present invention is described with reference to OVSF code and Hadamard code generation. However, it will be apparent to those skilled in the art that the same principles can be applied to other code sequences, and the present invention is not limited to only the exemplary embodiments described herein.

  FIG. 2 will be described. FIG. 2 illustrates a system 10 that generates a pseudo-random sequence. The system 10 includes a bit position counter 12, a multiplexer 14, a spreading factor selector 16, a bit-by-bit AND gate 18, an index selector 20, and an XOR gate 22. The counter 12 is a free running binary counter and supplies its output to the first input of the multiplexer 14. The counter 12 is initialized to 0 and operates “freely” when the desired OVSF code is generated. Code generation is repeated as many times as necessary to spread the data. For each code generation, the counter is initialized to zero. Alternatively, the counter 12 can be free run ignoring the most significant bits that are not used. This alternative method will be described in detail later.

  The spreading factor selector 16 provides an output to the second input terminal of the multiplexer 14 that identifies how many bits from the counter 12 should be output. When generating the OSVF code, the multiplexer 14 reverses the order of the output bits so that the output bits are output in reverse order. This can be done by connecting the multiplexers 14 in FIGS. 3A and 3B with broken lines.

  FIG. 2 will be described again. The index selector 20 outputs an index, that is, binary identification information of a “branch” of the code tree. For example, as shown in FIG. 1, it is desirable that the spreading coefficient is 4, and when the third branch of the code tree is to be generated, the index selector 20 displays a 2-bit value representing the numerical value 2. 10 which is a binary number sequence is output. Similarly, it is desirable that the spreading coefficient is 8, and when the fourth branch of the code tree is to be generated, the index selector 20 is a 3-bit binary sequence indicating the numerical value 3. Some 011 is output.

  The output of the index selector 20 and the output of the multiplexer 14 are ANDed by a bit-by-bit AND gate 18. The result of this AND operation is output to an XOR gate 22, which is actually an XOR “tree” with multiple XOR gates well known to those skilled in the art.

The system 10 according to the present invention is illustrated in detail in FIGS. 3A and 3B, which is configured to be functionally different depending on the desired diffusion coefficient. 3A and 3B, the multi-bit outputs C _{1 to} C _N from the counter 12 and the multi-bit outputs I _{1 to} I _M from the index selector 20 are shown. FIG. 3A will be described. If it is desired to set the spreading factor to 4, the spreading factor selector 16 causes the multiplexer 14 to output only the desired bit from the first two bits “position” C ₁ and C _{2 of the} counter 12 to the AND gate 18. Bit positions C ₃ -C _N from the counter 12 are essentially “zeroed out” or ignored. Each desired bit is fetched in reverse order from the counter 12 and ANDed with the desired bit from the index selector 20 and bit-by-bit. For example, the bit from the first bit position C ₁ of the counter 12 is ANDed with the second bit I ₂ from the index selector 20. The bit from the second bit position C ₂ of the counter 12 is ANDed with the first bit I ₁ from the index selector 20. Once the bits from all desired bit positions of the counter 12 are ANDed with the desired bit from the index selector 20 bit by bit, the AND gate 18 outputs the operation result to the XOR gate 22. . The output of the XOR gate 22 is a code sequence having the desired bit. When the counter 12 is ordered, each bit of the code sequence is newly generated.

A second example shown in FIG. 3B will be described. If it is desirable for the spreading factor to be 8, the multiplexer 14 outputs the bits from the _{first through} third bit positions C ₁ , C ₂ , and C ₃ of the counter 12 to the AND gate 18. . The bit from the first bit position C ₁ of the counter 12 is ANDed with the third bit I ₃ from the index selector 20. Similarly, the bit from the second bit position C ₂ of the counter 12 is ANDed with the second bit I ₂ from the index selector 20. Finally, the bit from the third bit position C ₃ from the counter 12 is ANDed with the first bit I ₁ from the index selector 20. Once the bits from all the desired bit positions of the counter 12 are ANDed with the desired bits from the index selector 20 bit by bit, the AND gate 18 outputs the operation result to the XOR gate 22. To do. The output of the XOR gate 22 becomes the desired code sequence.

  The system 10 made in accordance with the present invention can be used to generate OVSF codes with any length of spreading factor, but for ease of explanation, the above example has a spreading factor of 8. A case will be described. In this example, as shown in FIG. 4, a 3-bit diffusion coefficient selector 16, a 3-bit counter 12 for ordering bits, a 3-input AND gate 18, and a 3-input XOR gate 22 are required. In this example, the following Tables 1 to 3 are also referred to.

In this example, the generated code sequence preferably has a spreading factor of 8 and comprises the seventh branch of the code tree marked with an asterisk in FIG. This is identified in FIG. 1 as C _ch8,6 , ie 1, -1, -1, 1, 1, -1, -1, -1. It can be seen from Table 1 that the desired number of bits is 3 because the desired spreading factor is 8. Since the seventh branch of the code tree is generated, it can be seen from Table 2 that the index selector output is a binary sequence of 1, 1, 0. Next, as shown in Table 3, the binary counter 12 orders the binary count from 0 (0, 0, 0) to 7 (1, 1, 1).

The first bit of the sequence C _{ch, 8,6} includes 000 which is a binary sequence from the counter 12 (the inverted result is also 000) and 110 which is a binary sequence from the index selector 20. The bit-by-bit AND operation is performed. The bit obtained by the AND operation is XORed, and 0 of the operation result is output. The second input 001 is inverted and the resulting 100 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, resulting in 100. The bit obtained by the AND operation is XORed and the obtained 1 is output. Similarly, the third input 010 is inverted, and the obtained 010 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed. 1 of the XOR operation result is output. The fourth input 011 is inverted and the obtained 110 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed, and this XOR operation The result 0 is output. The fifth input 100 is inverted, and the obtained 0001 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed. The result 0 is output. The sixth input 101 is inverted, and the obtained 101 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed, and this XOR operation The result 1 is output. The seventh input 110 is inverted, and the obtained 001 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed. This XOR operation The result 1 is output. Finally, the eighth input 111 is reversed, and the obtained 111 and the binary sequence 110 from the index selector 20 are ANDed bit by bit, and the obtained bit is XORed. 0 of the XOR operation result is output.

  This iterative process results in a sequence output of 0, 1, 1, 0, 0, 1, 1, 0 (note that the rightmost bit is generated first in time). These output values are then mapped with output 1 to -1 and output 0 to 1. Therefore, the sequences used for spreading are 1, -1, -1, 1, 1, -1, -1, 1. This is consistent with the seventh branch of the OSVF code tree shown in FIG.

Note that the structure shown in FIG. 5 can be expanded to any desired number of inputs. Alternatively, the system can be “expanded in scale” as shown in FIG. 5, and by extending the scale, unnecessary counter 12 and index selector 20 bits are essentially ignored. As shown in FIG. 5, since the necessary bits are four bits C _{1 to} C ₄ , the bits C _{5 to} C _N are not allowed to pass through the multiplexer 14 or are zeroed out. In addition, only the desired bits C ₁ -C ₄ are reordered by the multiplexer 14. Similarly, only bits I1-I4 are “processed” by the AND gate. This is because there is no input from the corresponding bit C ₅ -C _N, because other parts of the AND gate is zero-out. The output from the XOR gate 22 becomes the bits of the desired code sequence.

  FIG. 6 illustrates a Hadamard sequence code tree. The code tree code is generated by the alternative embodiment of the invention shown in FIG.

  FIG. 7 shows a system 100 that generates several types of pseudo-random sequences. Similar to the embodiment shown in FIG. 2, the system 100 includes a bit position counter 12, a multiplexer 14, a spreading factor selector 16, a bit-by-bit AND gate, an index selector 20, and an XOR gate 22. . However, this embodiment includes a mode switch 60 that switches between a first mode for generating an OVSF code and a second mode for generating a Hadamard code. When the mode select switch 60 is in the first position, the system 100 operates in the same manner as the system 10 shown in FIG. 2 and the multiplexer 14 reverses the bit order of the bits output from the bit position counter 12. . On the other hand, when the mode selection switch 60 is in the second position, the multiplexer 14 passes the bits output from the bit position counter 12 directly to the bit-by-bit AND gate 18 without changing the order thereof. This is shown in FIG. In FIG. 8, the broken lines in the multiplexer 14 indicate that the bits pass through the multiplexer 14 without being reordered.

  An example of generating a Hadamard code will be described with reference to FIG. In this example, the generated code sequence preferably has a spreading factor of 8 and comprises the fourth branch of the code tree marked with an asterisk in FIG. This sequence is illustrated as 0, 1, 1, 0, 0, 1, 1, 0 in FIG. Since the desired diffusion coefficient is 8, it can be seen that the desired number of bits is from Tables 1 to 3. Since the fourth branch of the code tree is generated, it can be seen that the output of the index selector is a binary sequence of 0, 1, 1 as shown in Table 2. Next, as shown in Table 3, the binary counter 12 orders the binary counts 0 (0, 0, 0) to 7 (1, 1, 1).

  The processes of the AND operation and the XOR operation are the same processes as described for the generation of the OVSF code except that the bits from the counter 12 are not reversed. Then, the output from the system 100 is 0, 1, 1, 0, 1, 1, 0. This exactly matches the fourth branch of the Hadamard code pre-structure shown in FIG. The output from the system 100 can optionally map output 1 to -1 and output 0 to 1.

  FIG. 9 shows a second alternative form of system 200 that generates several types of pseudo-random sequences. The system 200 includes an index selector 20, a bit-by-bit AND gate 18, and an XOR 22. However, the bit position counter 12, the multiplexer 14, and the diffusion coefficient selector 16 are replaced with a numerical value generator 202 and a selector 204. The numerical value generator 202 stores the numerical values of a predetermined sequence, for example, the numerical values in Table 3, and sequentially outputs those numerical values. Therefore, can the numerical value generator 202 sequentially output the numerical values in Table 3? Alternatively, the “reordered” sequence of bits shown in Table 4 can be output. The selector 204 can select which bit sequence is output by the numerical value generator 202. In the case of the OVSF code, the first sequence is output, and in the case of the Hadamard code, the second sequence is output. In this embodiment, it is necessary to use additional memory, but this additional memory capacity is less than the memory capacity required when the entire pseudo-random sequence code tree is stored. In addition, although a pseudo random code having a spreading coefficient of 8 has been described in the present embodiment, any desired sequence can be stored in the numerical value generator 202.

  As mentioned above, although preferred embodiment of this invention was described, it is remarkable for those skilled in the art that other various deformation | transformation aspects do not deviate from a claim.

It is a figure which shows the code tree by a prior art of an OVSF code | symbol. 1 is a diagram showing a system for generating an OFSF code according to the present invention. FIG. It is a figure which shows the system which produces | generates an OVSF code when a spreading | diffusion coefficient is 4. FIG. It is a figure which shows the system which produces | generates an OVSF code when a spreading | diffusion coefficient is 8. It is a figure which shows the production | generation of the 7th code | symbol of an OVSF code tree when a spreading | diffusion coefficient is 8. FIG. It is a figure which shows the extensibility of a structure. It is a figure which shows the code tree by a prior art of Hadamard code. FIG. 6 illustrates an alternative embodiment of the present invention that generates both Hadamard code and OVSF code. It is a figure which shows the production | generation of the 4th code | cord | chord of a Hadamard code | cord | chord when a spreading | diffusion coefficient is 8. FIG. FIG. 6 shows a second alternative embodiment of the present invention for generating pseudo-random codes.

Claims (11)

In a system for generating OVSF code,
A binary counter that outputs a binary count value that is a sequential M-bit binary number;
Order changing means for selectively changing the bit order of the binary count value from the least significant bit to the most significant bit;
A logical reduction means having an index selector that outputs M-bit binary identification information of the OVSF code, a first input from the binary counter, a second input from the index selector, and an output. And a logical reduction means for outputting a desired OVSF code from the output. In a code generator that generates a binary code consisting of 2 ^M bits,
A counter that outputs in parallel M-bit count values that are sequentially incremented by one;
An index selector for outputting M-bit code identifiers in parallel;
A parallel array of M logic gates each having an output, a first input that is a count value output from the counter, and a second input that is a code identifier output from the index selector;
Each time the M-bit count value is input to the parallel array of logic gates from the counter so that a binary code identified by the M-bit code identifier is generated after 2 ^M iterations. And a reduction network of logic gates associated with the output of the parallel array of logic gates to output a single code bit.   3. The bit order changing means coupled to an output of the counter according to claim 2, wherein the bit order changing means receives an M-bit count value, and the M-bit count value is changed from the least significant bit to the most significant bit. A code generator, further comprising bit order changing means for ordering and changing the order from the most significant bit to the least significant bit. In a system for generating a desired pseudo-random code,
A binary counter that outputs a plurality of M-bit serial binary numbers;
An index selector that outputs an M-bit code identifier of the desired pseudo-random code;
At least M logic gates each having a first input from the binary counter, a second input from the index selector, and an output;
A system comprising: an XOR tree for performing an XOR operation on the output of the logic gate and thereby outputting the desired pseudo-random code.   5. The system according to claim 4, further comprising bit order changing means for changing the order of the bits of the binary count so that they are in order from the least significant bit to the most significant bit. A code generator for generating a binary code included in a set of binary codes having N M-bit binary codes,
A counter that sequentially increments and outputs an M-bit binary number by one;
An index selector for outputting an M-bit code;
A logic gate array having a first input from the counter, a second input from the index selector, and an output;
A reduction network of logic gates associated with the output of the logic gate array, wherein the binary code identified by the M-bit code identifier is generated from the counter so that it is generated after 2 ^M iterations. A code generator comprising: a logic gate reduction network that outputs a single code bit each time an M-bit count value is input to the logic gate array.   7. Bit order changing means coupled to the output of said counter, said bit order changing means receiving an M-bit binary number having bits ordered from least significant bit to most significant bit, comprising: A code generator, further comprising bit order changing means for changing the order of the bits in order from the least significant bit.   8. The switch according to claim 7, wherein the switch is connected to the bit order changing means, and when the switch is located at the first position, the bit order changing means is connected to the output of the counter, A switch for changing the order and disconnecting the bit order changing means from the output of the counter so as not to change the order of the binary bits when the switch is in the second position; A code generator characterized by comprising. In the code generator for generating a binary code in the set of binary codes 2 ^M bits,
A binary generator for outputting M-bit binary numbers contained in a predetermined sequence of binary numbers;
An index selector for outputting an M-bit code identifier;
A parallel array of M logic gates each having an output, a first input that is one bit of the binary number, and a second input that is one bit of the code identifier;
A reduced network of logic gates associated with the output of the parallel array of M logic gates, such that a binary code identified by the M-bit code identifier is generated after 2 ^M iterations. A code generator comprising: a logic gate reduction network that outputs a single code bit each time a binary number is input to the parallel array of M logic gate arrays. 10. The code generator according to claim 9 , wherein the predetermined sequence is a binary sequence, and each binary number is incremented by 1 bit from the previous binary number. In a system that generates the desired OVSF code,
A binary generator that outputs a predetermined sequence of M-bit binary numbers;
An index selector that outputs an M-bit code identifier of the desired OVSF code;
At least M logic gates each having a first input from the binary generator, a second input from the index selector, and an output;
A system comprising: an XOR tree for outputting the desired OVSF code by XORing the output.

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