JP3781083B2 - Correlator - Google Patents

Description

だだし、ψ₁＝０，π ψ₂＝０，π
で表される。
【０００６】
ψ₁とψ₂はそれぞれ送信シンボルを位相で表したものであり、a(t)はＰＮ系列信号、A/2^1/2はキャリアの振幅、ωはキャリアの角周波数、θ₁はキャリアを掛け合わせるときに発生する位相オフセットである。また、式(1)は三角関数の定理から以下のように書き直すことができる。
E(t)＝a(t)・Acos（ωt＋ψ＋θ₂） ・・・(2)
だだし、θ₂＝π/4＋θ₁
ψ＝０，π/2，π，3π/2
これが受信機に入力されるので、この信号Ｅを図１０に入力信号源５１として表す。
【０００７】
受信機側では、この信号Ｅは２経路に分けられ、それぞれ周波数ミキサ５２，５３に入力される。５４はローカル信号源であり、位相検波器５５を利用して例えばコスタスループ等の手法により、キャリア位相に対して同期のとれた正弦波信号
IL1(t)＝cos（ωt＋θ₁） ・・・(3)
を発生する。
【０００８】
ミキサ５２はローカル信号源５４から信号IL1をそのまま入力し、ミキサ５３には同信号IL1を９０度移相器５６によって９０度位相をずらせた正弦波信号
QL1(t)＝sin（ωt＋θ₁） ・・・(4)
を入力して、それぞれ入力信号Ｅに掛け合わせる。
【０００９】
この結果、２つのミキサ５２，５３の出力には、それぞれ以下の信号がえられる。

【００１０】
これをローパスフィルタ５７，５８を用いることにより２ωｔの高周波項を除去する。ψ₁＝０，π、ψ₂＝０，πであることから、
sin（ψ₁)＝sin（ψ₂）=0 ・・・(7)
であるから、
ILPF(t)=(1／２^3/2）A・a(t)cos（ψ₁) ・・・(8)
QLPF(t)=(1／２^3/2）A・a(t)cos（ψ₂) ・・・(9)
のベースバンド信号が得られる。
【００１１】
これらを図１０に示した相関器（matched filter）５９，６０にかけることにより、送信機で掛け合わされたＰＮ系列を除去する。相関器は、田近，”スペクトラム拡散におけるデジタルマッチドフィルタ技術とその問題点”，信学技報等に詳しいが、変調に使用したＰＮ系列で重み付けされ、１シンボル周期に１度相関ピークと呼ばれるパルスを出力する一種の時間領域フィルタである。出力されるパルスの極性は、式(8)、式(9)のψ₁とψ₂によって決定されるので、この相関ピークの極性をもとに送信シンボルを復調することができる。
【００１２】
なお、一般に受信機側で送信機の絶対位相を知ることは困難であることから、前後のシンボル変化を差動信号によって表現して変調する場合が多い。このような変調方式はDQPSKと呼ばれる。
【００１３】
【発明が解決しようとする課題】
以上説明した従来技術は、以下に述べる問題を有している。
（１）受信機はミキサ５７，５８や９０度移相器５６といった集積化の難しい素子を含んでおり、小型化、低消費電力化の妨げとなる。
（２）一般にスペクトラム拡散通信は、Ｃ／Ｎ比の低い環境で使われるので、キャリアに対する同期をとることがしばしば技術的に困難となる。
（３）無線ＬＡＮ等の短いパケットを何回にもわたってやりとりするアプリケーションを想定した場合、システムとして高速な同期捕捉が必要になる。従来の技術で示したようなキャリア同期を必要とする受信機では、キャリア同期確立に要する時間が、システム全体のスループットを低下させるおそれがある。
【００１４】
本発明は以上のような点に鑑みてなされたものであり、その目的は、キャリアから直接的に位相情報を抽出できるようにし、ミキサや９０度移相器を不要にして集積化し易くし、またキャリア同期をとる必要を無くしてＣ／Ｎ比の低い環境下であっても復調を可能にし、更に同期捕捉を高速化してスループットを向上させた相関器を提供することである。
【００１５】
【課題を解決するための手段】
上記目的を達成するための第１の発明は、入力信号の瞬時値をキャリア周期の４倍数分の１の周期で離散的に抽出する信号抽出器と、該信号抽出器の出力に接続され１タップ当たりの遅延量が入力信号のキャリア周期の４倍数分の１である離散的な遅延線とを具備し、前記遅延線の１シンボル期間に相当する複数のタップの内から前記入力信号のキャリアの半周期毎の信号を取り出して、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第１の中間相関出力とし、該第１の中間相関出力を得るために使用したタップから前記入力信号のキャリアの４分の１周期相当ずれたタップの信号を取り出して、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第２の中間相関出力とし、前記第１の中間相関出力を得るために使用したタップから１シンボル期間前又は後にずれた複数のタップの信号を取り出して、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第３の中間相関出力とし、該第３の中間相関出力を得るために使用したタップから前記入力信号のキャリアの４分の１周期相当ずれたタップの信号を取り出して、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第４の中間相関出力とし、前記第３と第４の中間相関出力の和と前記第１の中間相関出力との積を第１の相関出力とし、前記第３と第４の中間相関出力の和と前記第２の中間相関出力との積を第２の相関出力とするよう構成した。
第２の発明は、入力信号の瞬時値をキャリア周期の４倍数分の１の周期で離散的に抽出する信号抽出器と、該信号抽出器の出力に接続され１タップ当たりの遅延量が入力信号のキャリア周期の４倍数分の１である離散的な第１の遅延線と、遅延量が１シンボル期間に相当する第２の遅延線とを具備し、前記第１の遅延線の１シンボル期間に相当する複数のタップの内から前記入力信号のキャリアの半周期毎の信号を取り出し、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第１の中間相関出力とし、該第１の中間相関出力を得るために使用した前記第１の遅延線のタップから前記入力信号のキャリアの４分の１周期相当ずれたタップの信号を取り出し、それら各々をＰＮ系列の重みで乗算し該乗算結果を加算して第２の中間相関出力とし、前記第１の中間相関出力と前記第２の中間相関出力との和を前記第２の遅延線に入力して、前記第２の遅延線の出力を第３の中間相関出力とし、前記第３の中間相関出力と前記第１の中間相関出力との積を第１の相関出力とし、前記第３の中間相関出力と前記第２の中間相関出力との積を第２の相関出力とするよう構成した。
第３の発明は、第１又は第２の発明において、前記信号抽出器をＡ／Ｄ変換器で構成し、前記遅延線を複数のフリップフロップからなるシフトレジスタで構成した。
第４の発明は、第１又は第２の発明において、前記信号抽出器を電荷抽出回路で構成し、前記遅延線をＣＣＤで構成した。
第５の発明は、第１又は第２の発明において、前記信号抽出器をトランジスタ又はダイオード等のゲート素子とメモリキャパシタからなるサンプルホールド回路で構成し、前記遅延線をトランジスタ又はダイオード等のゲート素子とメモリキャパシタからなる複数のサンプルホ−ルド回路を遅延素子として構成した。
第６の発明は、第１又は第２の発明において、前記信号抽出器をカレントミラー回路とスイッチング回路からなる電流型サンプルホールド回路で構成し、前記遅延線をカレントミラー回路とスイッチング回路からなる複数の電流型サンプルホールド回路を遅延素子として構成した。
【００１６】
【発明の実施の形態】
［第１の実施の形態］
図１は本発明の第１の実施の形態の相関器を示す図である。この例では、１チップ当たりのキャリア数が１波で、１チップ当たり４サンプリングのデジタル相関器を示している。１は従来の技術で示した信号原５１と同じ入力信号Ｅの信号源であって、チップ長ＬｃのＰＮ系列で直接拡散され、さらにキャリア角周波数ωでQPSK変調されたDS-SS信号を発生する。２はA/D変換器（信号抽出器）であって、キャリア周波数の４倍のレートでA/D変換を行う。３，４は各々総遅延量が１シンボル周期に相当する離散的遅延線であり、入力端子IN1，IN2と遅延信号出力端子OUT1，OUT2の他に、２つの中間相関信号出力端子IOUT1とQOUT1，IOUT2とQOUT2を持っている。遅延線３，４の構成については後述する。
【００１７】
遅延線３の出力端子OUT1の遅延信号は遅延線４の入力端子IN2に入力する。遅延線４の出力端子IOUT2，QOUT2から得られる中間相関信号が加算器５によって加算される。また遅延線３の出力端子IOUT1から得られる中間相関信号と加算器５の出力信号を乗算器６によって乗算し、遅延線３の出力端子QOUT1から得られる中間相関信号と加算器５の出力信号を乗算器７によって乗算して、相関器の最終的な相関出力信号をIOUT、QOUTとして取り出す。
【００１８】
図２は遅延線３の詳細な構成を示す図である。遅延線４も同じであるので、ここでは遅延線３を代表して説明する。３１はシフトレジスタを構成する遅延器（フリップフロップ）であり、１タップあたりキャリア周期の1/4の時間の遅延を行う。A/D変換器２で変換されたデータは、１クロックにつき、１タップづつ順次後段に送られていく。各タップのデータは、外部から参照することができ、キャリア周期の1/4毎に相当するステージのデータ毎に交互に２系統に振り分けて出力される。ここでは、ちょうど遅延量がキャリア周期の1/4であるため、１つおきに２系統に分けている。
【００１９】
２つの系統に分けた信号は、それぞれ後ろから順にＰＮ系列で重み付けされた正負の値を乗算器３２で掛け合わせた上で、加算器３３，３４により総和をとり、それぞれ中間相関信号として出力端子OUT1、QOUT1に出力している。ＰＮ系列による重み付けは、本例の場合、あるチップの符号が1(＝+1)の場合は後ろから順に{+1,-1}、そのチップの符号が0(＝-1)の場合は後ろから順に{-1,+1}で行っている。符号の反転を厭わなければ他の組合せで重み付けしても良い。
【００２０】
以上のように、本実施の形態の相関器では、キャリア周期の1/4の周期で離散的に信号を取り出すA/D変換器２と、キャリア周期の1/4の周期で遅延信号を取り出す遅延タップを持ち且つ各々が１シンボルを格納できる遅延線３，４とを用いる。遅延線３では１個おきのタップからキャリア周期の半周期毎の信号を取り出し、これにＰＮ系列の重み付けをした後に同相相関をとることによって、出力端子IOUT1から同相成分の中間相関出力を得、また、残りのタップからキャリア周期の1/4周期相当ずれた信号を取り出し、これにＰＮ系列の重み付けをした後に直交相関をとることによって、出力端子QOUT1から直交成分の中間相関出力を得る。また、１シンボル前の信号について、遅延線４において同様にして出力端子IOUT2、QOUT2から同相、直交成分の中間相関出力を得る。そして、出力端子IOUT2，QOUT2の加算信号と出力端子IOUT1の信号と乗算信号を同相成分の出力信号IOUTとし、出力端子IOUT2，QOUT2の加算信号と出力端子QOUT1の信号と乗算信号を直交成分の出力信号QOUTとするものである。
【００２１】
最終的な２個の相関出力信号IOUT、QOUTから発生するパルス列について、キャリアとサンプリング時刻の位相差により形状が変化する。しかしながら、その積分値はほぼ一定であり、極性も送信信号の差分により決定される。したがって、このパルス列に適切なローパスフィルタをかけることにより得られるパルスの極性から、送信シンボルの差分を求めることができる。また、この過程において信号キャリアに対して同期をとる必要はない。
【００２２】
以下、回路動作の詳細を計算を交えながら見ていく。入力信号源Ｅは従来例で説明したものと同じであり、その信号e(t)は、式(2)より、
e(t)＝ａ(t)・Acos（ωt＋ψ＋θ₂） ・・・(2)'
ψ＝｛０，π/2，π，3π/2｝
【００２３】
これをA/D変換器２においてキャリア周波数の４倍でサンプリングすると、遅延線３の内部（ｎ番目のタップ）には以下の数列が得られる。
C(n)＝ａ(n＋π）・Acos（ω/4・（n＋τ）＋ψ(t)＋θ） ・・・(10)
ここで、τは、各遅延器３１のタップで重み付けした固定符号と、その時点で遅延線の内部に蓄積されているシンボルとの位相差（ずれ）であり、整数値をとる。θはA/D変換時に発生するA/D変換クロックとキャリアとの位相差に、式(2)'で表された送信機でのオフセットθ₂を足し合わせたもので、０〜２πの間の実数値をとる。
【００２４】
DS-SS信号の相関ピークは、τがほぼ０、即ち、遅延線にほぼ１シンボルが格納されたときのみ発生する。従って、相関ピークが発生する前後では、遅延線３は最新のシンボルψ₀、遅延線４は１つ前のシンボルであるψ_-1で満たされていると近似的に見なして良い。
【００２５】
今は、キャリアから直接位相情報を抽出しているので、自己相関関数Ｒ（τ）にキャリアの瞬時値をかけたものが、遅延線３、４に格納されていることになる。そこで、各遅延器３１からなる遅延器群の出力をτの関数として計算してみよう。
【００２６】
遅延線３の出力端子IOUT1の出力信号Icorr1（τ）は、ＰＮ系列の自己相関関数 Ｒ（τ）＝Σa(n)・a(n＋τ） ・・・(12)
を使って以下のように書くことができる。

ここで、LcはＰＮ系列のチップ長である。
【００２７】
同様に、遅延線３の出力端子QOUT1の出力信号Qcorr1（τ）、遅延線４の出力端子IOUT2の出力信号Icorr2（τ）、遅延線４の出力端子QOUT2の出力信号Qcorr2（τ）を求めると、次のようになる。
Qcorr1（τ）＝２Lc・A・R（τ）・cos（ω/4・τ＋π/2＋ψ₀＋θ）・・・(14)
Icorr2（τ）＝２Lc・A・R（τ）・cos（ω/4・τ＋ψ_-1＋θ） ・・・(15)
Qcorr2（τ）＝２Lc・A・R（τ）・cos（ω/4・τ＋π/2＋ψ_-1＋θ） ・・・(16)
【００２８】
よって、相関器の最終的な出力端子IOUTに現れる信号Ｉ（τ）は、

ただし、Ｋ＝８（Lc・Ａ）²とした。
【００２９】
同様に、出力端子QOUTに現れる出力信号Ｑ(τ)も、

と計算される。
【００３０】
よく設計されたＰＮ系列の自己相関関数は、図３の(a)に示すように、１チップ周期を半値幅とした三角波形状となることが知られている。ここでは、後の計算の便宜上、自己相関関数Ｒ（τ）が以下のようになるＰＮ系列a(n)を以下のように定義する。

ここで、定義したＰＮ系列の自己相関関数Ｒ（τ）を図３の(ｂ)に示しておく。
【００３１】
τ≧３，τ≦−３ではＩ(τ）、Ｑ（τ）は０であるから、−２≦τ≦２の範囲で、Ｉ(τ）とＱ（τ）を計算すると、次にようになる。

これらの出力は、キャリアに対する同期をとっていないため、オフセットθの値により出力パルス列は図４のごとく変化する。この図４はＩ(-2)からＩ(+2)の値を、ψ₀＝ψ_-1＝０の場合について求めたものである。
【００３２】
次にこれらのパルス列の総和をとってみると、三角関数の公式から
cos（ｘ−π/2）＝−cos（ｘ＋π/2）
cos（ｘ＋3π/2）＝−cos（ｘ＋π/2）
cos（ｘ＋π）＝−cosｘ
であることを考慮して、

となる。
【００３３】
例えば、式(30)にψ₀＝ψ_-1＝０を代入すると、

となり、右辺第２項と第４項は互いにキャンセルし、cos（θ＋π/2）＝−sin（θ）であるから、

【００３４】
このようにψ₀とψ_-1に｛０，π/2，π，−π/2｝の内の任意のデータを代入すると、式(30)と式(31)の右辺中括弧の中の４つの項のうち２つは、＋cosθ・sinθと、−cosθ・sinθの関係になり、互いにキャンセルする。残る項の２つは、＋cos²θと＋sin²θ、又は−cos²θと−sin²θの関係になる。結果として式(30)と式(31)の右辺中括弧の中身は、θの値にかかわらず、+1又は-1の値しかとることができない。同様に、ΣＱ（τ）についても、

となる。
ΣＩ（τ）とΣＱ（τ）の極性は、ψ₀とψ_-1の差（ψ₀−ψ_-1）に応じて図５に示す値をとる。図５において、Posは正数、Negは負数を表す。
【００３５】
ここで、Ｉ（τ）、Ｑ（τ）で表されるパルス群に、適切なローパスフィルタをかけることにより、時間的に連続で振幅がほぼ一定なパルスを得ることができる。このパルスの極性は、図５に示したψ₀とψ_-1の関係に一致しており、ψ₀とψ_-1の差分、すなわち、送信データが復調できることは、当業者であれば容易に理解できよう。
【００３６】
なお、以上の計算では、ＰＮ系列の自己相関関数が図３の(b)もしくは式(19)のごとくなると仮定した。検証のため、より実際に近いと考えられる図３の(a)の三角波分布についても計算してみる。ＰＮ系列の自己相関関数を、

とした場合、出力端子IOUT,QOUTに出力するパルスの時間積分ΣＩ（τ）、ΣＱ（τ）は以下のようになる。
【００３７】

であり、右辺中括弧の中身に係数を持つ。
【００３８】
このため、ΣＩ（τ）、ΣＱ（τ）の絶対値は、θの値によって変動し、式(36)と式(37)の中括弧の中身の絶対値は0.8〜1.0の値をとる。しかしながら、その極性は図５のものと一致しており、現実の相関器でも、式(30),(31)で示した内容が近似的に成立しているものと考えることができる。また、絶対値の変動幅は、１チップあたりのサンプリング数を8,12,16，・・・と４の整数倍分に増やしていくことにより、小さくなっていく。例えば、サンプリング数が８の場合には、変動幅は21/22〜１の間をとり、サンプリング数が16の場合には変動幅は85/86〜１の間をとる。
【００３９】
［第２の実施の形態］
本発明の第２の実施の形態を図６に示す。この実施の形態では、あらかじめ遅延線３の出力端子IOUT1、QOUT1の相関信号の和を加算器５でとって、遅延線４の入力端子IN2に入力している。そして、この遅延線４の出力端子OUT2の遅延信号をあらためて遅延線３の出力端子IOUT1、QOUT1の相関信号とそれぞれ乗算器６，７で乗算し、最終的な相関出力IOUT、QOUTを得ている。この方法でも、第１の実施の形態の場合と同じ作用効果を得ることができる。また、図６からも明らかなように、遅延線４の信号相関出力は不要となる。従って、遅延線４の内部の信号参照手段、乗算器、加算器等を省略できるので、図１の構成に比べて回路規模を小さくすることができる
【００４０】
［第３の実施の形態］
本発明の第３の実施の形態を図７に示す。この実施の形態では、図１に示した遅延線３，４を使用したディジタル相関部を、CCD（Charge Coupled Device)遅延線８，９を使用した相関部に置き換え、入力信号に接続したA/D変換器２を電荷抽出回路１０に置き換えたものである。電荷抽出回路１０における抽出とCCD遅延線８，９における電荷転送はキャリア周波数の1/4のレートで行われる。なお、この第３の実施の形態においても、第２の実施の形態と同様の置き換えが可能である。
【００４１】
［第４の実施の形態］
本発明の第４の実施の形態を図８に示す。この実施の形態では、図１に示した遅延線３，４によるディジタル相関部を、トランジスタやダイオード等のゲート素子とメモリキャパシタからなる複数の電圧型サンプルホールド回路を遅延素子して使用した遅延線１１，１２による相関部に置き換え、入力信号に接続したA/D変換器２を、同様の構成で電圧型サンプルホールド回路１３に置き換えたものである。遅延線１１，１２における信号転送と電圧型サンプルホールド回路１３におけるサンプリングは、キャリア周波数の1/4のレートで行われる。この第４の実施の形態においても、第２の実施の形態と同様な置き換えが可能である。
【００４２】
［第５の実施の形態］
本発明の第５の実施の形態を図９に示す。この実施の形態では、図１に示した遅延線３，４によるディジタル相関部を、カレントミラー回路とスイッチング回路で構成された複数の電流型サンプルホールド回路を遅延素子として使用した遅延線１４，１５による相関部に置き換え、入力信号に接続したA/D変換器２を同様の構成の電流型サンプルホールド回路１６に置き換えたものである。遅延線１４，１５における信号転送と電流型サンプルホールド回路１６におけるサンプリングは、キャリア周波数の1/4のレートで行われる。この第５の実施の形態においても、第２の実施の形態と同様な置き換えが可能である。
【００４３】
以上の第３〜第５の実施の形態に示した回路は、時間的には離散的であるが、電圧信号に対しては連続的であるため、第１の実施の形態で示したディジタル相関器に比較して、量子化誤差による信号の劣化がないというメリットを持つ。
【００４４】
【発明の効果】
以上から本発明によれば、ミキサや９０度移相器等の集積化し難い素子が不要であり、キャリア同期をとる必要がなく、離散的な遅延線で構成された相関器を構成する事ができる。よって、その工業的価値は大きい。
【図面の簡単な説明】
【図１】 本発明の第１の実施の形態の相関器を示すブロック図である。
【図２】 遅延線を示すブロック図である。
【図３】 ＰＮ系列の自己相関関数の説明図である。
【図４】 オフセットθによるパルスの変動の説明図である。
【図５】 ΣＩ（τ）とΣＱ（τ）の極性の説明図である。
【図６】 本発明の第２の実施の形態の相関器を示すブロック図である。
【図７】 本発明の第３の実施の形態の相関器を示すブロック図である。
【図８】 本発明の第４の実施の形態の相関器を示すブロック図である。
【図９】 本発明の第５の実施の形態の相関器を示すブロック図である。
【図１０】 従来のQPSK変調されたDS-SS信号の復調回路を示すブロック図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a correlator for demodulating a DQPSK (Differential Quad Phase Shift Keying) modulated DS-SS (Direct Sequence-Spectrum Spreading) signal standardized by IEEE 802.11, for example. In particular, the present invention relates to a delay detection type correlator that can be demodulated without carrier synchronization.
[0002]
[Prior art]
A conventional method for generating a transmission signal of a QPSK (Quad Phase Shift Keying) modulated DS-SS signal and a demodulation method in a receiver will be described with reference to FIG.
[0003]
Transmission signal generation is performed in two stages. In the first stage, transmission data for one symbol is prepared by a set of 2 bits represented by +1 and -1, and a pseudo random signal represented by +1 and -1 is also called a PN sequence. Multiply and modulate. The minimum unit of the PN sequence is called one chip in the field of spread spectrum communication, and the chip period is 1 / integer of the symbol period. This integer is called the chip length.
[0004]
In the second stage, the two binary signals multiplied by the PN sequence are multiplied by two carriers that are orthogonal to each other, and the two carriers are added and transmitted.
[0005]
As a result, the transmitted signal e (t) is generally

However, ψ ₁ = 0, π ψ ₂ = 0, π
It is represented by
[0006]
ψ ₁ and ψ ₂ represent the transmission symbols in terms of phase, a (t) is the PN sequence signal, A / 2 ^1/2 is the carrier amplitude, ω is the carrier angular frequency, and θ ₁ is the carrier. This is the phase offset that occurs when multiplying. Equation (1) can be rewritten as follows from the trigonometric theorem.
E (t) = a (t) · Acos (ωt + ψ + θ ₂ ) (2)
However, θ ₂ = π / 4 + θ ₁
ψ = 0, π / 2, π, 3π / 2
Since this is input to the receiver, this signal E is represented as an input signal source 51 in FIG.
[0007]
On the receiver side, the signal E is divided into two paths and input to the frequency mixers 52 and 53, respectively. A local signal source 54 is a sine wave signal synchronized with the carrier phase by using a phase detector 55 by a method such as a Costas loop.
IL1 (t) = cos (ωt + θ ₁ ) (3)
Is generated.
[0008]
The mixer 52 inputs the signal IL1 from the local signal source 54 as it is, and the mixer 53 receives a sine wave signal whose phase is shifted 90 degrees by a 90-degree phase shifter 56.
QL1 (t) = sin (ωt + θ ₁ ) (4)
Are respectively multiplied by the input signal E.
[0009]
As a result, the following signals are obtained at the outputs of the two mixers 52 and 53, respectively.

[0010]
By using low-pass filters 57 and 58, the high frequency term of 2ωt is removed. Since ψ ₁ = 0, π and ψ ₂ = 0, π,
sin (ψ ₁ ) = sin (ψ ₂ ) = 0 (7)
Because
ILPF (t) = (1/2 ^3/2 ) A ・ a (t) cos (ψ ₁ ) (8)
QLPF (t) = (1/2 ^3/2 ) A ・ a (t) cos (ψ ₂ ) (9)
Baseband signals are obtained.
[0011]
By applying these to the matched filters 59 and 60 shown in FIG. 10, the PN sequence multiplied by the transmitter is removed. The correlator is familiar to Tajika, “Digital Matched Filter Technology in Spread Spectrum and its Problems”, IEICE Technical Report, etc., but weighted by the PN sequence used for modulation and called a correlation peak once per symbol period Is a kind of time domain filter that outputs. Since the polarity of the output pulse is determined by ψ ₁ and ψ ₂ in the equations (8) and (9), the transmission symbol can be demodulated based on the polarity of this correlation peak.
[0012]
In general, since it is difficult for the receiver side to know the absolute phase of the transmitter, symbol changes before and after are often expressed by differential signals and modulated. Such a modulation scheme is called DQPSK.
[0013]
[Problems to be solved by the invention]
The conventional technology described above has the following problems.
(1) The receiver includes elements that are difficult to integrate, such as the mixers 57 and 58 and the 90-degree phase shifter 56, and hinders miniaturization and low power consumption.
(2) Since spread spectrum communication is generally used in an environment with a low C / N ratio, it is often technically difficult to achieve synchronization with a carrier.
(3) When an application such as a wireless LAN in which a short packet is exchanged over and over is assumed, high-speed synchronization acquisition is required as a system. In a receiver that requires carrier synchronization as shown in the prior art, the time required to establish carrier synchronization may reduce the overall system throughput.
[0014]
The present invention has been made in view of the above points, and its purpose is to enable extraction of phase information directly from a carrier, making a mixer and a 90-degree phase shifter unnecessary, facilitating integration, Another object of the present invention is to provide a correlator that eliminates the need for carrier synchronization, enables demodulation even in an environment with a low C / N ratio, and further increases the synchronization acquisition speed to improve the throughput.
[0015]
[Means for Solving the Problems]
According to a first aspect of the present invention for achieving the above object, there is provided a signal extractor for discretely extracting an instantaneous value of an input signal at a period that is a quarter of a carrier period, and connected to an output of the signal extractor. A discrete delay line whose delay amount per tap is one-fourth of the carrier period of the input signal, and the carrier of the input signal among a plurality of taps corresponding to one symbol period of the delay line Are extracted from the taps used to obtain the first intermediate correlation output by extracting the signals for each half cycle of the signal, multiplying each of them by the weight of the PN sequence , and adding the multiplication results to obtain the first intermediate correlation output. The tap signals shifted by a quarter period of the carrier of the input signal are extracted, each of them is multiplied by the weight of the PN sequence , and the multiplication result is added to obtain a second intermediate correlation output, Used to obtain intermediate correlation output Remove the plurality of taps of the signal which is shifted in one symbol period before or after tapping, by adding the multiplication multiplication result their respective the weight of the PN sequence as a third intermediate correlation output, intermediate correlation of third Tap signals that are shifted by a quarter of a period of the carrier of the input signal are taken out from the taps used to obtain the output, each of them is multiplied by the weight of the PN sequence , and the multiplication result is added to obtain the fourth An intermediate correlation output; a product of the sum of the third and fourth intermediate correlation outputs and the first intermediate correlation output as a first correlation output; and a sum of the third and fourth intermediate correlation outputs and the The product of the second intermediate correlation output is used as the second correlation output.
According to a second aspect of the present invention, a signal extractor that discretely extracts an instantaneous value of an input signal at a period that is a quarter of a carrier period, and a delay amount per tap that is connected to an output of the signal extractor is input. A discrete first delay line that is one-fourth of the carrier period of the signal, and a second delay line having a delay amount corresponding to one symbol period, and one symbol of the first delay line A signal for each half cycle of the carrier of the input signal is extracted from a plurality of taps corresponding to a period, each of them is multiplied by the weight of the PN sequence , and the multiplication result is added to obtain a first intermediate correlation output, The tap signals shifted by a quarter of the carrier of the input signal are extracted from the taps of the first delay line used to obtain the first intermediate correlation output, and each of them is multiplied by the weight of the PN sequence. And adding the multiplication results to obtain the second intermediate correlation A sum of the first intermediate correlation output and the second intermediate correlation output is input to the second delay line, and an output of the second delay line is a third intermediate correlation output, A product of the third intermediate correlation output and the first intermediate correlation output is defined as a first correlation output, and a product of the third intermediate correlation output and the second intermediate correlation output is defined as a second correlation output. It comprised so that.
According to a third invention, in the first or second invention, the signal extractor is configured by an A / D converter, and the delay line is configured by a shift register including a plurality of flip-flops.
According to a fourth invention, in the first or second invention, the signal extractor is constituted by a charge extraction circuit, and the delay line is constituted by a CCD.
According to a fifth invention, in the first or second invention, the signal extractor is configured by a sample hold circuit including a gate element such as a transistor or a diode and a memory capacitor, and the delay line is a gate element such as a transistor or a diode. And a plurality of sample hold circuits composed of memory capacitors are configured as delay elements.
According to a sixth aspect of the present invention, in the first or second aspect, the signal extractor includes a current type sample-and-hold circuit including a current mirror circuit and a switching circuit, and the delay line includes a plurality of current mirror circuits and a switching circuit. The current type sample and hold circuit was configured as a delay element.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a diagram showing a correlator according to a first embodiment of the present invention. In this example, a digital correlator is shown in which the number of carriers per chip is one wave and the sampling rate is 4 samples per chip. 1 is a signal source of the same input signal E as the signal source 51 shown in the prior art, and generates a DS-SS signal that is directly spread by a PN sequence of chip length Lc and further QPSK modulated at a carrier angular frequency ω. To do. Reference numeral 2 denotes an A / D converter (signal extractor) that performs A / D conversion at a rate four times the carrier frequency. 3 and 4 are discrete delay lines each having a total delay amount corresponding to one symbol period. In addition to the input terminals IN1 and IN2 and the delay signal output terminals OUT1 and OUT2, two intermediate correlation signal output terminals IOUT1 and QOUT1, I have IOUT2 and QOUT2. The configuration of the delay lines 3 and 4 will be described later.
[0017]
The delay signal at the output terminal OUT1 of the delay line 3 is input to the input terminal IN2 of the delay line 4. Intermediate correlation signals obtained from the output terminals IOUT2 and QOUT2 of the delay line 4 are added by the adder 5. Also, the intermediate correlation signal obtained from the output terminal IOUT1 of the delay line 3 and the output signal of the adder 5 are multiplied by the multiplier 6, and the intermediate correlation signal obtained from the output terminal QOUT1 of the delay line 3 and the output signal of the adder 5 are obtained. Multiplication is performed by the multiplier 7 to take out the final correlation output signals of the correlator as IOUT and QOUT.
[0018]
FIG. 2 is a diagram showing a detailed configuration of the delay line 3. Since the delay line 4 is the same, here, the delay line 3 will be described as a representative. Reference numeral 31 denotes a delay device (flip-flop) that constitutes a shift register, and performs a delay of 1/4 of the carrier period per tap. The data converted by the A / D converter 2 is sequentially sent to the subsequent stage one tap at a time per clock. The data of each tap can be referred from the outside, and is output by being divided into two systems alternately for each stage data corresponding to 1/4 of the carrier cycle. Here, since the delay amount is 1/4 of the carrier period, every other line is divided into two systems.
[0019]
The signals divided into the two systems are multiplied by positive and negative values weighted by the PN sequence in order from the back, multiplied by a multiplier 32, summed by adders 33 and 34, and output terminals as intermediate correlation signals, respectively. Output to OUT1 and QOUT1. In the case of this example, the weighting by the PN sequence is {+ 1, -1} from the back when the code of a certain chip is 1 (= + 1), and when the code of the chip is 0 (= -1) The order is {-1, + 1} from the back. If the inversion of the sign is not required, weighting may be performed with other combinations.
[0020]
As described above, in the correlator of this embodiment, the A / D converter 2 that extracts signals discretely at a quarter of the carrier period and the delayed signal at a quarter of the carrier period are extracted. Delay lines 3 and 4 each having a delay tap and each capable of storing one symbol are used. In the delay line 3, by taking out the signal of every half cycle of the carrier period from every other tap, weighting the PN sequence to this and taking the in-phase correlation, the intermediate correlation output of the in-phase component is obtained from the output terminal IOUT1, Further, an intermediate correlation output of an orthogonal component is obtained from the output terminal QOUT1 by taking out a signal that is shifted by a quarter of the carrier period from the remaining taps, weighting this with a PN sequence, and then performing an orthogonal correlation. Similarly, for the signal one symbol before, an intermediate correlation output of in-phase and quadrature components is obtained from the output terminals IOUT2 and QOUT2 in the delay line 4. Then, the addition signal of the output terminals IOUT2 and QOUT2, the signal of the output terminal IOUT1 and the multiplication signal are set as an in-phase component output signal IOUT, and the addition signal of the output terminals IOUT2 and QOUT2, the signal of the output terminal QOUT1 and the multiplication signal are output as quadrature components. This is the signal QOUT.
[0021]
The shape of the pulse train generated from the final two correlation output signals IOUT and QOUT changes depending on the phase difference between the carrier and the sampling time. However, the integral value is almost constant, and the polarity is also determined by the difference between the transmission signals. Therefore, the difference between the transmission symbols can be obtained from the polarity of the pulse obtained by applying an appropriate low-pass filter to the pulse train. In this process, it is not necessary to synchronize with the signal carrier.
[0022]
Hereafter, the details of the circuit operation will be seen with calculation. The input signal source E is the same as that described in the conventional example, and the signal e (t) is obtained from the equation (2):
e (t) = a (t) · Acos (ωt + ψ + θ ₂ ) (2) '
ψ = {0, π / 2, π, 3π / 2}
[0023]
When this is sampled at four times the carrier frequency in the A / D converter 2, the following sequence is obtained inside the delay line 3 (nth tap).
C (n) = a (n + π) · Acos (ω / 4 · (n + τ) + ψ (t) + θ) (10)
Here, τ is a phase difference (shift) between the fixed code weighted by the tap of each delay unit 31 and the symbol accumulated in the delay line at that time, and takes an integer value. θ is the sum of the phase difference between the A / D conversion clock and carrier generated during A / D conversion plus the offset θ ₂ at the transmitter expressed by equation (2) ′, between 0 and 2π. Take the real value of.
[0024]
The correlation peak of the DS-SS signal occurs only when τ is approximately 0, that is, when approximately 1 symbol is stored in the delay line. Therefore, before and after the occurrence of the correlation peak, the delay line 3 may be approximately regarded as being filled with the latest symbol ψ ₀ , and the delay line 4 is filled with ψ ₋₁ which is the previous symbol.
[0025]
Since the phase information is now extracted directly from the carrier, the product obtained by multiplying the autocorrelation function R (τ) by the instantaneous value of the carrier is stored in the delay lines 3 and 4. Therefore, let us calculate the output of the delay group consisting of each delay unit 31 as a function of τ.
[0026]
The output signal Icorr1 (τ) of the output terminal IOUT1 of the delay line 3 is the PN sequence autocorrelation function R (τ) = Σa (n) · a (n + τ) (12)
Can be written as follows.

Here, Lc is the chip length of the PN sequence.
[0027]
Similarly, the output signal Qcorr1 (τ) of the output terminal QOUT1 of the delay line 3, the output signal Icorr2 (τ) of the output terminal IOUT2 of the delay line 4, and the output signal Qcorr2 (τ) of the output terminal QOUT2 of the delay line 4 are obtained. It becomes as follows.
Qcorr1 (τ) = 2Lc ・ A ・ R (τ) ・ cos (ω / 4 ・ τ + π / 2 + ψ ₀ + θ) (14)
Icorr2 (τ) = 2Lc ・ A ・ R (τ) ・ cos (ω / 4 ・ τ + ψ _-1 + θ) (15)
Qcorr2 (τ) = 2Lc ・ A ・ R (τ) ・ cos (ω / 4 ・ τ + π / 2 + ψ _-1 + θ) (16)
[0028]
Therefore, the signal I (τ) appearing at the final output terminal IOUT of the correlator is

However, K = 8 (Lc · A) ² .
[0029]
Similarly, the output signal Q (τ) appearing at the output terminal QOUT is

Is calculated.
[0030]
A well-designed PN sequence autocorrelation function is known to have a triangular wave shape with a half-width of one chip period as shown in FIG. Here, for convenience of later calculations, a PN sequence a (n) having an autocorrelation function R (τ) as follows is defined as follows.

Here, the autocorrelation function R (τ) of the defined PN sequence is shown in FIG.
[0031]
When τ ≧ 3 and τ ≦ −3, I (τ) and Q (τ) are 0. Therefore, when I (τ) and Q (τ) are calculated in the range of −2 ≦ τ ≦ 2, the following is obtained. become.

Since these outputs are not synchronized with the carrier, the output pulse train changes as shown in FIG. 4 depending on the value of the offset θ. FIG. 4 shows values obtained from I (−2) to I (+2) in the case of ψ ₀ = ψ ₋₁ = 0.
[0032]
Next, taking the sum of these pulse trains, the trigonometric formula
cos (x−π / 2) = − cos (x + π / 2)
cos (x + 3π / 2) = − cos (x + π / 2)
cos (x + π) = − cosx
Considering that

It becomes.
[0033]
For example, substituting ψ ₀ = ψ _-1 = 0 into equation (30),

Since the second term and the fourth term on the right side cancel each other and cos (θ + π / 2) = − sin (θ),

[0034]
Thus, if any data in {0, π / 2, π, −π / 2} is substituted into ψ ₀ and ψ ₋₁ , the right side braces of Equation (30) and Equation (31) Two of the four terms have a relationship of + cos θ · sin θ and −cos θ · sin θ, and cancel each other. The remaining two terms have a relationship of + cos ² θ and + sin ² θ or −cos ² θ and −sin ² θ. As a result, the contents of the braces on the right side of Equation (30) and Equation (31) can only take values of +1 or −1 regardless of the value of θ. Similarly, for ΣQ (τ),

It becomes.
The polarities of ΣI (τ) and ΣQ (τ) take the values shown in FIG. 5 in accordance with the difference (ψ ₀ −ψ ₋₁ ) between ψ ₀ and ψ ₋₁ . In FIG. 5, Pos represents a positive number and Neg represents a negative number.
[0035]
Here, by applying an appropriate low-pass filter to the pulse group represented by I (τ) and Q (τ), it is possible to obtain pulses that are continuous in time and substantially constant in amplitude. The polarity of this pulse coincides with the relationship between ψ ₀ and ψ ₋₁ shown in FIG. 5, and it is easy for those skilled in the art that the difference between ψ ₀ and ψ ₋₁ , that is, transmission data can be demodulated. I understand.
[0036]
In the above calculation, it is assumed that the autocorrelation function of the PN sequence is as shown in FIG. For the sake of verification, let us also calculate the triangular wave distribution shown in FIG. PN sequence autocorrelation function

In this case, the time integrals ΣI (τ) and ΣQ (τ) of the pulses output to the output terminals IOUT and QOUT are as follows.
[0037]

It has a coefficient in the contents of the curly braces on the right side.
[0038]
For this reason, the absolute values of ΣI (τ) and ΣQ (τ) vary depending on the value of θ, and the absolute value of the contents of the curly braces of Expressions (36) and (37) takes a value of 0.8 to 1.0. However, the polarity is the same as that of FIG. 5, and it can be considered that the contents shown in the equations (30) and (31) are approximately established even in an actual correlator. In addition, the fluctuation range of the absolute value is reduced by increasing the number of samplings per chip to 8, 12, 16,. For example, when the sampling number is 8, the fluctuation range is between 21/22 and 1, and when the sampling number is 16, the fluctuation range is between 85/86 and 1.
[0039]
[Second Embodiment]
A second embodiment of the present invention is shown in FIG. In this embodiment, the sum of the correlation signals of the output terminals IOUT1 and QOUT1 of the delay line 3 is previously obtained by the adder 5 and input to the input terminal IN2 of the delay line 4. Then, the delayed signals at the output terminal OUT2 of the delay line 4 are again multiplied by the correlation signals at the output terminals IOUT1 and QOUT1 of the delay line 3 by the multipliers 6 and 7, respectively, to obtain final correlation outputs IOUT and QOUT. . Even in this method, the same operational effects as in the case of the first embodiment can be obtained. Further, as apparent from FIG. 6, the signal correlation output of the delay line 4 is not necessary. Accordingly, signal reference means, multipliers, adders and the like inside the delay line 4 can be omitted, and the circuit scale can be reduced as compared with the configuration of FIG.
[Third Embodiment]
A third embodiment of the present invention is shown in FIG. In this embodiment, the digital correlation unit using the delay lines 3 and 4 shown in FIG. 1 is replaced with a correlation unit using CCD (Charge Coupled Device) delay lines 8 and 9, and the A / D connected to the input signal is used. The D converter 2 is replaced with a charge extraction circuit 10. Extraction in the charge extraction circuit 10 and charge transfer in the CCD delay lines 8 and 9 are performed at a rate of 1/4 of the carrier frequency. In the third embodiment, the same replacement as in the second embodiment is possible.
[0041]
[Fourth Embodiment]
A fourth embodiment of the present invention is shown in FIG. In this embodiment, a delay line using the digital correlator by the delay lines 3 and 4 shown in FIG. 1 as a delay element using a plurality of voltage-type sample and hold circuits composed of gate elements such as transistors and diodes and memory capacitors. The A / D converter 2 connected to the input signal is replaced with the voltage type sample hold circuit 13 with the same configuration. The signal transfer in the delay lines 11 and 12 and the sampling in the voltage type sample and hold circuit 13 are performed at a rate of 1/4 of the carrier frequency. In the fourth embodiment, the same replacement as in the second embodiment is possible.
[0042]
[Fifth Embodiment]
FIG. 9 shows a fifth embodiment of the present invention. In this embodiment, the digital correlator by the delay lines 3 and 4 shown in FIG. 1 is used as a delay line 14, 15 using a plurality of current-type sample-and-hold circuits each composed of a current mirror circuit and a switching circuit as a delay element. The A / D converter 2 connected to the input signal is replaced with a current-type sample and hold circuit 16 having the same configuration. Signal transfer in the delay lines 14 and 15 and sampling in the current type sample and hold circuit 16 are performed at a rate of 1/4 of the carrier frequency. In the fifth embodiment, the same replacement as in the second embodiment is possible.
[0043]
The circuits shown in the third to fifth embodiments described above are discrete in time but continuous with respect to the voltage signal. Therefore, the digital correlation shown in the first embodiment is used. This has the advantage that there is no signal degradation due to quantization error compared to the device.
[0044]
【The invention's effect】
As described above, according to the present invention, elements that are difficult to integrate, such as a mixer and a 90-degree phase shifter, are unnecessary, and it is not necessary to synchronize the carrier, and a correlator configured with discrete delay lines can be configured. it can. Therefore, its industrial value is great.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a correlator according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a delay line.
FIG. 3 is an explanatory diagram of an autocorrelation function of a PN sequence.
FIG. 4 is an explanatory diagram of pulse fluctuations due to an offset θ.
FIG. 5 is an explanatory diagram of polarities of ΣI (τ) and ΣQ (τ).
FIG. 6 is a block diagram showing a correlator according to a second embodiment of the present invention.
FIG. 7 is a block diagram showing a correlator according to a third embodiment of the present invention.
FIG. 8 is a block diagram showing a correlator according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a correlator according to a fifth embodiment of the present invention.
FIG. 10 is a block diagram showing a conventional demodulating circuit for a QPSK modulated DS-SS signal.

Claims (6)

A signal extractor that discretely extracts an instantaneous value of the input signal at a period that is a quarter of the carrier period, and a delay amount per tap that is connected to the output of the signal extractor is 4 of the carrier period of the input signal. A discrete delay line that is a multiple of
First, a signal for each half cycle of the carrier of the input signal is extracted from a plurality of taps corresponding to one symbol period of the delay line, each of them is multiplied by the weight of the PN sequence , and the multiplication result is added. The intermediate correlation output of
From the taps used to obtain the first intermediate correlation output, tap signals shifted by a quarter of the carrier of the input signal are extracted, and each of them is multiplied by the weight of the PN sequence , and the multiplication result is obtained. Add to the second intermediate correlation output,
A plurality of tap signals shifted from the tap used for obtaining the first intermediate correlation output by one symbol period before or after are extracted, multiplied by the PN sequence weights, and the multiplication result is added. 3 intermediate correlation output,
From the taps used to obtain the third intermediate correlation output, tap signals shifted by a quarter of the carrier of the input signal are extracted, and each of them is multiplied by the weight of the PN sequence , and the multiplication result is obtained. Add to the fourth intermediate correlation output,
A product of the sum of the third and fourth intermediate correlation outputs and the first intermediate correlation output is defined as a first correlation output;
A correlator characterized in that a product of a sum of the third and fourth intermediate correlation outputs and the second intermediate correlation output is used as a second correlation output. A signal extractor that discretely extracts an instantaneous value of the input signal at a period that is a quarter of the carrier period, and a delay amount per tap that is connected to the output of the signal extractor is 4 of the carrier period of the input signal. A discrete first delay line that is a multiple of a multiple, and a second delay line with a delay amount corresponding to one symbol period;
A signal for each half cycle of the carrier of the input signal is extracted from a plurality of taps corresponding to one symbol period of the first delay line, each of them is multiplied by the weight of the PN sequence , and the multiplication result is added. The first intermediate correlation output,
From the taps of the first delay line used to obtain the first intermediate correlation output, tap signals that are shifted by a quarter period of the carrier of the input signal are extracted, and each of them is weighted with a PN sequence . Multiply and add the multiplication results to the second intermediate correlation output,
The sum of the first intermediate correlation output and the second intermediate correlation output is input to the second delay line, and the output of the second delay line is used as a third intermediate correlation output,
The product of the third intermediate correlation output and the first intermediate correlation output is the first correlation output,
A correlator characterized in that a product of the third intermediate correlation output and the second intermediate correlation output is a second correlation output. 3. The correlator according to claim 1, wherein the signal extractor is configured by an A / D converter, and the delay line is configured by a shift register including a plurality of flip-flops. 3. The correlator according to claim 1, wherein the signal extractor is constituted by a charge extraction circuit, and the delay line is constituted by a CCD. The signal extractor is composed of a sample and hold circuit composed of a gate element such as a transistor or a diode and a memory capacitor, and the delay line is composed of a plurality of sample and hold circuits composed of a gate element such as a transistor or a diode and a memory capacitor as a delay element. The correlator according to claim 1 or 2, wherein The signal extractor comprises a current type sample and hold circuit comprising a current mirror circuit and a switching circuit, and the delay line comprises a plurality of current type sample and hold circuits comprising a current mirror circuit and a switching circuit as delay elements. The correlator according to claim 1 or 2.

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