JP3760995B2 - Shared memory vector processing system, control method therefor, and storage medium storing vector processing control program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shared memory vector processing system that includes a plurality of CPUs that share a main memory, and each CPU includes a vector processing unit that forms a scalar processing unit and a plurality of vector pipelines.
[0002]
[Prior art]
FIG. 9 shows a configuration of a shared memory parallel processing system using a CPU in a conventional vector processing apparatus. In this system, a plurality of CPUs 100 a to 100 n are connected by sharing one main storage device 200.
[0003]
A detailed configuration diagram of each of the CPUs 100a to 100n is shown in FIG. Each of the CPUs 100a to 100n includes a scalar processing unit 101, an instruction control unit 102, vector processing units 104a to 104n, and a memory access network unit 105, as illustrated.
[0004]
The external processing instruction “EX-RQ” issued from the scalar processing unit 101 is transferred to the instruction control unit 102. The instruction control unit 102 issues a vector processing instruction “V-RQ” by managing the resources of the vector processing units 104 a to 104 n existing only within the CPU.
[0005]
Therefore, the configuration of the scalar processing unit 101 and the vector pipeline in each of the CPUs 100a to 100n is always constant and cannot be changed.
[0006]
Examples of conventional vector processing apparatuses are disclosed in, for example, Japanese Patent Laid-Open Nos. 63-127368 and 63-10263. In the vector processing devices disclosed in these publications, the configuration of the scalar processing unit and the vector pipeline is constant, and the number of vector pipelines attached to the scalar processing unit can be flexibly changed according to the application. It is not.
[0007]
[Problems to be solved by the invention]
The conventional vector processing apparatus described above has the following problems.
[0008]
The first problem is that an appropriate vector processing resource cannot be assigned to a vectorization rate or the like depending on an application to be executed.
[0009]
The reason is that the number of vector pipelines in each CPU is always constant. Therefore, when an application with a vectorization rate lower than expected is executed, a surplus of vector resources occurs. Conversely, even if an application with a higher vectorization rate or a longer vector length is executed, the upper limit of vector processing performance is fixed by the vector pipeline configuration that is fixedly configured in advance. There is no improvement.
[0010]
The second problem is that the scalar processing unit and the vector pipeline need to be developed as separate LSIs even if the integration degree of the LSIs is improved.
[0011]
The reason is that the degree of integration of LSIs has improved, and one scalar processing unit and a vector pipeline can be integrated into one chip. In the conventional multi-vector pipeline configuration, such an LSI is used. Since a scalar processing unit existing in each LSI cannot be used at the time of multiple connection and the amount of hardware is wastefully used, the scalar processing unit and the vector pipeline are developed as separate LSIs as before. turn into. However, this method increases items such as an increase in the number of LSI development steps, an increase in the number of LSI development varieties, and a decrease in the number of production per LSI.
[0012]
An object of the present invention is to provide a vector processing system that can flexibly change the number of vector pipelines associated with a scalar processing unit according to the application.
[0013]
Another object of the present invention is to provide a vector processing system that operates so as to share a single vector pipeline from the scalar processing unit of each independent processor.
[0014]
[Means for Solving the Problems]
The present invention according to claim 1, which achieves the above object, is a shared memory type vector processing system comprising a plurality of CPUs sharing a main memory, wherein each CPU has scalar processing means and vector processing means. The CPUs are connected to each other by a path for transferring vector processing instructions generated from each CPU to each CPU, and each CPU issues a vector processing instruction to which issuance source CPU information for identifying the issuing CPU is added. A plurality of instruction stacks corresponding to each CPU based on the issuing source CPU information, and issuing means for transferring to all CPUs including the CPU of itself via the path. And based on the vector processing instruction based on the priority for each of the plurality of instruction stacks and the resource information of the vector processing means Characterized in that it comprises a vector processing instruction control means for controlling the decree issued.
[0015]
3. The shared memory vector processing system according to claim 2, wherein the vector processing instruction control means of each CPU includes a plurality of instruction stacks corresponding to each CPU, and the issuance included in the transferred vector processing instruction. Instruction issuer detection means for detecting original CPU information and storing the vector processing instruction in the corresponding instruction stack, and issuing an instruction based on a vector processing instruction of any instruction stack for each of the plurality of instruction stacks Arbitration means for determining whether to give priority, and instruction issue processing means for issuing an instruction based on the vector processing instruction to the vector processing means based on the content determined by the arbitration means and the resource information of the vector processing means. It is characterized by providing.
[0016]
The present invention of claim 3 is a control method of a shared memory type vector processing system comprising a plurality of CPUs sharing a main memory, each CPU having a scalar processing means and a vector processing means. CPUs are connected to each other by a path for transferring vector processing instructions generated from each CPU to each CPU, and each CPU issues a vector processing instruction to which issuance source CPU information for identifying the issuing CPU is added. Then, the vector processing instruction transferred to all CPUs including its own CPU via the path is stored in a plurality of instruction stacks corresponding to each CPU based on the issuing CPU information. Controlling instruction issuance based on the vector processing instruction based on the priority order of the plurality of instruction stacks and resource information of the vector processing means And wherein the Rukoto.
[0017]
According to a fourth aspect of the present invention, there is provided a shared memory type vector processing system control method, wherein each of the CPUs detects the issuer CPU information included in the transferred vector processing instruction, and the instruction corresponding to the vector processing instruction is detected. It is stored in a stack, and for each of the plurality of instruction stacks, the instruction processing based on the vector processing instruction of which instruction stack is prioritized, based on the determination content and the resource information of the vector processing means, An instruction issuance based on a vector processing instruction is performed to the vector processing means.
[0018]
The present invention of claim 5 includes a plurality of CPUs sharing a main memory, and each CPU has a scalar processing means and a vector processing means, and the CPU of the issuer is included in the CPU of the shared memory type vector processing system. Issuing a vector processing instruction to which issuance source CPU information for identifying the CPU is issued, transferring it to all CPUs including its own CPU via a mutually connected path, and the transferred vector processing instruction, An instruction based on the vector processing instruction is stored in a plurality of instruction stacks corresponding to each CPU based on the issuing CPU information, and based on the priority for each of the plurality of instruction stacks and the resource information of the vector processing means. The storage medium stores a program for executing processing for controlling issuance.
[0019]
According to a sixth aspect of the present invention, the CPU detects the issuer CPU information included in the transferred vector processing instruction and stores the vector processing instruction in a corresponding instruction stack.
The vector processing instruction based on the determination content and the resource information of the vector processing means for determining the instruction processing based on the vector processing instruction of which instruction stack is prioritized for each of the plurality of instruction stacks And executing a process of issuing an instruction based on the vector processing means to the vector processing means.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of the entire vector processing system according to the first embodiment of the present invention.
[0021]
The vector processing system according to the present embodiment includes a plurality of CPUs 10a to 10n, and constitutes a shared memory parallel processing system in which these CPUs 10a to 10n share a single main storage device 20. The CPUs 10a to 10n are connected to each other via the vector request bus 30 and can send and receive requests and replies related to vector processing.
[0022]
A detailed configuration of each of the CPUs 10a to 10n will be described with reference to FIG.
[0023]
Each of the CPUs 10a to 10n includes a single scalar processing unit 11, a memory access instruction control unit 12, a vector processing instruction control unit 13, a plurality of vector processing units 14a to 14n, and a memory access network unit 15.
[0024]
An external processing instruction “EX-RQ” issued from the scalar processing unit 11 to the outside is transferred to the main storage device 20 via the memory access network unit 15 through the memory access control unit 12 or via the vector request bus 30. Via this, it is sent to the vector processing instruction control unit 13 of all the CPUs 10a to 10n, and issued to the vector processing units 14a to 14n.
[0025]
Here, FIG. 3 is a block diagram showing a detailed configuration of the vector processing instruction control unit 13.
[0026]
The vector processing instruction control unit 13 separates the contents of the two registers 42 and 43, the comparator 45 that compares the contents of the registers 42 and 43, and the contents of the vector processing instruction transferred via the vector request bus 30. A comparator 44 for comparing the issuer information of the vector processing instruction obtained by the instruction issuer information extracting unit 41 to the contents of one register 42, an instruction invalidation processing unit 46, an instruction stack 47, resource management / instruction An issue processing unit 48 is provided.
[0027]
The vector processing instruction obtained from the instruction issuer information extraction unit 41 and the output of the comparator 44 are input to the invalidation processing unit 46 and then stored in the instruction stack 47. The vector processing instruction stored in the instruction stack 47 is input to the resource management / instruction issue processing unit 48 together with resource information from the vector processing units 14a to 14n, and is issued to the vector processing units 14a to 14n. Done.
[0028]
Next, the operation of the vector processing system according to the first embodiment configured as described above will be described.
[0029]
In FIG. 2, the scalar processing unit 11 decodes the instruction and executes the execution process of the scalar processing instruction. Here, when an instruction that cannot be executed by the scalar processing unit 11, such as an access instruction to the main storage device 20 or a vector processing instruction, the scalar processing unit 11 regards these instructions as an external processing instruction “EX-RQ”. Transfer to the memory access instruction control unit 12.
[0030]
The memory access instruction control unit 12 decodes the external processing instruction “EX-RQ” received from the scalar processing unit 11, and if it is an instruction “M-RQ” for the main memory access system, the memory access instruction control unit 12 directly sends it to the memory access network unit 15. Issue instructions.
[0031]
On the other hand, if it is a vector processing instruction, it is sent to the vector request bus 30 and issued to the own vector processing instruction control unit 13 via the vector request bus 30.
[0032]
The vector processing instruction control unit 13 receives the vector processing instruction issued from its own CPU sent from the memory access instruction control unit 12 and the vector processing instruction transferred from the other CPU via the vector request bus 30. The command is issued to the vector processing units 14a to 14n in the own CPU while managing the resource state.
[0033]
The memory access network unit 15 receives the main memory access command “M-RQ” from the memory access command control unit 12, issues a command to the main memory device 20, and receives read data from the main memory device 20. The data is returned to the scalar processing unit 11 or the vector processing units 14a to 14n according to the instruction type.
[0034]
Next, the operation of the vector processing instruction control unit 13 will be described with reference to the flowcharts of FIGS.
[0035]
The vector processing instruction sent to the vector processing instruction control unit 13 is separated into information related to the CPU that sent the instruction and the vector processing instruction body in the instruction issuer information extraction unit 41 (step 401).
[0036]
The vector processing instruction control unit 13 includes a register 42 that stores a CPU number set as an external master for the CPU and a register 43 that stores the CPU number. It is assumed that the above numbers are set for these two registers 42 and 43 as initialization operations before the system is started.
[0037]
In the present embodiment, the CPUs 10a to 10n of the shared memory parallel processing system are set separately for the master CPU and the slave CPU. The master CPU can execute scalar processing and issue vector processing instructions to other CPUs. On the other hand, the slave CPU receives the vector processing instruction transferred from the master CPU, and operates as a multi-vector pipeline in synchronization with the vector processing units 14a to 14n in the master CPU. At this time, the scalar processing unit 11 of the slave CPU is in a dormant state, and only the vector processing units 14a to 14n, the vector processing instruction control unit 13, and the memory access network unit 15 function effectively.
[0038]
The contents of the register 42 storing the master CPU number and the register 43 storing the own CPU number are compared by the comparator 45 (step 402). If they do not match, it is determined that the own CPU is a slave CPU and Control is made to stop the operation of the scalar processing unit 11 of the CPU (step 403).
[0039]
On the other hand, the instruction issuer CPU number extracted in the instruction issuer information extraction unit 41 from the vector processing instruction transferred through the vector request bus 30 and the contents of the register 42 storing the master CPU number are another one. The comparison is made by the comparator 44 (step 404). The comparison result at this time and the vector processing instruction separated by the instruction issuer information extraction unit 41 are input to the invalidation processing unit 46 (step 405).
[0040]
If the comparison result by the comparator 44 is inconsistent (step 406), the input vector processing instruction is not a vector processing instruction issued from the master CPU of its own CPU operating as a slave, and therefore invalidation processing is performed. It is invalidated by the unit 46 (step 407). Specifically, according to the comparison result by the comparator 44, a flag indicating validity or invalidity is attached to the vector processing instruction, and the invalidation processing unit 46 puts only a valid vector processing instruction in the instruction stack 47 by the flag. Store. Invalid vector processing instructions are not stored in the instruction stack 47.
[0041]
Of course, if the own CPU is operating as the master CPU and the transferred vector processing instruction is an instruction issued by the own CPU, the result of the comparator 44 indicates a match and is invalidated. Absent.
[0042]
Since the vector processing instruction that has not been invalidated by the invalidation processing unit 46 is an instruction to be processed by the vector processing units 14a to 14n in its own CPU, it is stored in the instruction stack 47 in the order of acceptance (step 408). The invalidated vector processing instruction is discarded without being stored in the instruction stack 47.
[0043]
The resource management / instruction issuance control unit 48 manages the resources 14a to 14n of the vector processing unit in its own CPU. Instructions stored in the instruction stack 47 are issued in the order in which the instructions can be issued in the resource management / instruction issue processing unit 48 according to the priority order and the resource status of the vector processing units 14a to 14n. An instruction is issued to 14n (step 409). Here, it is possible to overtake and issue instructions without following the order of storage in the instruction stack 47.
[0044]
When the vector processing in each slave CPU is completed, the master CPU is notified of the end of the processing. The master CPU issues the next vector processing instruction after confirming that end notifications have been received from all slave CPUs.
[0045]
As described above, the CPU set as the master CPU and the plurality of CPUs storing the CPU number as the master CPU number can be regarded as a processor of a multi-vector pipeline that operates as a unit.
[0046]
At this time, only the scalar processing unit 11 of the master CPU is functioning, and the function of the scalar processing unit 11 of the slave CPU is stopped by the control signal “HALT” from the vector processing instruction control unit 13.
[0047]
The vector processing instruction issued from the scalar processing unit 11 of the master CPU is judged to be valid in each vector processing instruction control unit 13 of the slave CPU including the own CPU through the vector request bus 30, and the vector processing unit in the plurality of CPUs 14a to 14n are processed by parallel operation.
[0048]
If there is one vector processing unit in one CPU, assuming that the number of CPUs sharing the main storage device 20 is 32, there are usually 32 CPUs of “1 scalar processing unit + 1 vector processing unit”. However, if one slave CPU is associated with one master CPU, it can be operated like a system having 16 CPUs of “1 scalar processing unit + 2 vector processing unit”. It becomes possible.
[0049]
In addition, depending on the setting contents of the master CPU and slave CPU, a configuration in which a CPU of “1 scalar processing unit + 1 vector processing unit” and a CPU of “1 scalar processing unit + 4 vector processing unit” are mixed in one system. Can be taken. That is, various configurations can be constructed depending on the settings of the master CPU and slave CPU.
[0050]
Next, a vector processing system according to the second embodiment will be described.
[0051]
FIG. 5 is a block diagram showing a configuration of the vector processing instruction control unit 13 of the vector processing system according to the second embodiment. The configuration other than the vector processing instruction control unit 13 is the same as that in the first embodiment.
[0052]
The vector processing instruction control unit 13 shown in FIG. 5 has a register 42a storing a master CPU number and a register 43a storing its own CPU number, and compares the contents of the two registers 42a and 43a. The function of the scalar processing unit 11 of the own CPU is stopped based on the output of the comparator 44a, which is the same as in the configuration of FIG. The vector processing instruction control unit 13 has a function of comparing the master CPU number of the register 42a with the issuer CPU information included in the vector processing instruction and a function of controlling instruction issuance based on the comparison result. A management / command issue controller 48a is provided.
[0053]
The operation of the vector processing instruction control unit 13 will be described with reference to the flowchart of FIG. In this configuration example, as shown in FIG. 6, the vector processing instructions transferred through the vector request bus 30 are sequentially stored in the instruction stack 47a without any processing (step 601). Therefore, the instruction stack 47a is provided with a record for storing the issuer CPU information together with the vector processing instruction.
[0054]
Further, the contents of the register 42a storing the master CPU number and the register 43a storing the own CPU number are compared by the comparator 45a (step 602). If they do not match, it is determined that the own CPU is a slave CPU. Then, it controls the scalar processing unit 11 of its own CPU to stop the operation (step 603).
[0055]
Next, when the resource management / instruction issue control unit 48a issues an instruction to the vector processing unit, the issuer CPU information attached to the vector processing instruction and the register 42a storing the master CPU number are stored. By comparing the contents (step 604), if the numbers do not match, issuance of an inappropriate vector processing instruction is suppressed and the corresponding area in the instruction stack 47a is released (step 605). That is, the invalidation process is not performed before the instruction stack 47a is stored, but the invalidation process is performed when the instruction is actually issued.
[0056]
If the numbers match, the instruction stored in the instruction stack 47a is assigned the priority level and the vector processing units 14a to 14n as in the resource management / instruction issue control unit 48 in the first embodiment. Depending on the resource status, instructions are issued to the vector processing units 14a to 14n of the CPU in the order in which they can be issued (step 606).
[0057]
In the first embodiment described above, the instruction issuer information extraction unit 41 that extracts the instruction issuer CPU number of the vector processing instruction, the comparator 44 that compares the instruction issuer CPU number and the master CPU number, and the comparison result. By providing the invalidation processing unit 46 for invalidating the vector processing instruction, an invalid vector processing instruction is not stored in the instruction stack 47, whereas in the second embodiment, the issued issue is sent. All vector processing instructions including the original CPU information are stored in the instruction stack 47a, and only appropriate vector processing instructions are issued at the stage of instruction issue processing by the resource management instruction issue processing unit 48a. The area of the stack 47a is released. Therefore, when the first embodiment and the second embodiment are compared, the second embodiment requires less hardware, and the storage capacity of the instruction stack is the first. The form of can be made smaller.
[0058]
On the other hand, a multi-vector pipeline shared by a plurality of independent scalar processing units is also possible as a system configuration that emphasizes scalar performance. That is, a system that operates so that all vector pipelines existing in a plurality of processors are collectively regarded as one multi-vector pipeline and a single vector pipeline is shared by the scalar processing units of the independent processors. It is a configuration.
[0059]
FIG. 7 shows the configuration of the vector processing instruction control unit 13 of the vector processing system according to the third embodiment that realizes this. Since the configuration other than the vector processing instruction control unit 13 is the same as that of the first embodiment described above, the same reference numerals are given and description thereof is omitted.
[0060]
In the vector processing system according to the third embodiment, the vector processing instruction control unit 13 sets the instruction issuer detection unit 61, the instruction stacks 63a to 63n provided for each CPU, and the instruction stacks 63a to 63n. The arbitration unit 62 performs arbitration in the issue order based on the priority order and the resource management / instruction issue processing unit 64.
[0061]
The operation of the vector processing instruction control unit 13 according to the present embodiment will be described below with reference to the flowchart of FIG.
[0062]
The vector processing instructions transferred through the vector request bus 30 are stored in instruction stacks 63a to 63n provided for each CPU via the instruction issuer detection unit 61. The stored vector processing instruction is input to the resource management / instruction issuance control unit 64 together with the arbitration result by the arbitration unit 62 and the resource information “V-RP” from each of the vector processing units 14a to 12n. Issued to 14a-14n.
[0063]
Here, for the vector processing instruction transferred through the vector request bus 30, the instruction issuer detection unit 61 checks the issuer CPU number (step 801). Thereafter, the vector processing instructions are divided and stored in instruction stacks 63a to 63n provided for each issuing CPU (step 802).
[0064]
Then, whether or not to issue an instruction from any of the instruction stacks 63a to 63n is determined by the arbitration unit 62 that performs the arbitration according to the priority order (step 803). The arbitrating unit 62 determines whether to issue an instruction from any of the instruction stacks 63a to 63n by, for example, a round robin method. Using the output of the arbitration unit 62 and the resource information of each vector processing unit, the resource management / command issue control unit 64 determines an issue command (step 804).
[0065]
At this time, vector processing instructions with the same issuer CPU cannot be issued by overtaking beyond the order of storage in the instruction stack. However, if the issuer CPU is different, it may be issued by overtaking depending on the resource status. There is no problem because there is no data race. Therefore, it is not necessary to memorize the storage order between the instruction stacks. Further, even if the issuing CPU has the same vector processing instruction, overtaking issuance is possible by preparing corresponding resource management means for avoiding access to the same address by comparing the access addresses.
[0066]
As described above, the vector processing instruction issued from each CPU is transferred to the vector processing instruction control unit of all CPUs, and issuance processing is performed. At this time, since the vector processing instructions are managed according to the issuing CPUs, the vector processing unit existing in each CPU seems to be shared from the scalar processing units of all CPUs as a single vector processing unit integrated by all the CPUs. Will work.
[0067]
The above-described vector processing system is not only realized in hardware, but, as shown in FIG. 2, controls for realizing the above-described functions recorded on a magnetic disk, semiconductor memory or other recording medium 18 are provided. It can be realized by software by a program. This control program is read from the recording medium 18 to the CPU and controls the operation of the CPU, thereby realizing the above-described vector processing instruction control function. That is, the processing shown in FIGS. 4, 6 and 8 is executed.
[0068]
The present invention is not limited to the above-described embodiments, and can be implemented with various modifications within the scope of the technical idea. For example, in the overall system configuration diagram in FIG. 1, the vector request bus 30 for transferring vector processing instructions between the CPUs 10a to 10n is described as a single bus. However, this transfer means is not limited to a single bus and can obviously be realized by any connection means such as multiple buses or crossbar switches.
[0069]
【The invention's effect】
As described above, according to the vector processing system and the control method of the present invention, the following effects can be obtained.
[0070]
First, it is possible to provide a shared memory type parallel processing system having a single vector processing unit shared by a plurality of scalar processing units for applications that place more importance on scalar processing performance.
[0071]
This prepares a vector processing instruction stack for each CPU for the vector processing instruction control of each CPU, classifies vector processing instructions transferred between the CPUs for each issuing CPU and stores them in the instruction stack, By sequentially issuing vector processing instructions to the vector processing unit while arbitrating the competition of instructions in each instruction stack, the vector processing means existing in all CPUs can be regarded as a single vector processing means from all CPUs. This is because they can operate as if they are shared.
[0072]
As a result, it is possible to provide a system capable of performing more efficient processing by effectively using vector processing resources even in an application field where importance is placed on scalar throughput performance in which the appearance frequency of vector processing instructions is extremely low.
[0073]
Second, it is possible to develop an LSI in which scalar processing means and vector processing means are integrated on a single chip, thereby reducing development man-hours and costs.
[0074]
This is because the configuration of the multi-vector pipeline for the scalar processing means can be flexibly changed by setting from the outside, so the scalar processing means and the vector processing means, which were difficult until now, are integrated in the same LSI As a result, the number of LSI development types can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an entire vector processing system according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of each CPU of the vector processing system according to the first embodiment.
FIG. 3 is a block diagram showing details of a vector processing instruction control unit of the vector processing system according to the first embodiment.
FIG. 4 is a flowchart illustrating an operation of a vector processing instruction control unit of the vector processing system according to the first embodiment.
FIG. 5 is a block diagram showing a configuration of a vector processing instruction control unit of a vector processing system according to a second embodiment.
FIG. 6 is a flowchart illustrating an operation of a vector processing instruction control unit of the vector processing system according to the second embodiment.
FIG. 7 is a block diagram showing a configuration of a vector processing instruction control unit of a vector processing system according to a third embodiment.
FIG. 8 is a flowchart illustrating an operation of a vector processing instruction control unit of the vector processing system according to the third embodiment.
FIG. 9 is a block diagram showing the configuration of a shared memory parallel processing system using a CPU in a conventional vector processing apparatus.
10 is a block diagram showing a configuration of each CPU 0 of the vector processing device shown in FIG. 9;
[Explanation of symbols]
10a-10n CPU
11 Scalar processing part
12 Memory access instruction control unit
13 Vector processing instruction control unit
14a-14n Vector processing unit
15 Memory access network section
20 Main memory
30 vector request bus
41 Instruction issuer information extraction unit
42, 43, 42a, 43a registers
44, 45, 44a comparator
46 Invalidation processing part
47, 47a Instruction stack
48, 48a Resource management instruction issue processor
61 Instruction issuer detection
62 Mediation Department
63a-63n instruction stack
64 Resource Management / Instruction Issue Processor

Claims (6)

In a shared memory type vector processing system comprising a plurality of CPUs sharing a main memory, each CPU having a scalar processing means and a vector processing means,
The CPUs are connected to each other by a path for transferring vector processing instructions generated from the CPUs to the CPUs.
Each of the CPUs
Issuing means for issuing a vector processing instruction to which issuance source CPU information for identifying the issuance CPU is added and transferring the instruction to all CPUs including the own CPU via the path;
The transferred vector processing instruction is stored in a plurality of instruction stacks corresponding to each CPU based on the issuing CPU information, and based on the priority for each of the plurality of instruction stacks and the resource information of the vector processing means. And a vector processing instruction control means for controlling instruction issuance based on the vector processing instruction. The vector processing instruction control means of each CPU is
A plurality of instruction stacks corresponding to each CPU;
Instruction issuer detection means for detecting the issuer CPU information included in the transferred vector processing instruction and storing the vector processing instruction in the corresponding instruction stack;
Arbitration means for deciding whether to give priority to instruction issue based on a vector processing instruction of which instruction stack for each of the plurality of instruction stacks;
2. An instruction issuance processing unit for issuing an instruction based on the vector processing instruction to the vector processing unit based on a determination by the arbitration unit and resource information of the vector processing unit. A shared memory type vector processing system according to claim 1. A control method of a shared memory type vector processing system comprising a plurality of CPUs sharing a main memory, each CPU having a scalar processing means and a vector processing means,
The CPUs are connected to each other by a path for transferring vector processing instructions generated from the CPUs to the CPUs.
In each CPU,
Issuing a vector processing instruction to which the issuer CPU information for identifying the issuer CPU is added is transferred to all CPUs including the own CPU via the path,
The transferred vector processing instruction is stored in a plurality of instruction stacks corresponding to each CPU based on the issuing CPU information, and based on the priority for each of the plurality of instruction stacks and the resource information of the vector processing means. And controlling the issuance of instructions based on the vector processing instructions. In each CPU,
Detecting the issuer CPU information included in the transferred vector processing instruction, and storing the vector processing instruction in a corresponding instruction stack;
For each of the plurality of instruction stacks, determine which instruction stack is prioritized to issue instructions based on vector processing instructions,
4. The shared memory type vector processing system according to claim 3, wherein an instruction based on the vector processing instruction is issued to the vector processing means based on the determined content and resource information of the vector processing means. Control method. The CPU of the shared memory type vector processing system having a plurality of CPUs sharing the main memory, each CPU having a scalar processing unit and a vector processing unit,
A process of issuing a vector processing instruction added with issuer CPU information for identifying the issuer CPU and transferring it to all CPUs including the own CPU via a mutually connected path;
The transferred vector processing instruction is stored in a plurality of instruction stacks corresponding to each CPU based on the issuing CPU information, and based on the priority for each of the plurality of instruction stacks and the resource information of the vector processing means. And a storage medium storing a program for executing processing for controlling command issuance based on the vector processing command. In the CPU,
Detecting the issuer CPU information included in the transferred vector processing instruction and storing the vector processing instruction in a corresponding instruction stack;
A process for determining, for each of the plurality of instruction stacks, which instruction stack is prioritized to be issued based on a vector processing instruction;
6. The program according to claim 5, wherein a program for issuing an instruction based on the vector processing instruction to the vector processing means is executed based on the determined content and resource information of the vector processing means. Stored storage medium.

Images