JP3758477B2 - Microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an operation clock setting device that switches an operation clock of a microcomputer according to a processing load of the microcomputer.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known an operation clock setting device that switches an operation clock of a microcomputer according to a processing load of the microcomputer in order to reduce power consumption of the microcomputer or suppress heat generation.
[0003]
[Problems to be solved by the invention]
However, the conventional operation clock setting device, for example, as described in JP-A-6-124150, sets the operation clock at a high speed when the processing load of the microcomputer is large, and when the processing load is small. Since the operation clock was set to low speed, when the microcomputer operation clock was switched from high speed to low speed, the processing operation of the microcomputer was delayed and the control by the microcomputer was executed stably. There was a problem that it was impossible.
[0004]
In other words, a microcomputer is generally used for controlling various devices, and software for such control is controlled by a timer for measuring time in synchronization with an operation clock (so-called system clock) of the microcomputer. It is configured to determine the timing and perform arithmetic processing for control.
[0005]
On the other hand, when the system clock is switched from a high speed to a low speed or from a low speed to a high speed, the frequency of the system clock is not immediately switched at the switching timing, and a delay of a certain time width (lag time) occurs. The lag time when the system clock is switched from high speed to low speed is significantly larger than that when the system clock is switched from low speed to high speed.
[0006]
In addition, switching from the low speed to the high speed of the system clock is usually performed when the microcomputer starts control from a state in which various controls are stopped according to the control software, resulting in a delay in switching the system clock. However, the start of the control is only delayed, and there is no support for the control, but the system clock is switched from the high speed to the low speed when the microcomputer executes various controls according to the control software. There is a possibility that.
[0007]
And, as described above, when the system clock is switched from high speed to low speed when the microcomputer is operating according to the control software, a large shift occurs in the control cycle and timing due to the lag time, and depending on the control, Real-time performance cannot be ensured and normal control cannot be executed.
[0008]
The present invention has been made in view of these problems, and in an apparatus for switching the operation clock of a microcomputer according to the processing load of the microcomputer, the operation clock is optimal without affecting the control processing executed by the microcomputer. It is intended to be able to switch to.
[0009]
[Means for Solving the Problems]
The microcomputer according to claim 1, which has been made to achieve such an object, executes control processing based on each of a plurality of application programs according to an operation clock, and operates at either a high speed or a low speed. An operation clock generating means capable of generating the operation clock, a plurality of application programs, and a control state of each of the plurality of application programs for switching the operation clock Based on the storage means in which the status management program is stored and the status management program, the control status of each application program is monitored to determine whether the operating clock is to be high speed, low speed, or stopped. Set high and low speeds for the clock generator, and Includes a CPU for controlling the generation and stop of the operation clock, a.
Then, after starting the microcomputer, the CPU sets the operation clock at a high speed, and when the microcomputer is operating at high speed according to the high-speed operation clock, all control processes based on each application program have been completed. When the determination is made, the operation clock is set to a low speed so that the microcomputer operates at a low speed when the microcomputer returns to the operation state from the sleep state, and then the operation clock is stopped to shift the microcomputer to the sleep state.
[0010]
Further, when the CPU is operating at a low speed when the preset wake-up time elapses or when the microcomputer returns from the sleep state to the operation state due to an external wake-up request being input, If it is determined to shift to the control processing by one of the application programs, the operation clock is set at a high speed.
[0011]
In the microcomputer of the present invention, switching of the operation clock from the high-speed operation of the microcomputer is limited to the transition to the sleep state in which the operation clock is stopped, and control processing based on any of a plurality of application programs The operation clock cannot be switched from the high speed to the low speed during execution.
As a result, according to the microcomputer of the present invention, after activation of the microcomputer, or when the operation clock after returning from the sleep state is set at high speed, then a series of processes to be executed by the microcomputer Until all the operations are completed, the operation clock does not change.
[0012]
Therefore, according to the present invention, when the microcomputer is executing control processing based on a plurality of application programs that are control software, a shift occurs in the control cycle and timing due to switching of the operation clock. Therefore, it is possible to prevent the stable control from being performed.
Also, when the microcomputer shifts to the sleep state, the CPU sets the operation clock to a low speed so that the microcomputer operates at a low speed when the microcomputer returns from the sleep state to the operation state, and then stops the operation clock. When the microcomputer returns from the sleep state (during wakeup), the microcomputer operates at a low speed. Thereafter, CPU is only when it is determined that the process proceeds to the control process according to any of the plurality of application programs, since the operation clock is to switch at high speed, to suppress unnecessary power consumption, also, micro Computer heat generation can also be suppressed.
According to a second aspect of the present invention, the microcomputer according to the first aspect is configured to execute an initialization process immediately after startup, and the operation clock generating means further includes a reference speed slower than a high speed. The operation clock can be generated. The CPU sets the operation clock to the reference speed during the initialization process immediately after startup, and then performs control to set the operation clock to a high speed. The operation clock at the reference speed performs the initialization process. It is characterized by being used only during execution. The invention described in claim 3 is characterized in that the microcomputer described in claim 1 or claim 2 is mounted on an automobile and configured to control each part of the automobile.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a microcomputer (hereinafter simply referred to as a microcomputer) 10 to which the present invention is applied.
[0014]
The microcomputer 10 of this embodiment is mounted on a car and used to control each part of the car, for example, and executes various control processes according to preset control software as shown in FIG. CPU 2 for controlling the vehicle, ROM 4 in which various data necessary for the CPU 2 to execute various control processes are stored in advance, and data for temporarily storing data used when the CPU 2 executes the various control processes The RAM 6 is mainly composed of an input / output unit 8 for inputting a detection signal indicating a state of each part of the automobile to be controlled and a command from an occupant and outputting various actuators for a control signal according to a calculation result in the CPU 2. These parts are connected to each other via a bus line.
[0015]
Further, the microcomputer 10 has a frequency divider that divides the reference clock having a constant frequency F0 input from the external oscillator 20 by N as an operation clock generation circuit that generates its own operation clock (hereinafter referred to as a system clock). 12 and a multiplier 14 that multiplies the frequency (= F0 / N) of the clock frequency-divided by the frequency divider 12 by a factor of M. The constant frequency F1 (= F0) output from the multiplier 14 is provided. × M / N) signal is supplied to an internal circuit (CPU 2 or the like) of the microcomputer 0 as a system clock.
[0016]
Then, the frequency dividing value N of the frequency divider 12 and the frequency multiplying value M of the multiplier 14 that determine the frequency F1 of the system clock are switched by the CPU 2 executing a program for setting an operation clock described later. For example, the frequency F1 of the system clock is switched from a reference speed of F1 = 8 MHz to a high speed of F1 = 16 MHz or a low speed of F1 = 4 MHz. Further, the frequency divider 12 or the multiplier 14 is configured to be able to switch the system clock to the stopped state at the frequency F1 = 0 by stopping the operation from the CPU 2 side.
[0017]
Next, the vehicle control software stored in the ROM 4 includes a plurality of applications (app A, app B, app C, app D, app E shown in the figure) as shown in FIG. ing. The ROM 4 also stores a state management program that realizes a function as a state management unit that manages a control state for each application generated by the CPU 2 executing these applications.
[0018]
This state management unit is realized by the CPU 2 periodically executing the state management program. As shown in FIG. 2 (b), each application for vehicle control is sequentially called and By fetching various requests, the control state by each application is detected, and each application is notified of the current control state (current state) of another application. In addition, when a call is received from the state management unit, each application outputs a request indicating a control state such as starting control or stopping control, and further increases the processing load for control. A speed-up request for raising the clock or a sleep prohibition request such as prohibiting the system clock from stopping and entering the sleep state because it is currently waiting for input of a detection signal from the outside is also output.
[0019]
As a result, each application side can grasp the overall control state by the microcomputer 10 and switch its own control state. The state management unit side operates the current microcomputer 10 at high speed based on the control state by each application. It is possible to determine whether the state is to be operated, the state to be operated at a low speed, or the state in which the sleep state is possible. Then, the state management unit switches the system clock from the reference speed to any one of high speed, stop, and low speed according to such a determination result.
[0020]
That is, the state management unit not only manages the control state of each application, but also switches the system clock according to the control state .
In this embodiment, the state management program for realizing the function as the state management unit is configured to switch the system clock as shown in FIGS. Hereinafter, the operation of the state management unit will be described with reference to FIGS.
[0021]
FIG. 3 is an explanatory diagram showing changes in the system clock, (a) is a state transition diagram showing transitions of the system clock, and (b) is a time chart showing an example of temporal changes in the system clock. FIG. 4 is a flowchart showing processing executed by the CPU 2 in accordance with the state management program in order to realize the function as the state management unit.
[0022]
First, immediately after the power is turned on to the microcomputer 10 (at power-on reset) and immediately after the CPU 2 is restarted (reset) (at CPU reset), the divided value of the frequency divider 12 and the multiplier 14 are multiplied. Since the value M is set to an initial value, the system clock has a reference speed of the frequency F1 = 8 MHz, and the CPU 2 has the system clock in the state of the reference speed and each part (the RAM 6 and the input / output unit 8, Alternatively, an initialization process for initializing a register (not shown) is executed. As shown in FIG. 4, the CPU 2 executes the initialization process (specifically, immediately before the initialization process ends). In S110 (S represents a step), the frequency division value of the frequency divider 12 and the frequency multiplication value M of the multiplier 14 are set so that the system clock has a high speed of frequency F1 = 16 MHz.
[0023]
As a result, as shown in FIG. 3, when the CPU 2 completes the initialization process and shifts to the normal control process for executing each application, the system clock is switched at high speed, and the CPU 2 operates at high speed. Then, the control process based on each application is started.
[0024]
Then, when the CPU 2 is executing the control process based on each application, as shown in FIG. 4, the control state is periodically monitored in S120, and all the control processes based on each application are performed in S130. Is once finished and it is determined whether or not it is in a control waiting state (that is, an idle state).
[0025]
The process of S120 and S130 is repeatedly executed until it is determined in S130 that all the control processes are completed, and if it is determined in S130 that all the control processes are completed (in other words, When the control process by the CPU 2 is in an idle state), in S140, the frequency division value of the frequency divider 12 and the frequency multiplication value M of the frequency multiplier 14 are set so that the system clock becomes a low speed of the frequency F1 = 4 MHz. In subsequent S150, the microcomputer 10 is switched to the sleep state by stopping the system clock.
[0026]
Thus, when the microcomputer 10 enters the sleep state, the sleep state continues until the preset wake-up time elapses or a wake-up request is input from the outside, and the preset wake-up time is reached. When the time elapses or a wakeup request is input from the outside, the microcomputer 10 automatically returns (wakes up) by a wakeup circuit (not shown).
[0027]
At this time, the frequency division value N of the frequency divider 12 and the frequency multiplication value M of the multiplier 14 are set so that the system clock becomes low speed. F1 = 4 MHz, and the microcomputer 10 operates at a low speed.
[0028]
Next, when the microcomputer 10 starts operating as described above, the control process based on each application is started. Therefore, after the microcomputer 10 is woken up, in S160, a speed-up request is made from the control process based on each application. Alternatively, a sleep prohibition request is made, and it is determined whether or not it is necessary to increase the system clock.
[0029]
If it is determined in S160 that it is necessary to increase the system clock speed, in S170, the frequency division value and the multiplier of the frequency divider 12 are set so that the system clock becomes a high speed of frequency F1 = 16 MHz. After the multiplication value M of 14 is set, the process proceeds to S120 described above. Conversely, if it is determined in S160 that the system clock does not need to be increased, the process proceeds to S150 and the microcomputer 10 is set to sleep again. Transition to the state.
[0030]
As a result, when the microcomputer 10 once enters the sleep state and wakes up, as shown in FIG. 3, the microcomputer 10 operates at a low speed and the control processing by each application is started. If it does not shift to normal control with a large processing load, it returns to the sleep state again, and only when any control process shifts to normal control with a large processing load, the system clock is switched at a high speed, and the microcomputer 10 operates at high speed. Will work.
[0031]
As described above, in the microcomputer 10 of the present embodiment, the system clock is set at a high speed after the start by the power-on reset or the CPU reset, and the control process for vehicle control is executed at a high speed. Thereafter, once each control process is finished and the idle state is entered, the system clock is stopped and the microcomputer 10 enters the sleep state.
[0032]
Also, when returning from the sleep state (wakeup), each control process is executed with the system clock set to a low speed, and if there is no clock-up request from each control process at that time, the system again The system clock is switched at high speed only when the clock is stopped, the sleep state is entered, and a clock up request is made.
[0033]
Therefore, according to the present embodiment, immediately after the microcomputer 10 is activated, each control process can be executed at high speed to quickly start the vehicle control, and at the time of return from the sleep state (wakeup). ) At low speed , unnecessary power consumption can be suppressed, and the microcomputer can be prevented from generating heat.
[0034]
In particular, in this embodiment, as is apparent from FIG. 3A, the microcomputer operates at low speed only when returning from the sleep state, and the system clock is not switched from high speed to low speed. Therefore, it is possible to prevent the vehicle from being unable to perform stable vehicle control due to a shift in the control cycle or timing in each control process as the system clock is switched.
[0036]
As mentioned above, although one Example of this invention was described, this invention is not limited to the said Example, A various aspect can be taken.
For example, in the above-described embodiment, the microcomputer 10 is described as being for vehicle control. However, the present invention is not limited to vehicle control, and may be any microcomputer as long as it is a microcomputer that controls various devices. When applied, the same effect can be obtained.
[0037]
In the above embodiment, the control software executed by the CPU 2 is composed of a plurality of applications, and switching the system clock to high speed, low speed, or stop is a state management as a state management unit that manages the control state of each application. The control program is explained as being realized by the CPU 2 executing, but there may be only one control software, and the CPU 2 executes the control software for switching the system clock. It may be realized by.
[0038]
In the above embodiment, the operation clock generation circuit for generating the system clock is built in the microcomputer 10, and the circuit is constituted by the frequency divider 12 and the multiplier 14. The operation clock generation circuit may be configured separately from the microcomputer 10, or the operation clock generation circuit may be configured only by the frequency divider 12 or the multiplier 14.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a microcomputer according to an embodiment.
FIG. 2 is an explanatory diagram illustrating the structure of software executed by the microcomputer according to the embodiment and the operation of the state management unit.
FIG. 3 is an explanatory diagram showing a state of a system clock that changes when a CPU executes a program as a state management unit.
FIG. 4 is a flowchart showing processing as a state management unit executed by a CPU.
[Explanation of symbols]
2 ... CPU, 4 ... ROM, 6 ... RAM, 8 ... input / output unit, 10 ... microcomputer, 12 ... frequency divider, 14 ... multiplier, 20 ... oscillator.

Claims (3)

  In a microcomputer that executes control processing based on each of a plurality of application programs according to an operation clock,
  An operation clock generating means capable of generating either the high-speed or low-speed operation clock and capable of stopping the operation clock;
  Storage means for storing the plurality of application programs, and a state management program for managing the control state of each of the plurality of application programs and switching the operation clock;
  Based on the state management program, the control state of each application program is monitored to determine whether the operation clock is high speed, low speed, or stopped. CPU that controls the setting and generation / stop of the operation clock,
  With
  The CPU
  After starting up the microcomputer, set the operating clock at high speed,
  When the microcomputer is operating at high speed according to the high-speed operation clock, if it is determined that all control processing based on each application program has been completed, the microcomputer operates at low speed when the microcomputer returns from the sleep state to the operating state. The operation clock is set to low speed, and then the operation clock is stopped to shift the microcomputer to the sleep state,
  When the preset wake-up time elapses or when the microcomputer returns to the operation state from the sleep state and receives a wake-up request from the outside, the plurality of applications -If it is determined that the control process is to be shifted to one of the programs, control is performed to set the operation clock at a high speed.
  A microcomputer in which the operation clock cannot be switched from a high speed to a low speed while a control process based on any one of the plurality of application programs is being executed.   The microcomputer is configured to execute an initialization process immediately after startup,
  The operation clock generation means can further generate an operation clock having a reference speed slower than the high speed,
  The CPU sets the operation clock to the reference speed while executing the initialization process immediately after startup, and then performs control to set the operation clock at a high speed.
  2. The microcomputer according to claim 1, wherein the operation clock at the reference speed is used only while the initialization process is being executed.   The microcomputer according to claim 1, wherein the microcomputer is mounted on a vehicle and controls each part of the vehicle.

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