JP3753421B2 - Semiconductor wafer processing method - Google Patents

Semiconductor wafer processing method Download PDF

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JP3753421B2
JP3753421B2 JP2002008910A JP2002008910A JP3753421B2 JP 3753421 B2 JP3753421 B2 JP 3753421B2 JP 2002008910 A JP2002008910 A JP 2002008910A JP 2002008910 A JP2002008910 A JP 2002008910A JP 3753421 B2 JP3753421 B2 JP 3753421B2
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tape
protective tape
semiconductor wafer
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adhesive
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JP2003209073A (en
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尾 秀 男 妹
元 公 市 永
米 克 彦 堀
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Lintec Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

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Description

【0001】
【産業上の利用分野】
本発明は、半導体ウエハの加工方法に関係し、特に半導体ウエハの回路面を保護しながらダイシング加工を行う加工方法に関する。
【0002】
【従来の技術】
半導体装置を製造する際、ダイシング工程においては回路が形成されている面は、通常は保護されず、むき出しの状態でダイシングが行われている。
しかしながらCCDのような光学センサの機能を発揮する半導体装置では、安定した性能を得るために、回路面を確実に保護できる保護用の粘着テープ(以下、保護テープ)が望まれている。しかし、単に保護テープを回路面に貼付した状態でダイシング工程を行うと、保護用テープも一緒にダイシングされてしまう。ダイシング後には、保護テープを各チップの回路面から剥離するが、保護テープも多数のチップ毎に分割されているため、その剥離作業は繁雑になる。また、保護テープよりも広い剥離用の粘着テープを用いて保護テープを剥離しようとすると、部分的に接着不足の箇所ができてしまうため、保護テープのすべてをチップから確実には剥離できなかった。
【0003】
これを解消するために、本出願人は特公平5−7168において、熱収縮フィルムと放射線硬化性粘着剤層からなる保護テープを用いたウエハ切断方法を提案している。このウエハ切断方法は、ダイシング後に粘着剤層を放射線硬化して粘着力を低下させた後、加熱により熱収縮フィルムを収縮させることにより、保護テープがウエハからめくれる形で剥離し、エアブローすることにより、ダイシングされてバラバラになった保護テープを除去することができる。
【0004】
【発明の解決しようとする課題】
しかしながら、前記の方法においては粘着剤が加熱され軟化しているため、めくれた後の保護テープがチップ表面に付着している部分と、剥離した部分との境界線において微小な糊残りが発生しやすくなっている。この境界線はチップの中央部となるため、高精度の光学センサのような半導体装置の保護には、前記の方法は不充分である場合があった。
【0005】
本発明の目的は、前記のような問題点を鑑み、糊残りを発生させずにバラバラとなった保護テープを確実に回路面から剥離できる半導体ウエハの加工方法を提供することにある。
【0006】
【課題を解決するための手段】
本発明に係る半導体ウエハの加工方法は、
半導体ウエハの回路面側に保護テープを貼付し、
該半導体ウエハの裏面側にダイシングテープを貼付し、
保護テープとともに半導体ウエハをダイシングしてチップを形成した後、
ダイシングされた保護テープ上に剥離テープを貼付し、
加熱によって保護テープを部分的に変形させた後、剥離テープとともにダイシングされた保護テープをチップより剥離することを特徴としている。
【0007】
このような本発明においては、前記半導体ウエハの裏面側にダイシングテープを貼付する前に、該半導体ウエハの裏面側を所定の厚さに研磨又はエッチングすることが好ましい。
また、本発明における好ましい態様として、
保護テープが熱収縮性フィルムを基材とする粘着テープよりなり、
保護テープを変形させる際の加熱条件が、該基材の熱収縮率が3%〜50%となる条件である態様があげられる。
【0008】
また、本発明における他の好ましい態様として、
保護テープが熱可塑性フィルムを基材とする粘着テープよりなり、
保護テープを変形させる際の加熱条件が、該基材の融点−20℃以上且つ融点+40℃以下となる条件である態様があげられる。
このような本発明に係る半導体ウエハの加工方法によれば、糊残りを発生させずに、バラバラとなった保護テープを確実にチップ裏面から剥離できる。
【0009】
【発明の実施の形態】
以下、本発明に係る半導体ウエハの加工方法について、具体的に説明する。
本発明に係る半導体ウエハの加工方法では、まず図1に示すように、半導体ウエハ10の回路面側に保護テープ11を貼付し、回路面の保護を行う。
半導体ウエハ10に保護テープ11を貼付した後、研磨又はエッチングにより裏面側を所定の厚さとする加工を行ったもよい。また既に研磨又はエッチングによる裏面側の加工を施した半導体ウエハを用いてもよい。
【0010】
保護テープ11は、図1に示すように、基材1とその上に形成された粘着剤層2とからなり、粘着剤層2をウエハ表面に貼着し、回路面の保護を行う。
基材1としては、加熱により変形しうる樹脂フィルムが用いられ、好ましくは熱収縮性フィルムまたは熱可塑性フィルムが用いられる。
熱収縮性フィルムとしては、たとえば、ポリエチレン、ポリプロピレン、ポリメチルペンテン等のポリオレフィン、ポリ塩化ビニル、ポリエステル等からなる延伸フィルムが好ましく用いられる。また、熱収縮性フィルムは、上記のようなフィルムの単層品であってもよく、またこれらの積層品であってもよい。積層フィルムの場合は、収縮率の異なるフィルムを組み合わせることが好ましく、たとえば上層を高収縮性フィルムとし、下層を低収縮性フィルムとすることが好ましい。
【0011】
熱収縮性フィルムとしては、後述する変形工程の加熱条件下での熱収縮率が3%〜50%、さらに好ましくは4〜40%、特に好ましくは5〜30%であるものが好適に選択される。すなわち、保護テープの変形を、100℃で行う場合には、該熱収縮性フィルムとしては、100℃における熱収縮率が、3%〜50%となるものが選択される。
【0012】
ここで、熱収縮率は、該フィルム単独を所定温度において、1分間保持した後に、収縮前の寸法と収縮後の寸法とから、下記の数式に基づき算出する。
【0013】
【数1】

Figure 0003753421
【0014】
すなわち、変形工程の加熱条件とは、前記熱収縮性フィルムの熱収縮率が、3%〜50%となるように設定されるものである。
熱可塑性フィルムとしては、たとえば、ポリエチレン、ポリプロピレン、ポリメチルペンテン等のポリオレフィン、ポリ塩化ビニル、ポリエステル等からなる未延伸フィルムが好ましく用いられる。
【0015】
熱可塑性フィルムは、後述する変形工程の加熱条件下での加熱温度が、該熱可塑性フィルムの融点−20℃以上且つ融点+40℃以下、好ましくは融点−15℃以上且つ融点+35℃以下、特に好ましくは融点−10℃以上且つ融点+30℃以下となるように選択される。
これらの熱収縮性フィルムまたは熱可塑性フィルムからなる基材1の厚さは特に限定はされないが、好ましくは5〜200μm、特に好ましくは10〜150μmである。
【0016】
粘着剤層2は、汎用の粘着剤からなるものであってもよく、またいわゆるエネルギー線硬化型粘着剤からなるものであってもよい。
汎用粘着剤としては、アクリル系、ポリエステル系、天然ゴム系等従来公知の粘着剤が特に制限されることなく用いられる。これらの内でも、アクリル系粘着剤が好ましく、特にアクリル酸エステルを主たる構成単位とするアクリル系粘着剤が好ましい。
【0017】
また、エネルギー線硬化型粘着剤としては、たとえば特開昭60−196,956号公報、特開昭60−223,139号公報、特開平5−32946号公報、特開平8−27239号公報等に記載のものが特に制限されることなく用いられる。
粘着剤層2の厚さは特に限定はされないが、好ましくは3〜100μm、特に好ましくは5〜50μmである。
【0018】
本発明では、上記保護テープ11を、ウエハ回路面に貼着し、回路面の保護した後、半導体ウエハ10の裏面側にダイシングテープ12を貼付してウエハ10を固定し、保護テープ11とともに半導体ウエハ10をダイシングしてチップ13を形成する(図2参照)。チップ13の回路面側には、ダイシングされて小さくなった保護テープ11がなお貼付されている。
【0019】
ダイシングテープ12としては、汎用のダイシングテープが特に制限されることなく用いられる。しかし、後述する変形工程の加熱温度が高温である場合には、ダイシングテープの基材としては、ポリエチレンテレフタレート等の耐熱性に優れた樹脂フィルムを用いることが好ましい。
このようなダイシングにより、ダイシングテープ11上には、回路面側に保護テープ11が貼付されているチップ13が整列固着されている状態になる。
【0020】
次いで、本発明では、チップ13の回路面から保護テープ11を剥離する。
保護テープ11の剥離に際しては、まず、ダイシングされた保護テープ11上に剥離テープ14を貼付する(図3参照)。
なお、保護テープ11の粘着剤層2をエネルギー線硬化型粘着剤で形成した場合には、剥離テープ14は、基材、粘着剤層ともにエネルギー線透過性のものを用いる。この場合、剥離テープ14の貼付後、剥離テープ側からエネルギー線を照射し、粘着剤層2の粘着力を低減しておくことが好ましい。また、剥離テープ14の貼付前にエネルギー線を照射してもよいが、この場合には、剥離テープ14はエネルギー線透過性はなくてもよい。
【0021】
剥離テープ14としては、ウエハと略同形状の粘着テープが用いられ、好ましくは強粘着テープが用いられる。このような剥離テープとしては、汎用の粘着テープが特に制限されることなく用いられるが、後述する変形工程の加熱温度が高温である場合には、剥離テープ14の基材としては、ポリエチレンテレフタレート等の耐熱性に優れた樹脂フィルムを用いることが好ましい。
【0022】
次に、剥離テープ14が貼付された状態で加熱し、保護テープ11を変形させる。
加熱は、たとえばオーブンを用いることにより行われるが、これに限定されず、保護テープ11を変形しうる手段であればよい。
加熱により、保護テープ11の基材1が部分的に変形し、剥離テープ14と密着するようになる。
【0023】
基材1として熱収縮性フィルムを用いた場合には、熱収縮率が3%〜50%となる温度範囲で加熱を行う。この結果、基材1が収縮変形し、保護テープ11と剥離テープ14とが密着する。
また、基材1として熱可塑性フィルムを用いた場合には、該熱可塑性フィルムの融点−20℃以上且つ融点+40℃以下の温度範囲で加熱を行う。この結果、基材1が軟化あるいは溶融して変形し、保護テープ11と剥離テープ14とが密着する。
【0024】
このように、保護テープ11と剥離テープ14とが密着しているため、剥離テープ14を剥離すると、保護テープ11もこれに同伴して剥離する(図4)。この結果、多数に分割されたチップ上の保護テープ11を一括して簡便に剥離できることとなり、作業効率は大幅に向上し、また、チップ上への糊残りも無くなるので、歩留も改善される。
【0025】
剥離テープ14を剥離する際には、剥離テープ14の基材側に、さらに強粘着テープあるいはヒートシールテープを固着して、これを起点として剥離してもよく、また剥離テープ14の端部に掴み部を設けておき、これを起点として機械的に剥離してもよい。
この結果、ダイシングテープ12上には、回路面が露出したチップ13が整列している状態となる。その後、常法により、チップのピックアップ、マウントを行うことで半導体装置が得られる。
【0026】
このような本発明により奏される作用効果のメカニズムは、何ら限定されるものではないが、次のように考えられる。
従来法(特公平5−7168)における加工方法においては、保護テープの加熱収縮によるめくれが止まった段階では、まだ粘着剤も加熱状態で流動性があり、接着部分と剥離部分の境界線では加熱により図5のような変形が起こる。このとき変形した粘着剤の一部は、チップの表面に再付着するようになる。粘着剤の変形部分は基材フィルムに対する密着力が低下しているため、冷却して保護テープを除去する力が加われば、変形し再付着した部分の粘着剤が基材から脱落し、これがチップへの糊残りの要因となると考えられる。
【0027】
これに対し、本発明の加工方法においては、保護テープの粘着剤層をチップから剥離するまで熱変形させない。加熱前に、保護テープ面上に剥離テープを貼付するため、加熱時には保護テープは、チップと剥離シートに挟持された状態にある。このため、保護シートの熱変形は抑制され、基材の端部のみが部分的に変形し、これによって剥離テープの粘着剤との密着が向上する。このため、場所によっては保護テープと剥離テープとの密着が不足していた箇所(特に剥離の起点となる端部)においても、充分な接着力が得られる。これによって、剥離テープを引き剥がせば切断された保護テープの全てが確実にチップ面より除去できるようになる。
【0028】
また、保護テープは加熱によっても剥離することがないため、粘着剤層はほとんど変形しない。このため、粘着剤層と基材フィルムとの密着力は低下しておらず、剥離を行ってもチップ面に糊残りが起こることがないと考えられる。
【0029】
【発明の効果】
本発明に係る半導体ウエハの加工方法によれば、糊残りを発生させずに、バラバラとなった保護テープを確実にチップ裏面から剥離できる。したがってCCDに例示される光学センサのような半導体装置の製造に好適な加工方法を提供できる。
【0030】
【実施例】
以下本発明を実施例により説明するが、本発明はこれら実施例に限定されるものではない。
【0031】
【実施例1】
テープラミネータ(リンテック社製、Adwill RAD-3500m/12)を用いて、150mm径のシリコンウエハの回路面に、基材として熱収縮フィルム(80℃における熱収縮率9%)及び紫外線硬化型の粘着剤層を使用した保護テープ(リンテック社製、Adwill P-5780LS123E)を貼付し、シリコンウエハの裏面側を研磨装置(ディスコ社製、DFG−840)を用いて350μm厚に加工した。次に、テープマウンタ(リンテック社製、Adwill RAD-2500m/8)を用いて、ダイシングテープ(リンテック社製、Adwill D-220)をシリコンウエハの裏面(研磨面)側に貼付し、リングフレーム(ディスコ社製、MODTF2−6−1)に固定した。さらに、 ダイシング装置(東京精密社製、AWD-4000B)を用いて、保護テープごとシリコンウエハを1mm×15mmのサイズにフルカットダイシングした。
【0032】
続いて、紫外線照射装置(リンテック社製、Adwill RAD-2000m/8)を用いて保護テープ側に紫外線を照射し、保護テープの粘着力を低減化した。次に、下記構成の剥離テープを、ダイシングされた保護テープ面に貼付した。さらに、オーブンにリングフレームに固定されたシリコンウエハを投入し、80℃1分間の加熱を行った。常温に冷却した後、剥離テープの背面に強粘着力タイプの引剥し用のテープ(リンテック社製、Adwill S-6、幅50mm)を貼着し剥離テープと保護テープを同時に引き剥がした。
【0033】
保護テープの剥離性と剥離後のシリコンウエハ面の糊残りを100倍の光学顕微鏡を用いて確認した。結果を表1に示す。
剥離テープの構成:
50μm厚のポリエチレンテレフタレートフィルムの片面に、10μm厚のアクリル系強粘着剤(リンテック社製、PK)を塗布した粘着テープ(直径150mmの略ウエハ形状)
【0034】
【実施例2】
融点が98℃の熱可塑性フィルムを基材に使用し、紫外線硬化型の粘着剤層を有するリンテック社製、Adwill D-611を保護テープとして使用し、加熱条件を100℃1分間とした以外は、実施例1と同様にして操作を行った。結果を表1に示す。
【0035】
【比較例1】
加熱を行わなかった以外は、実施例1と同様にして操作を行った。結果を表1に示す。
【0036】
【比較例2】
加熱を行わなかった以外は、実施例2と同様にして操作を行った。結果を表1に示す。
【0037】
【比較例3】
剥離テープを使用せず、保護テープを加熱で熱収縮させエアブローで保護テープを除去した以外は、実施例1と同様にして操作を行った。結果を表1に示す。
【0038】
【表1】
Figure 0003753421
【0039】
(1)剥離テープと保護テープの界面で剥離するチップが発生し、すべてのチップ上から保護テープを除去することが不可能。
(2)エアブローによりすべてのチップ上から収縮した保護テープを除去することが可能。
【図面の簡単な説明】
【図1】本発明に係る半導体ウエハの加工方法の一工程を示す。
【図2】本発明に係る半導体ウエハの加工方法の一工程を示す。
【図3】本発明に係る半導体ウエハの加工方法の一工程を示す。
【図4】本発明に係る半導体ウエハの加工方法の一工程を示す。
【図5】従来法(特公平5−7168)における糊残りの要因を示す。
【符号の説明】
1…基材
2…粘着剤層
10…半導体ウエハ
11…保護テープ
12…ダイシングテープ
13…チップ
14…剥離テープ[0001]
[Industrial application fields]
The present invention relates to a semiconductor wafer processing method, and more particularly, to a processing method for performing dicing while protecting a circuit surface of a semiconductor wafer.
[0002]
[Prior art]
When manufacturing a semiconductor device, a surface on which a circuit is formed is not usually protected in a dicing process, and dicing is performed in an exposed state.
However, in a semiconductor device that exhibits the function of an optical sensor such as a CCD, a protective adhesive tape (hereinafter referred to as a protective tape) that can reliably protect a circuit surface is desired in order to obtain stable performance. However, if the dicing process is performed with the protective tape simply applied to the circuit surface, the protective tape is also diced together. After dicing, the protective tape is peeled off from the circuit surface of each chip. However, since the protective tape is also divided into a large number of chips, the peeling work becomes complicated. In addition, when trying to peel off the protective tape using an adhesive tape for peeling wider than the protective tape, a partially insufficiently bonded part was created, so the entire protective tape could not be reliably peeled off from the chip. .
[0003]
In order to solve this problem, the present applicant has proposed a wafer cutting method using a protective tape comprising a heat-shrinkable film and a radiation-curable pressure-sensitive adhesive layer in Japanese Patent Publication No. 5-7168. In this wafer cutting method, after dicing, the adhesive layer is radiation-cured to reduce the adhesive force, and then the heat-shrinkable film is shrunk by heating, so that the protective tape is peeled off from the wafer and air blown. The protective tape that has been diced to pieces can be removed.
[0004]
[Problem to be Solved by the Invention]
However, in the above method, since the adhesive is heated and softened, a minute adhesive residue is generated at the boundary line between the part where the protective tape is attached to the chip surface and the peeled part. It has become easier. Since this boundary line is at the center of the chip, the above-described method may not be sufficient for protecting a semiconductor device such as a high-precision optical sensor.
[0005]
In view of the above-described problems, an object of the present invention is to provide a semiconductor wafer processing method capable of reliably peeling a separated protective tape from a circuit surface without generating adhesive residue.
[0006]
[Means for Solving the Problems]
A method for processing a semiconductor wafer according to the present invention includes:
Affix the protective tape to the circuit side of the semiconductor wafer,
Affixing dicing tape on the back side of the semiconductor wafer,
After dicing the semiconductor wafer together with the protective tape to form the chip,
Affix the release tape on the diced protective tape,
After the protective tape is partially deformed by heating, the protective tape diced together with the release tape is peeled off from the chip.
[0007]
In the present invention, it is preferable to polish or etch the back surface side of the semiconductor wafer to a predetermined thickness before applying the dicing tape to the back surface side of the semiconductor wafer.
Moreover, as a preferable aspect in the present invention,
The protective tape consists of an adhesive tape based on a heat-shrinkable film,
There is an embodiment in which the heating condition when deforming the protective tape is a condition in which the thermal shrinkage of the substrate is 3% to 50%.
[0008]
Moreover, as another preferred embodiment of the present invention,
The protective tape consists of an adhesive tape based on a thermoplastic film,
There is an embodiment in which the heating condition for deforming the protective tape is a condition in which the melting point of the substrate is −20 ° C. or more and the melting point + 40 ° C.
According to such a method for processing a semiconductor wafer according to the present invention, the separated protective tape can be reliably peeled off from the back surface of the chip without generating adhesive residue.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor wafer processing method according to the present invention will be specifically described below.
In the semiconductor wafer processing method according to the present invention, first, as shown in FIG. 1, a protective tape 11 is applied to the circuit surface side of the semiconductor wafer 10 to protect the circuit surface.
After applying the protective tape 11 to the semiconductor wafer 10, the back surface may be processed to have a predetermined thickness by polishing or etching. Further, a semiconductor wafer that has already been processed on the back side by polishing or etching may be used.
[0010]
As shown in FIG. 1, the protective tape 11 includes a base material 1 and an adhesive layer 2 formed thereon, and the adhesive layer 2 is adhered to the wafer surface to protect the circuit surface.
As the substrate 1, a resin film that can be deformed by heating is used, and a heat-shrinkable film or a thermoplastic film is preferably used.
As the heat-shrinkable film, for example, a stretched film made of polyolefin such as polyethylene, polypropylene, polymethylpentene, polyvinyl chloride, polyester or the like is preferably used. In addition, the heat-shrinkable film may be a single layer product of the above film or a laminate of these. In the case of a laminated film, it is preferable to combine films having different shrinkage rates. For example, the upper layer is preferably a highly shrinkable film and the lower layer is preferably a low shrinkage film.
[0011]
As the heat-shrinkable film, a film having a heat shrinkage rate of 3% to 50%, more preferably 4 to 40%, and particularly preferably 5 to 30% under the heating conditions of the deformation process described later is suitably selected. The That is, when the protective tape is deformed at 100 ° C., the heat shrinkable film is selected such that the heat shrinkage rate at 100 ° C. is 3% to 50%.
[0012]
Here, the thermal shrinkage rate is calculated based on the following formula from the dimensions before shrinkage and the dimensions after shrinkage after holding the film alone at a predetermined temperature for 1 minute.
[0013]
[Expression 1]
Figure 0003753421
[0014]
That is, the heating conditions of the deformation step are set so that the heat shrinkage rate of the heat shrinkable film is 3% to 50%.
As the thermoplastic film, for example, an unstretched film made of polyolefin such as polyethylene, polypropylene, polymethylpentene, polyvinyl chloride, polyester or the like is preferably used.
[0015]
The thermoplastic film has a heating temperature under the heating conditions of the deformation step described later, the melting point of the thermoplastic film is −20 ° C. or higher and the melting point + 40 ° C. or lower, preferably the melting point −15 ° C. or higher and the melting point + 35 ° C. or lower, particularly preferably. Is selected so as to have a melting point of −10 ° C. or higher and a melting point of + 30 ° C. or lower.
Although the thickness of the base material 1 which consists of these heat-shrinkable films or thermoplastic films is not specifically limited, Preferably it is 5-200 micrometers, Most preferably, it is 10-150 micrometers.
[0016]
The pressure-sensitive adhesive layer 2 may be made of a general-purpose pressure-sensitive adhesive, or may be made of a so-called energy beam curable pressure-sensitive adhesive.
As the general-purpose pressure-sensitive adhesive, known pressure-sensitive adhesives such as acrylic, polyester, and natural rubber are used without particular limitation. Among these, an acrylic pressure-sensitive adhesive is preferable, and an acrylic pressure-sensitive adhesive having an acrylate ester as a main constituent unit is particularly preferable.
[0017]
Examples of the energy ray-curable pressure-sensitive adhesive include, for example, JP-A-60-196,956, JP-A-60-223,139, JP-A-5-32946, and JP-A-8-27239. Those described in (1) are used without particular limitation.
Although the thickness of the adhesive layer 2 is not specifically limited, Preferably it is 3-100 micrometers, Most preferably, it is 5-50 micrometers.
[0018]
In the present invention, the protective tape 11 is attached to the wafer circuit surface to protect the circuit surface, and then the dicing tape 12 is attached to the back side of the semiconductor wafer 10 to fix the wafer 10. The wafer 10 is diced to form chips 13 (see FIG. 2). On the circuit surface side of the chip 13, the protective tape 11 that has been diced and made smaller is still attached.
[0019]
As the dicing tape 12, a general-purpose dicing tape is used without particular limitation. However, when the heating temperature in the deformation process described later is high, it is preferable to use a resin film excellent in heat resistance such as polyethylene terephthalate as the base material of the dicing tape.
By such dicing, the chip 13 having the protective tape 11 attached to the circuit surface side is aligned and fixed on the dicing tape 11.
[0020]
Next, in the present invention, the protective tape 11 is peeled off from the circuit surface of the chip 13.
When peeling off the protective tape 11, first, the peeling tape 14 is stuck on the diced protective tape 11 (see FIG. 3).
When the pressure-sensitive adhesive layer 2 of the protective tape 11 is formed of an energy ray-curable pressure-sensitive adhesive, the base material and the pressure-sensitive adhesive layer are both transparent to the energy ray. In this case, it is preferable to reduce the adhesive strength of the pressure-sensitive adhesive layer 2 by applying energy rays from the side of the release tape after the release tape 14 has been applied. Moreover, although an energy ray may be irradiated before sticking of the peeling tape 14, in this case, the peeling tape 14 does not need to be energy-beam permeable.
[0021]
As the peeling tape 14, an adhesive tape having substantially the same shape as the wafer is used, and preferably a strong adhesive tape is used. As such a release tape, a general-purpose pressure-sensitive adhesive tape is used without particular limitation, but when the heating temperature in the deformation process described later is high, the base material of the release tape 14 is polyethylene terephthalate or the like. It is preferable to use a resin film having excellent heat resistance.
[0022]
Next, the protective tape 11 is deformed by heating with the release tape 14 attached.
The heating is performed by using, for example, an oven, but is not limited to this, and any means that can deform the protective tape 11 may be used.
By heating, the substrate 1 of the protective tape 11 is partially deformed and comes into close contact with the peeling tape 14.
[0023]
When a heat-shrinkable film is used as the substrate 1, heating is performed in a temperature range where the heat shrinkage rate is 3% to 50%. As a result, the base material 1 shrinks and deforms, and the protective tape 11 and the peeling tape 14 are in close contact with each other.
When a thermoplastic film is used as the substrate 1, heating is performed in a temperature range of the melting point of the thermoplastic film from −20 ° C. to the melting point + 40 ° C. As a result, the base material 1 is softened or melted and deformed, and the protective tape 11 and the peeling tape 14 are in close contact with each other.
[0024]
Thus, since the protective tape 11 and the peeling tape 14 are closely_contact | adhered, if the peeling tape 14 is peeled, the protective tape 11 will also be accompanied and will peel (FIG. 4). As a result, the protective tape 11 on the chip divided into a large number can be easily and collectively peeled off, the working efficiency is greatly improved, and the adhesive residue on the chip is eliminated, so that the yield is also improved. .
[0025]
When the release tape 14 is peeled off, a strong adhesive tape or a heat seal tape may be further fixed to the substrate side of the release tape 14 and may be peeled off from the starting point. A gripping portion may be provided and mechanically peeled off starting from this.
As a result, the chips 13 whose circuit surfaces are exposed are aligned on the dicing tape 12. Thereafter, a semiconductor device is obtained by picking up and mounting the chip by a conventional method.
[0026]
Although the mechanism of the effect produced by this invention is not limited at all, it is considered as follows.
In the processing method in the conventional method (Japanese Patent Publication No. 5-7168), the adhesive is still fluid in the heated state at the stage where the curling due to the heat shrinkage of the protective tape has stopped, and is heated at the boundary line between the bonded portion and the peeled portion. As a result, deformation as shown in FIG. 5 occurs. At this time, a part of the deformed adhesive comes to reattach to the surface of the chip. Since the adhesive force of the deformed part of the adhesive is reduced to the base film, if the cooling force is applied to remove the protective tape, the deformed and reattached part of the adhesive will fall off the base, and this will be the chip. It is thought that it becomes a factor of glue residue.
[0027]
On the other hand, in the processing method of the present invention, the adhesive layer of the protective tape is not thermally deformed until it is peeled from the chip. Since the release tape is stuck on the surface of the protective tape before heating, the protective tape is sandwiched between the chip and the release sheet during heating. For this reason, the thermal deformation of the protective sheet is suppressed, and only the end portion of the substrate is partially deformed, thereby improving the adhesion of the release tape to the adhesive. For this reason, sufficient adhesive force is obtained also in the location (especially edge part used as the starting point of peeling) where adhesion with the protective tape and the peeling tape was insufficient depending on the location. Thus, if the release tape is peeled off, all of the cut protective tape can be surely removed from the chip surface.
[0028]
Further, since the protective tape is not peeled off even by heating, the pressure-sensitive adhesive layer hardly deforms. For this reason, the adhesive force between the pressure-sensitive adhesive layer and the base film is not lowered, and it is considered that no adhesive residue occurs on the chip surface even when peeling is performed.
[0029]
【The invention's effect】
According to the semiconductor wafer processing method of the present invention, the separated protective tape can be reliably peeled from the chip back surface without generating adhesive residue. Therefore, it is possible to provide a processing method suitable for manufacturing a semiconductor device such as an optical sensor exemplified by a CCD.
[0030]
【Example】
EXAMPLES The present invention will be described below with reference to examples, but the present invention is not limited to these examples.
[0031]
[Example 1]
Using tape laminator (Adwill RAD-3500m / 12, manufactured by Lintec Corporation), heat shrink film (heat shrinkage 9% at 80 ° C) and UV curable adhesive on the circuit surface of 150mm diameter silicon wafer A protective tape (Adwill P-5780LS123E manufactured by Lintec Co., Ltd.) using the agent layer was applied, and the back side of the silicon wafer was processed to a thickness of 350 μm using a polishing apparatus (DFG-840 manufactured by Disco Co.). Next, using a tape mounter (Adwill RAD-2500m / 8, manufactured by Lintec), a dicing tape (Adwill D-220, manufactured by Lintec) is attached to the back surface (polished surface) of the silicon wafer, and a ring frame ( It was fixed to MODTF2-6-1) manufactured by DISCO. Furthermore, using a dicing machine (AWD-4000B, manufactured by Tokyo Seimitsu Co., Ltd.), the silicon wafer along with the protective tape was fully cut into a size of 1 mm × 15 mm.
[0032]
Subsequently, UV light was irradiated to the protective tape side using an ultraviolet irradiation device (Adwill RAD-2000m / 8, manufactured by Lintec Corporation) to reduce the adhesive strength of the protective tape. Next, the peeling tape of the following structure was stuck on the diced protective tape surface. Furthermore, the silicon wafer fixed to the ring frame was put into an oven and heated at 80 ° C. for 1 minute. After cooling to room temperature, a strong adhesive type peeling tape (Adwill S-6, manufactured by Lintec Co., Ltd., width 50 mm) was attached to the back surface of the peeling tape, and the peeling tape and the protective tape were peeled off simultaneously.
[0033]
The peelability of the protective tape and the adhesive residue on the silicon wafer surface after peeling were confirmed using a 100 × optical microscope. The results are shown in Table 1.
Composition of release tape:
Adhesive tape with a 10 μm thick acrylic adhesive (PK, manufactured by Lintec Corporation) applied to one side of a 50 μm thick polyethylene terephthalate film (approximately wafer shape with a diameter of 150 mm)
[0034]
[Example 2]
Except for using a thermoplastic film with a melting point of 98 ° C. as a base material, using Adwill D-611 made by Lintec Co., Ltd. having a UV curable adhesive layer as a protective tape, and heating conditions at 100 ° C. for 1 minute. The operation was performed in the same manner as in Example 1. The results are shown in Table 1.
[0035]
[Comparative Example 1]
The operation was performed in the same manner as in Example 1 except that heating was not performed. The results are shown in Table 1.
[0036]
[Comparative Example 2]
The operation was performed in the same manner as in Example 2 except that heating was not performed. The results are shown in Table 1.
[0037]
[Comparative Example 3]
The operation was performed in the same manner as in Example 1 except that the peeling tape was not used and the protective tape was thermally contracted by heating and the protective tape was removed by air blowing. The results are shown in Table 1.
[0038]
[Table 1]
Figure 0003753421
[0039]
(1) A chip is peeled off at the interface between the peeling tape and the protective tape, and it is impossible to remove the protective tape from all the chips.
(2) It is possible to remove the shrinking protective tape from above all the chips by air blow.
[Brief description of the drawings]
FIG. 1 shows one step of a semiconductor wafer processing method according to the present invention.
FIG. 2 shows one step of a method for processing a semiconductor wafer according to the present invention.
FIG. 3 shows one step of a method for processing a semiconductor wafer according to the present invention.
FIG. 4 shows one step of a method for processing a semiconductor wafer according to the present invention.
FIG. 5 shows the cause of adhesive residue in the conventional method (Japanese Patent Publication No. 5-7168).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base material 2 ... Adhesive layer 10 ... Semiconductor wafer 11 ... Masking tape 12 ... Dicing tape 13 ... Chip 14 ... Release tape

Claims (4)

半導体ウエハの回路面側に保護テープを貼付し、
該半導体ウエハの裏面側にダイシングテープを貼付し、
保護テープとともに半導体ウエハをダイシングしてチップを形成した後、
ダイシングされた保護テープ上に剥離テープを貼付し、
加熱によって保護テープを部分的に変形させた後、剥離テープとともにダイシングされた保護テープをチップより剥離することを特徴とする半導体ウエハの加工方法。
Affix the protective tape to the circuit side of the semiconductor wafer,
Affixing dicing tape on the back side of the semiconductor wafer,
After dicing the semiconductor wafer together with the protective tape to form the chip,
Affix the release tape on the diced protective tape,
A method for processing a semiconductor wafer, comprising: partially deforming a protective tape by heating; and then peeling the protective tape diced together with the release tape from the chip.
前記半導体ウエハの裏面側にダイシングテープを貼付する前に、該半導体ウエハの裏面側を所定の厚さに研磨又はエッチングすることを特徴とする請求項1記載の半導体ウエハの加工方法。2. The method of processing a semiconductor wafer according to claim 1, wherein the back side of the semiconductor wafer is polished or etched to a predetermined thickness before a dicing tape is attached to the back side of the semiconductor wafer. 保護テープが熱収縮性フィルムを基材とする粘着テープよりなり、
保護テープを変形させる際の加熱条件が、該基材の熱収縮率が3%〜50%となる条件であることを特徴とする請求項1又は2記載の半導体ウエハの加工方法。
The protective tape consists of an adhesive tape based on a heat-shrinkable film,
The method for processing a semiconductor wafer according to claim 1 or 2, wherein the heating condition when the protective tape is deformed is a condition that the thermal shrinkage of the substrate is 3% to 50%.
保護テープが熱可塑性フィルムを基材とする粘着テープよりなり、
保護テープを変形させる際の加熱条件が、該基材の融点−20℃以上且つ融点+40℃以下となる条件であることを特徴とする請求項1又は2記載の半導体ウエハの加工方法。
The protective tape consists of an adhesive tape based on a thermoplastic film,
The method for processing a semiconductor wafer according to claim 1 or 2, wherein the heating condition when the protective tape is deformed is a condition that the melting point of the substrate is -20 ° C or higher and the melting point + 40 ° C or lower.
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Publication number Priority date Publication date Assignee Title
KR100486290B1 (en) * 2002-12-23 2005-04-29 삼성전자주식회사 Assembling method of semiconductor package and removal apparatus of protection tape in semiconductor process
JP2006316078A (en) * 2003-10-17 2006-11-24 Lintec Corp Method and apparatus for peeling adhesive tape
CN1894796B (en) 2003-12-15 2010-09-01 株式会社半导体能源研究所 Process for fabricating thin film integrated circuit device, noncontact thin film integrated circuit device and its fabrication process
US7271076B2 (en) 2003-12-19 2007-09-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of thin film integrated circuit device and manufacturing method of non-contact type thin film integrated circuit device
US7566010B2 (en) 2003-12-26 2009-07-28 Semiconductor Energy Laboratory Co., Ltd. Securities, chip mounting product, and manufacturing method thereof
US7632721B2 (en) 2004-02-06 2009-12-15 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film integrated circuit, and element substrate
JP4558345B2 (en) * 2004-02-19 2010-10-06 リンテック株式会社 Protective sheet and semiconductor wafer processing method
US7820529B2 (en) 2004-03-22 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing integrated circuit
JP2007134390A (en) * 2005-11-08 2007-05-31 Disco Abrasive Syst Ltd Processing process of wafer
JP2009275060A (en) * 2008-05-12 2009-11-26 Nitto Denko Corp Adhesive sheet, method for processing adherend using the adhesive sheet, and adhesive sheet-peeling device
JP2010087280A (en) * 2008-09-30 2010-04-15 Panasonic Electric Works Co Ltd Manufacturing method of functional device and manufacturing method of semiconductor device, which uses functional device manufactured by the same
JP2011014652A (en) * 2009-06-30 2011-01-20 Panasonic Electric Works Co Ltd Method of manufacturing functional device, and method of manufacturing semiconductor device using functional device manufactured by the method
JP2011054641A (en) * 2009-08-31 2011-03-17 Nitto Denko Corp Method for separating and removing dicing surface protection tape from object to be cut
KR101909633B1 (en) 2011-12-30 2018-12-19 삼성전자 주식회사 Method of cutting light emitting device chip wafer using laser scribing
JP2013222846A (en) 2012-04-17 2013-10-28 Nitto Denko Corp Substrate dicing method
JP6667489B2 (en) * 2017-11-09 2020-03-18 古河電気工業株式会社 Method for manufacturing semiconductor chip

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