JP3722779B2 - Differential output circuit - Google Patents

Differential output circuit Download PDF

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JP3722779B2
JP3722779B2 JP2002122848A JP2002122848A JP3722779B2 JP 3722779 B2 JP3722779 B2 JP 3722779B2 JP 2002122848 A JP2002122848 A JP 2002122848A JP 2002122848 A JP2002122848 A JP 2002122848A JP 3722779 B2 JP3722779 B2 JP 3722779B2
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実 川畑
賢一 川上
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Ｎｅｃマイクロシステム株式会社
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Description

【０００１】
【発明の属する技術分野】
本発明は、デバイス間で信号を伝送するための出力回路に関し、特に高速、小振幅で動作する電流出力の通信用差動出力回路に関する。
【０００２】
【従来の技術】
近年、伝送回路の伝送レートの高速化は目覚しく、所望のシステムを実現するためには、デバイス間を接続する、高速且つ小振幅の差動出力回路が不可欠となっている。
【０００３】
図１０は、従来の省電力機能を備えた差動出力回路の一例のブロック図である。図１０を参照すると、従来の差動出力回路は、差動出力部１２０とこの差動出力部１２０を制御する制御部１３０を備えている。
【０００４】
差動出力部１２０は、いずれもｐチャネル電界効果トランジスタ（以下、ｐＭＯＳとする）であるMP１、MP２、いずれもｎチャネル電界効果トランジスタ（以下ｎＭＯＳとする）であるMN１、MN２を含み構成される。又、制御部１３０は、いずれもインバータ回路であるINV1乃至INV6、いずれも２入力のＮＡＮＤ回路であるＮＡＮＤ１，ＮＡＮＤ２、いずれも２入力のＮＯＲ回路であるＮＯＲ１，ＮＯＲ２で構成されている。
【０００５】
差動出力部１２０の接続構成は次のようになっている。MP１のソース、ドレイン及びゲートを、それぞれノードN101、ノードN102及びＮＡＮＤ１の出力端に接続し、MP２のソース、ドレイン及びゲートを、それぞれノードN101、ノードN103及びＮＡＮＤ２の出力端に接続している。又、MN１のソース、ドレイン及びゲートを、それぞれノードＮ104、ノードN102及びＮＯＲ２の出力端に接続し、MN２のソース、ドレイン及びゲートを、それぞれノードN104、ノードＮ103及びＮＯＲ１の出力端に接続している。更に定電流源１０１をＶDDとノードN101との間に接続し、定電流源１０２をＧＮＤとノードN104との間に接続している。即ち、MP1及びMP2が定電流源１０１の出力を定電流とする差動出力段を構成し、MN1及びMN2が定電流源１０２の出力を定電流とする差動出力段を構成している。又、ノードN102及びノードN103が差動出力部１２０の出力端となっており、プラス出力端子１１３及びマイナス出力端子１１４にそれぞれ接続されている。
【０００６】
次に、論理処理部１３０の接続構成を説明する。INV1の入力端はデータ入力端子１１１に接続し、INV1の出力端はINV2の入力端及びINV4の入力端に接続し、INV2の出力端はＮＡＮＤ１及びＮＯＲ２のそれぞれの一方の入力端に接続し、INV4の出力端はINV5の入力端に接続し、INV5の出力端はＮＡＮＤ２及びＮＯＲ１のそれぞれの一方の入力端に接続している。又、INV3の入力端は端子１１２に接続し、INV3の出力端はINV6の入力端、ＮＡＮＤ１及びＮＡＮＤ２のそれぞれの他方の入力端に接続し、INV6の出力端はＮＯＲ１及びＮＯＲ２のそれぞれの他方の入力端に接続している。
【０００７】
この構成で、データ入力端子１１１に入力した信号に応じて、プラス出力端子１１３とマイナス出力端子１１４の間で差動信号が出力される。端子１１２には、省電力制御信号が入力され、必要に応じて差動出力回路の動作を停止させ電力消費を削減する。
【０００８】
【発明が解決しようとする課題】
しかし、図１０に示すような従来の差動出力回路では、出力差動段MP１、MP２及びMN１、MN２のゲートに接続されるＮＡＮＤ１，２、ＮＯＲ１，２等のプリドライバの出力は、低電位側電源（以下、ＧＮＤとする）の電位レベルから高電位側電源（以下、ＶDDとする）の電位レベルまでの振幅があり、高速で動作させるための能力を確保しようとすると、図１１の出力波形のように、容量やインダクタンスによるオーバーシュート、アンダーシュートが発生し、伝送時のエラーを引き起こしたり、ＥＭＩ（electro-magnetic interference ）によるシステム等への影響も無視できないため、プリドライバの駆動能力を適切に設定した差動出力回路が必要となってきた。
【０００９】
従って、本発明の目的は、信号の高速伝送を可能にしながら、信号波形のオーバシュートやアンダーシュートによる伝送時のエラー発生を低減し、更にＥＭＩの発生を軽減できる差動出力回路を提供することにある。
【００１０】
【課題を解決するための手段】
そのため、本発明による第１の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１乃至第４スイッチ手段と、第１及び第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１乃至第４制御信号をそれぞれ出力する第１乃至第４制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記低電位側電源に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。
【００１１】
又、本発明による第２の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１乃至第４スイッチ手段と、第１及び第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１乃至第４制御信号をそれぞれ出力する第１乃至第４制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第１制御出力部乃至前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。
【００１２】
このとき、第１及び第２の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段及び第６スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第１ノードにそれぞれ接続し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第４ノードにそれぞれ接続し、前記５スイッチ手段及び前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにしてもよい。
【００１３】
又、本発明による第３の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１スイッチ手段及び第２スイッチ手段と、第１抵抗素子及び第２抵抗素子と、第１定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１制御信号及び第２制御信号をそれぞれ出力する第１制御出力部及び第２制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記第１抵抗素子を前記第２ノードと低電位側電源との間に接続し、
前記第２抵抗素子を前記第３ノードと前記低電位側電源との間に接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記低電位側電源に接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。このとき、第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第１ノードにそれぞれ接続し、前記５スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにしてもよい。
【００１４】
又、本発明による第４の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１スイッチ手段及び第２スイッチ手段と、第１抵抗素子及び第２抵抗素子と、第１定電流出力手段と、第１電位補正手段と、第１信号入力端に入力するデータ信号に基づいて第１制御信号及び第２制御信号をそれぞれ出力する第１制御出力部及び第２制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記第１抵抗素子を前記第２ノードと低電位側電源との間に接続し、
前記第２抵抗素子を前記第３ノードと前記低電位側電源との間に接続し、
前記第１定電流出力手段を第５ノードと高電位側電源との間に接続し、
前記第１電位補正手段を前記第１ノーと前記第５ノードとの間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第５ノードと前記低電位側電源に接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。このとき、第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第５ノードにそれぞれ接続し、前記５スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにしてもよい。
【００１５】
又、第４の差動出力回路の前記第１電位補正手段は、ゲート電極に所定の電位を供給し、ソースドレイン路を前記第１ノードと前記第５ノードとの間に接続したｐチャネル電界効果トランジスタとすることができる。
【００１６】
又、前記第５スイッチ手段は、ソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端であるｐチャネル電界効果トランジスタで構成することができる。
【００１７】
又、本発明による第５の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第３スイッチ手段及び第４スイッチ手段と、第３抵抗素子及び第４抵抗素子と、第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第３制御信号及び第４制御信号をそれぞれ出力する第３制御出力部及び第４制御出力部を含む制御手段を有し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第３抵抗素子を前記第２ノードと高電位側電源との間に接続し、
前記第４抵抗素子を前記第３ノードと前記高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。このとき、第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第６スイッチ手段を更に有し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第４ノードにそれぞれ接続し、前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにしてもよい。
【００１８】
又、本発明による第６の差動出力回路は、それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第３スイッチ手段及び第４スイッチ手段と、第３抵抗素子及び第４抵抗素子と、第２定電流出力手段と、第２電位補正手段と、第１信号入力端に入力するデータ信号に基づいて第３制御信号及び第４制御信号をそれぞれ出力する第３制御出力部及び第４制御出力部を含む制御手段を有し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第３抵抗素子を前記第２ノードと高電位側電源との間に接続し、
前記第４抵抗素子を前記第３ノードと前記高電位側電源との間に接続し、
前記第２定電流出力手段を第６ノードと低電位側電源との間に接続し、
前記第２電位補正手段を前記第４ノーと前記第６ノードとの間に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第６ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする。このとき、第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第６スイッチ手段を更に有し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第６ノードにそれぞれ接続し、前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにしてもよい。
【００１９】
又、第６の差動出力回路の前記第２電位補正手段は、ゲート電極に所定の電位を供給し、ソースドレイン路を前記第４ノードと前記第６ノードとの間に接続したｎチャネル電界効果トランジスタであってよい。
【００２０】
又、前記第６スイッチ手段は、ソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端であるｎチャネル電界効果トランジスタで構成することができる。
【００２１】
又、前記第１スイッチ手段及び前記第２スイッチ手段は、いずれも、ソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端であるｐチャネル電界効果トランジスタで構成することができ、前記第３スイッチ手段及び前記第４スイッチ手段は、いずれも、ソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端であるｎチャネル電界効果トランジスタで構成することができる。
【００２２】
【発明の実施の形態】
次に、本発明について図面を参照して説明する。尚、以下の説明において、１１は第１信号入力端であるデータ入力端子、１２は第２信号入力端であるパワーダウン信号入力端子（以下、PD端子とする）、２１は第１定電流出力手段である電流値がI0の第１定電流源、２２は第２定電流出力手段である電流値がI0の第２定電流源、１３はプラス信号出力端子、１４はマイナス信号出力端子である。又、MP１乃至MP８はｐＭＯＳ、MN１乃至MN８はｎＭＯＳ、R1乃至R4及びＲ11乃至Ｒ14は抵抗素子、INV1乃至INV6はインバータ回路（以下、ＩＮＶとする）、AND1及びAND2は２入力ＡＮＤ回路、OR１並びにOR２は２入力OR回路である。又、R1乃至R4及びＲ11乃至Ｒ14の抵抗値は、それぞれR1乃至R4及びＲ11乃至Ｒ14で表すこととし、特に断ることなく適宜使用する。
【００２３】
図１は、本発明の差動出力回路の第１の実施形態を示すブロック図である。図１を参照すると、本実施形態の差動出力回路１は、差動出力部２０と制御手段である制御部３０を備えて構成され、制御部３０が差動出力部２０を制御する。
【００２４】
差動出力部２０は、第１スイッチ手段であるMP１、第２スイッチ手段であるMP２、第３スイッチ手段であるMN１、及び第４スイッチ手段であるMN２を含み構成される。そして、MP１，MP２，MN１及びMN２のそれぞれのソース、ドレイン及びゲートが、第１乃至第４スイッチ手段それぞれの第１接続端、第２接続端及び制御入力端となっている。
【００２５】
制御部３０は、論理処理部３１、第１制御出力部３２、第２制御出力部３３、第３制御出力部３４及び第４制御出力部３５を含み構成される。具体的には、論理処理部３１はINV1乃至INV6、AND1、AND2、OR１及びOR２で構成され、第１制御出力部３２はMP３とMN３からなるＩＮＶで、第２制御出力部３３はMP４とMN４からなるＩＮＶで、第３制御出力部３４はMP５とMN５からなるＩＮＶで、第４制御出力部３５はMP６とMN６からなるＩＮＶで、それぞれ構成される。尚、差動出力回路１は、第５スイッチ手段３７であるMP７と、第６スイッチ手段３８であるMN７を更に備えている。
【００２６】
次に、これらの接続関係について説明する。先ず、差動出力部２０の接続を説明する。MP１のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第２ノードＮ２及びMP３のドレインに接続し、MP２のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第３ノードＮ３及びMP４のドレインに接続する。又、MN１のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第２ノードＮ２及びMP６のドレインに接続し、MN２のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第３ノードＮ３及びMP５のドレインに接続する。更に第１定電流源２１をＶDDと第１ノードＮ１との間に接続し、第２定電流源２２をＧＮＤと第４ノードＮ４との間に接続する。即ち、MP1及びMP2が第１定電流源２１の出力を定電流とする差動出力段を構成し、MN1及びMN2が第２定電流源２２の出力を定電流とする差動出力段を構成する。又、第２ノードＮ２及び第３ノードＮ３が差動出力部２０の出力端となり、プラス出力端子１３及びマイナス出力端子１４にそれぞれ接続する。
【００２７】
次に、論理処理部３１の接続を説明する。INV1の入力端はデータ入力端子１１に接続し、INV1の出力端はINV2の入力端及びINV4の入力端に接続し、INV2の出力端はAND1及びOR２のそれぞれの一方の入力端に接続し、INV4の出力端はINV5の入力端に接続し、INV5の出力端はAND2及びOR１のそれぞれの一方の入力端に接続する。又、INV3の入力端はPD端子１２に接続し、INV3の出力端はINV6の入力端、AND1及びAND2のそれぞれの他方の入力端並びにMP７のゲートに接続し、INV6の出力端はOR１及びOR２のそれぞれの他方の入力端並びにMN７のゲートに接続する。
【００２８】
次に、第１制御出力部３２乃至第４制御出力部３５の接続を説明する。先ず、MP３のソース、ドレイン及びゲートは、それぞれ第１ノードＮ１、MN３のドレイン及びAND1の出力端に接続し、MN３のソース及びゲートは、それぞれＧＮＤ及びAND1の出力端に接続する。次に、MP４のソース、ドレイン及びゲートは、それぞれ第１ノードＮ１、MN４のドレイン及びAND2の出力端に接続し、MN４のソース及びゲートは、それぞれＧＮＤ及びAND2の出力端に接続する。次に、MP５のソース、ドレイン及びゲートは、それぞれＶDD、MN５のドレイン及びOR１の出力端に接続し、MN５のソース及びゲートは、それぞれ第４ノードＮ４及びOR１の出力端に接続する。更に、MP６のソース、ドレイン及びゲートは、それぞれＶDD、MN６のドレイン及びOR２の出力端に接続し、MN６のソース及びゲートは、それぞれ第４ノードＮ４及びOR２の出力端に接続する。
【００２９】
次に、本実施形態の差動出力回路１の動作について説明する。図１において、データ入力端子１１にパルス波による入力信号を加えると、プラス出力端子１３、マイナス出力端子１４にはそれぞれ、入力信号と同相あるいは逆相で最大値がI0の電流出力信号が発生する。この電流出力信号は、例えば図２のようなバイアス回路７０で、電圧値に変換されて次段へ伝送される。ＶDDの電圧値をＶ0 として、この時の出力信号の中点電位をＶｃ、最高電位をＶmax 、最低電位をＶmin とすると、
Ｖｃ ＝Ｖ0×Ｒ11／（Ｒ11＋Ｒ12）
Ｖmax ＝Ｖｃ＋I0×Ｒ11×Ｒ12／（Ｒ11＋Ｒ12）
Ｖmin ＝Ｖｃ−I0×Ｒ11×Ｒ12／（Ｒ11＋Ｒ12）
の関係がある。従って、差動出力部２０の出力端である第２ノードＮ２及び第３ノードＮ３の電位、並びに第１ノードＮ１及び第４ノードＮ４の電位と、前段の第１制御出力部３２乃至第４制御出力部３５の各出力端の電位との関係は、図３で示すようになる。又、図４は、差動出力回路１の出力端を図２のバイアス回路７０に接続して、PD端子１２の電位を低レベルに固定し、データ入力端子１１にパルス波による入力信号を加えたときのプラス出力端子１３の電位波形ＯＰと、マイナス出力端子１４の電位波形ＯＭのシミュレーション波形である。図４から分かるとおり、本実施形態の差動出力回路１では、出力のオーバシュート、アンダーシュートが十分抑制されている。
【００３０】
図１のように、第１スイッチ手段及び第２スイッチ手段を駆動する第１制御出力部３２及び第２制御出力部３３の高電位側電源端であるMP３，MP４のソースを第１ノードＮ１に接続し、第３スイッチ手段及び第４スイッチ手段を駆動する第３制御出力部３４及び第４制御出力部３５の低電位側電源端であるMN３，MN４のソースを第４ノードＮ４に接続した構成にすると、差動対MP１、MP２を駆動する第１制御出力部３２及び第２制御出力部３３のそれぞれの出力は、ハイレベルからロウレベルへ遷移する場合は急速に行われるが、ロウレベルからハイレベルへ遷移する場合は、定電流I0で次段の入力容量を充電するため、立ち下がりくらべ緩やかに遷移する。一方、差動対MN１，MN２を駆動する第３制御出力部３４及び第４制御出力部３５の出力の場合は、この逆にハイレベルからロウレベルへの遷移が緩やかになる。且つ、各制御出力部の出力振幅も制限されるため、実際のプラス出力端子１３及びマイナス出力端子１４からそれぞれ出力される出力波形ＯＰ及びＯＭは、立ち上がり立ち下がりとも、高電位側電源端及び低電位側電源端をＶDD及びＧＮＤにそれぞれ接続した一般的なＩＮＶで差動対MP１、MP２及び差動対MN１，MN２を駆動した場合よりも緩やかになる。従って、本実施形態の差動出力回路１は、出力波形のオーバーシュート、アンダーシュートの発生を抑制すると共に、ＥＭＩも抑制することができる。
【００３１】
次に、本実施形態の変形例について説明する。図５は、この変形例の差動出力回路２のブロック図である。差動出力回路２は、第１制御出力部３２及び第２制御出力部３３の各低電位側電源端を第４ノードＮ４に接続し、第３制御出力部３４及び第４制御出力部３５の各高電位側電源端を第１ノードＮ１に接続した点が、差動出力回路１と異なるだけで、他の部分の構成は差動出力回路１と同じである。これにより、図１の差動出力回路１の構成より第１制御出力部３２乃至第４制御出力部３５の出力振幅が更に制限されるため、出力振幅が大きい場合に好適な構成となっている。尚、差動出力回路２の動作は、差動出力回路１の動作と同様であり、説明は省略する。
【００３２】
次に、本発明の第２の実施形態について説明する。図６は、本発明の差動出力回路の第２の実施形態を示すブロック図である。図６を参照すると、本実施形態の差動出力回路３は、差動出力部２０ａと制御手段である制御部３０ａを備えて構成され、制御部３０ａが差動出力部２０ａを制御する。
【００３３】
差動出力部２０ａは、第１スイッチ手段であるMP１、第２スイッチ手段であるMP２、第１抵抗素子であるR1、及び第２抵抗素子であるR2を含み構成される。そして、MP１及びMP２のそれぞれのソース、ドレイン及びゲートが、第１及び第２スイッチ手段それぞれの第１接続端、第２接続端及び制御入力端となっている。又、R1＝R2となっている。
【００３４】
制御部３０ａは、論理処理部３１ａ、第１制御出力部３２及び第２制御出力部３３を含み構成される。具体的には、論理処理部３１ａはINV1乃至INV5、AND1及びAND2で構成され、第１制御出力部３２はMP３とMN３からなるＩＮＶで、第２制御出力部３３はMP４とMN４からなるＩＮＶで、それぞれ構成される。尚、差動出力回路３は、第５スイッチ手段３７であるMP７を更に備えている。
【００３５】
次に、これらの接続関係について説明する。先ず、差動出力部２０ａの接続を説明する。MP１のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第２ノードＮ２及びMP３のドレインに接続し、MP２のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第３ノードＮ３及びMP４のドレインに接続する。又、R1を第２ノードＮ２とＧＮＤとの間に接続し、R2を第３ノードＮ３とＧＮＤとの間に接続する。更に第１定電流源２１をＶDDと第１ノードＮ１との間に接続する。即ち、本実施形態の差動出力回路３では、差動出力段が第１定電流源２１の出力を定電流としてMP1及びMP2のみで構成される。又、本実施形態においても第２ノードＮ２及び第３ノードＮ３が差動出力部２０ａの出力端となり、プラス出力端子１３及びマイナス出力端子１４にそれぞれ接続する。
【００３６】
次に、論理処理部３１ａの接続を説明する。INV1の入力端はデータ入力端子１１に接続し、INV1の出力端はINV2の入力端及びINV4の入力端に接続し、INV2の出力端はAND1の一方の入力端に接続し、INV4の出力端はINV5の入力端に接続し、INV5の出力端はAND2の一方の入力端に接続する。又、INV3の入力端はPD端子１２に接続し、INV3の出力端はAND1及びAND2のそれぞれの他方の入力端並びにMP７のゲートに接続する。尚、第１制御出力部３２、第２制御出力部３３及び第５スイッチ手段３７の構成及び接続は、第１の実施形態の場合と全く同様であり、説明を省略する。又、本実施形態の差動出力回路３の動作も、第１の実施形態の場合と同様であり、説明は省略する。
【００３７】
本実施形態の差動出力回路３は、上記の通り差動出力回路１の差動出力部２０におけるMN１，MN２及び第２定電流源２２部分をR1，R2に置き換えると共に、制御部３０のMN１及びMN２の制御及び駆動に関わる部分を削除した構成となっており、第１の実施形態の場合と同様の作用効果が得られる。
【００３８】
又、この差動出力回路３の出力信号を次段へ伝送するため、出力端を図２のようなバイアス回路７０に接続したときの出力信号の中点電位をＶｃ、最高電位をＶmax 、最低電位をＶmin とし、ＶDDの電圧値をＶ0 とすると、
Ｒｘ＝（R1×Ｒ12）／（R1＋Ｒ12）として、
Ｖｃ ＝Ｖ0×Ｒ11／（Ｒ11＋Ｒｘ）
Ｖmax ＝Ｖｃ＋I0×Ｒ11×Ｒｘ／（Ｒ11＋Ｒｘ）
Ｖmin ＝Ｖｃ−I0×Ｒ11×Ｒｘ／（Ｒ11＋Ｒｘ）
となる。
【００３９】
次に、本実施形態の変形例について説明する。図７は、第２の実施形態の変形例を示す差動出力回路４のブロック図である。差動出力回路４は、差動出力部２０ａが、第１電位補正手段４１であるカスコードトランジスタとなるMP８と、MP８のゲートに接続したバイアス回路７２を更に有している点、及びMP８を追加したことに伴う一部の接続が変更された点が、差動出力回路３と異なる。以下、図７を参照して、変形例の差動出力回路４の構成を説明する。
【００４０】
先ず、差動出力部２０ａの接続について説明する。MP１のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第２ノードＮ２及びMP３のドレインに接続し、MP２のソース、ドレイン及びゲートを、それぞれ第１ノードＮ１、第３ノードＮ３及びMP４のドレインに接続する。又、R1を第２ノードＮ２とＧＮＤとの間に接続し、R2を第３ノードＮ３とＧＮＤとの間に接続する。ここまでは、差動出力回路３の場合と同様である。更に、MP８のソースドレイン路を第１ノードＮ１と第５ノードＮ５との間に接続し、MP８のゲートをバイアス回路７２の出力端に接続し、第１定電流源２１をＶDDと第５ノードＮ５との間に接続する。
【００４１】
次に、制御部３０ａの接続について、差動出力回路３の接続と異なる点を中心に説明する。この変形例では、第１制御出力部３２及び第２制御出力部３３のそれぞれの高電位側電源端であるMP３及びMP４のソース並びにMP７のドレインをいずれも第５ノードＮ５に接続した点のみが、差動出力回路３の場合と異なっている。尚、論理処理部３１ａの構成を含めて、制御部３０ａの他の接続関係は差動出力回路３の場合と同様であるので、これらの説明は省略する。又、この差動出力回路４の動作も、第１の実施形態の動作と同様であり説明は省略する。
【００４２】
この変形例においても、第１の実施形態の場合と同様の作用効果が得られる。又、図６の差動出力回路３のような構成で、差動出力部２０ａの出力振幅が小さい場合は、第１ノードＮ１の電位が低いため、第１制御出力部３２及び第２制御出力部３３が十分動作できない場合が生じ得るが、この変形例では、上記構成により第５ノードＮ５の電位が持ち上げられるので、第１制御出力部３２及び第２制御出力部３３を動作させるのに必要な高電位側電源端の電位を確保することができると共に、第１定電流源２１の電流値I0の電源電圧依存性を改善する効果も有する。
【００４３】
次に、本発明の第３の実施形態について説明する。図８は、本発明の第３の実施形態を示す差動出力回路５のブロック図である。図８を参照すると、本実施形態の差動出力回路５は、差動出力部２０ｂと制御手段である制御部３０ｂを備えて構成され、制御部３０ｂが差動出力部２０ｂを制御する。
【００４４】
差動出力部２０ｂは、第３スイッチ手段であるMN１、第４スイッチ手段であるMN２、第３抵抗素子であるR3、及び第４抵抗素子であるR4を含み構成される。そして、MN１及びMN２のそれぞれのソース、ドレイン及びゲートが、第３及び第４スイッチ手段それぞれの第１接続端、第２接続端及び制御入力端となっている。又、R3＝R4となっている。
【００４５】
制御部３０ｂは、論理処理部３１ｂ、第３制御出力部３４及び第４制御出力部３５を含み構成される。具体的には、論理処理部３１ｂはINV1，INV3乃至INV6、OR１及びOR２で構成され、第３制御出力部３４はMP５とMN５からなるＩＮＶで、第４制御出力部３５はMP６とMN６からなるＩＮＶで、それぞれ構成される。尚、差動出力回路５は、第６スイッチ手段３８であるMN７を更に備えている。
【００４６】
次に、これらの接続関係について説明する。先ず、差動出力部２０ｂの接続を説明する。MN１のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第２ノードＮ２及びMP６のドレインに接続し、MN２のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第３ノードＮ３及びMP５のドレインに接続する。又、R3をＶDDと第２ノードＮ２との間に接続し、R4をＶDDと第３ノードＮ３との間に接続する。更に第２定電流源２２を第４ノードＮ４とＧＮＤとの間に接続する。即ち、本実施形態の差動出力回路５では、差動出力段が第２定電流源２２の出力を定電流としてMN1及びMN2のみで構成される。又、本実施形態においても第２ノードＮ２及び第３ノードＮ３が差動出力部２０ｂの出力端となり、プラス出力端子１３及びマイナス出力端子１４にそれぞれ接続する。
【００４７】
次に、論理処理部３１ｂの接続を説明する。INV1の入力端はデータ入力端子１１に接続し、INV1の出力端はINV4の入力端に接続し、INV4の出力端はINV5の入力端及びOR２の一方の入力端に接続し、INV5の出力端はOR１の一方の入力端に接続する。又、INV3の入力端はPD端子１２に接続し、INV3の出力端はINV6の入力端に接続し、INV6の出力端はOR１及びOR２のそれぞれの他方の入力端並びにMN７のゲートに接続する。尚、第３制御出力部３４、第４制御出力部３５及び第６スイッチ手段３８の構成、接続は、第１の実施形態の場合と全く同様であり、説明を省略する。尚、本実施形態の差動出力回路５の動作も、第１の実施形態の動作と同様であり説明は省略する。
【００４８】
本実施形態の差動出力回路５は、上記の通り差動出力回路１の差動出力部２０におけるMP１，MP２及び第１定電流源２１部分をR3，R4に置き換えると共に、制御部３０のMP１及びMP２の制御及び駆動に関わる部分を削除した構成となっており、第１の実施形態の場合と同様の作用効果が得られる。
【００４９】
又、この差動出力回路５の出力信号を次段へ伝送するため、出力端を図２のようなバイアス回路７０に接続したときの出力信号の中点電位をＶｃ、最高電位をＶmax 、最低電位をＶmin とし、ＶDDの電圧値をＶ0 とすると、
Ｒｙ＝（R3×Ｒ11）／（R3＋Ｒ11）として、
Ｖｃ ＝Ｖ0×Ｒｙ／（Ｒｙ＋Ｒ12）
Ｖmax ＝Ｖｃ＋I0×Ｒｙ×Ｒ12／（Ｒｙ＋Ｒ12）
Ｖmin ＝Ｖｃ−I0×Ｒｙ×Ｒ12／（Ｒｙ＋Ｒ12）
となる。
【００５０】
次に、本実施形態の変形例について説明する。図９は、第３の実施形態の変形例を示す差動出力回路６のブロック図である。差動出力回路６は、差動出力部２０ｂが、第２電位補正手段４３であるカスコードトランジスタとなるMN８と、MN８のゲートに接続したバイアス回路７４を更に有している点、及びMN８を追加したことに伴う一部の接続が変更された点が、差動出力回路５と異なる。以下、図９を参照して、変形例の差動出力回路６の構成を説明する。
【００５１】
先ず、差動出力部２０ｂの接続について説明する。MN１のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第２ノードＮ２及びMP６のドレインに接続し、MN２のソース、ドレイン及びゲートを、それぞれ第４ノードＮ４、第３ノードＮ３及びMP５のドレインに接続する。又、R3をＶDDと第２ノードＮ２との間に接続し、R4をＶDDと第３ノードＮ３との間に接続する。ここまでは、差動出力回路５の場合と同様である。更に、MN８のソースドレイン路を第４ノードＮ４と第６ノードＮ６との間に接続し、MN８のゲートをバイアス回路７４の出力端に接続し、第２定電流源２２を第６ノードＮ６とＧＮＤとの間に接続する。
【００５２】
次に、制御部３０ｂの接続について、差動出力回路５の接続と異なる点を中心に説明する。この変形例では、第３制御出力部３４及び第４制御出力部３５のそれぞれの低電位側電源端であるMN５及びMN６のソース並びにMN７のドレインをいずれも第６ノードＮ６に接続した点のみが、差動出力回路５の場合と異なっている。尚、論理処理部３１ｂの構成を含めて、制御部３０ｂの他の接続関係は差動出力回路５の場合と同様であるので、これらの説明は省略する。又、この差動出力回路６の動作も、第１の実施形態の動作と同様であり説明は省略する。
【００５３】
この変形例においても、第１の実施形態の場合と同様の作用効果が得られる。又、図８の差動出力回路５のような構成で、差動出力部２０ｂの出力振幅が小さい場合は、第４ノードＮ４の電位が高いため、第３制御出力部３４及び第４制御出力部３５が十分動作できない場合が生じ得るが、この変形例では、上記構成により第６ノードＮ６の電位を下げることができるので、第３制御出力部３４及び第４制御出力部３５を動作させるのに必要な低電位側電源端の電位を確保することができると共に、第２定電流源２２の電流値I0の電源電圧依存性を改善する効果も有する。
【００５４】
尚、本発明は上記実施形態の説明に限定されるものでなく、その要旨の範囲内で種々変更が可能であることは言うまでもない。例えば、制御部に含まれる論理処理部の構成は、その出力論理を維持していれば、省電力機能等の付加機能の有無や必要な遅延時間等に応じて任意に変更してよい。
【００５５】
【発明の効果】
以上説明したように、本発明の差動出力回路は、信号の高速伝送を可能にしながら、出力波形のオーバーシュートやアンダーシュートの発生を抑制し、伝送時のエラー発生を低減できると共に、出力波形の遷移を緩やかにすることで、ＥＭＩを軽減できる等の効果がある。
【図面の簡単な説明】
【図１】本発明の差動出力回路の第１の実施形態を示すブロック図である。
【図２】本発明の差動出力回路の動作を説明するための図で、（ａ）は図１の差動出力回路で信号を伝送する際の外部のバイアス回路及びこのバイアス回路との接続構成例を示す部分接続図、（ｂ）は（ａ）の接続における差動出力回路へのデータ入力信号と出力信号の模式的な波形図である。
【図３】本発明の差動出力回路の動作を説明するための図で、図１の差動出力回路の主要ノードにおける電位波形図である。
【図４】図１の差動出力回路の出力端を図２のバイアス回路に接続したときの、動作シミュレーション波形図である。
【図５】第１の実施形態の変形例の差動出力回路のブロック図である。
【図６】本発明の差動出力回路の第２の実施形態を示すブロック図である。
【図７】第２の実施形態の変形例の差動出力回路のブロック図である。
【図８】本発明の差動出力回路の第３の実施形態を示すブロック図である。
【図９】第３の実施形態の変形例の差動出力回路のブロック図である。
【図１０】従来の省電力機能を備えた差動出力回路の一例のブロック図である。
【図１１】図１０の従来の差動出力回路の出力端を所定のバイアス回路に接続したときの動作シミュレーション波形図である。
【符号の説明】
１，２，３，４，５，６ 差動出力回路
１１ データ入力端子
１２ PD端子
１３ プラス出力端子
１４ マイナス出力端子
２０，２０ａ，２０ｂ 差動出力部
２１ 第１定電流源
２２ 第２定電流源
３０，３０ａ，３０ｂ 制御部
３１，３１ａ，３１ｂ 論理処理部
３２ 第１制御出力部
３３ 第２制御出力部
３４ 第３制御出力部
３５ 第４制御出力部
３７ 第５スイッチ手段
３８ 第６スイッチ手段
４１ 第１電位補正手段
４３ 第２電位補正手段
７０，７２，７４ バイアス回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output circuit for transmitting a signal between devices, and more particularly, to a differential output circuit for communication with a current output that operates at a high speed and a small amplitude.
[0002]
[Prior art]
In recent years, the transmission rate of transmission circuits has been rapidly increased, and in order to realize a desired system, a high-speed and small-amplitude differential output circuit that connects devices is indispensable.
[0003]
FIG. 10 is a block diagram of an example of a differential output circuit having a conventional power saving function. Referring to FIG. 10, the conventional differential output circuit includes a differential output unit 120 and a control unit 130 that controls the differential output unit 120.
[0004]
The differential output unit 120 includes MP1 and MP2 which are p-channel field effect transistors (hereinafter referred to as pMOS), and MN1 and MN2 which are both n-channel field effect transistors (hereinafter referred to as nMOS). . The control unit 130 includes INV1 to INV6 that are inverter circuits, NAND1 and NAND2 that are both 2-input NAND circuits, and NOR1 and NOR2 that are both 2-input NOR circuits.
[0005]
The connection configuration of the differential output unit 120 is as follows. The source, drain, and gate of MP1 are connected to the output terminals of node N101, node N102, and NAND1, respectively, and the source, drain, and gate of MP2 are connected to the output terminals of node N101, node N103, and NAND2, respectively. The source, drain, and gate of MN1 are connected to the output terminals of node N104, node N102, and NOR2, respectively, and the source, drain, and gate of MN2 are connected to the output terminals of node N104, node N103, and NOR1, respectively. Yes. Further, the constant current source 101 is connected between VDD and the node N101, and the constant current source 102 is connected between GND and the node N104. That is, MP1 and MP2 constitute a differential output stage that uses the output of the constant current source 101 as a constant current, and MN1 and MN2 constitute a differential output stage that uses the output of the constant current source 102 as a constant current. Further, the node N102 and the node N103 are output terminals of the differential output unit 120, and are connected to the plus output terminal 113 and the minus output terminal 114, respectively.
[0006]
Next, the connection configuration of the logic processing unit 130 will be described. The input terminal of INV1 is connected to the data input terminal 111, the output terminal of INV1 is connected to the input terminal of INV2 and the input terminal of INV4, the output terminal of INV2 is connected to one input terminal of each of NAND1 and NOR2, The output terminal of INV4 is connected to the input terminal of INV5, and the output terminal of INV5 is connected to one input terminal of each of NAND2 and NOR1. The input terminal of INV3 is connected to the terminal 112, the output terminal of INV3 is connected to the input terminal of INV6, the other input terminal of each of NAND1 and NAND2, and the output terminal of INV6 is the other terminal of each of NOR1 and NOR2. Connected to the input end.
[0007]
With this configuration, a differential signal is output between the plus output terminal 113 and the minus output terminal 114 in accordance with the signal input to the data input terminal 111. A power saving control signal is input to the terminal 112, and the operation of the differential output circuit is stopped as necessary to reduce power consumption.
[0008]
[Problems to be solved by the invention]
However, in the conventional differential output circuit as shown in FIG. 10, the outputs of the pre-drivers such as NAND1, 2, NOR1, 2 connected to the gates of the output differential stages MP1, MP2 and MN1, MN2 are low potentials. When there is an amplitude from the potential level of the side power supply (hereinafter referred to as GND) to the potential level of the high potential side power supply (hereinafter referred to as VDD), an attempt is made to secure the capability to operate at high speed. Like waveforms, overshoot and undershoot due to capacitance and inductance occur, causing errors during transmission and the influence of EMI (electro-magnetic interference) on the system etc. cannot be ignored. An appropriately configured differential output circuit has become necessary.
[0009]
Accordingly, an object of the present invention is to provide a differential output circuit capable of reducing the occurrence of errors during transmission due to overshooting or undershooting of a signal waveform and further reducing the occurrence of EMI while enabling high-speed signal transmission. It is in.
[0010]
[Means for Solving the Problems]
Therefore, each of the first differential output circuits according to the present invention includes a first connection terminal, a second connection terminal, and a control input terminal, and the first connection terminal and the second connection circuit are input according to a signal input to the control input terminal. First to fourth control means based on first to fourth switch means for controlling conduction and non-conduction with the connection end, first and second constant current output means, and a data signal inputted to the first signal input end. Control means including first to fourth control output units for outputting signals,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the first node and the low potential side power supply, respectively;
Connecting the high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit to the high potential side power supply and the fourth node, respectively;
The second node and the third node are configured as differential output terminals.
[0011]
Each of the second differential output circuits according to the present invention includes a first connection end, a second connection end, and a control input end, and the first connection end and the second connection circuit according to a signal input to the control input end. First to fourth control means based on first to fourth switch means for controlling conduction and non-conduction with the connection end, first and second constant current output means, and a data signal inputted to the first signal input end. Control means including first to fourth control output units for outputting signals,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit to the fourth control output unit to the first node and the fourth node, respectively;
The second node and the third node are configured as differential output terminals.
[0012]
At this time, each of the first and second differential output circuits includes a first connection terminal, a second connection terminal, and a control input terminal, and the first connection terminal and the first differential circuit are controlled by a signal input to the control input terminal. And further includes fifth switch means and sixth switch means for controlling conduction and non-conduction with the two connection ends, wherein the first connection end and the second connection end of the fifth switch means are connected to the high potential side power source and the first switch. The first connection terminal and the second connection terminal of the sixth switch means are connected to the low-potential side power source and the fourth node, respectively, and the fifth switch means and the sixth switch means are connected to each other. The non-conduction may be controlled by a power saving control signal input to the second signal input terminal of the control means.
[0013]
Each of the third differential output circuits according to the present invention includes a first connection end, a second connection end, and a control input end, and the first connection end and the second connection are input according to a signal input to the control input end. First switch means and second switch means for controlling conduction and non-conduction with the connection end, first resistance element and second resistance element, first constant current output means, and data input to the first signal input end Control means including a first control output unit and a second control output unit that respectively output a first control signal and a second control signal based on the signal;
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first resistance element between the second node and a low-potential-side power supply;
Connecting the second resistive element between the third node and the low-potential-side power supply;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the first node and the low potential side power supply, respectively;
The second node and the third node are configured as differential output terminals. At this time, a first connection end, a second connection end, and a control input end are provided, and a fifth that controls conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end. A switch means for connecting the first connection end and the second connection end of the fifth switch means to the high-potential side power source and the first node, respectively, and controlling the conduction and non-conduction of the five switch means; You may make it control by the power saving control signal input into the 2nd signal input terminal of a means.
[0014]
Each of the fourth differential output circuits according to the present invention includes a first connection end, a second connection end, and a control input end, and the first connection end and the second connection are input by a signal input to the control input end. First switch means and second switch means for controlling conduction and non-conduction with the connection end, first resistance element and second resistance element, first constant current output means, first potential correction means, Control means including a first control output unit and a second control output unit for outputting a first control signal and a second control signal based on a data signal input to the signal input terminal,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first resistance element between the second node and a low-potential-side power supply;
Connecting the second resistive element between the third node and the low-potential-side power supply;
Connecting the first constant current output means between a fifth node and a high-potential side power supply;
Connecting the first potential correcting means between the first node and the fifth node;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the fifth node and the low potential side power supply, respectively;
The second node and the third node are configured as differential output terminals. At this time, a first connection end, a second connection end, and a control input end are provided, and a fifth that controls conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end. A switch means for connecting the first connection end and the second connection end of the fifth switch means to the high-potential side power source and the fifth node, respectively, and controlling the conduction and non-conduction of the five switch means; You may make it control by the power saving control signal input into the 2nd signal input terminal of a means.
[0015]
The first potential correcting means of the fourth differential output circuit supplies a predetermined potential to the gate electrode, and a p-channel electric field having a source / drain path connected between the first node and the fifth node. It can be an effect transistor.
[0016]
In addition, the fifth switch means may be composed of a p-channel field effect transistor in which a source electrode, a drain electrode, and a gate electrode are the first connection end, the second connection end, and the control input end, respectively.
[0017]
Each of the fifth differential output circuits according to the present invention includes a first connection end, a second connection end, and a control input end, and the first connection end and the second connection are input by a signal input to the control input end. Third switch means and fourth switch means for controlling conduction and non-conduction with the connection end, third resistance element and fourth resistance element, second constant current output means, and data input to the first signal input end Control means including a third control output unit and a fourth control output unit for outputting a third control signal and a fourth control signal, respectively, based on the signal;
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the third resistance element between the second node and a high-potential side power supply;
Connecting the fourth resistance element between the third node and the high-potential-side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit to the high potential side power supply and the fourth node, respectively;
The second node and the third node are configured as differential output terminals. At this time, a sixth connection terminal having a first connection terminal, a second connection terminal, and a control input terminal, and controlling conduction and non-conduction between the first connection terminal and the second connection terminal by a signal input to the control input terminal. Switch means, and the first connection end and the second connection end of the sixth switch means are connected to the low-potential side power source and the fourth node, respectively, and the conduction and non-conduction of the sixth switch means are You may make it control by the power saving control signal input into the 2nd signal input terminal of a control means.
[0018]
Each of the sixth differential output circuits according to the present invention includes a first connection end, a second connection end, and a control input end, and the first connection end and the second connection are input by a signal input to the control input end. Third switch means and fourth switch means for controlling conduction and non-conduction with the connection end, third resistance element and fourth resistance element, second constant current output means, second potential correction means, Control means including a third control output unit and a fourth control output unit for outputting a third control signal and a fourth control signal based on a data signal input to the signal input terminal,
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the third resistance element between the second node and a high-potential side power supply;
Connecting the fourth resistance element between the third node and the high-potential-side power supply;
The second constant current output means is connected between the sixth node and the low potential side power supply;
Connecting the second potential correcting means between the fourth node and the sixth node;
The high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit are connected to the high potential side power supply and the sixth node, respectively.
The second node and the third node are configured as differential output terminals. At this time, a sixth connection terminal having a first connection terminal, a second connection terminal, and a control input terminal, and controlling conduction and non-conduction between the first connection terminal and the second connection terminal by a signal input to the control input terminal. And further comprising a switch means, wherein the first connection end and the second connection end of the sixth switch means are connected to the low-potential side power source and the sixth node, respectively, and the conduction and non-conduction of the sixth switch means are You may make it control by the power saving control signal input into the 2nd signal input terminal of a control means.
[0019]
The second potential correcting means of the sixth differential output circuit supplies a predetermined potential to the gate electrode, and an n-channel electric field having a source / drain path connected between the fourth node and the sixth node. It may be an effect transistor.
[0020]
Further, the sixth switch means may be composed of an n-channel field effect transistor in which a source electrode, a drain electrode and a gate electrode are the first connection end, the second connection end and the control input end, respectively.
[0021]
The first switch means and the second switch means both have a p-channel field effect in which the source electrode, the drain electrode, and the gate electrode are the first connection end, the second connection end, and the control input end, respectively. Each of the third switch means and the fourth switch means may include a source electrode, a drain electrode, and a gate electrode, the first connection end, the second connection end, and the control input end, respectively. The n-channel field effect transistor can be used.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings. In the following description, 11 is a data input terminal which is a first signal input terminal, 12 is a power down signal input terminal (hereinafter referred to as PD terminal) which is a second signal input terminal, and 21 is a first constant current output. 1 is a first constant current source with a current value of I0, 22 is a second constant current source with a current value of I0 which is a second constant current output means, 13 is a positive signal output terminal, and 14 is a negative signal output terminal. . MP1 to MP8 are pMOS, MN1 to MN8 are nMOS, R1 to R4 and R11 to R14 are resistance elements, INV1 to INV6 are inverter circuits (hereinafter referred to as INV), AND1 and AND2 are 2-input AND circuits, OR1 and OR2 is a 2-input OR circuit. The resistance values of R1 to R4 and R11 to R14 are represented by R1 to R4 and R11 to R14, respectively, and are used as appropriate without particular notice.
[0023]
FIG. 1 is a block diagram showing a first embodiment of a differential output circuit of the present invention. Referring to FIG. 1, the differential output circuit 1 according to the present embodiment includes a differential output unit 20 and a control unit 30 that is a control unit, and the control unit 30 controls the differential output unit 20.
[0024]
The differential output unit 20 includes MP1 as the first switch means, MP2 as the second switch means, MN1 as the third switch means, and MN2 as the fourth switch means. The sources, drains, and gates of MP1, MP2, MN1, and MN2 serve as the first connection end, the second connection end, and the control input end of the first to fourth switch means, respectively.
[0025]
The control unit 30 includes a logic processing unit 31, a first control output unit 32, a second control output unit 33, a third control output unit 34, and a fourth control output unit 35. Specifically, the logic processing unit 31 includes INV1 to INV6, AND1, AND2, OR1, and OR2, the first control output unit 32 is an INV composed of MP3 and MN3, and the second control output unit 33 is MP4 and MN4. The third control output unit 34 is an INV consisting of MP5 and MN5, and the fourth control output unit 35 is an INV consisting of MP6 and MN6. The differential output circuit 1 further includes MP7 as the fifth switch means 37 and MN7 as the sixth switch means 38.
[0026]
Next, these connection relationships will be described. First, the connection of the differential output unit 20 will be described. The source, drain, and gate of MP1 are connected to the drains of the first node N1, the second node N2, and MP3, respectively, and the source, drain, and gate of MP2 are the drains of the first node N1, the third node N3, and MP4, respectively. Connect to. The source, drain, and gate of MN1 are connected to the drains of the fourth node N4, second node N2, and MP6, respectively, and the source, drain, and gate of MN2 are connected to the fourth node N4, third node N3, and MP5, respectively. Connect to the drain. Further, the first constant current source 21 is connected between VDD and the first node N1, and the second constant current source 22 is connected between GND and the fourth node N4. That is, MP1 and MP2 constitute a differential output stage using the output of the first constant current source 21 as a constant current, and MN1 and MN2 constitute a differential output stage using the output of the second constant current source 22 as a constant current. To do. The second node N2 and the third node N3 serve as output terminals of the differential output unit 20, and are connected to the plus output terminal 13 and the minus output terminal 14, respectively.
[0027]
Next, connection of the logic processing unit 31 will be described. The input terminal of INV1 is connected to the data input terminal 11, the output terminal of INV1 is connected to the input terminal of INV2 and the input terminal of INV4, the output terminal of INV2 is connected to one input terminal of each of AND1 and OR2, The output terminal of INV4 is connected to the input terminal of INV5, and the output terminal of INV5 is connected to one input terminal of each of AND2 and OR1. The input terminal of INV3 is connected to PD terminal 12, the output terminal of INV3 is connected to the input terminal of INV6, the other input terminal of AND1 and AND2, and the gate of MP7, and the output terminal of INV6 is OR1 and OR2. Are connected to the other input terminal of MN7 and the gate of MN7.
[0028]
Next, connection of the first control output unit 32 to the fourth control output unit 35 will be described. First, the source, drain and gate of MP3 are connected to the first node N1, the drain of MN3 and the output terminal of AND1, respectively, and the source and gate of MN3 are connected to the output terminals of GND and AND1, respectively. Next, the source, drain, and gate of MP4 are connected to the first node N1, the drain of MN4, and the output terminal of AND2, respectively, and the source and gate of MN4 are connected to the output terminals of GND and AND2, respectively. Next, the source, drain and gate of MP5 are connected to VDD, the drain of MN5 and the output terminal of OR1, respectively, and the source and gate of MN5 are connected to the fourth node N4 and the output terminal of OR1, respectively. Further, the source, drain, and gate of MP6 are connected to VDD, the drain of MN6, and the output terminal of OR2, respectively, and the source and gate of MN6 are connected to the output terminals of the fourth node N4 and OR2, respectively.
[0029]
Next, the operation of the differential output circuit 1 of the present embodiment will be described. In FIG. 1, when an input signal by a pulse wave is applied to the data input terminal 11, a current output signal having a maximum value I0 in phase or opposite phase to the input signal is generated at the plus output terminal 13 and minus output terminal 14, respectively. . This current output signal is converted into a voltage value by a bias circuit 70 as shown in FIG. 2, for example, and transmitted to the next stage. Assuming that the voltage value of VDD is V0, the midpoint potential of the output signal at this time is Vc, the maximum potential is Vmax, and the minimum potential is Vmin.
Vc = V0 × R11 / (R11 + R12)
Vmax = Vc + I0 * R11 * R12 / (R11 + R12)
Vmin = Vc-I0 * R11 * R12 / (R11 + R12)
There is a relationship. Therefore, the potentials of the second node N2 and the third node N3, which are the output terminals of the differential output unit 20, the potentials of the first node N1 and the fourth node N4, and the first control output unit 32 to the fourth control of the previous stage. The relationship with the potential of each output terminal of the output unit 35 is as shown in FIG. 4 shows that the output terminal of the differential output circuit 1 is connected to the bias circuit 70 of FIG. 2, the potential of the PD terminal 12 is fixed at a low level, and an input signal by a pulse wave is applied to the data input terminal 11. FIG. 6 shows a simulation waveform of the potential waveform OP of the plus output terminal 13 and the potential waveform OM of the minus output terminal 14 at the time. As can be seen from FIG. 4, in the differential output circuit 1 of the present embodiment, output overshoot and undershoot are sufficiently suppressed.
[0030]
As shown in FIG. 1, the sources of MP3 and MP4, which are the high potential side power supply terminals of the first control output unit 32 and the second control output unit 33 that drive the first switch unit and the second switch unit, are connected to the first node N1. A configuration in which the sources of MN3 and MN4, which are the low-potential side power supply terminals of the third control output unit 34 and the fourth control output unit 35 that connect and drive the third switch means and the fourth switch means, are connected to the fourth node N4. Then, the respective outputs of the first control output unit 32 and the second control output unit 33 that drive the differential pair MP1, MP2 are rapidly performed when transitioning from the high level to the low level, but from the low level to the high level. When the transition is made, the input capacitance of the next stage is charged with the constant current I0, so that the transition is more gradual than the fall. On the other hand, in the case of the outputs of the third control output unit 34 and the fourth control output unit 35 that drive the differential pair MN1, MN2, on the contrary, the transition from the high level to the low level becomes gradual. In addition, since the output amplitude of each control output unit is also limited, the output waveforms OP and OM output from the actual positive output terminal 13 and the negative output terminal 14 respectively have a high-potential-side power supply end and a low level at both rising and falling edges. This is slower than when the differential pair MP1, MP2 and the differential pair MN1, MN2 are driven by a general INV in which the potential side power supply terminal is connected to VDD and GND, respectively. Therefore, the differential output circuit 1 of the present embodiment can suppress the occurrence of overshoot and undershoot of the output waveform, and can also suppress EMI.
[0031]
Next, a modification of this embodiment will be described. FIG. 5 is a block diagram of the differential output circuit 2 of this modification. The differential output circuit 2 connects the low-potential side power supply terminals of the first control output unit 32 and the second control output unit 33 to the fourth node N4, and connects the third control output unit 34 and the fourth control output unit 35 to each other. The configuration of the other parts is the same as that of the differential output circuit 1 except that the high-potential side power supply terminals are connected to the first node N1 only in that the differential output circuit 1 is different. Thereby, the output amplitudes of the first control output unit 32 to the fourth control output unit 35 are further limited as compared with the configuration of the differential output circuit 1 of FIG. 1, so that the configuration is suitable when the output amplitude is large. . Note that the operation of the differential output circuit 2 is the same as that of the differential output circuit 1, and a description thereof will be omitted.
[0032]
Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a second embodiment of the differential output circuit of the present invention. Referring to FIG. 6, the differential output circuit 3 of this embodiment includes a differential output unit 20a and a control unit 30a that is a control unit, and the control unit 30a controls the differential output unit 20a.
[0033]
The differential output unit 20a includes MP1 that is a first switch means, MP2 that is a second switch means, R1 that is a first resistance element, and R2 that is a second resistance element. The sources, drains, and gates of MP1 and MP2 are the first connection end, the second connection end, and the control input end of the first and second switch means, respectively. R1 = R2.
[0034]
The control unit 30a includes a logic processing unit 31a, a first control output unit 32, and a second control output unit 33. Specifically, the logic processing unit 31a is composed of INV1 to INV5, AND1 and AND2, the first control output unit 32 is INV composed of MP3 and MN3, and the second control output unit 33 is INV composed of MP4 and MN4. , Each configured. The differential output circuit 3 further includes MP7 which is a fifth switch means 37.
[0035]
Next, these connection relationships will be described. First, the connection of the differential output unit 20a will be described. The source, drain, and gate of MP1 are connected to the drains of the first node N1, the second node N2, and MP3, respectively, and the source, drain, and gate of MP2 are the drains of the first node N1, the third node N3, and MP4, respectively. Connect to. R1 is connected between the second node N2 and GND, and R2 is connected between the third node N3 and GND. Further, the first constant current source 21 is connected between VDD and the first node N1. That is, in the differential output circuit 3 of the present embodiment, the differential output stage is configured by only MP1 and MP2 using the output of the first constant current source 21 as a constant current. Also in the present embodiment, the second node N2 and the third node N3 serve as output ends of the differential output unit 20a and are connected to the plus output terminal 13 and the minus output terminal 14, respectively.
[0036]
Next, connection of the logic processing unit 31a will be described. The input terminal of INV1 is connected to the data input terminal 11, the output terminal of INV1 is connected to the input terminal of INV2 and the input terminal of INV4, the output terminal of INV2 is connected to one input terminal of AND1, and the output terminal of INV4 Is connected to the input terminal of INV5, and the output terminal of INV5 is connected to one input terminal of AND2. The input terminal of INV3 is connected to the PD terminal 12, and the output terminal of INV3 is connected to the other input terminal of each of AND1 and AND2 and the gate of MP7. Note that the configurations and connections of the first control output unit 32, the second control output unit 33, and the fifth switch means 37 are exactly the same as those in the first embodiment, and a description thereof will be omitted. The operation of the differential output circuit 3 of this embodiment is the same as that of the first embodiment, and the description thereof is omitted.
[0037]
The differential output circuit 3 of the present embodiment replaces the MN1, MN2 and the second constant current source 22 portion in the differential output unit 20 of the differential output circuit 1 with R1 and R2 as described above, and also the MN1 of the control unit 30. In addition, the configuration related to the control and driving of the MN 2 is deleted, and the same operational effects as in the case of the first embodiment can be obtained.
[0038]
Further, in order to transmit the output signal of the differential output circuit 3 to the next stage, when the output terminal is connected to the bias circuit 70 as shown in FIG. 2, the midpoint potential of the output signal is Vc, the maximum potential is Vmax, and the minimum If the potential is Vmin and the voltage value of VDD is V0,
As Rx = (R1 × R12) / (R1 + R12),
Vc = V0 × R11 / (R11 + Rx)
Vmax = Vc + I0 * R11 * Rx / (R11 + Rx)
Vmin = Vc-I0 * R11 * Rx / (R11 + Rx)
It becomes.
[0039]
Next, a modification of this embodiment will be described. FIG. 7 is a block diagram of the differential output circuit 4 showing a modification of the second embodiment. The differential output circuit 4 includes the MP8 that the differential output unit 20a further includes an MP8 serving as a cascode transistor as the first potential correction means 41, and a bias circuit 72 connected to the gate of the MP8, and MP8 is added. This is different from the differential output circuit 3 in that some connections are changed. Hereinafter, the configuration of the differential output circuit 4 of the modification will be described with reference to FIG.
[0040]
First, the connection of the differential output unit 20a will be described. The source, drain, and gate of MP1 are connected to the drains of the first node N1, the second node N2, and MP3, respectively, and the source, drain, and gate of MP2 are the drains of the first node N1, the third node N3, and MP4, respectively. Connect to. R1 is connected between the second node N2 and GND, and R2 is connected between the third node N3 and GND. The process up to this point is the same as that of the differential output circuit 3. Further, the source / drain path of MP8 is connected between the first node N1 and the fifth node N5, the gate of MP8 is connected to the output terminal of the bias circuit 72, and the first constant current source 21 is connected to VDD and the fifth node. Connect to N5.
[0041]
Next, the connection of the control unit 30a will be described focusing on differences from the connection of the differential output circuit 3. In this modification, only the source of MP3 and MP4 and the drain of MP7 which are the high potential side power supply terminals of the first control output unit 32 and the second control output unit 33 are all connected to the fifth node N5. This is different from the case of the differential output circuit 3. In addition, since the other connection relation of the control part 30a including the structure of the logic processing part 31a is the same as that of the case of the differential output circuit 3, these description is abbreviate | omitted. The operation of the differential output circuit 4 is the same as that of the first embodiment, and the description thereof is omitted.
[0042]
Also in this modification, the same effect as the case of the first embodiment can be obtained. When the output amplitude of the differential output unit 20a is small in the configuration like the differential output circuit 3 of FIG. 6, the first control output unit 32 and the second control output are low because the potential of the first node N1 is low. However, in this modification, the potential of the fifth node N5 is raised by the above-described configuration, so that it is necessary to operate the first control output unit 32 and the second control output unit 33. In addition to securing the potential of the high potential side power supply terminal, it also has the effect of improving the power supply voltage dependency of the current value I0 of the first constant current source 21.
[0043]
Next, a third embodiment of the present invention will be described. FIG. 8 is a block diagram of the differential output circuit 5 showing the third embodiment of the present invention. Referring to FIG. 8, the differential output circuit 5 of the present embodiment is configured to include a differential output unit 20b and a control unit 30b as control means, and the control unit 30b controls the differential output unit 20b.
[0044]
The differential output unit 20b includes MN1, which is a third switch means, MN2, which is a fourth switch means, R3, which is a third resistance element, and R4, which is a fourth resistance element. The sources, drains, and gates of MN1 and MN2 are the first connection end, the second connection end, and the control input end of the third and fourth switch means, respectively. R3 = R4.
[0045]
The control unit 30b includes a logic processing unit 31b, a third control output unit 34, and a fourth control output unit 35. Specifically, the logic processing unit 31b is composed of INV1, INV3 to INV6, OR1 and OR2, the third control output unit 34 is INV composed of MP5 and MN5, and the fourth control output unit 35 is composed of MP6 and MN6. Each is composed of INV. The differential output circuit 5 further includes a MN 7 that is a sixth switch means 38.
[0046]
Next, these connection relationships will be described. First, the connection of the differential output unit 20b will be described. The source, drain, and gate of MN1 are connected to the drains of the fourth node N4, second node N2, and MP6, respectively. The source, drain, and gate of MN2 are connected to the drains of the fourth node N4, third node N3, and MP5, respectively. Connect to. R3 is connected between VDD and the second node N2, and R4 is connected between VDD and the third node N3. Further, the second constant current source 22 is connected between the fourth node N4 and GND. That is, in the differential output circuit 5 of the present embodiment, the differential output stage is configured by only MN1 and MN2 using the output of the second constant current source 22 as a constant current. Also in the present embodiment, the second node N2 and the third node N3 serve as the output terminals of the differential output unit 20b and are connected to the plus output terminal 13 and the minus output terminal 14, respectively.
[0047]
Next, connection of the logic processing unit 31b will be described. The input terminal of INV1 is connected to the data input terminal 11, the output terminal of INV1 is connected to the input terminal of INV4, the output terminal of INV4 is connected to the input terminal of INV5 and one input terminal of OR2, and the output terminal of INV5 Is connected to one input of OR1. The input terminal of INV3 is connected to the PD terminal 12, the output terminal of INV3 is connected to the input terminal of INV6, and the output terminal of INV6 is connected to the other input terminal of each of OR1 and OR2 and the gate of MN7. The configurations and connections of the third control output unit 34, the fourth control output unit 35, and the sixth switch means 38 are exactly the same as those in the first embodiment, and a description thereof will be omitted. Note that the operation of the differential output circuit 5 of this embodiment is the same as that of the first embodiment, and a description thereof will be omitted.
[0048]
The differential output circuit 5 of the present embodiment replaces MP1, MP2 and the first constant current source 21 portion in the differential output unit 20 of the differential output circuit 1 with R3, R4 as described above, and MP1 of the control unit 30. In addition, the configuration relating to the control and driving of the MP2 is omitted, and the same operational effects as in the case of the first embodiment can be obtained.
[0049]
Further, in order to transmit the output signal of the differential output circuit 5 to the next stage, when the output terminal is connected to the bias circuit 70 as shown in FIG. 2, the midpoint potential of the output signal is Vc, the maximum potential is Vmax, and the minimum If the potential is Vmin and the voltage value of VDD is V0,
As Ry = (R3 × R11) / (R3 + R11),
Vc = V0 × Ry / (Ry + R12)
Vmax = Vc + I0 * Ry * R12 / (Ry + R12)
Vmin = Vc-I0 * Ry * R12 / (Ry + R12)
It becomes.
[0050]
Next, a modification of this embodiment will be described. FIG. 9 is a block diagram of the differential output circuit 6 showing a modification of the third embodiment. The differential output circuit 6 further includes a MN8, which is a cascode transistor as the second potential correction means 43, and a bias circuit 74 connected to the gate of the MN8. This is different from the differential output circuit 5 in that some connections are changed. Hereinafter, the configuration of the differential output circuit 6 according to a modification will be described with reference to FIG.
[0051]
First, the connection of the differential output unit 20b will be described. The source, drain, and gate of MN1 are connected to the drains of the fourth node N4, second node N2, and MP6, respectively. The source, drain, and gate of MN2 are connected to the drains of the fourth node N4, third node N3, and MP5, respectively. Connect to. R3 is connected between VDD and the second node N2, and R4 is connected between VDD and the third node N3. The process up to this point is the same as that of the differential output circuit 5. Further, the source / drain path of MN8 is connected between the fourth node N4 and the sixth node N6, the gate of MN8 is connected to the output terminal of the bias circuit 74, and the second constant current source 22 is connected to the sixth node N6. Connect to GND.
[0052]
Next, the connection of the control unit 30b will be described focusing on differences from the connection of the differential output circuit 5. In this modification, only the points where the sources of MN5 and MN6 and the drain of MN7, which are the low potential side power supply terminals of the third control output unit 34 and the fourth control output unit 35, are all connected to the sixth node N6. This is different from the case of the differential output circuit 5. In addition, since the other connection relation of the control part 30b including the structure of the logic process part 31b is the same as that of the case of the differential output circuit 5, these description is abbreviate | omitted. The operation of the differential output circuit 6 is the same as that of the first embodiment, and the description thereof is omitted.
[0053]
Also in this modification, the same effect as the case of the first embodiment can be obtained. Further, in the configuration like the differential output circuit 5 of FIG. 8, when the output amplitude of the differential output unit 20b is small, since the potential of the fourth node N4 is high, the third control output unit 34 and the fourth control output. However, in this modification, the potential of the sixth node N6 can be lowered by the above configuration, so that the third control output unit 34 and the fourth control output unit 35 are operated. The potential of the low-potential-side power supply terminal required for the second constant current source 22 can be secured and the power supply voltage dependency of the current value I0 of the second constant current source 22 can be improved.
[0054]
Needless to say, the present invention is not limited to the description of the above-described embodiment, and various modifications can be made within the scope of the gist thereof. For example, the configuration of the logic processing unit included in the control unit may be arbitrarily changed according to the presence / absence of an additional function such as a power saving function or a necessary delay time as long as the output logic is maintained.
[0055]
【The invention's effect】
As described above, the differential output circuit of the present invention can suppress the occurrence of overshoot and undershoot of the output waveform while reducing the occurrence of errors during transmission while enabling the high-speed transmission of the signal, and the output waveform. By gradual transition of EMI, there is an effect that EMI can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a differential output circuit of the present invention.
2A and 2B are diagrams for explaining the operation of the differential output circuit of the present invention. FIG. 2A is an external bias circuit when a signal is transmitted by the differential output circuit of FIG. 1 and connection to the bias circuit. Partial connection diagrams showing configuration examples, (b) are schematic waveform diagrams of data input signals and output signals to the differential output circuit in the connection of (a).
3 is a diagram for explaining the operation of the differential output circuit of the present invention, and is a potential waveform diagram at the main node of the differential output circuit of FIG. 1; FIG.
4 is an operation simulation waveform diagram when the output terminal of the differential output circuit of FIG. 1 is connected to the bias circuit of FIG. 2;
FIG. 5 is a block diagram of a differential output circuit according to a modification of the first embodiment.
FIG. 6 is a block diagram showing a second embodiment of the differential output circuit of the present invention.
FIG. 7 is a block diagram of a differential output circuit according to a modification of the second embodiment.
FIG. 8 is a block diagram showing a third embodiment of the differential output circuit of the present invention.
FIG. 9 is a block diagram of a differential output circuit according to a modification of the third embodiment.
FIG. 10 is a block diagram of an example of a differential output circuit having a conventional power saving function.
11 is an operation simulation waveform diagram when the output terminal of the conventional differential output circuit of FIG. 10 is connected to a predetermined bias circuit.
[Explanation of symbols]
1, 2, 3, 4, 5, 6 Differential output circuit
11 Data input terminal
12 PD terminal
13 Positive output terminal
14 Negative output terminal
20, 20a, 20b Differential output section
21 First constant current source
22 Second constant current source
30, 30a, 30b control unit
31, 31a, 31b Logic processing unit
32 1st control output part
33 Second control output unit
34 Third control output section
35 Fourth control output section
37 Fifth switch means
38 Sixth switch means
41 First potential correction means
43 Second potential correction means
70, 72, 74 Bias circuit

Claims (17)

それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１乃至第４スイッチ手段と、第１及び第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１乃至第４制御信号をそれぞれ出力する第１乃至第４制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記低電位側電源に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each includes a first connection end, a second connection end, and a control input end, and controls first and second conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. Fourth switch means, first and second constant current output means, and first to fourth control output sections for outputting first to fourth control signals based on a data signal input to the first signal input terminal, respectively. Having control means including,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the first node and the low potential side power supply, respectively;
Connecting the high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit to the high potential side power supply and the fourth node, respectively;
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１乃至第４スイッチ手段と、第１及び第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１乃至第４制御信号をそれぞれ出力する第１乃至第４制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第１制御出力部乃至前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each includes a first connection end, a second connection end, and a control input end, and controls first and second conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. Fourth switch means, first and second constant current output means, and first to fourth control output sections for outputting first to fourth control signals based on a data signal input to the first signal input terminal, respectively. Having control means including,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit to the fourth control output unit to the first node and the fourth node, respectively;
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段及び第６スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第１ノードにそれぞれ接続し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第４ノードにそれぞれ接続し、前記５スイッチ手段及び前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御するようにした請求項１又は２に記載の差動出力回路。Each of the fifth switches includes a first connection end, a second connection end, and a control input end, and controls conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. And a sixth switch means, wherein the first connection end and the second connection end of the fifth switch means are respectively connected to the high potential side power source and the first node, and the first switch terminal of the sixth switch means A connection end and a second connection end are connected to the low-potential-side power source and the fourth node, respectively, and conduction and non-conduction of the 5 switch means and the sixth switch means are input to a second signal input end of the control means. The differential output circuit according to claim 1, wherein the differential output circuit is controlled by a power saving control signal. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１スイッチ手段及び第２スイッチ手段と、第１抵抗素子及び第２抵抗素子と、第１定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第１制御信号及び第２制御信号をそれぞれ出力する第１制御出力部及び第２制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記第１抵抗素子を前記第２ノードと低電位側電源との間に接続し、
前記第２抵抗素子を前記第３ノードと前記低電位側電源との間に接続し、
前記第１定電流出力手段を前記第１ノードと高電位側電源との間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第１ノードと前記低電位側電源に接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each of the first switches includes a first connection end, a second connection end, and a control input end, and controls conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. Means, second switch means, first resistance element and second resistance element, first constant current output means, and a first control signal and a second control signal based on a data signal input to the first signal input terminal. Control means including a first control output unit and a second control output unit for outputting respectively,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first resistance element between the second node and a low-potential-side power supply;
Connecting the second resistive element between the third node and the low-potential-side power supply;
Connecting the first constant current output means between the first node and a high potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the first node and the low potential side power supply, respectively;
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. 第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第１ノードにそれぞれ接続し、前記５スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御する請求項４記載の差動出力回路。A fifth switch means having a first connection end, a second connection end, and a control input end, and controlling conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end; And connecting the first connection end and the second connection end of the fifth switch means to the high-potential-side power source and the first node, respectively. The differential output circuit according to claim 4, wherein the differential output circuit is controlled by a power saving control signal input to the two-signal input terminal. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第１スイッチ手段及び第２スイッチ手段と、第１抵抗素子及び第２抵抗素子と、第１定電流出力手段と、第１電位補正手段と、第１信号入力端に入力するデータ信号に基づいて第１制御信号及び第２制御信号をそれぞれ出力する第１制御出力部及び第２制御出力部を含む制御手段を有し、
前記１スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第２ノード及び前記第１制御出力部の出力端と接続し、
前記２スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第１ノード、第３ノード及び前記第２制御出力部の出力端と接続し、
前記第１抵抗素子を前記第２ノードと低電位側電源との間に接続し、
前記第２抵抗素子を前記第３ノードと前記低電位側電源との間に接続し、
前記第１定電流出力手段を第５ノードと高電位側電源との間に接続し、
前記第１電位補正手段を前記第１ノーと前記第５ノードとの間に接続し、
前記第１制御出力部及び前記第２制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記第５ノードと前記低電位側電源に接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each of the first switches includes a first connection end, a second connection end, and a control input end, and controls conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. Means and second switch means; first resistance element and second resistance element; first constant current output means; first potential correction means; and first control based on a data signal input to the first signal input terminal. Control means including a first control output unit and a second control output unit for outputting a signal and a second control signal,
Connecting the first connection end, the second connection end and the control input end of the one switch means with the first node, the second node and the output end of the first control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the two switch means with the first node, the third node and the output end of the second control output unit, respectively;
Connecting the first resistance element between the second node and a low-potential-side power supply;
Connecting the second resistive element between the third node and the low-potential-side power supply;
Connecting the first constant current output means between a fifth node and a high-potential side power supply;
Connecting the first potential correcting means between the first node and the fifth node;
Connecting the high potential side power supply end and the low potential side power supply end of the first control output unit and the second control output unit to the fifth node and the low potential side power supply, respectively;
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. 前記第１電位補正手段は、ゲート電極に所定の電位を供給し、ソースドレイン路を前記第１ノードと前記第５ノードとの間に接続したｐチャネル電界効果トランジスタである請求項６記載の差動出力回路。7. The difference according to claim 6, wherein the first potential correction means is a p-channel field effect transistor in which a predetermined potential is supplied to a gate electrode and a source / drain path is connected between the first node and the fifth node. Dynamic output circuit. 第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第５スイッチ手段を更に有し、前記第５スイッチ手段の第１接続端及び第２接続端を前記高電位側電源及び前記第５ノードにそれぞれ接続し、前記５スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御する請求項６又は７に記載の差動出力回路。A fifth switch means having a first connection end, a second connection end, and a control input end, and controlling conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end; And connecting the first connection end and the second connection end of the fifth switch means to the high-potential-side power source and the fifth node, respectively. The differential output circuit according to claim 6, wherein the differential output circuit is controlled by a power saving control signal input to the two-signal input terminal. 前記第５スイッチ手段は、ｐチャネル電界効果トランジスタで構成され、該ｐチャネル電界効果トランジスタのソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端である請求項３，５及び８のいずれか１項に記載の差動出力回路。The fifth switch means is composed of a p-channel field effect transistor, and a source electrode, a drain electrode and a gate electrode of the p-channel field effect transistor are respectively at the first connection end, the second connection end and the control input end. The differential output circuit according to any one of claims 3, 5, and 8. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第３スイッチ手段及び第４スイッチ手段と、第３抵抗素子及び第４抵抗素子と、第２定電流出力手段と、第１信号入力端に入力するデータ信号に基づいて第３制御信号及び第４制御信号をそれぞれ出力する第３制御出力部及び第４制御出力部を含む制御手段を有し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第３抵抗素子を前記第２ノードと高電位側電源との間に接続し、
前記第４抵抗素子を前記第３ノードと前記高電位側電源との間に接続し、
前記第２定電流出力手段を前記第４ノードと低電位側電源との間に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第４ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each of the third switches includes a first connection end, a second connection end, and a control input end, and controls conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end. Means, fourth switch means, third resistance element and fourth resistance element, second constant current output means, and third control signal and fourth control signal based on the data signal input to the first signal input terminal. Control means including a third control output unit and a fourth control output unit for outputting respectively,
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the third resistance element between the second node and a high-potential side power supply;
Connecting the fourth resistance element between the third node and the high-potential-side power supply;
Connecting the second constant current output means between the fourth node and a low-potential side power supply;
Connecting the high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit to the high potential side power supply and the fourth node, respectively;
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. 第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第６スイッチ手段を更に有し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第４ノードにそれぞれ接続し、前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御する請求項１０記載の差動出力回路。Sixth switch means having a first connection end, a second connection end, and a control input end, and controlling conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. And connecting the first connection end and the second connection end of the sixth switch means to the low-potential-side power source and the fourth node, respectively, and setting the conduction and non-conduction of the sixth switch means to the control means. The differential output circuit according to claim 10, wherein the differential output circuit is controlled by a power saving control signal input to the second signal input terminal. それぞれが第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第３スイッチ手段及び第４スイッチ手段と、第３抵抗素子及び第４抵抗素子と、第２定電流出力手段と、第２電位補正手段と、第１信号入力端に入力するデータ信号に基づいて第３制御信号及び第４制御信号をそれぞれ出力する第３制御出力部及び第４制御出力部を含む制御手段を有し、
前記３スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第２ノード及び前記第４制御出力部の出力端と接続し、
前記４スイッチ手段の第１接続端、第２接続端及び制御入力端をそれぞれ第４ノード、第３ノード及び前記第３制御出力部の出力端と接続し、
前記第３抵抗素子を前記第２ノードと高電位側電源との間に接続し、
前記第４抵抗素子を前記第３ノードと前記高電位側電源との間に接続し、
前記第２定電流出力手段を第６ノードと低電位側電源との間に接続し、
前記第２電位補正手段を前記第４ノーと前記第６ノードとの間に接続し、
前記第３制御出力部及び前記第４制御出力部の高電位側電源端と低電位側電源端をそれぞれ前記高電位側電源と前記第６ノードに接続し、
前記第２ノードと前記第３ノードを差動出力端とする構成を有することを特徴とする差動出力回路。Each of the third switches includes a first connection end, a second connection end, and a control input end, and controls conduction and non-conduction between the first connection end and the second connection end according to a signal input to the control input end. Means and fourth switch means, third resistance element and fourth resistance element, second constant current output means, second potential correction means, and third control based on the data signal input to the first signal input terminal Control means including a third control output unit and a fourth control output unit for outputting a signal and a fourth control signal, respectively.
Connecting the first connection end, the second connection end and the control input end of the three switch means to the fourth node, the second node and the output end of the fourth control output unit, respectively;
Connecting the first connection end, the second connection end and the control input end of the four switch means with the fourth node, the third node and the output end of the third control output unit, respectively;
Connecting the third resistance element between the second node and a high-potential side power supply;
Connecting the fourth resistance element between the third node and the high-potential-side power supply;
The second constant current output means is connected between the sixth node and the low potential side power supply;
Connecting the second potential correcting means between the fourth node and the sixth node;
The high potential side power supply end and the low potential side power supply end of the third control output unit and the fourth control output unit are connected to the high potential side power supply and the sixth node, respectively.
A differential output circuit having a configuration in which the second node and the third node are differential output terminals. 前記第２電位補正手段は、ゲート電極に所定の電位を供給し、ソースドレイン路を前記第４ノードと前記第６ノードとの間に接続したｎチャネル電界効果トランジスタである請求項１２記載の差動出力回路。13. The difference according to claim 12, wherein the second potential correcting means is an n-channel field effect transistor in which a predetermined potential is supplied to a gate electrode and a source / drain path is connected between the fourth node and the sixth node. Dynamic output circuit. 第１接続端、第２接続端及び制御入力端を備え、該制御入力端に入力する信号により前記第１接続端と前記第２接続端との導通、非導通を制御する第６スイッチ手段を更に有し、前記第６スイッチ手段の第１接続端及び第２接続端を前記低電位側電源及び前記第６ノードにそれぞれ接続し、前記第６スイッチ手段の導通、非導通を前記制御手段の第２信号入力端に入力される省電力制御信号により制御する請求項１２又は１３に記載の差動出力回路。Sixth switch means comprising a first connection end, a second connection end, and a control input end, and controlling conduction and non-conduction between the first connection end and the second connection end by a signal input to the control input end. And connecting the first connection end and the second connection end of the sixth switch means to the low-potential side power source and the sixth node, respectively, and setting the conduction and non-conduction of the sixth switch means to the control means. The differential output circuit according to claim 12, wherein the differential output circuit is controlled by a power saving control signal input to the second signal input terminal. 前記第６スイッチ手段は、ｎチャネル電界効果トランジスタで構成され、該ｎチャネル電界効果トランジスタのソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端である請求項３，１１及び１４のいずれか１項に記載の差動出力回路。The sixth switch means comprises an n-channel field effect transistor, and the source electrode, drain electrode, and gate electrode of the n-channel field effect transistor are the first connection end, the second connection end, and the control input end, respectively. The differential output circuit according to any one of claims 3, 11, and 14. 前記第１スイッチ手段及び前記第２スイッチ手段は、いずれもｐチャネル電界効果トランジスタで構成され、該ｐチャネル電界効果トランジスタのソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端である請求項１乃至９いずれか１項に記載の差動出力回路。Each of the first switch means and the second switch means is composed of a p-channel field effect transistor, and a source electrode, a drain electrode, and a gate electrode of the p-channel field effect transistor are respectively connected to the first connection end, the second switch The differential output circuit according to claim 1, which is a connection end and the control input end. 前記第３スイッチ手段及び前記第４スイッチ手段は、いずれもｎチャネル電界効果トランジスタで構成され、該ｎチャネル電界効果トランジスタのソース電極、ドレイン電極及びゲート電極がそれぞれ前記第１接続端、前記第２接続端及び前記制御入力端である請求項１乃至３，及び１０乃至１５のいずれか１項に記載の差動出力回路。Each of the third switch means and the fourth switch means is composed of an n-channel field effect transistor, and the source electrode, drain electrode and gate electrode of the n-channel field effect transistor are the first connection end, the second switch The differential output circuit according to claim 1, which is a connection end and the control input end.
JP2002122848A 2002-04-24 2002-04-24 Differential output circuit Expired - Fee Related JP3722779B2 (en)

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