JP3712140B2 - Electron beam drawing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a drawing pattern formation using a charged particle beam, and in particular, an electron beam drawing apparatus using a collective figure irradiation method. In Related.
[0002]
[Prior art]
Recent semiconductor integrated circuits have been miniaturized and highly integrated, and lithography techniques for realizing microfabrication have also been improved in accuracy of the apparatus. With further miniaturization and higher precision, an electron beam drawing apparatus has been used instead of the conventionally used photolithography. One of the drawbacks of an electron beam lithography apparatus for optical lithography is low throughput. To overcome this, Saito et al. Described in "Proceedings of International Microprocess Conference (1990), pp. 48-51". The aperture is used to irradiate the graphic aperture with a larger electron beam, and an image of the graphic aperture is formed on the sample to improve the throughput.
[0003]
[Problems to be solved by the invention]
The above prior art is effective for a memory cell having a repetitive pattern, but cannot be applied to a peripheral logic circuit. Therefore, the peripheral circuit is drawn using the conventional variable rectangle method. The problem with the variable rectangle method is that an electron beam having a rectangular size can be freely formed, but there is a problem that an error in the rectangular size caused by thermal drift or charge-up of the mask becomes an error in resist pattern formation. This lowers the yield of the integrated circuit formed using the electron beam, and in an extreme case, an electron beam having a size below a certain level cannot be substantially formed.
An object of the present invention is to realize high-accuracy pattern formation by electron beam drawing, improve the drawing accuracy of peripheral circuits of memory cells and non-repetitive logic circuits, and contribute to improving the yield of integrated circuits. It is in.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a mask having a graphic opening for collective graphic irradiation method has a graphic opening for collective graphic irradiation method consisting of one opening. Then, using this opening, an integrated circuit, particularly a logic circuit part, is drawn. Further, a relatively small pattern of a circuit is formed by a graphic opening, and a relatively large pattern is formed by a variable molding method. It is even better if the size of the rectangular opening is less than or equal to the minimum size on the sample. At this time, the thickness of the mask is made smaller than the range of the electron beam, and a stop for blocking scattered electrons of the mask is provided downstream. The shape of the opening is particularly rectangular, and it is even better if there are a plurality of rectangular openings with different sizes. In particular, it is important to have a graphic opening composed of one rectangular opening for the collective graphic irradiation method and a graphic opening composed of a rectangular opening rotated by 90 degrees. Moreover, it is set as the shape which added the opening smaller than a rectangle in the corner vicinity of these rectangles. In addition, these opening shapes are graphic opening shapes for one cell unit of repeated graphics used for the collective graphic.
Furthermore, if mark detection is performed using a rectangular opening of an appropriate size and drawing is performed, drawing with high positional accuracy is possible. A suitable size is between 2% and 25% of the maximum collective figure.
It should be noted that the figure opening for the collective figure irradiation method consisting of one opening is arranged closer to the first mask image when the figure selection deflector is not used than the figure opening consisting of a plurality of openings, and consists of one opening. Various apertures are selected more effectively by selecting a graphic aperture for the collective graphic irradiation method using a graphic aperture consisting of a plurality of apertures and a different deflector.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an apparatus configuration for a batch graphic irradiation method to which the present invention is applied, and the effectiveness of the electron beam drawing apparatus and the drawing pattern forming method of the present invention will be described. 2 shows a plan view (a) and a cross-sectional view (b) of the mask shown in FIG. 1, and an enlarged view of one figure opening group 32 on the silicon mask 31. FIG. The electrons that have passed through the rectangular opening on the first mask 2 are imaged on the second mask 5. On the second mask shown in FIG. 2, there are a rectangular opening 34 (125 μm square) for variable molding and a graphic opening 33 having a memory cell pattern composed of a plurality of openings. The first mask image 35 on the second mask is 150 μm square, and the collective figure on the second mask is a maximum of 125 μm square. For the first mask image, a batch figure is selected in units of 150 μm. The graphic beam transmitted through the second mask is reduced by the reduction lens 8 and further imaged on the sample by the objective lens 14. The collective figure is, for example, a hole pattern, for example, a wiring pattern. On the second mask, there is also a graphic opening 36 consisting of one opening. In FIG. 2, it is a rectangular opening, which corresponds to one cell of a collective figure of a hole pattern. In a normal hole pattern forming process, a hole pattern is formed not only in a memory cell but also in a peripheral circuit. Therefore, if a graphic opening consisting of one opening, particularly a rectangular opening, is prepared, the peripheral circuit can be formed using this opening. The size of the electron beam transmitted through the figure opening on the sample can be adjusted by adjusting the reduction ratio, and the reduction ratio is very stable. Accordingly, the size of the rectangular aperture graphic aperture beam on the sample can be adjusted with high accuracy. This makes it possible to improve the accuracy of a rectangular beam, which is difficult with a variable rectangle. If one side is equal to or smaller than the dimension on the mask corresponding to the minimum dimension on the sample, the present invention can be easily applied to the drawing of these fine patterns that require high accuracy. Furthermore, the dimension on the mask corresponding to the minimum dimension or 1/2 of the dimension is good. The above operation is the same even without a memory cell circuit, and the collective graphic irradiation method of the present invention is effective even with only a logic circuit. Further, in a normal memory circuit, since many memory cell portions and peripheral circuit portions use holes of the same size, it is effective to use a graphic opening having one cell of the collective graphic opening of the memory cell portion.
[0006]
Also, the peripheral circuit is not necessarily composed of a single rectangle. FIG. 3 shows a plan view (a) and a cross-sectional view (b) of a mask having drawing openings of different sizes, and an enlarged view of one opening group 32 on the silicon mask 31. FIG. As shown in FIG. 3, it is configured to have a plurality of openings 37 of different sizes, each having a graphic opening made up of one rectangular opening. In particular, if a minute pattern, which is difficult with the variable rectangle method, is performed with one rectangular opening and a relatively large pattern is drawn with the conventional variable rectangle method, it is possible to efficiently draw peripheral circuits composed of rectangles of different sizes. Become. If there is a graphic opening consisting of a single rectangular opening for batch graphic irradiation and a rectangular opening rotated 90 degrees, a wiring pattern can be formed in two orthogonal directions when a long and narrow pattern such as wiring is required It can be applied and the application range is expanded.
Further, when the resolution limit of the electron beam drawing system is approached, for example, even if a rectangular opening is used, the drawing pattern does not necessarily have a rectangular shape, but has a shape close to a circle. Therefore, as shown in the plan view of the mask of FIG. 4 (including an enlarged view of one opening group) (a) and the sectional view (b), the result is obtained by adding small openings to the corners of the opening pattern of the collective figure. Thus, a drawing pattern having a good corner shape can be obtained. This method can also be applied to an opening figure composed of one rectangular opening. In FIG. 4, reference numeral 38 denotes a modified figure opening made up of a plurality of openings, and 39 denotes a modified figure opening made up of one opening. As a result, the shape of the rectangular pattern of the peripheral circuit, which has been impossible in the past, can be improved. Of course, the same applies to a logic circuit having no memory cell, and the batch graphic irradiation method is effective in the logic circuit. In this case, deformation of the opening forms a finely shaped opening. Therefore, it is effective to improve the processing accuracy by thinning the mask. A sufficient mask contrast can be obtained by providing a stop for blocking scattered electrons transmitted through the mask.
[0007]
Furthermore, in conventional mark detection with a variable rectangular beam, an error in the size of the rectangle leads to an error in the detection of the mark position. Therefore, mark detection using a rectangular aperture with a determined size is expected to provide higher accuracy. it can. This will be described with reference to FIGS. As shown in FIG. 5, a means generally used in mark detection scans a cross mark 203 with a rectangular beam 200, and obtains a signal as shown in FIG. 6 based on the difference in reflectance between the ground and the mark. The coordinate that is most accurately obtained from this signal waveform is the midpoint of the waveform, and the coordinate is (K + L) / 2 relative to the rising point A of the waveform. That is, it depends on the size L of the rectangle. Usually, the rectangular beam position reference 201 is a rectangular edge portion, and the position of the mark is measured by obtaining the relative distance between the position 201 and the center position of the mark 203. Accordingly, the relative position of the mark can be obtained by subtracting L / 2 from the center coordinates with reference to the rising point A of the waveform shown in FIG. 6 (ie, K / 2). Therefore, if the actual width L ′ of the rectangle at the time of measurement is different from the width L of the set value, an error occurs in the measurement coordinates by (L′−L) / 2. According to the present invention, the rectangular width of the set value can be realized with high accuracy, and this error can be avoided. Further, by using a rectangle, a conventional mark detection method such as a slice level method or an objectivity calculation method can be used as it is. If the size of the rectangle is too small, sufficient signal intensity cannot be obtained, and if it is too large, the beam is stunned by the Coulomb effect, so 2% to 25% of the maximum collective figure is appropriate. Further, when combined with the above drawing method, drawing is possible without using any variable rectangle. This is effective for simplifying the apparatus.
As described above, according to the present invention, the collective graphic irradiation method can be effectively used even for a non-repetitive pattern. As a result, it is possible to perform drawing with higher accuracy than in the past, and the yield of integrated circuit fabrication can be improved.
[0008]
【Example】
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 7 shows an apparatus configuration in this embodiment. A rectangular opening of 150 μm square is provided in the first mask 2, and a rectangular image is formed on the second mask 5. The figure opening on the second mask is selected by a figure selection deflector 4 separated into two stages. Reference numeral 18 denotes a variable rectangular deflector for the variable rectangle method. The second mask is made of silicon, and there are five figure openings for collective figures around the 125 .mu.m rectangular opening 34 for the variable rectangle as shown in FIG. 8A is a plan view of the mask (including an enlarged view of one opening group), FIG. 8B is a cross-sectional view thereof, and 71 shows graphic openings B and C each having one opening. The difference between the opening of the figure and the opening for the variable rectangle is determined only by the figure opening while the outline of the electron beam that has passed through the opening of the figure is the opening on the first mask. And the contour of the opening on the second mask. The electrons transmitted through the figure opening are reduced by the reduction lens 8 and finally reduced to 1/25 on the sample to form an image. There are 25 such aperture groups on the second mask, and the aperture groups are selected by moving the mask stage. The wafer 17 is carried in and out by the stage 16. In addition to wafers, reticles can be drawn by changing the cassette. In order to form a 0.2 μm square hole on the wafer, it is necessary to form a 5 μm square opening on the mask. The wafer figure opening A in FIG. 8 is a 0.2 μm rectangle on the wafer, and there is a 16-bit rectangle in the batch figure. On the other hand, the figure opening B has only one rectangle within the unit collective figure range of 125 μm. The same applies to the figure opening C. The difference between the graphic openings B and C is that they are 0.2 μm square and 0.25 μm square on the wafer, respectively. These openings are selected by the graphic selection deflector 4.
[0009]
FIG. 9 shows a part of the drawing pattern in this embodiment. The memory cell portion is drawn using the graphic opening A shown in FIG. 8, and the peripheral circuit is drawn using the graphic openings B and C and the variable rectangle shown in FIG. In FIG. 9, 80 is a figure of the memory cell portion drawn by the figure opening A, 81 and 82 are figures of the peripheral circuit portion drawn by the figure openings B and C, respectively, and 83 is a peripheral circuit drawn by the variable rectangle. It is a figure of the part. The pattern drawn by the variable rectangle is a pattern of 0.5 μm or more, and the 0.2 μm and 0.25 μm patterns in the outermost periphery of the memory cell are drawn by the graphic opening B. As a result, it is possible to draw a pattern with strict accuracy of the peripheral circuit without using a variable rectangle having an error in adjusting the rectangular size. Since drawing all the patterns with the figure openings causes an increase in the number of necessary figures, a loose pattern with an accuracy of 0.5 μm or more is drawn with a variable rectangle. The dimensional error of the drawing pattern of each hole of 0.2 μm and 0.25 μm in the peripheral circuit was ± 0.02 μm or less in a 6-inch wafer. On the other hand, since the 0.5 μm hole was drawn by the variable rectangle method, the dimensional error was not so good as ± 0.06 μm. However, since the size is large, there is no practical problem.
[0010]
10A to 10D are cross-sectional views of the element showing the steps in this example. A P well layer 46, a P layer 47, a field oxide film 48, a polycrystalline silicon / silicon oxide film gate 49, a P high concentration diffusion layer 50, an N high concentration diffusion layer 51, etc. It was formed (FIG. 8 (a)). Next, an insulating film 52 of phosphorus glass (PSG) was deposited by a normal method. An electron beam resist 53 was applied thereon, and a hole pattern 54 was formed by a method using the deformation mask of the present invention (FIG. 8B). Next, the insulating film 52 was dry etched using the electron beam resist as a mask to form a contact hole 55 (FIG. 8C). Next, a W / TiN electrode wiring 56 was formed by a normal method, and then an interlayer insulating film 57 was formed. Next, an electron beam resist was applied, and a hole pattern 58 was formed by a method using the deformation mask of the present invention. The hole pattern 58 was filled with a W plug, and the Al second wiring 59 was connected (FIG. 8D). Conventional methods were used for the subsequent passivation steps. Although only the main manufacturing process has been described in this embodiment, the same process as the conventional method was used except that the drawing pattern forming method of the present invention was used in the lithography process for forming the contact hole. With the above process, CMOS LSI can be manufactured with high yield. As a result of manufacturing the semiconductor device using this embodiment, it was possible to prevent the peripheral circuit from being defective, and the yield of non-defective products was greatly improved.
[0011]
(Second embodiment)
The apparatus configuration in this embodiment is the same as that in the first embodiment (FIG. 1), but the figure selection deflection is one stage, and the reduction ratio is set to 1 by changing the excitation of the reduction lens (8 in FIG. 1). / 50 is different. FIG. 11 shows a mask opening in this embodiment. 11A is a plan view of the mask (including an enlarged view of one opening group), FIG. 11B is a cross-sectional view thereof, 72 is a rectangular of 250 μm square, and 73 is a deformation made of one opening. A graphic opening E is shown. A collective figure is a deformed rectangular pattern for a hole. The pattern is a 0.15 μm square hole on the wafer. Therefore, a 7.5 μm square opening is required on the mask. Since the electron beam writing apparatus used in this example has an electron beam blur of about 0.1 μm, a 7.5 μm square opening is not a 0.15 μm square but a 0.15 μm circular hole. End up. Therefore, in FIG. 11, a modified opening in which an opening is further added to a rectangular corner is used. As a result, a hole pattern closer to a rectangle can be formed, which contributes to a reduction in hole contact resistance. As a result of drawing, a hole having a corner radius of curvature of 0.03 μm was obtained. Also in this embodiment, the figure opening E having one hole pattern opening and a figure opening D having a hole pattern of 16 bits is provided. Using this, the hole pattern of the peripheral circuit is drawn as shown in FIG. 12, 84 is a graphic formed by the graphic opening D shown in FIG. 11, and 85 is a graphic of the peripheral circuit portion formed by the modified graphic opening E shown in FIG. As a result, a peripheral circuit which has been conventionally drawn only with a rectangular electron beam can be drawn with a more preferable electron beam. As described above, the present invention can not only reduce the dimensional error of the peripheral circuit but also improve the drawing pattern shape. In this embodiment, the thickness of the silicon mask was set to 5 μm (1/4 of the used 50 kV electron range) in order to improve the precision of the fine processing of the mask opening. The electrons scattered and transmitted in 5 μm silicon are blocked by a limiting aperture (9 in FIG. 1) provided under the reduction lens so as to pass through the mask with a large angle and do not reach the wafer. The limiting aperture may be installed anywhere below the second mask, but it is preferable to use a lens after the reduction lens that increases the scattering angle. The diameter of the restriction aperture is 1 mm. A thin mask is suitable for forming an opening having a minute size necessary for deformation of the opening.
When this embodiment was applied to an integrated circuit process in the same manner as in the first embodiment, the contact resistance was reduced by 20% on average as compared with the rectangular opening, and the fluctuation could be ± 5% or less. As a result, the yield of the integrated circuit is greatly improved.
[0012]
(Third embodiment)
In this embodiment, an application example for forming a wiring pattern will be described. FIG. 13 shows the mask opening. 13A is a plan view of the mask (including an enlarged view of one opening group), FIG. 13B is a sectional view thereof, and 74 shows graphic openings Q to T each having one opening. In this embodiment, four types of graphic openings Q, R, S, and T having a rectangular pattern are provided in addition to the graphic opening P for the memory cell portion. The dimensions are 5 μm × 50 μm, 50 μm × 5 μm, 5 μm × 100 μm, and 100 μm × 5 μm, respectively. In this embodiment, since the reduction ratio of the apparatus is 1/25, the dimensions on the sample are 0.2 μm × 2 μm, 2 μm × 0.2 μm, 0.2 μm × 4 μm, and 4 μm × 0.2 μm, respectively. The feature of these openings is that they have a figure opening for batch figure irradiation consisting of one rectangular opening and a figure opening consisting of a rectangular opening rotated 90 degrees, and one side is the same length and the other side is The length is different.
Using this mask, the wiring process was drawn so as to show a part of the pattern in FIG. Reference numerals 86 to 89 denote figures formed by the figure openings P to S, respectively. In this embodiment, the memory cell portion is drawn with a graphic opening P and the peripheral circuits are drawn with graphic openings Q to T. In the wiring process, the peripheral pattern has many straight portions, and if these are drawn using a mask having a rectangular opening, drawing with high dimensional accuracy can be expected. Since the wiring normally extends in two directions, it is desirable to have a two-way rectangle. If rectangular openings having different lengths are provided, a graphic opening can be used efficiently as shown in FIG.
This example was applied to an aluminum wiring process of an integrated circuit. A metal is deposited to a thickness of 1 μm on the entire surface by chemical vapor deposition on the wafer after the hole formation process. Next, an electron beam resist is applied. Thereafter, drawing is performed using a mask having the mask pattern 72 of FIG. After the drawing, development is performed to form a resist pattern, and the metal layer is dry-etched using the resist pattern as a mask to form a metal wiring pattern. The resist is removed last. As a result, wiring with good dimensional accuracy (measured at 10 points for each of 20 wafers, wiring was formed with an accuracy of 0.2 μm ± 0.02 μm. In FIG. 14, T represents one of the measuring points. ) Was able to be formed. As a result, the fluctuation of the wiring resistance is reduced, and as a result, the yield of the integrated circuit is greatly improved.
[0013]
(Fourth embodiment)
In this embodiment, the present invention is applied to formation of a hole layer of a logic pattern. Therefore, there is no complicated figure opening for the memory circuit on the mask as shown in FIG. 15, (a) is a plan view of a mask (including an enlarged view of one opening group), (b) is a cross-sectional view thereof, and 37 is a graphic opening U to a different size consisting of one opening. W is shown. The mask has square openings of different sizes (0.2 μm, 0.25 μm and 0.3 μm on the wafer). FIG. 16 shows a part of the drawn circuit pattern. 16, 90 is a graphic formed by the graphic opening U shown in FIG. 15, and 91 is a graphic of the peripheral circuit portion formed by the graphic opening W shown in FIG. Since it is a logic circuit, there is no regularity in the position and size of holes. However, by applying the drawing pattern forming method of this embodiment, these minute holes can be formed with high accuracy.
[0014]
(Fifth embodiment)
In this embodiment, mark detection using a rectangular figure opening will be described. FIG. 17 shows an apparatus configuration. There are a beam calibration mark 102 made of heavy metal and a mark 103 on the wafer 17 on the stage. 18A and 18B show a mask structure, in which FIG. 18A is a plan view of a mask (including an enlarged view of one opening group), FIG. 18B is a cross-sectional view thereof, and 36 is a different size composed of one opening. Indicates a graphic opening. A rectangular opening 101 is a mark detection opening, and this figure is selected to form a rectangular beam having a predetermined size. The size of the rectangular opening 101 is 50 μm square, and the area is 16% of the maximum collective figure opening 125 μm square (rectangular opening 34). Since the reduction ratio is 1/25, it becomes 2 μm square on the wafer. Thus, the mark is scanned by scanning the mark and detecting reflected electrons and secondary electrons. If there is a mark on the wafer, it mainly detects the mark on the wafer, measures the position of the pattern on the lower layer and performs alignment drawing. If there is no mark on the wafer, such as a reticle, a beam calibration mark fixed on the stage Measure and draw the absolute position of the electron beam. FIG. 19 shows a mark shape, and FIG. 20 shows a reflected electron signal when a rectangular beam is scanned. The mark 111 is a cross mark formed of tungsten, and the rectangular beam 112 is scanned in the direction 113 by the mark 111. The mark position is detected by using the intersection of the line 121 and the signal 122 having an intensity half the maximum value of the obtained reflected electron signal. When the hole layer of the memory integrated circuit similar to that of FIG. 10 was drawn using this method, the alignment accuracy with the lower wiring layer was improved from ± 0.07 μm of the conventional variable rectangle method to ± 0.05 μm. This contributed to the improvement of the yield of the memory integrated circuit.
As for the shape of the graphic opening having only one opening, various devices according to the needs of other circuits can be considered. In particular, it is effective in all processes of semiconductor microfabrication such as element isolation and gate manufacturing processes other than the wiring and hole processes shown in the embodiments. Further, the method of forming the graphic beam is not limited to this embodiment, and the shape, size, reduction ratio, numerical aperture, arrangement, etc. of the aperture can be arbitrarily changed. Furthermore, in the present specification, all of them are mixed with variable molding, but if the present invention is used, it is possible to draw only with a graphic opening. The removal of the variable forming function is effective as an application of the present invention in order to reduce the apparatus cost.
[0015]
(Sixth embodiment)
In this example, the mask of FIG. 21 was used. There are 21 types of collective figures. The five graphic openings 36 on the inner periphery are composed of one opening, and the 16 graphic openings (including 33) on the outer periphery are complex graphic openings. Five figures on the inner periphery were selected by the figure selection deflector by the variable rectangle deflector. Selection of the inner peripheral figure can be performed at high speed because the deflection distance is short. Since a single rectangular opening is used in the logic circuit portion, drawing is performed by frequently selecting a plurality of rectangular openings. Therefore, high-speed selection is essential. Compared with the case of providing one opening on the outer periphery, the drawing time was about ½. In FIG. 21, 35 represents a first mask image and 34 represents a 125 μm square.
As for the shape of the graphic opening having only one opening, various devices according to the needs of other circuits can be considered. In particular, it is effective in all processes of semiconductor microfabrication such as element isolation and gate manufacturing processes other than the wiring and hole processes shown in the embodiments. Further, the method of forming the graphic beam is not limited to the present embodiment, and the shape, size, reduction ratio, numerical aperture, arrangement, etc. of the opening can be arbitrarily changed. Further, in the above-described embodiments, all are mixed with variable shaping, but if the drawing pattern forming method of the present invention is used, it is possible to draw only with a graphic opening. The removal of the variable forming function is effective as an application of the present invention in order to reduce the apparatus cost.
[0016]
【The invention's effect】
As described above, by having a graphic opening having only one opening, it is possible to improve the drawing accuracy of a logic circuit that is not particularly repeated. As a result, it contributes to improvement of the yield of the integrated circuit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an electron beam drawing apparatus for a collective figure irradiation method for explaining a drawing pattern forming method of the present invention.
FIG. 2 is a mask diagram for explaining a drawing pattern forming method of the present invention.
FIG. 3 is a mask diagram having a rectangular opening for explaining the drawing pattern forming method of the present invention.
FIG. 4 is a diagram showing a deformed graphic opening for explaining the drawing pattern forming method of the present invention.
FIG. 5 is a diagram showing a mark and a rectangular beam for explaining the positioning mark detection method of the present invention.
FIG. 6 is a diagram showing reflected electron signals for explaining the positioning mark detection method of the present invention.
FIG. 7 is a configuration diagram of an electron beam lithography apparatus according to the first embodiment of the present invention.
FIG. 8 is a mask diagram according to the first embodiment of the present invention.
FIG. 9 is a drawing pattern diagram according to the first embodiment of the present invention.
FIG. 10 is a process chart of drawing pattern formation in the first embodiment of the present invention.
FIG. 11 is a mask diagram in the second embodiment of the present invention.
FIG. 12 is a drawing pattern diagram according to the second embodiment of the present invention.
FIG. 13 is a mask diagram according to a third embodiment of the present invention.
FIG. 14 is a drawing pattern diagram according to the third embodiment of the present invention.
FIG. 15 is a mask diagram according to a fourth embodiment of the present invention.
FIG. 16 is a drawing pattern diagram according to the fourth embodiment of the present invention.
FIG. 17 is a configuration diagram of an electron beam lithography apparatus according to a fifth embodiment of the present invention.
FIG. 18 is a mask diagram in the fifth embodiment of the present invention.
FIG. 19 is a diagram illustrating a positioning mark and a rectangular beam used in an electron beam lithography apparatus according to a fifth embodiment of the present invention.
FIG. 20 is a diagram showing a reflected electron signal when a positioning mark is detected in the fifth embodiment of the present invention.
FIG. 21 is a mask diagram in the sixth embodiment of the present invention.
[Explanation of symbols]
1: electron gun, 2: first mask, 3: transfer lens, 4: figure selection deflector, 5: second mask, 6: mask exchange chamber, 7: mask stage, 8: reduction lens, 9: limiting aperture, 10: focus corrector, 11: main deflector, 12: sub deflector, 13: sub sub deflector, 14: objective lens, 15: electron detector, 16: stage, 17: wafer.

Claims (4)

An electron gun,
A first mask having an opening for shaping an electron beam emitted from the electron gun;
A second mask for shaping the electron beam transmitted through the first mask;
A deflector;
An objective lens;
A stage on which a sample is placed,
The second mask includes a graphic opening for a first collective graphic irradiation method including a single rectangular opening, and a graphic opening for a second collective graphic irradiation method including a plurality of openings,
The deflector includes a first polarization direction unit for the electron beam irradiation in the figure the opening for the first batch graphic irradiation method,
And a second polarization direction unit for the electron beam irradiation in the figure the opening for the second batch graphic irradiation method,
The graphic opening for the second batch graphic irradiation method is disposed at a position farther from the center of the second mask than the graphic opening for the first batch graphic irradiation method,
Electron beam lithography apparatus characterized by being configured to select the first polarization direction unit and a second polarization direction device according to the irradiation to the first or second graphic opening. The electron beam drawing apparatus according to claim 1 ,
The electron beam drawing apparatus according to claim 1, wherein the graphic opening for the first collective graphic irradiation method and the graphic opening for the second collective graphic irradiation method are a plurality of graphic opening groups. The electron beam drawing apparatus according to claim 1 ,
An electron beam drawing apparatus comprising: means for scanning the sample with an electron beam transmitted through a graphic opening of the second mask to detect a position. The electron beam drawing apparatus according to claim 1 ,
The stage includes a beam calibration mark,
An electron beam drawing apparatus comprising: means for irradiating the beam calibration mark with an electron beam transmitted through the graphic opening of the second mask and measuring an absolute position of the electron beam.

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