JP3708910B2 - Register circuit and cryptographic operation circuit using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a register circuit and a cryptographic operation circuit that is resistant to power analysis attacks using the register circuit.
[0002]
[Prior art]
A power analysis attack (DPA: Differential Power Analysis) is known as one of attacks for extracting secret information stored in a cryptographic operation circuit. DPA refers to extracting secret information stored in the cryptographic operation circuit by observing fluctuations in power consumption during the arithmetic processing of the cryptographic operation circuit and estimating the contents of the arithmetic processing from the power consumption pattern. . More specifically, in the DPA, a plurality of input data is input to the cryptographic operation circuit, and a graph (power consumption graph) showing fluctuations in power consumption in each case is created. The secret information in the cryptographic operation circuit is estimated from the characteristics of the power consumption graph for the input data. There is a correlation between the estimated secret information and the power consumption graph. When the estimated value is correct, a large correlation value appears, and when the estimation is incorrect, the correlation value is small. Based on this principle, secret information inside the cryptographic operation circuit can be extracted using DPA.
[0003]
One of the reasons for the correlation between the power consumption graph and the secret information largely depends on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor). When an arithmetic circuit is manufactured using a CMOS device, the arithmetic circuit consumes a large amount of power when the potential of the signal line transitions due to the characteristics of the CMOS device. Due to such characteristics of the CMOS device, the power consumption of the arithmetic circuit fluctuates because the number of signal lines whose potential changes in the arithmetic circuit varies depending on the input data.
[0004]
More specifically, for example, the number of signal lines whose potential changes when processing certain input data m1 in the cryptographic operation circuit and the number of signal lines whose potential changes when processing other input data m2 are as follows. If they are different, there is a difference between the power consumption graphs PG1 and PG2 when the input data m1 and the input data m2 are processed. When the difference between the power consumption graphs PG1 and PG2 is related to secret information stored in the cryptographic operation circuit, DPA is performed on the cryptographic operation circuit to identify the secret information inside. I can do it.
[0005]
In Japanese Patent Laid-Open No. 2001-268071, a reconfigurable arithmetic circuit is used as a cryptographic arithmetic circuit in order to provide resistance (tamper resistance) to DPA, and this arithmetic circuit is functionally the same and has different internal operations. Technology that makes it difficult to identify internal secret information from the power consumption pattern by holding multiple configuration data for configuration and selectively writing these configuration data to the arithmetic circuit to update the circuit configuration Is disclosed.
[0006]
However, an arithmetic circuit such as an FPGA / PLD that can be reconfigured generally has a large hardware scale, which increases the cost of the cryptographic arithmetic circuit. Further, even if the circuit configuration of the cryptographic operation circuit is updated with the configuration data, the power consumption pattern does not change depending on the secret information inside the operation circuit. Therefore, it is not impossible for this cryptographic operation circuit to specify the internal secret information by repeating detailed analysis of the power consumption pattern, and is not necessarily sufficient in terms of tamper resistance.
[0007]
[Problems to be solved by the invention]
As described above, when the fluctuation in power consumption due to input data correlates with the secret information inside the cryptographic operation circuit and the input data, the secret information inside the cryptographic operation circuit can be extracted by DPA using the power consumption graph. End up. In the case of an attack method such as physically destroying from the outside, it is immediately known that the attack was made because the trace of the attack remains, but the internal secret information can be identified from the power consumption like DPA. In the case of a simple attack method, since it is difficult to determine whether or not an attack has been received from the appearance, it is a serious problem in terms of security.
[0008]
The cryptographic operation circuit is usually configured by using a combinational circuit composed of a plurality of logic elements for performing operations and a register circuit for holding the operation results and states. Here, the register circuit is used to hold the operation result and state of the combinational circuit as input data. The register circuit consumes more power when the data held by the input data or the secret information transits between the low level and the high level.
[0009]
Therefore, if there is a bias in the number of data transitions held in the internal registers in relation to the input data in the cryptographic operation circuit, the influence of the number of data transitions appears in the power consumption graph of the operation circuit. When a characteristic appears in the power graph, the dependency relationship between the input data and the secret information can be found, and the secret information can be obtained from the outside by the DPA.
[0010]
An object of the present invention is to provide a register circuit with constant power consumption regardless of a change in an internal state and a cryptographic operation circuit using the register circuit.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, a register circuit according to the present invention captures an original register for holding input data, that is, captures data input from a first data input line in synchronization with a clock signal. Apart from the first register that holds the data and outputs it to the first data output line, a second register is provided as a dummy register that does not contribute to holding the input data. The second register captures data input from the second data input line in synchronization with the clock signal, holds the captured data, and outputs it to the second data output line. Further, a monitoring circuit is provided for monitoring the data values on the first data input line and the data output line in synchronization with the clock signal, and generating a control signal when the two data values coincide with each other. The value of the data held in the register is inverted.
[0012]
More specifically, for example, an inverting element that inverts data output from the second data output line and outputs the inverted data to the second data input line is provided, and data values on the first data input line and the data output line are provided. When the two coincide with each other, the second register is set in the write enable state by the control signal generated from the monitoring circuit, so that the value of the data held in the second register is inverted based on the output of the inverting element.
[0013]
As described above, the register circuit according to the present invention always inverts one of the data values held in the first and second registers in synchronization with the clock signal. The power consumption is constant regardless of the transition of the data value. Therefore, when this register circuit is used as a cryptographic operation circuit and the operation result and state of the combinational circuit are held as input data, a change in power consumption is less likely to be observed externally and resistance to DPA is improved.
[0014]
A cryptographic operation circuit according to the present invention includes the register circuit and the combinational circuit described above.
[0015]
According to another aspect, a cryptographic operation circuit according to the present invention includes at least one first logic element related to cryptographic operation, at least one second logic element not related to cryptographic operation, and a second logic element. Means for operating in a complementary manner with respect to the first logic element (for example, causing the internal state of the second logic element to make a complementary transition with respect to the internal state of the first logic element). It is desirable that the first and second logic elements have substantially the same power consumption when their internal states transition.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a partial configuration of the cryptographic operation circuit. Data input from the data input line 1 is held by the register circuit 2 and input to the combinational circuit 4 via the data output line 3. The operation result of the combinational circuit 4 is input to another register circuit 6 through the data output line 5.
[0017]
When the data value on the data input line 1 changes, the data value held in the register circuit 2 changes in synchronization with the clock signal. In the next clock signal, the data value on the data output line 3 transits, and the data value held in the register circuit 6 transits through the data output line 5 of the combinational circuit 4.
[0018]
At this time, in the transition of the data value held by the register circuit 2 and the register circuit 6, if the number of transitions is biased in relation to the input data and the secret information, the influence of the bias is expressed in the form of fluctuation of power consumption from the outside. It becomes possible to observe. If the power consumption varies depending on the value of the input data, it becomes possible to extract secret information based on the power consumption graph.
[0019]
FIG. 2 shows a configuration of a register circuit according to an embodiment of the present invention in which power consumption is constant so that the influence of secret information and input data is eliminated on the number of transitions of data values to be held. In this register circuit, corresponding to a main register (first register) 11 that holds 1-bit data, a monitoring circuit 12, a dummy register 13 (second register) that holds 1-bit data, and a NOT element 14 is provided.
[0020]
It is desirable that the main register 11 and the dummy register 13 have, for example, the same configuration, that is, the same power consumption when the internal state (held data value) transitions. In this embodiment, the power consumption of the register circuit is kept constant by operating the main register 11 and the dummy register 13 complementarily in synchronization with the clock signal CLK, for example, as follows.
[0021]
Data input to the data input line 21 is taken into the main register 11 in synchronization with the clock signal CLK and held by the main register 11. The data held in the main register 11 is output to the data output line 22.
The monitoring circuit 12 monitors the data values on the data input line 21 and the main register data output line 22 connected to the input terminal and the output terminal of the main register 11, respectively, so that the data value held by the main register 11 is maintained. Whether or not there is a transition is determined. That is, if the data values on the data input line 21 and the data output line 22 match, the monitoring circuit 12 does not change the data value held by the main register 11 and the data input line 21 and the data output line 22 If the upper data value does not match, it is determined that the data value held in the main register 11 has changed.
[0022]
FIG. 3 shows an example of the monitoring circuit 12. The monitoring circuit 12 is realized by an XOR (exclusive OR) arithmetic element 30. When the data value I1 on the data input line 21 and the data value I2 on the data output line 22 do not match, the output data value O of the XOR operation element 30 is “1”. On the other hand, when the data value I1 matches the data value I2, the output data value O of the XOR operation element 30 is “0”. In this way, a mismatch between the data values I1 and I2 on the data input line 21 and the data output line 22 can be detected.
[0023]
The output terminal of the monitoring circuit 12 is connected to the write enable line 23 of the dummy register 13. The data output line 24 of the dummy register 12 is connected to the input terminal of the NOT element 14, and the output terminal of the NOT element 14 is connected to the data input line 25 of the dummy register 12. The dummy register 13 captures and holds the data value on the data input line 25, that is, the output data value of the NOT element 14 in synchronization with the same clock signal CLK supplied to the main register 11.
[0024]
Next, the operation of the register circuit shown in FIG. 2 will be described.
First, when the data values on the data input line 21 connected to the input terminal of the main register 11 and the data output line 22 connected to the output terminal are the same, the output signal of the monitoring circuit 12 becomes “0”. That is, the write enable signal on the write enable line 23 is activated. When the write enable signal is activated, the dummy register 13 captures the data value on the data input line 25 at the rising timing of the clock signal CLK. Since the data value on the data input line 25 is a value obtained by inverting the data value on the data output line 24 connected to the output terminal of the dummy register 13 by the NOT element 14, the data value held by the dummy register 13 is inverted. To do. At this time, since the data values on the data input line 21 and the data output line 22 of the main register 11 are the same, the data held in the main register 11 does not change.
[0025]
Next, when the data values on the data input line 21 and the data output line 22 of the main register 11 are different, the output of the monitoring circuit 12 is “1”. That is, in this case, since the write enable signal on the write enable line 23 is not activated, the dummy register 13 continues to hold the original data value. On the other hand, the main register 11 captures the data value on the data input line 21 at the rising timing of the clock signal CLK, so that the stored data value is inverted and the data value on the data output line 22 changes. .
[0026]
As described above, in the register circuit of the present embodiment, the data values on the input data line 21 and the data output line 22 connected to the main register 11 are monitored by the monitoring circuit 12, and when these data values match, The data value held in the dummy register 13 is inverted by taking the output data value of the NOT element 14 into the dummy register 13 in synchronization with the signal CLK. On the other hand, when the data values on the input data line 21 and the data output line 22 do not match, the data value held in the main register 11 is inverted in synchronization with the clock signal CLK, but held in the dummy register 13. The existing data value is not inverted and keeps its original value.
[0027]
As described above, every time the clock signal CLK rises, one of the data values held in the main register 11 and the dummy register 12 is always inverted. Therefore, when the register circuit of this embodiment is applied to the cryptographic operation circuit as shown in FIG. 1, the number of transitions of the data value of the register circuit in the operation circuit is always during the operation regardless of the operation result of the combinational circuit. Can be kept constant.
[0028]
That is, by configuring all the register circuits in the cryptographic operation circuit as shown in FIG. 1 as shown in FIG. 2, transition of the stored data value occurs without depending on input data or secret information. It is possible to always keep the total number of register circuits (the number of data value transitions of the register circuit group in the cryptographic operation circuit) constant. As a result, it is possible to make the power consumption of the cryptographic operation circuit constant without depending on the input data and secret information, and it is possible to realize a cryptographic operation circuit having effective resistance against DPA.
[0029]
In the present embodiment, it is more desirable that the power consumption of the monitoring circuit 12 itself be kept constant. This is because there is a possibility that a correlation occurs between the internal state in the cryptographic operation circuit and the power consumption during calculation due to the influence of the power consumption of the monitoring circuit 12. Hereinafter, an example of a technique for making the monitoring circuit 12 have a constant power consumption will be described.
[0030]
FIG. 4 shows a circuit example of the XOR operation element 30 shown in FIG. 3 effective as the monitoring circuit 12. Between the first power line 40 on the high potential side and the ground 50 which is the second power line on the low potential side, the nMOS transistor 41 which is the first MOS switch and the pMOS transistor which is the second MOS switch The logic operation unit 45 is connected through 42 in series.
[0031]
The logical operation unit 45 is configured by a parallel circuit of a series circuit of two nMOS transistors 46 and 48 and a series circuit of two pMOS transistors 47 and 49. The drain terminals of the transistors 46 and 47 are commonly connected to the source terminal of the transistor 42. The source terminals of the transistors 46 and 47 are connected to the drain terminals of the transistors 48 and 49, respectively. The source terminals of the transistors 48 and 49 are connected to the ground 50. The gate terminals of the transistors 46 and 47 are commonly connected to the first input signal line 53, and the gate terminals of the transistors 48 and 49 are commonly connected to the second input signal line 54.
[0032]
The logical operation result of the logical operation unit 45 is output to the output signal line 55, and the logical operation result is held as a charge in the capacitor 44 connected between the output signal line 55 and the ground 50. The capacitor 44 is formed as an element, realized by a parasitic capacitance of the output signal line 55, or a combined capacitance of the capacitor as the element and the parasitic capacitance is used.
[0033]
On the other hand, the gate terminals of the transistors 41 and 42 are connected to a charge control signal line 51 which is a first control signal line. The output signal line 55 is connected to a connection point between the transistor 41 and the transistor 42. An nMOS transistor 43 as a third MOS switch is connected between the output signal line 55 and the ground 50, that is, in parallel with the capacitor 44. The gate terminal of the transistor 43 is connected to a discharge control signal line 52 that is a second control signal line. The transistors 41, 42, 43, the charge control signal line 51, and the discharge control signal line 52 form a charge / discharge circuit, and the capacitor 44 is charged / discharged by this charge / discharge circuit.
[0034]
The timing control circuit 26 controls the potentials of the charge control signal line 11 and the discharge control signal line 12 so as to satisfy the conditions described below in accordance with a clock signal CLK that is a synchronization signal for synchronizing the entire cryptographic operation circuit. To do.
[0035]
The charge control signal line 51 is at the “H” level for the time required to charge the capacitor 44, and the setup time of the dummy register 13 that receives the output signal line 55 of the logic element as the write enable signal 23, and the input Considering a period during which the potential of the output signal line 55 is stabilized based on the calculation results of the signal lines 53 and 54, the timing control circuit 56 controls the transition to the “L” level before the rising edge of the clock signal CLK. .
[0036]
The discharge control signal line 52 is at the “H” level for a period required to discharge the charge of the capacitor 44, and the hold time of a storage element such as a flip-flop (not shown) that receives the output signal 55 of the logic element. After satisfying the above, the timing control circuit 56 controls the transition to “H” level.
[0037]
Further, the timing control circuit 56 sets the timing of the transition to the “H” level of the charge control signal line 51 or the “L” level and the period of the “H” level of the discharge control signal line 52 or the “H” level. In addition to the transition timing, the charge control signal line 51 and the discharge control signal line 52 are controlled so that the “H” level periods of the charge control signal line 51 and the discharge control signal line 52 do not overlap.
[0038]
Here, the correspondence between FIG. 4 and FIGS. 2 and 3 will be described. The input signal line 51 corresponds to the data input line 21, the input signal line 52 corresponds to the data output line 22, and the output signal line 55 corresponds to This corresponds to the write enable line 23.
[0039]
Next, the operation of the XOR operation element according to the present embodiment will be described using the time chart shown in FIG. FIG. 5 shows transitions of the clock signal CLK, the potentials φ1 and φ2 of the charge control signal line 51 and the discharge control signal line 52, the potentials I1 and I2 of the input signal lines 53 and 54, and the potential Vo of the output signal line 55. . The potentials I1 and I2 of the input signal lines 51 and 52 are assumed to transition in synchronization with the clock signal CLK. 5, T1, T2, T3, T4,... Indicate unit operation periods in which the XOR operation element periodically performs charge / discharge operations according to the clock signal CLK.
[0040]
[Period T1] First, as shown in the period T1 in FIG. 5, in order to charge the capacitor 44 connected to the output signal line 55 first, the charge control signal line 51 of the clock signal CLK rises at time t0. The potential φ1 is set to a high level (“H” level). As a result, the transistor 41 becomes conductive, a current flows from the power supply line 40 to the capacitor 44 via the transistor 41, and the capacitor 44 is charged. Therefore, the potential Vo of the output signal line 55 temporarily becomes “H” level.
[0041]
If the charging / discharging circuit is allowed to pass charges from the capacitor 44 to the logic operation unit 45 during charging of the capacitor 44, depending on the potentials of the input signal lines 53 and 54, the power supply line There is a possibility of a short circuit between 40 and the ground 50. In order to prevent such a short circuit between the power supply line 40 and the ground 50, in the present embodiment, the transistor 42 is inserted into the logic operation unit 45 side in the charge / discharge circuit unit, and the transistor 42 is not connected during the charging of the capacitor 44. By setting the conductive state, the charge of the capacitor 44 is prevented from flowing to the logic operation unit 45.
[0042]
Next, after the capacitor 44 is charged at time t1, the potential φ1 of the charge control signal line 51 is set to a low level (“L” level). As a result, the transistor 41 is turned off, and no current flows from the power supply line 40. On the other hand, when the potential φ1 of the charge control signal line 51 is set to the “L” level, the transistor 42 becomes conductive, so that the charge of the capacitor 44 can flow to the logic operation unit 45 via the transistor 42.
[0043]
In the logic operation unit 45, one of the nMOS transistor 46 and the pMOS transistor 47 is turned on and the other is turned off according to the potential I1 of the input signal line 53. Similarly, one of the nMOS transistor 48 and the pMOS transistor 49 is turned on and the other is turned off according to the potential I2 of the input signal line 54. When both of the two nMOS transistors 46 and 48 are in a conducting state or both of the two pMOS transistors 47 and 49 are in a conducting state, the charge of the capacitor 44 can flow through the logic operation unit 45 to the ground 50. is there. At other times, that is, one of the two nMOS transistors 46 and 48 is conductive, the other is non-conductive, and one of the two pMOS transistors 47 and 49 is conductive and the other is non-conductive. Sometimes, the charge of the capacitor 44 cannot flow into the ground 20.
[0044]
When the logic operation unit 45 cannot flow the charge of the capacitor 44 to the ground 50 in accordance with the potentials I1 and I2 of the input signal lines 53 and 54, the charge of the capacitor 44 is held. The potential Vo becomes “H” level. On the other hand, in a state where the logic operation unit 45 can flow the charge of the capacitor 44 to the ground 50, the charge of the capacitor 44 passes through the logic operation unit 45 and flows into the ground 50, thereby causing the potential Vo of the output signal line 55. Becomes “L” level. Thereafter, the potential Vo of the output signal line 55 at the time t2 when the clock signal CLK rises becomes the output value of the XOR operation element.
[0045]
Specifically, in the example of FIG. 5, the potential I1 of the input signal line 53 at the time t1 is “H” level, and the potential I2 of the input signal line 54 is “L” level. At this time, in the logic operation unit 45, the nMOS transistor 46 and the pMOS transistor 49 are turned on, and the nMOS transistor 48 and the pMOS transistor 47 are turned off. Therefore, since the charge of the capacitor 44 cannot pass through the logic operation unit 45, the charge of the capacitor 44 is retained, and the potential Vo of the output signal line 55 when the clock signal CLK rises at time t2 is at “H” level. It becomes. That is, when I1 = "H" and I2 = "L", the logical operation result is Vo = "H", which satisfies the operation of the XOR operation element.
[0046]
Next, as described above, after the clock signal CLK rises at time t2, the potential φ2 of the discharge control signal line 52 is set to the “H” level at time t3. As a result, the nMOS transistor 43 becomes conductive, the charge of the capacitor 44 is discharged to the ground 50 through the nMOS transistor 43, and the potential Vo of the output signal line 55 becomes “L” level.
[0047]
[Period T2] On the other hand, as shown in period T2 in FIG. 5, the potentials I1 and I2 of the input signal lines 53 and 54 after the capacitor 44 is charged at the falling time of the clock signal CLK are I1 = “H When “, I2 =“ H ”, since both the nMOS transistors 46 and 48 are in a conductive state (both pMOS transistors 47 and 49 are in a nonconductive state), the charge of the capacitor 44 is transferred to the ground 50 through the nMOS transistors 46 and 48. The electric potential Vo of the output signal line 55 when the clock signal CLK rises next time becomes “L” level. That is, when I1 = "H" and I2 = "H", the logical operation result is Vo = "L", which satisfies the operation of the XOR operation element.
[0048]
[Period T3] Similarly, as shown in period T3 in FIG. 5, the potentials I1 and I2 of the input signal lines 53 and 54 after the capacitor 44 is charged at the falling time of the clock signal CLK are I1 = “L When “, I2 =“ L ”, the pMOS transistors 47 and 49 are both conductive (the nMOS transistors 46 and 48 are both non-conductive), so that the charge of the capacitor 44 is transferred to the ground 50 through the pMOS transistors 47 and 49. The potential Vo of the output signal line 55 when the clock signal CLK rises next time becomes “L” level. That is, similarly to the case of I1 = “H” and I2 = “H”, the logical operation result when I1 = “L” and I2 = “L” is Vo = “L”, and the operation of the XOR operation element is Fulfill.
[0049]
Also in these cases, the potential φ2 of the discharge control signal line 52 is set to the “H” level next, and the nMOS transistor 43 becomes conductive. However, since the charge of the capacitor 44 has already been discharged, the nMOS transistor 43 becomes conductive. Even if it becomes a state, it is not newly discharged to the ground 50.
[0050]
[Period T4] Next, as shown in period T4 in FIG. 5, the potentials I1 and I2 of the input signal lines 53 and 54 after the capacitor 14 is charged at the falling time of the clock signal CLK are I1 = " When L ”and I2 =“ H ”, the nMOS transistor 46 and the pMOS transistor 49 are in a non-conductive state and the nMOS transistor 48 and the pMOS transistor 47 are in a conductive state, contrary to the case of the period T1. The charge of the capacitor 44 cannot pass through the logic operation unit 45, and the charge of the capacitor 44 is retained. Therefore, the potential Vo of the output signal line 55 when the clock signal CLK rises next becomes “H” level. That is, when I1 = "L" and I2 = "H", the logical operation result is Vo = "H", which satisfies the operation of the XOR operation element.
[0051]
Next, when the potential φ2 of the discharge control signal line 52 is set to the “H” level, the nMOS transistor 43 becomes conductive, and the charge of the capacitor 44 is discharged to the ground 50 through the nMOS transistor 43. The potential Vo of the signal line 55 becomes “L” level.
[0052]
As described above, when I1 = "H" and I2 = "L" (period T1) and when I1 = "L" and I2 = "H" (period T4), the logical operation results are all Vo = "H" When I1 = "H" and I2 = "H" (period T2) and when I1 = "L" and I2 = "L" (period T3), the logical operation results are Vo = "L"", And the XOR operation becomes possible.
[0053]
As described above, the charging / discharging operation of the capacitor 44 by the charge control signal line 51 and the discharge control signal line 52 is repeatedly performed in synchronization with the clock signal CLK. That is, in the XOR operation element of this embodiment, in each period (T1, T2, T3, T4,...) From the rising time of the potential φ1 of the charge control signal line 51 to the rising time of the potential φ2 of the discharge control signal line 52. Regardless of the transition state of the potentials I1 and I2 of the input signal lines 53 and 54, that is, the capacitor 44 always performs one charge and one discharge including charging and discharging of the capacitor 44 by I1 and I2, so Consume a certain amount of power.
4 is useful as the monitoring circuit 12 shown in FIG. 2 because the power consumption is always constant. That is, when the register circuit using the monitoring circuit 12 is applied to all the register circuits in the cryptographic operation circuit, the power consumption of all the register circuits in the cryptographic operation circuit is always constant, Power consumption fluctuations are eliminated. Therefore, the cryptographic operation circuit can greatly contribute to improving the resistance to DPA.
[0054]
【The invention's effect】
As described above, according to the present invention, the power consumption is biased by the transition of the data value always held in the register without depending on the input data and the secret information during the calculation and the register circuit with constant power consumption. It is possible to realize a register circuit having constant power consumption and a cryptographic operation circuit having resistance against DPA.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a cryptographic operation circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a register circuit according to an embodiment of the present invention.
3 is a block diagram showing an example of a monitoring circuit in FIG.
4 is a circuit diagram showing a specific configuration when the power consumption of the monitoring circuit in FIG. 2 is reduced;
FIG. 5 is a timing chart showing the operation of the monitoring circuit shown in FIG.
[Explanation of symbols]
1 ... Data input line
2, 6 ... register circuit
4 ... Combination circuit
3, 5 ... Data output line
11: Main register (first register)
12 ... Monitoring circuit
13: Dummy register (second register)
14 ... NOT element (inversion element)
21: First data input line
22: First data output line
23: Write enable line
24: Second data output line
25: First data input line
30 ... XOR (exclusive OR) arithmetic element
40 ... power line (first power line)
41 ... nMOS transistor (first MOS switch)
42 ... pMOS transistor (second MOS switch)
43 ... nMOS transistor (third MOS switch)
44 ... Capacitor
45. Logic operation section
46, 48 ... nMOS transistors
47, 49 ... pMOS transistors
50 ... Ground (second power line)
51 ... Charging control signal line (first control signal line)
52 ... Discharge control signal line (second control signal line)
53. First input signal line
54 ... Second input signal line
55 ... Output signal line
56 ... Timing control circuit

Claims (5)

A first data input line and a data output line;
A first register that captures data input from the first data input line in synchronization with a clock signal, holds the captured data, and outputs the data to the first data output line;
A second data input line and a data output line;
A second register that captures data input from the second data input line in synchronization with the clock signal, holds the captured data, and outputs the data to the second data output line;
The data value on the first data input line and the data output line is monitored in synchronization with the clock signal, and a predetermined control signal is generated when the two data values coincide with each other, and the data held in the second register And a monitoring circuit for inverting the value of.   And an inverting element that inverts data output from the second data output line and outputs the inverted data to the second data input line, and the monitoring circuit includes data on the first data input line and the data output line. 2. The register circuit according to claim 1, wherein when the values coincide with each other, the control signal is generated to put the second register in a write enable state, thereby inverting the value of data held in the second register.   The monitoring circuit performs an exclusive OR operation on the data on the first data input line and the data output line, and outputs an operation result to the output signal line as the control signal; and the output signal line Connected to the capacitor for holding the calculation result as a charge, and connected to the output signal line, and the capacitor is connected to the first data input line and the data output line at a constant cycle regardless of charge / discharge accompanying data transition. The register circuit according to claim 1, further comprising a charge / discharge circuit for charging / discharging. The monitoring circuit is
First and second power supply lines having different power supply potentials;
Inserted between the first power supply line and the second power supply line, performs an exclusive OR operation with the data on the first data input line and the data output line as input, and outputs the operation result to the control signal An arithmetic unit including a plurality of MOS transistors that output to the output signal line as
A capacitor that is inserted between the output signal line and the second power supply line and holds a calculation result of the calculation unit as a charge;
First and second control signal lines to which a potential of either the first level or the second level is selectively applied;
The first control signal line is connected between the first power supply line and the output signal line, is turned on by the first level potential of the first control signal line, and is not turned on by the second level potential of the first control signal line. A first MOS switch that is rendered conductive;
It is connected between the output signal line and the arithmetic unit, and is turned off by a first level potential of the first control signal line, and turned on by a second level potential of the first control signal line. A second MOS switch to be
A third circuit connected in parallel to the capacitor and made conductive by the first level potential of the second control signal line and made non-conductive by the second level potential of the second control signal line. MOS switch,
In order to charge and discharge the capacitor at a constant period regardless of charging and discharging accompanying data transition on the first data input line and the data output line, the first potential of each of the first and second control signal lines is set. 2. The control circuit according to claim 1, further comprising: a control circuit that periodically transitions the potentials of the first and second control signal lines between the first level and the second level so that periods of one level do not overlap each other. Register circuit. 5. A cryptographic operation circuit including at least one register circuit according to claim 1 and a combinational circuit.

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