JP3705459B2 - Digital image signal recording apparatus and image signal recording / reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital image signal recording apparatus and a recording / reproducing apparatus, and more particularly to an apparatus for recording / reproducing image signals having different definition levels.
[0002]
[Prior art]
A standard called “DVC” (hereinafter referred to as “DVC standard”) has been proposed as a standard for a digital VTR (video tape recorder) that records and compresses image data (for example, National Technical Report Vol. 41 No. 41). 2 Apr. 1995, pages 48-55). The DVC standard includes an SD standard for recording a normal-resolution image signal (SD signal) at a current broadcast level and a standard for recording a high-definition image signal (HD signal). An outline of the HD standard for recording HD signals will be described below.
[0003]
In the HD standard, as shown in FIG. 11, the luminance signal is horizontal 1008 pixels, the number of vertical lines is 1024 (1024 pixels), and the two color difference signals (Cr, Cb) are horizontal 336 pixels and the number of vertical lines is 512 (512). This is a standard for recording and reproducing an image signal in which one frame is composed of pixels. One frame is composed of two fields obtained by interlaced scanning. According to this standard, these effective pixel data are blocked and a DCT (Discrete Cosine Transform) operation is performed. Specifically, the block for DCT calculation (hereinafter referred to as “DCT block”) is 8 horizontal pixels × 8 vertical pixels for one frame pixel for each of the luminance (Y) signal and the color difference (Cb, Cr) signal. Separated by Then, as shown in FIG. 12, an 8DCT block including six DCT blocks of Y signal corresponding to the same area at the same position on the screen and one DCT block of Cb signal and Cr signal is called a “macro block”. Call it.
[0004]
The DCT calculation includes a stationary mode in which 8 × 8 DCT is performed by 8 horizontal pixels × vertical 8 pixels in a frame unit, and 8 × 4 DCT is performed in 8 horizontal pixels × vertical 4 pixels in a field unit. A motion mode that takes the sum and difference of each DCT coefficient is provided, and can be switched adaptively during encoding. This switching is performed so that the motion is detected based on the difference between the fields, and the motion mode is selected when a predetermined motion or more is detected.
[0005]
The DCT coefficient obtained by the DCT calculation is selected by selecting a quantization table so that the amount of data after quantization and variable length coding is equal to or less than a predetermined value and closest to the predetermined value. It becomes.
The data after quantization and variable length coding is formatted on a macroblock basis and recorded on the magnetic tape in the form of a sync block to which a SYNC word, an ID code, and a parity word for error correction are added. The format on the magnetic tape is as shown in FIG.
[0006]
[Problems to be solved by the invention]
LSIs (Large Scale Integrated Circuits) compliant with the HD standard are usually used for recording and reproduction of HD signals, but as they are, progressively scanned image signals with lower definition (for example, EDTV (Enhanced Definition TV)) Signal) cannot be recorded or played back.
[0007]
The present invention has been made paying attention to this point, and by adding a few circuits to the LSI for HD signals, it is possible to record a progressively scanned image signal with a lower definition, and more finely. It is an object of the present invention to provide a digital image signal recording apparatus capable of improving the compression efficiency when a low-speed progressive scanning image signal is compressed and recorded.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention comprises means described in 1) to 4) below.
That is,
1) An image signal having a first definition based on the DVC standard in which an image signal of one frame is formed by two fields obtained by interlaced scanning, and a second definition lower than the first definition is recorded. A digital image signal recording apparatus adapted to convert and record the image signal of the first definition when the image signal of progressive scanning is received,
Converting means for converting the one-frame image signal into the first-definition one-field image signal and outputting the image signal when the second-definition progressive scan one-frame image signal is received; ,
Recording means for performing a predetermined process on the output signal of the conversion means and recording it on a recording medium,
When recording the first definition image signal in which one frame of image signal is formed by two fields obtained by interlaced scanning , the recording means performs orthogonal transform on a frame basis in the stationary mode and each field. What converts the motion mode in which orthogonal transformation is performed and the difference component and sum component of orthogonal transformation coefficients of two consecutive fields are output at the time of encoding, is converted to 2 of the transformed first definition. When an image signal consisting of two fields arrives, it has an image information compression means for compressing the image information while fixing it to the motion mode , and the conversion means comprises two consecutive image signals of the second definition. one of the image signal corresponding to the same position of the frame, the digital image signal recording apparatus characterized by constituting said predetermined pixel block of the first resolution image signal
2) The digital image signal recording apparatus according to claim 1, wherein the conversion means performs the conversion by inserting dummy data having the same value in the predetermined pixel block unit.
3) When a macro block is configured by n the predetermined pixel blocks of luminance signals (n is an integer of 2 or more) and m of the predetermined pixel blocks of two color difference signals (m is an integer of 1 or more),
According to the ratio of the first definition and the second definition, k predetermined pixel blocks (k is an integer satisfying 1 ≦ k <n) among the predetermined pixel blocks of the n luminance signals. The digital data according to claim 2, wherein the pixel block of the dummy data is used as the pixel block of the dummy data, the pixel block of the dummy data is arranged after the predetermined pixel block of the luminance signal in units of the macroblock, and the conversion is performed. Image signal recording device.
4) Recording and reproducing an image signal of the first definition based on the DVC standard in which an image signal of one frame is constituted by two fields obtained by interlaced scanning, and a second definition lower than the first definition. A digital image signal recording / reproducing apparatus that converts the image signal into the first definition image signal and records / reproduces the image signal when the progressive scanning image signal is received;
Converting means for converting the one-frame image signal into the first-definition one-field image signal and outputting the image signal when the second-definition progressive scan one-frame image signal is received; ,
Recording means for performing a predetermined process on the output signal of the conversion means and recording the recording signal on a recording medium;
Reproducing means for reproducing a signal recorded on the recording medium, performing a predetermined reproduction process, and outputting the reproduction signal;
Reproduction conversion means for converting the reproduction output signal into the image signal of the second definition and outputting it,
When recording the first definition image signal in which one frame of image signal is formed by two fields obtained by interlaced scanning , the recording means performs orthogonal transform on a frame basis in the stationary mode and each field. What converts the motion mode in which orthogonal transformation is performed and the difference component and sum component of orthogonal transformation coefficients of two consecutive fields are output at the time of encoding, is converted to 2 of the transformed first definition. When an image signal consisting of two fields arrives, it has an image information compression means for compressing the image information while fixing it to the motion mode , and the conversion means comprises two consecutive image signals of the second definition. the image signal corresponding to the same position of the one frame digital image signal recording and reproducing, characterized in that configuring the predetermined pixel block of the first resolution image signal Location.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing the configuration of a digital image signal recording / reproducing apparatus according to an embodiment of the present invention. This system includes an image signal switching processing unit 1 and an image signal recording / reproducing unit 2. An image signal having a lower definition than the HD signal (hereinafter referred to as “ED signal”) input to the image signal switching processing unit 1 is a sequential scanning signal composed of a Y signal and Cr, Cb signals, and Y constituting one frame. The signals are 712 pixels in the horizontal direction and 480 lines in the vertical direction, and the Cr and Cb signals are 356 pixels in the horizontal direction and 240 lines in the vertical direction. One frame of this signal is processed in 1/60 second.
[0017]
The image signal switching processing unit 1 includes an input terminal 11 to which a digitized HD signal is input, an input terminal 12 to which a digitized ED signal is input, and an output terminal 19 to which a reproduced ED signal is output. An output terminal 20 for outputting the reproduced HD signal, first and second switch circuits 13 and 14 for switching the HD signal and the ED signal, and a frame memory 15 for storing the ED signal in units of frames. The main components are a dummy data processing circuit 16 for inserting / removing dummy data and an address control circuit 17 for controlling read / write addresses of the frame memory 15.
[0018]
As shown in FIG. 2, the dummy data processing circuit 16 includes, for example, a dummy data generation circuit 101 that generates dummy data whose values are all “0”, a switch 102 that is used to insert dummy data during recording, It consists of a switch 103 that is sometimes used to remove dummy data. A switch control signal is supplied from the address control circuit 17 to the switches 102 and 103, and dummy data is inserted / removed as will be described later.
[0019]
As shown in FIG. 11, the Y signal of the HD signal has 1008 effective pixels in the horizontal direction and the effective line number in the vertical direction is a frame (hereinafter, the HD signal frame is referred to as an “HD frame”. The number of frames is 1024 within an “ED frame”, and the Cr and Cb signals are 336 pixels in the horizontal direction and 512 in the vertical direction. One field of the HD signal is processed in 1/60 seconds, and one frame is processed in 1/30 seconds. In the present embodiment, the ED signal is a sequential scanning signal composed of a Y signal and Cr, Cb signals, the Y signal is 712 pixels in the horizontal direction, 480 pixels in the vertical direction, and the Cr and Cb signals are 356 pixels in the horizontal direction. There are 240 in the vertical direction. One frame of this signal is processed in 1/60 second.
[0020]
The input ED signal is supplied to the frame memory 15, and ED signals for one ED frame are stored in the frame memory 15. The address control circuit 17 controls the read address of the frame memory 15 as will be described later, and rearranges the pixels of the ED signal. The signal read from the frame memory 15 is supplied to the first switch circuit 13 via the dummy data processing circuit 16. The first switch circuit 13 switches between the HD signal and the ED signal in which the pixels are rearranged, and supplies the switched signal to the blocking circuit 21 of the image signal recording / reproducing unit 2. In the present embodiment, the first switch circuit 13 in FIG. 1 is switched when the user selects recording of the HD signal or recording of the ED signal.
[0021]
In this embodiment, the image signal recording / reproducing unit 2 is composed of a VTR conforming to the DVC standard for HD signals, and is hereinafter referred to as a “VTR unit 2”. The image signal recording system of the VTR section 2 performs a blocking circuit 21 that performs blocking for DCT operation, a DCT circuit 22 that performs DCT operation, a quantization circuit 23 that performs quantization, and variable length coding. A VLC (Variable Length Coding) circuit 24, an auxiliary information writing circuit 25 for writing information to a subcode sector, adding video AUX data, and the like, and an error correction coding circuit 26 for adding a parity bit for error correction And a sync block synthesizing / recording / modulating circuit 27 for synthesizing sync blocks and performing modulation for recording on the magnetic tape, and a magnetic head 28 for recording on the magnetic tape 41 as main components. The system includes a magnetic head 28 for reproducing from the magnetic tape 41, and a SYNC detection reproducing demodulation circuit for detecting and demodulating the sync block. Path 29, error correction decoding circuit 30 that performs error correction based on the information of the parity bit, auxiliary information reading circuit 31 that reads data of subcode sectors, video AUX data, and the like, and variable length decoding The main components are a VLD (Variable Length Decoding) circuit 32, an inverse quantization circuit 33 that performs inverse quantization, an inverse DCT circuit 34 that performs inverse DCT operation, and a pixel rearrangement circuit 35 that performs pixel rearrangement. To do.
[0022]
The output signal of the pixel rearrangement circuit 35 of the VTR unit 2 is input to the second switch circuit 14 of the image signal switching processing unit 1. When the reproduction signal is an HD signal, the second switch circuit 14 outputs it to the HD signal output terminal 20 side, and when it is an ED signal, it outputs it to the frame memory 15 via the dummy data processing circuit 16. When reproducing the ED signal, the address control circuit 17 controls the write address of the frame memory 15 so that the arrangement of the pixels rearranged at the time of recording is restored, and the image for one ED frame is reconstructed. The read address is controlled so that the pixel data is output in the order of the original ED signal.
[0023]
Next, a conversion method during recording of the ED signal will be described.
The input ED signal is stored in the frame memory 15 as an image signal of 1 frame in 1/60 second, and the same value is obtained by the read address control of the frame memory 15 and the switching control of the switch circuit 102 of the dummy data processing circuit. While inserting dummy data (for example, blank data), it is converted into an image signal corresponding to one field of the HD signal. Specifically, horizontal 712 pixels × vertical 480 pixels of the luminance signal are converted as follows.
[0024]
1) First, an area A of horizontal 672 pixels × vertical 480 pixels shown in FIG. 4A is read, and dummy data processing circuit 16 performs dummy processing at a ratio of 8 pixels of dummy data to 16 pixels of read data of frame memory 15. Data is inserted and converted into data of horizontal 1008 pixels × vertical 480 pixels as shown in FIG. In this figure, hatched areas are dummy data areas. For example, dummy data is inserted by switching the switch circuit 102 of the dummy data processing circuit 16 to the period terminal a side corresponding to 16 pixels and the subsequent period terminal b side corresponding to 8 pixels as shown in FIG. Repeat this step.
[0025]
2) Regarding the region B of horizontal 40 pixels × vertical 480 pixels in FIG. 4A, as shown in FIG. 5, a region B1 of horizontal 32 pixels × vertical 480 pixels and a region B2 of horizontal 8 pixels × vertical 480 pixels The data in the frame memory 15 is read out as follows. 5, L1, L8,... Indicate the line numbers in the vertical direction, and the numbers in each line indicate the reading order. That is, the line L1 in the area B1, the line L17 in the area B1, the line L1 in the area B2, the line L17 in the area B2, the line L2 in the area B1, the line L18 in the area B1, the line L2 in the area B2, and the line L18 in the area B2. After reading in order and reading to the line L24 in the area B2, the process proceeds to the line L33 in the area B1, and the same reading process is repeated. After reading up to the line L256 (not shown) in the area B1 (that is, 672 pixels), the process returns to the line L9 in the area B1 and the same reading process (1 ′ → 2 ′ → 3 ′...) Is repeated. Also in this case, dummy data is inserted in the same manner as in 1) above. In this way, the pixel data in the region B is converted into pixel data having a horizontal direction of 1008 pixels.
[0026]
When this conversion is viewed in units of DCT blocks, pixel data of 5 blocks in the horizontal direction (32 pixels + 8 pixels) as shown in FIG. 6A is converted into 126 blocks (1008 pixels in the horizontal direction as shown in FIG. 6B). ) Pixel data. That is, by performing the read address control as shown in 2) above, the vertical positional relationship between the blocks B1, B2, etc. and the blocks B1 ′, B2 ′, etc. can be maintained.
[0027]
Through the above processing, the pixel data of the luminance signal of one frame of the ED signal is converted into the pixel data of the luminance signal corresponding to one field of the HD signal. Since the number of pixels in one field of the HD signal (1008 × 512) is slightly larger than the number of pixels in one frame of the ED signal (712 × 480), dummy data is inserted in the empty area.
[0028]
Next, the conversion of the color difference signal will be described.
1) Since the color difference signal of the ED signal is horizontal 356 pixels × vertical 240 pixels as shown in FIG. 7, first, a region C of horizontal 336 pixels × vertical 240 pixels in FIG. In the case of a color difference signal, no dummy data is inserted.
[0029]
2) Next, the area D in FIG. 7 is divided into an area D1 of horizontal 16 pixels × vertical 240 pixels and an area D2 of horizontal 4 pixels × vertical 240 pixels as shown in FIG. 15 data are read out. That is, the line L1 in the area D1, the line L9 in the area D1, the line L1 in the area D2, the line L9 in the area D2, the line L2 in the area D1, the line L10 in the area D1, the line L2 in the area D2, and the line L10 in the area D2. When reading is sequentially performed and the line L16 in the area D2 is read, the process proceeds to the line L17 in the area D1, and the same reading process is repeated. In this way, the pixel data in the region D is converted into pixel data having a horizontal direction of 336 pixels.
[0030]
When this conversion is viewed in units of DCT blocks, pixel data of 2.5 blocks in the horizontal direction (16 pixels + 4 pixels) is shown in FIG. 9A, and 42 blocks in the horizontal direction are shown in FIG. 9B. The pixel data is converted to (336 pixels).
By performing the above processing on the color difference signals of Cr and Cb, the pixel data of the color difference signal of one frame of the ED signal is converted into the pixel data of the color difference signal corresponding to one field of the HD signal. Note that the number of pixels in the chrominance signal for one field of the HD signal (336 × 512) is slightly larger than the number of pixels in the chrominance signal for one frame of the ED signal (356 × 480). Insert.
[0031]
As described above, the Y signal of one frame of the ED signal, the pixel data of the Cr and Cb signals are sequentially converted into the pixel data of the Y signal, the Cr and Cb signals corresponding to one field of the HD signal, and the VTR unit 2 Is input.
In the recording system of the VTR unit 2, signal processing such as DCT calculation, quantization, and variable length coding according to the DVC standard as described above is performed, and image information is recorded on the magnetic tape. At this time, when the ED signal is recorded, information indicating that is recorded in the subcode sector which is the auxiliary information recording area.
[0032]
Through the conversion process as described above, the image data corresponding to one frame of the HD signal input to the VTR unit 2 corresponds to the image data of two frames of the ED signal, and the data of the same line of the two frames of the ED signal is the same. The HD signal is alternately inserted for each line of one frame. Therefore, when there is little movement between ED frames, the DCT calculation in the VTR unit 2 is all performed in units of 8 pixels × 4 pixels, and the movement of taking the sum and difference components of the DCT coefficients of two consecutive fields When it is performed in the mode, the difference component becomes almost zero, so only the sum component remains, and the compression efficiency can be improved. That is, when recording a normal HD signal, the DCT operation is performed for each field only when motion detection is performed and a motion exceeding a predetermined value is detected. However, when recording an ED signal in the present embodiment, it is always performed for each field. It is desirable to use a DCT operation.
[0033]
Also, with respect to the luminance signal, since the DCT block of the dummy data having the same value is inserted at the rate of 1 DCT block with respect to the pixel data of the 2DCT block, the DCT block composed of the same value data performs the DCT operation. As a result, all the AC coefficients become “0”, so the number of bits can be assigned to other DCT blocks by code amount control, and high-quality recording and reproduction are possible.
[0034]
Next, processing in the playback system of the VTR unit 2 will be described. Data recorded on the magnetic tape is reproduced and demodulated into a digital data string. A SYNC word is detected from this data string, and data of one sync block is obtained. The reproduced data obtained in this way is subjected to error detection / correction processing using inner parity in the sync block, and video data and the like are further subjected to error detection / correction processing using outer parity. . Thereafter, reading of auxiliary information, variable-length decoding processing (reverse processing of variable-length coding), inverse quantization processing, and inverse DCT calculation are sequentially performed, and rearranged in the original pixel arrangement to switch the image signal The data is output to the second switch circuit 14 of the processing unit 1. Further, the auxiliary information reading circuit 31 reads the data of the subcode sector and supplies the information to the image signal switching processing unit 1 when the ED signal is recorded.
[0035]
The switch circuit 14 of the image signal switching processing unit 1 is switched by a switching signal output by a control unit (not shown) with reference to a subcode sector of reproduction data.
The dummy data processing circuit 16 of the image signal switching processing unit 1 removes dummy data added during recording. Specifically, the dummy data is removed by switching the switch circuit 103 of FIG. 2 to the terminal b side only for the timing of dummy data. When the information indicating that the signal is an ED signal is input from the VTR unit 2, the address control circuit 17 controls the address of the frame memory 15 as described above. In this way, the recorded ED signal is reproduced.
[0036]
As described above, according to the present embodiment, it is possible to record and reproduce the ED signal using the VTR unit 2 compliant with the DVC standard for HD signals. That is, recording and reproduction of ED signals by sequential scanning can be performed by adding a few circuits to a circuit using an LSI for HD signals.
[0037]
(Second Embodiment)
In the present embodiment, two consecutive frames (first frame and second frame) of the ED signal are divided into two equal parts, and the first and second signals corresponding to the first frame are divided into the second frame. The corresponding 2a signal and 2b signal are configured, the 1a signal and 2a signal are converted into a signal of one field of the HD signal, and the 1b signal and 2b signal are converted into the next field of the HD signal. The signal is converted into a signal.
[0038]
Specifically, two consecutive frames of ED signals are stored in the frame memory 15, and only odd-numbered lines (the 1a signal and the 2a signal) of the two frames are read and converted into one field HD signals. Then, only the even-numbered lines (the first b signal and the second b signal) of the two frames are read and converted into the next one field HD signal. At this time, the pixel data of the region B is read next to the pixel data of the region A (horizontal 672 pixels × vertical 240 pixels) of FIG. 4 included in the signal 1a, and dummy data is inserted and inserted as in the first embodiment. Sort. The same processing is performed for the 2a signal, the 1b signal, and the 2b signal.
[0039]
As a result, the pixel data of the first frame of the two consecutive frames of the ED signal correspond to the region E (upper half) of the HD frame, as shown in FIG. Conversion is performed so as to correspond to the region F (lower half).
Except for the above points, the second embodiment is the same as the first embodiment.
[0040]
As a result of the conversion processing as described above, the 1HD frame of the image signal input to the VTR unit 2 is a group of odd lines or even lines of the 1ED frame in which two fields constituting the 1HD frame are each a frame unit of the HD signal. If a DCT block is configured in this manner, the DCT block is configured in units of ED signal frames. In other words, in this case, the pixel compression in the ED frame can be used by fixing to the still mode in which the DCT calculation of 8 pixels × 8 pixels is performed on a frame basis, and the data compression efficiency can be improved.
[0041]
(Other embodiments)
The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, in the second embodiment, the first frame of the ED signal is made to correspond to the upper half of the HD frame and the second frame is made to correspond to the lower half, but for example, the first frame is made to correspond to the left half of the HD frame. The second frame may correspond to the right half.
[0042]
The recording medium is not limited to a magnetic tape, and may be a magnetic disk, a magneto-optical disk, or the like.
[0043]
【The invention's effect】
As described above in detail, the image signal of one frame of the first lower definition of the second resolution progressive scan is converted into an image signal of one field in the first definition, the signal after the conversion Is orthogonally converted for each predetermined pixel block and recorded on the recording medium. Therefore, the second lower resolution can be obtained by adding a relatively simple circuit to the apparatus for recording the image signal of the first definition. It is also possible to record a progressive scanning image signal of definition. The first definition image signal is converted into the predetermined image signal of the first definition by an image signal corresponding to the same position in two consecutive frames of the second definition image signal. Since it is performed so as to constitute a pixel block, information compression efficiency can be improved by performing orthogonal transformation of a so-called motion mode.
[0045]
Further, since the dummy data having the same value in Jo Tokoro pixel block is inserted, with minimal amount of data when encoding, it is possible to increase the amount of recorded data in other areas, reproduction Image quality can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a digital image signal recording / reproducing apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing in detail the configuration of a part of the apparatus of FIG.
FIG. 3 is a diagram for explaining switching control of the switch circuit of FIG. 2;
FIG. 4 is a diagram for explaining a pixel rearrangement method of luminance signals.
FIG. 5 is a diagram for explaining a method of rearranging pixels of a luminance signal.
FIG. 6 is a diagram for explaining the result of pixel rearrangement of luminance signals in units of blocks.
FIG. 7 is a diagram for explaining a pixel rearrangement method of color difference signals.
FIG. 8 is a diagram for explaining a pixel rearrangement method of color difference signals.
FIG. 9 is a diagram for explaining the result of pixel rearrangement of color difference signals in units of blocks;
FIG. 10 is a diagram for explaining a pixel rearrangement method according to the second embodiment;
FIG. 11 is a diagram illustrating a configuration of image data of an HD (high definition) signal.
FIG. 12 is a diagram for explaining a macroblock of the DVC standard (HD signal);
FIG. 13 is a diagram showing a data structure on a DVC standard magnetic tape.
[Explanation of symbols]
1 Image signal switching processing unit 2 Image signal recording / reproducing unit 10 Address control circuit 15 Frame memory 16 Dummy data processing circuit 21 Blocking circuit 22 DCT operation circuit 23 Quantization circuit 24 Variable length encoding circuit 25 Auxiliary information writing circuit 26 Error correction Encoding circuit 27 Sync block synthesis recording modulation circuit

Claims (4)

An image signal of a first definition based on the DVC standard in which an image signal of one frame is formed by two fields obtained by interlaced scanning, and a second definition sequentially lower than the first definition is recorded. A digital image signal recording apparatus for converting and recording the image signal of the first definition when the scanning image signal is received;
Converting means for converting the one-frame image signal into the first-definition one-field image signal and outputting the image signal when the second-definition progressive scan one-frame image signal is received; ,
Recording means for performing a predetermined process on the output signal of the conversion means and recording it on a recording medium,
The recording means includes a still mode for performing orthogonal transform in units of frames when recording an image signal having a first definition in which an image signal of one frame is formed by two fields obtained by interlaced scanning, Of the converted first definition is applied to the motion mode that outputs the difference component and the sum component of orthogonal transform coefficients of two consecutive fields . When an image signal composed of two fields arrives, it has an image information compression means for compressing the image information while being fixed in the motion mode , and the conversion means is a sequence of the image signals of the second definition. the image signal corresponding to the same position of the two frames, the digital image signal SL, characterized by configuring the predetermined pixel block of the first resolution image signal Apparatus.   The digital image signal recording apparatus according to claim 1, wherein the conversion unit performs the conversion by inserting dummy data having the same value in units of the predetermined pixel block. When a macro block is configured by the n predetermined pixel blocks of luminance signals (n is an integer of 2 or more) and m of the predetermined pixel blocks of two color difference signals (m is an integer of 1 or more),
According to the ratio of the first definition and the second definition, k predetermined pixel blocks (k is an integer satisfying 1 ≦ k <n) among the predetermined pixel blocks of the n luminance signals. The digital data according to claim 2, wherein the pixel block of the dummy data is used as the pixel block of the dummy data, the pixel block of the dummy data is arranged after the predetermined pixel block of the luminance signal in units of the macroblock, and the conversion is performed. Image signal recording device. An image signal having a first definition based on the DVC standard in which an image signal of one frame is formed by two fields obtained by interlaced scanning is recorded and reproduced, and a second definition lower than the first definition is recorded. A digital image signal recording / reproducing apparatus that converts a first-definition image signal into a first-definition image signal for recording / reproduction when a sequentially scanned image signal is received,
Converting means for converting the one-frame image signal into the first-definition one-field image signal and outputting the image signal when the second-definition progressive scan one-frame image signal is received; ,
Recording means for performing a predetermined process on the output signal of the conversion means and recording the recording signal on a recording medium;
Reproducing means for reproducing a signal recorded on the recording medium, performing a predetermined reproduction process, and outputting the reproduction signal;
Reproduction conversion means for converting the reproduction output signal into the image signal of the second definition and outputting it,
The recording means includes a still mode for performing orthogonal transform in units of frames when recording an image signal having a first definition in which an image signal of one frame is formed by two fields obtained by interlaced scanning, Of the converted first definition is applied to the motion mode that outputs the difference component and the sum component of orthogonal transform coefficients of two consecutive fields . When an image signal composed of two fields arrives, it has an image information compression means for compressing the image information while being fixed in the motion mode , and the conversion means is a sequence of the image signals of the second definition. the image signal corresponding to the same position of the two frames, the digital image signal SL, characterized by configuring the predetermined pixel block of the first resolution image signal Reproducing apparatus.

Images