JP3698478B2 - Debug device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a debugging device, that is, a debugging device for verifying (debugging) whether or not a program operates on hardware as intended by a programmer, and more particularly to a debugging device compliant with JTAG.
[0002]
[Prior art]
As an example of a conventional debugging device, a debugging device using a test access port (TAP) controller that conforms to the test architecture and test interface defined by IEEE Standard 1149.1 by JTAG (Joint Test Action Group) is known. ing. "JTAG" is originally an organization for standardization of testability design methods, but today, the test interface specifications standardized by this organization are also commonly called JTAG.
[0003]
FIG. 14 is a block diagram showing the configuration of a test & debug device built in a Motorola DSP161X series LSI chip as an example of a debug device using such a technology.
[0004]
In FIG. 14, reference numeral 1 denotes a test access port (TAP) controller (hereinafter referred to as a TAP controller) compliant with a test architecture and test interface defined by JTAG as IEEE standard 1149.1. This TAP controller 1 is predetermined according to a TCK (Test ClocK) signal given to the input terminal 54 from the outside, a TMS (Test Mode Select) signal given to the input terminal 55, and a TRST (Test ReSeT) signal given to the input terminal 53. State transition is performed (refer to FIG. 2 for details). A control signal generated in accordance with the state transition of the TAP controller 1 and a signal resulting from decoding of an instruction code by an instruction decoder 3 described later is sent to an instruction register 2, a flag register 5, a transfer register 6, a control register 16, and a multiplexer 8 described later. Is given.
[0005]
The instruction register 2 is connected between an input terminal 51 for a TDI (Test Data Input) signal, which is an N-bit serial input, and an output terminal 52 for a TDO (Test Data Output) signal, which is an N-bit serial output. Are located on an N-bit scan path accessible by a protocol defined by JTAG. In the following description, accessing by a protocol defined by JTAG is referred to as JTAG access. The instruction register 2 stores the test instruction input from the outside as a TDI signal via this scan path. In addition to the instruction register 2, a flag register 5, a transfer register 6, and a control register 16 are located on the scan path formed between the TDI signal input terminal 51 and the TDO signal input terminal 52. .
[0006]
The instruction decoder 3 decodes the contents of the instruction register 2, that is, the instruction code stored in the instruction register 2, and gives a signal obtained as a result to the TAP controller 1. The instruction decoded by the instruction decoder 3 supports private instructions necessary for testing and debugging in addition to three kinds of essential instructions defined in IEEE standard 1149.1 (1990).
[0007]
The flag register 5 is accessible through the above-described N-bit scan path accessible by JTAG, and stores the internal state of the chip. The flag register 5 has a plurality of bits and includes, for example, an interrupt flag such as JINT (JTAG interrupt) and PINT (JTAG interrupt status), a flag of carry of an operation result, an overflow, and the like.
[0008]
The transfer register 6 can be accessed through the above-described N-bit scan path that can be accessed by JTAG. By performing JTAG access from the outside, it is possible to access internal registers and memories. Specifically, the transfer register 6 can transfer data to and from a program memory 9, an internal register 10 and an internal memory 11 to be described later, and its control is controlled by a control register 16 to be described later.
[0009]
The multiplexer 8 selects one of the N-bit scan path outputs, that is, one of the outputs of the instruction register 2, the flag register 5, the transfer register 6, and the control register 16 under the control of the TAP controller 1, and TDO Serial output as a signal.
[0010]
The program memory 9 can transfer data to and from the transfer register 6 as described above, and stores a program to be executed by this chip.
[0011]
The internal register 10 is one or a plurality of registers normally provided in the chip, and data can be transferred to and from the transfer register 6 as described above. The internal memory 11 is one or a plurality of memories usually provided in the chip, and can transfer data to and from the transfer register 6 as described above.
[0012]
The control register 16 controls connection between the transfer register 6 and any one of the program memory 9, the internal register 10, and the internal memory 11. Under the control of the control register 16, data is transferred from the transfer register 6 to the program memory 9, the internal register 10 or the internal memory 11, and data is transferred from the program memory 9, the internal register 10 or the internal memory 11 to the transfer register 6. The
[0013]
Reference numeral 17 indicates an interrupt control unit. The interrupt control unit 17 manages interrupt control for synchronizing the transfer between the transfer register 6 and the program memory 9, the internal register 10, and the internal memory 11 by the control register 16 described above. Specifically, the interrupt control unit 17 stops the operation of the chip based on the JINT signal given from the flag register 5 and transfers the contents of the transfer register 6 to any one of the program memory 9, the internal register 10, and the internal memory 11. Conversely, the contents of any one of the program memory 9, the internal register 10, and the internal memory 11 are transferred to the transfer register 6, and then the PINT signal is set.
[0014]
The operation of the conventional debugging apparatus as described above is as follows. First, the operation at the time of writing data from the outside to the inside of the chip will be described.
[0015]
The write instruction is set in the instruction register 2 and the control register 16 is set by the JTAG access from the outside of the chip as to whether the write destination is the program memory 9, the internal register 10, or the internal memory 11. Data to be written is set in the transfer register 6 from outside the chip by JTAG access, and after the setting is completed, the JINT flag of the flag register 5 is set from outside the chip by JTAG access. When the JINT flag is set, the interrupt control unit 17 stops the operation of the chip, and the contents of the transfer register 6 are transferred to the transfer destination set in the control register 16, that is, the program memory 9, the internal register 10, and the internal memory 11 Transfer to one of the following. Thus, the write operation is completed.
[0016]
Next, the operation at the time of reading data from the inside of the chip to the outside will be described.
[0017]
The read instruction is set in the instruction register 2 and the control register 16 is set as to whether the read source is the program memory 9, the internal register 10, or the internal memory 11 from the outside of the chip using JTAG access. The JINT flag of the flag register 5 is set by JTAG access from outside the chip. When the JINT flag is set, the interrupt control unit 17 stops the operation of the chip and transfers the contents of the data transfer source set in the control register 16 to the transfer register 6. When this data transfer ends, the interrupt control unit 17 sets the PINT flag. Next, after confirming the setting of the PINT flag by monitoring the contents of the flag register 5 using JTAG access from the outside, the contents of the transfer register 6 are read out of the chip using JTAG access. Thus, the read operation is completed.
[0018]
[Problems to be solved by the invention]
By the way, the following two problems can be considered as problems in the conventional debugging apparatus as described above. First, when writing or reading data, hardware (control register 16) is used to set which of the program memory 9, the internal register 10, and the internal memory 11 is connected to the transfer register 6; Has been increasing. Furthermore, since it is necessary to increase the bit width of the hardware (control register 16) in accordance with the combination of connections described above, the hardware resources are further increased.
[0019]
Second, when reading data, dedicated hardware (interrupt control unit 17) is required to detect the end of data transfer from the register / memory to the transfer register 6, and as a result, hardware resources increase as described above. Moreover, the control is complicated.
[0020]
The present invention has been made in view of such circumstances, and suppresses an increase in hardware resources necessary for testing and debugging, and allows flexible setting by setting the data write destination and read source by software. The purpose is to provide a debugging device that enables the above.
[0021]
[Means for Solving the Problems]
A debugging device according to the present invention basically includes a control circuit that operates in response to an external input signal, an instruction register capable of inputting a predetermined instruction from the outside by an access controlled by the control circuit, and an instruction register An instruction decoder that decodes the contents of the program, an output controlled by the control circuit that can output the contents to the outside, a program counter that generates a program address to be executed, and an access according to the value of the program counter And a program memory. The program memory stores a program including a pause process that does not execute an address after a predetermined address after the end of a specific process. When a predetermined instruction is decoded by the instruction decoder, the control circuit accesses the program counter and outputs the value to the outside, so that the end of the specific process is completed when the address of the pause processing is output. Detected.
[0022]
Further, in the debugging device according to the present invention, in order to realize the basic configuration described above, the temporary pause process stored in the program memory is a program that loops between predetermined addresses after the end of the specific process, Alternatively, it is a program that waits for execution of a program at a specific address after completion of a specific process. Therefore, since the address of a program that loops between predetermined addresses or a program that waits for execution of the program is output to the outside after the specific process is completed, the end of the specific process is detected.
[0023]
The debugging device according to the present invention includes a first register (DINT register) capable of holding a value of a signal input from the outside by an access controlled by the control circuit, and a first register (DINT register). A second register (flag register) that holds the held signal value in synchronization with a signal input from the outside at an arbitrary timing and releases the pause processing according to this value is provided. Thereby, the execution of the program is temporarily stopped after the specific process is completed, but the program can be re-executed thereafter.
[0024]
Furthermore, the debugging device according to the present invention can output the contents to the outside by access controlled by the control circuit, and has a transfer register connectable to a plurality of storage means (internal registers, internal memories). The program memory stores a transfer program between at least a part of a plurality of storage means (internal registers, internal memory) connectable to the transfer register and the transfer register. When a predetermined instruction is decoded by the instruction decoder, the control circuit accesses the transfer register and outputs the value to the outside, whereby a plurality of storage means (internal register, internal memory) connectable to the transfer register It is possible to output at least part of the contents to the outside.
[0025]
Furthermore, the debugging device according to the present invention is characterized in that a part of the program memory is connected to a transfer register, and has an area that can be accessed by a value of the program counter and can be written and read. Therefore, by accessing the transfer register under the control of the control circuit, an arbitrary program can be written from the outside to a writable / readable program memory (RAM area). Specifically, it is possible to arbitrarily select the debug target by writing the transfer program between the register, memory, etc. to be debugged and the transfer register from the outside and writing to the readable program memory (RAM area). become.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof. FIG. 1 is a block diagram showing an example of the configuration of a debugging device according to the present invention, and shows the minimum components necessary for realizing the debugging device of the present invention when integrated as an LSI chip.
[0027]
In FIG. 1, reference numeral 1 indicates a test access port (TAP) controller (hereinafter referred to as a TAP controller) compliant with the test architecture and test interface defined by IEEE standard 1149.1 by JTAG. This TAP controller 1 Is It functions as a control circuit and is described later according to the TCK (Test Clock) signal given to the input terminal 54 from the outside, the TMS (Test Mode Select) signal given to the input terminal 55, and the TRST (Test ReSet) signal given to the input terminal 53. State transition as shown in the state transition diagram of FIG. A control signal generated in accordance with the transition state by the TAP controller 1 and a signal of the decoding result of the instruction code by the instruction decoder 3 which will be described later is an instruction register 2, a DINT register 4, a transfer register 6, a program counter 7 and a multiplexer 8 which will be described later. Is given to.
[0028]
The instruction register 2 is connected between an input terminal 51 for a TDI (Test Data Input) signal, which is an N-bit serial input, and an output terminal 52 for a TDO (Test Data Output) signal, which is an N-bit serial output. Are located on an N-bit scan path accessible by a protocol defined by JTAG. In the following description, accessing by a protocol defined by JTAG is referred to as JTAG access. Then, the instruction register 2 stores the test instruction input from the outside as a TDI signal via this scan path. In addition to the instruction register 2, a DINT register 4, a transfer register 6, and a program counter 7 are located on the scan path formed between the TDI signal input terminal 51 and the TDO signal output terminal 52. .
[0029]
The instruction decoder 3 decodes the contents of the instruction register 2, that is, the instruction code stored in the instruction register 2, and gives a signal obtained as a result to the TAP controller 1. The instructions decoded by the instruction decoder 3 include private instructions necessary for testing and debugging in addition to the three types of essential instructions defined in IEEE Standard 1149.1 (1990).
[0030]
The DINT register 4 functions as the first register and can be accessed through an N-bit scan path that allows JTAG access. By inputting JTAG access from the outside, a debugger interrupt (DINT) signal, which is a PC break signal, is input. Hold. The DINT signal held in the DINT register 4 is applied to a 2-input OR gate 14 which will be described later.
[0031]
Reference numeral 5 indicates a flag register that functions as a second register for storing the internal state of the chip. The flag register 5 is supplied with the logical sum output signal of the logical sum gate 14 described above. A pin input signal DINT input to the input terminal 56 from the outside of the chip and an output signal of the DINT register 4 are input to the OR gate 14. The flag register 5 is connected to the transfer register 6 and the program counter 7 via the local bus 13.
[0032]
The transfer register 6 can be accessed through the above-described N-bit scan path accessible by JTAG. In other words, by performing JTAG access to the transfer register 6 from the outside, it is possible to access internal registers and memories via the transfer register 6. Specifically, the transfer register 6 is connected to a program memory 9, an internal register 10 and an internal memory 11, which will be described later, via an internal bus 12, and the flag register 5 and the program counter 7 are connected to the local bus 13. Are connected to each other. The internal bus 12 is also connected to the input / output port 15.
[0033]
The program counter 7 is accessible through an N-bit scan path accessible by JTAG, and generates and holds an address of an instruction code to be read from the program memory 9.
[0034]
The multiplexer 8 selects one of the N-bit scan path outputs, that is, one of the outputs of the instruction register 2, the DINT register 4, the transfer register 6 and the program counter 7 under the control of the TAP controller 1, and TDO Serial output as a signal.
[0035]
As described above, the program memory 9 can transfer data to and from the transfer register 6 via the internal bus 12, and stores a program to be executed by this chip. The program memory 9 is essentially a ROM, but a RAM area 91 is provided as a writable and readable area.
[0036]
The internal register 10 is one or a plurality of registers normally provided in the chip, and can transfer data to and from the transfer register 6 via the internal bus 12 as described above. The internal memory 11 is one or a plurality of memories normally provided in a chip, and can transfer data to and from the transfer register 6 via the internal bus 12 as described above.
[0037]
Next, input signals and output signals of the components of the debugging device of the present invention will be described.
[0038]
The TCK (Test ClocK) signal is an input signal to the TAP controller 1 and is a clock signal for the test access port. The TMS (Test Mode Select) signal is an input signal to the TAP controller 1 and controls the state transition of the TAP controller 1. The TDI (Test Data Input) signal is a test data register (DINT register 4, transfer register 6, program counter 7, etc., hereinafter referred to as test data registers 4, 6, 7, etc.) having an instruction register 2 and a JTAG accessible scan path. ) Is a serial input signal to.
[0039]
A TDO (Test Data Output) signal is a serial output signal from the instruction register 2 and the test data registers 4, 6, 7, etc. having a scan path accessible by JTAG. The TRST (Test ReSeT) signal is an input signal to the TAP controller 1 and a reset input signal of the TAP controller 1. The pin input DINT signal is an input signal to the OR gate 14 and is a debugger interrupt input signal. The PC break DINT signal is an input signal to the DINT register 4, and is a signal that becomes “1” when a break condition is established by a break point set in the program memory 9.
[0040]
Note that these input / output signals to the TAP controller 1 are actually input from a host computer (not shown) and output to the host computer.
[0041]
Next, each component of the debugging device of the present invention shown in FIG. 1 will be described more specifically.
[0042]
The TAP controller 1 performs state transition according to the value of the TMS signal at all rising edges of the clock of the TCK signal, and takes one of the 16 states shown in FIG. Circuits such as the instruction register 2 and the test data registers 4, 6, and 7 operate on both the rising and falling edges of the clock of the TCK signal. Hereinafter, each state of the state transition by the TAP controller 1 will be specifically described below.
[0043]
* Test-Logic-Reset state
Reset state. In this state, the normal operation of the chip is not hindered. When the TAP controller 1 transitions to this state, the BYPASS instruction (b'11111) is forcibly loaded into the output latch (see FIG. 3) of the instruction register 2. The detailed configuration of the instruction register 2, DINT register 4, transfer register 6, and program counter 7 will be described later. “B ′” indicates binary display, and in this embodiment, the instruction code is 5 bits. Regardless of the initial state, the TAP controller 1 transitions to this Test-Logic-Reset state when the TRST signal is asserted or the TMS signal is maintained at b'1 for more than 5 clock periods of the TCK signal. After that, this Test-Logic-Reset state is maintained as long as the TMS signal maintains b'1. However, if the b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Run-Test / Idle state.
[0044]
* Run-Test / Idle state
Test instruction execution state. In this state, the scan operation is not performed, and the specified operation is executed according to the instruction held in the instruction register 2. In this state, the instruction does not change. The TAP controller 1 maintains this state as long as the TMS signal maintains b'0. When the b'1 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Select-DR-Scan state. “DR” represents the test data registers 4, 6, 7, and the like.
[0045]
* Select-DR-Scan status
Temporary state for transitioning to another state. The test data registers 4, 6, 7, etc. hold the values so far. In this state, the instruction does not change. In this state, when the b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transits to the Captur-DR state, and scans the test data registers 4, 6, 7, etc. designated by the instruction. Operation starts. When the b'1 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Select-IR-Scan state. “IR” represents the instruction register 2.
[0046]
* Select-IR-Scan status
Temporary state for transitioning to another state. The test data registers 4, 6, 7, etc. hold the values so far. In this state, the instruction does not change. In this state, when the b'0 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transits to the Captur-IR state, and the scan operation of the instruction register 2 is started. When the b'1 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Test-Logic-Reset state described above.
[0047]
* Captur-DR state
A state in which values are taken into the shift register stages such as test data registers 4, 6, and 7 from the outside. At the rising edge of the clock of the TCK signal, data is loaded from the parallel input port to any one of the test data registers 4, 6, 7, etc. designated by the current instruction. If the designated test data register 4, 6, 7, etc. does not have a parallel input port, or if parallel input is not instructed by an instruction, the test data register 4, 6, 7 etc. will retain the previous values To do. In this state, the instruction does not change. In this state, when the b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Shift-DR state, and at the rising edge of the TCK signal clock, the b'1 TMS signal is output. When input, TAP controller 1 transitions to the Exit1-DR state.
[0048]
* Shift-DR state
A state in which the test data registers 4, 6, 7, etc. are scanned. One of the test data registers 4, 6, 7, etc. specified by the current instruction is connected to the scan path formed between the input terminal 51 of the TDI signal and the output terminal 52 of the TDO signal, and the clock of the TCK signal Data is shifted by one bit in the serial output direction at every rising edge. In this state, the instruction does not change. The TAP controller 1 maintains this state as long as the TMS signal maintains b'0. When the TMS signal b'1 is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Exit1-DR state.
[0049]
* Exit1-DR state
Temporary state for transitioning to another state. The test data registers 4, 6, 7, etc. hold the values so far. In this state, the instruction does not change. In this state, when the b'1 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transits to the Update-DR state and ends the scanning process. When the b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Pause-DR state.
[0050]
* Pause-DR state
A state in which the shift operation of the test data registers 4, 6, 7, etc. is temporarily stopped. The test data registers 4, 6, 7, etc. hold the values so far. In this state, the instruction does not change. The TAP controller 1 maintains this state as long as the TMS signal maintains b'0. When the TMS signal of b'1 is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Exit2-DR state.
[0051]
* Exit2-DR status
Temporary state for transitioning to another state. The test data registers 4, 6, 7, etc. hold the values so far. In this state, the instruction does not change. In this state, when the b'1 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 ends the scan process and transitions to the Update-DR state. When the b'0 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transitions to the aforementioned Shift-DR state.
[0052]
* Update-DR status
A state in which output latches of test data registers 4, 6, 7, etc. are updated. Data is transferred from the shift registers such as the test data registers 4, 6, and 7 to the parallel output latch at the falling edge of the clock of the TCK signal, but the shift register holds the previous value. The parallel output latches of the test data registers 4, 6, 7, etc. are provided to prevent the parallel output values from changing while the test data registers 4, 6, 7, etc. are performing the scanning operation. In this state, the instruction does not change. In this state, when the b'1 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 shifts to the above-described Select-DR-Scan state, and at the rising edge of the clock of the TCK signal, b'0 When the TMS signal is input, the TAP controller 1 transits to the above-mentioned Run-Test / Idle state.
[0053]
* Captur-IR state
A state in which a fixed value is taken into the shift register stage of the instruction register 2. In the present embodiment, a fixed value b′00001 is loaded from the parallel input port of the instruction register 2 at the rising edge of the clock of the TCK signal. In this state, the test data registers 4, 6, 7, etc. hold the values so far and the instruction does not change. In this state, when a b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Shift-IR state, and at the rising edge of the TCK signal clock, the b'1 TMS signal is output. When input, TAP controller 1 transitions to the Exit1-IR state.
[0054]
* Shift-IR state
A state in which the instruction register 2 is scanned. The instruction register 2 is connected to a scan path formed between the TDI signal input terminal 51 and the TDO signal output terminal 52, and the data is shifted in the serial output direction bit by bit at every rising edge of the clock of the TCK signal. The In this state, the test data registers 4, 6, 7, etc. hold the values so far, and the instruction does not change. The TAP controller 1 maintains this state as long as the TMS signal maintains b'0. When the b'1 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transits to the Exit1-IR state.
[0055]
* Exit1-IR status
Temporary state for transitioning to another state. The instruction register 2 holds the previous value. In this state, the test data registers 4, 6, 7, etc. hold the values so far, and the instruction does not change. In this state, when the b'1 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transits to the Update-IR state and ends the scanning process. When the b'0 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transitions to the Pause-IR state.
[0056]
* Pause-IR state
A state in which the shift operation of the instruction register 2 is temporarily stopped. The instruction register 2 holds the previous value. In this state, the test data registers 4, 6, 7, etc. hold the values so far, and the instruction does not change. The TAP controller 1 maintains this state as long as the TMS signal maintains b'0. When the b'1 TMS signal is input at the rising edge of the TCK signal clock, the TAP controller 1 transits to the Exit2-IR state.
[0057]
* Exit2-IR status
Temporary state for transitioning to another state. The instruction register 2 holds the previous value. In this state, the test data registers 4, 6, 7, etc. hold the values so far, and the instruction does not change. In this state, when the b'1 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 ends the scan process and transitions to the Update-IR state. When the b'0 TMS signal is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transitions to the aforementioned Shift-IR state.
[0058]
* Update-IR status
A state in which the output latch of the instruction register 2 is updated. Data is transferred from the shift register of the instruction register 2 to the parallel output latch at the falling edge of the clock of the TCK signal. When a new instruction is latched into the output latch of instruction register 2, it becomes the current instruction. In this state, the test data registers 4, 6, 7, etc. hold the values so far. In this state, when the TMS signal b′1 is input at the rising edge of the clock of the TCK signal, the TAP controller 1 transitions to the above-described Select-DR-Scan state, and b′0 at the rising edge of the clock of the TCK signal. When the TMS signal is input, the TAP controller 1 transitions to the Run-Test / Idle state described above.
[0059]
The TAP controller 1 takes one of the above 16 states, but the Puase-DR state and the Puase-IR of these Status Is necessary to temporarily stop the operation while shifting data into the instruction register 2 or the test data registers 4, 6, 7, etc., for example, an automatic test equipment is installed in the memory from the disk. This is necessary when loading long test sequences.
[0060]
The TAP controller 1 performs three basic operations for testing. The three types of operations are signal input (Update-DR), execution (Run-Test / Idle), and result capture (Captur-DR). However, all of these test operations are not necessarily required in all tests.
[0061]
The driver for the TDO signal output in the multiplexer 8 drives b'1 or b'0 only when the TAP controller 1 is in the Shift-IR state or Shift-DR state, and is high when it is in the other state. It becomes an impedance state.
[0062]
Next, the configuration of the instruction register 2 will be described with reference to the block diagram of FIG. In this embodiment, the instruction register 2 as a whole is configured as a 5-bit wide register by connecting each 1-bit cell to the lower bit side serial output to the upper bit side serial input. In general, it has a two-stage configuration of a shift register stage having a parallel input, a serial input and a serial output, and an output latch having a parallel output and holding an instruction currently being executed.
[0063]
The internal structure of each cell constituting the instruction register 2 is the same, and is indicated by reference numeral 200 in the block diagram of FIG. Specifically, the shift register stage of each cell 200 of the instruction register 2 is composed of a multiplexer 231 and a flip-flop 232, and the output latch is composed of a flip-flop 233. The multiplexer 231 constituting the shift register stage has a parallel input and a serial input. The Shift / # Captur signal, that is, the Shift signal output from the TAP controller 1 in the Shift-DR state or the Shift-IR state, and the TAP controller 1 is Captur. -Either one is output to the flip-flop 232 in response to the #Captur signal which is an inverted signal of the signal output in the DR state or Captur-IR state. The flip-flop 232 latches the output signal of the multiplexer 231 using the TCK signal as a trigger signal, and outputs it as a serial output to the next cell or TDO signal to the outside. The flip-flop 233 latches the output of the flip-flop 232 using the Update-IR signal as a trigger signal, and outputs it in parallel to the instruction decoder 3.
[0064]
Therefore, the operation in which the TDI signal is input to the multiplexer 231 of the first stage cell 200 of the instruction register 2 and the output signal from the flip-flop 232 is input to the multiplexer 231 of the next stage cell 200 is repeated. An output signal from the flip-flop 232 of the cell 200 at the final stage is output to the multiplexer 8 as a TDO signal. The output from the flip-flop 233 of each cell 200 is input to the instruction decoder 3 as a 5-bit parallel output.
[0065]
In the instruction register 2 having such a configuration, the serial input to the first stage cell 200 and the serial output from the last stage cell 200 are the TDI signal input terminal 51 and the TDO signal output terminal 52 (multiplexer 8) in FIG. A 5-bit serial scan path is formed. In such a scan path, each cell 200 sequentially transfers data in synchronization with the rising edge of the clock of the TCK signal after the TAP controller 1 transitions to the Shift-IR state. Each bit of the fixed value b′00001 is loaded from the parallel input to the multiplexer 231 of each cell 200 in synchronization with the rising edge of the clock of the TCK signal after the TAP controller 1 transitions to the Captur-IR state. In this fixed value, b′1 is LSB and is loaded into the cell 200 at the final stage. The bit of the instruction code held in the flip-flop 232 of the shift register stage of each cell 200 is a flip-flop that constitutes an output latch in synchronization with the falling edge of the clock of the TCK signal when the TAP controller 1 is in the Update-IR state. Forwarded to 233. The parallel output latch of each cell 200 is reset when the TAP controller 1 transitions to the Test-Logic-Reset state, and b'11111 (BYPASS instruction) is set in synchronization with the falling edge of the TCK signal clock. When TRST signal is asserted, b'11111 (BYPASS command) is set asynchronously with the clock of TCK signal.
[0066]
The operation of the instruction register 2 in each state of the TAP controller 1 as described above is summarized in the list of FIG.
[0067]
The instruction decoded by the instruction decoder 3 supports four private instructions in addition to the three essential instructions defined in IEEE standard 1149.1 (1990). All test instructions have a 5-bit code, and the bit pattern of each instruction and the scan register to be used are shown in the list of FIG. In FIG. 5, the instruction code is displayed in hexadecimal. In the following explanation, 16 Progress The display is indicated by h ′.
[0068]
Of the instructions shown in Fig. 5, the BYPASS instruction (instruction code h'1F), SAMPLE / PRELOAD instruction (instruction code h'02) and EXTEST instruction (instruction code h'00) are essential instructions. Since they are not directly related to the invention, their details are omitted. The BYPASS instruction is an essential standard instruction for operating the bypass register, and the SAMPLE / PRELOAD instruction and the EXTEST instruction are essential standard instructions for operating the boundary scan register, and are called boundary scan register instructions.
[0069]
The instructions unique to the present invention are the SETDINT instruction (instruction code h'16), the RD_PC instruction (instruction code h'0C), the RD_Trans instruction (instruction code h'0E), and the WR_Trans instruction (instruction code h'0F). The SETDINT instruction (instruction code h'16) is an instruction for communication between the debugger and the monitor program during program debugging. The RD_PC instruction (instruction code h′0C) is an instruction for sampling the output of the latch of the program counter 7. The RD_Trans instruction (instruction code h'0E) and the WR_Trans instruction (instruction code h'0F) are instructions for sampling and writing to the transfer register 6, respectively. Details of how to use the above four private instructions will be described when explaining the operation of the debugging device of the present invention.
[0070]
FIG. 6 is a block diagram showing a configuration example of the DINT register 4. The DINT register 4 is a 1-bit register, inputs the TDI signal and DINT signal shown in FIG. 1 and outputs one of them according to the Shift / # Captur signal, and the output signal of the multiplexer 431 uses the TCK signal as a trigger signal. The flip-flop 432 that latches the output signal, the flip-flop 433 that latches the output signal of the flip-flop 432 using the output signal of the AND gate 436 as a trigger signal, the output signal of the flip-flop 433 and the DINT signal are input, and the SETDINT signal The multiplexer 434 that outputs one of them and the above-described AND gate 436 that receives the SETDINT signal and the Update-DR signal are included.
[0071]
The serial input to the multiplexer 431 is the TDI signal shown in FIG. 1. When this signal is once latched in the flip-flop 432 and serially output to the multiplexer 8 as an output signal, a 1-bit scan path is formed. In this scan path, the flip-flop 432 captures the data from the serial input to the multiplexer 431 and transfers the data to the serial output in synchronization with the rising edge of the TCK signal clock after the TAP controller 1 transitions to the Shift-DR state. To do. On the other hand, from the DINT input, the PC break DINT signal in FIG. 1 is fetched by the flip-flop 432 in synchronization with the rising edge of the TCK signal clock after the TAP controller 1 transitions to the Captur-DR state, and the data is transferred to the serial output. To do. Further, the flip-flop 433, the multiplexer 434, and the AND gate 436 allow the value of the flip-flop 432 to be synchronized with the falling edge of the clock of the TCK signal when the TAP controller 1 is in the Update-DR state by the SETDINT instruction. 433 and output from the DINT output of the multiplexer 434 to the OR gate 14 of FIG. In the case other than the SETDINT instruction, the value of the PC break DINT in FIG. 1 is output to the DINT output.
[0072]
The flag register 5 is a multi-bit register for storing various states inside the LSI chip, similar to that of a general computer. These various states include flags such as carry and overflow of operation results, and a bit width corresponding to the number of necessary states such as DINT (debugger interrupt) related to this embodiment is required. It is. In the present embodiment, only one bit of DINT is related. The DINT bit is also connected to the local bus 13 and can be accessed via the local bus 13 in addition to the access by the DINT register 4.
[0073]
FIG. 7 is a block diagram showing a configuration example of a cell for one bit of the transfer register 6. Since the transfer register 6 can be accessed by JTAG and is connected to the local bus 13 and the internal bus 12, the transfer register 6 is connected to the local bus 13 and the internal bus 12 by performing JTAG access to the transfer register 6 from the outside of the chip. All registers and memories inside the chip can be accessed from outside the chip.
[0074]
Each bit 600 of the transfer register 6 includes a data latch 630 that holds parallel data, a shift register stage (flip-flop 632) that holds serial data, and an output latch (flip-flop) that transfers serial data to the data latch 630. 633) latches, multiplexers 631, 634, 635 and an AND gate 636.
[0075]
The multiplexer 635 receives the parallel input and the output of the multiplexer 634, and outputs either to the data latch 630 according to the WR_Trans signal output from the TAP controller 1 in response to the WR_Trans command. The multiplexer 631 receives the held value of the data latch 630 and the serial input, and outputs either one according to the Shift / # Captur signal. The flip-flop 632 latches the output of the multiplexer 631 using the TCK signal as a trigger and outputs it as a serial output. The flip-flop 633 latches and outputs the serial output of the flip-flop 632 using the output signal of the AND gate 636 as a trigger. The multiplexer 634 receives the output signal of the flip-flop 633 and the hold value of the data latch 630, and outputs either one to the multiplexer 635 according to the WR_Trans signal output from the TAP controller 1 in response to the WR_Trans command. The AND gate 636 receives the WR_Trans signal and the Update-DR signal output from the TAP controller 1 in the Update-DR state.
[0076]
The transfer register 6 of the present embodiment is a 16-bit register having each bit of the cell 600 shown in FIG. Each cell 600 is configured to have a 16-bit width by connecting the serial output of the flip-flop 632 on the lower bit side to the serial input of the multiplexer 631 on the upper bit side. As shown in FIG. A 16-bit scan path is formed between the signal input terminal 51 and the TDO signal output terminal 62 (multiplexer 8).
[0077]
In this scan path, the multiplexer 631 and the flip-flop 632 synchronize with the rising edge of the clock of the TCK signal after the TAP controller 1 transitions to the Shift-DR state, from the serial input of the multiplexer 631 to the serial output of the flip-flop 632. Simultaneously with the data transfer, the output data of the flip-flop 632 is taken into the flip-flop 632. From the parallel output that is the output of the data latch 630, the held value of the data latch 630 is flip-flops via the multiplexer 631 in synchronization with the rising edge of the clock of the TCK signal after the TAP controller 1 transitions to the Captur-DR state. 632 is loaded. The value held in flip-flop 632 by flip-flop 633, multiplexer 634, AND gate 636, and multiplexer 635 is synchronized with the falling edge of the TCK signal clock when TAP controller 1 is in the Update-DR state with the WR_Trans instruction. Then, the data is taken into the flip-flop 633 and inputted to the data latch 630 via the multiplexers 634 and 635. In the case other than the WR_Trans instruction, the parallel input as the TDI signal is input to the data latch 630 via the multiplexer 635.
[0078]
FIG. 8 is a block diagram showing a configuration example of a cell for one bit of the program counter 7. The program counter 7 has functions such as increment, jump, loop, etc., in the same way as that of a general computer, and accesses the program memory 9 using this count value (PC value) as an access address. As a result, the instruction code is output. However, in the present invention, the original function of the program counter 7 is not important, and it is important that the value of the program counter 7 is JTAG accessible and can be monitored from the outside of the chip.
[0079]
The program counter 7 of the present embodiment is a 16-bit register having each bit of the cell 700 shown in FIG. Each cell 700 of the program counter 7 includes a data latch 730 that holds parallel data after processing such as increment, jump, and loop, latches of a shift register stage (flip-flop 732) that holds serial data, and a multiplexer 731. It is configured.
[0080]
The parallel input is input to the data latch 730, the held value of the data latch 730 and the serial input are input to the multiplexer 731, and the # Shift / Captur signal, that is, the TAP controller 1 is in the Shift-DR state or the Shift-IR state. Either the #Shift signal, which is an inverted signal of the output signal, and the Captur signal output by the TAP controller 1 in the Captur-DR state or Captur-IR state are output to the flip-flop 232. The flip-flop 732 latches the output signal of the multiplexer 731 using the TCK signal as a trigger and outputs it as a serial output.
[0081]
Each cell 700 is configured to have a 16-bit width by connecting the serial output of the flip-flop 732 on the lower bit side to the serial input of the multiplexer 731 on the upper bit side, as shown in FIG. A 16-bit scan path is formed between the TDI signal input terminal 51 and the TDO signal output terminal 52 (multiplexer 8).
[0082]
In this scan path, the multiplexer 731 and the flip-flop 732 cause the serial input of the multiplexer 731 to the serial output of the flip-flop 732 in synchronization with the rising edge of the clock of the TCK signal after the TAP controller 1 transitions to the Shift-DR state. At the same time as the data is transferred, the flip-flop 732 captures the data. From the parallel output that is the output of the data latch 730, the value of the data latch 730 is loaded into the flip-flop 732 in synchronization with the rising edge of the clock of the TCK signal after transition to the Captur-DR state.
[0083]
The multiplexer 8 drives a high-level or low-level signal, that is, a b′1 or b′0 signal only when the TAP controller 1 is in the Shift-IR state and the Shift-DR state. The multiplexer 8 selects the serial output at the final stage of the instruction register 2 and outputs it as the TDO signal when the TAP controller 1 is in the Shift-IR state. The multiplexer 8 selects the serial output of the DINT register 4 when the TAP controller 1 is in the Shift-DR state and the SETDINT instruction is executed, and the program counter 7 when the RD_PC instruction is executed. When the RD_Trans instruction and the WR_Trans instruction are executed, the serial output of the final stage of the transfer register 6 is selected and each is output as a TDO signal. When the TAP controller 1 is in any other state, the multiplexer 8 is in a high impedance state.
[0084]
The program memory 9 is a memory for storing the instruction code of a program necessary for the computer to execute processing, similar to that of a general computer with respect to its function, and the instruction code according to the address value indicated by the program counter 7 Is stored. However, in the debugging device of the present invention, the monitor program shown in the flowchart of FIG. 9 needs to be stored at a specific location in the program memory 9.
[0085]
The monitor program shown in FIG. 9 is executed when b′1 is set in the DINT bit of the flag register 5, in other words, when a DINT interrupt occurs. This can be easily realized by jumping the PC value of the program counter 7 to the head address of the monitor program when b'1 is set in the DINT bit of the flag register 5. However, it is also necessary to store the address before the jump in some storage means so that the address can be returned to that address upon return after execution of the monitor program, so-called context loading / restoration. Further, it is necessary to devise a mechanism so that the flag register 5 or the program counter 7 does not accept multiple DINT interrupts during the period from the start of execution of the monitor program due to the occurrence of the DINT interrupt until the return.
[0086]
The internal register 10 is a plurality of registers connected to the transfer register 6 via the internal bus 12. Data can be transferred to and from the transfer register 6 by a program.
[0087]
The internal memory 11 is a plurality of memories connected to the transfer register 6 via the internal bus 12. Data can be transferred to and from the transfer register 6 by a program.
[0088]
The internal bus 12 connects the transfer register 6 to the program memory 9, the internal register 10 and the internal memory 11. The local bus 13 connects the transfer register 6 to the flag register 5 and the program counter 7.
[0089]
The OR gate 14 is a logic gate that performs an OR operation on the pin input DINT signal set from the outside of the chip and the output signal of the DINT register 3, and the result is given to the flag register 5.
[0090]
The input / output port 15 is connected to the internal bus 12 and can be connected to a memory or the like outside the LSI chip of the debugging device of the present invention shown in FIG. Data can be transferred between the transfer register 6 and a memory outside the LSI chip by the program through the input / output port 15.
[0091]
The operation of the debugging device of the present invention configured as described above will be described below. In this embodiment, an LSI chip having the above-described configuration as a minimum and a host computer connected to the LSI chip by four (5) signal lines of TDI, TDO, TCK, TMS, (TRST) In the following description of the operation, it is assumed that the host computer is connected to the debugging device of the present invention shown in FIG. For the host computer, if the TDI, TDO, TCK, TMS, (TRST) signal protocol conforms to the IEEE1149.1 standard defined by JTAG, in other words, if JTAG access is possible. It is not limited.
[0092]
First, how the instruction is set from the host computer in the debugging apparatus of the present invention shown in FIG. 1 and how it is executed will be described with respect to the above-described four private instructions. The instruction setting procedure is the same for any instruction. In the state transition diagram of FIG. 2 described above, the host computer inputs the TMS signal to the TAP controller 1 while changing its value so that the TAP controller 1 performs the following state transition. The value of the TMS signal input from the host computer to the TAP controller 1 is sampled by the TAP controller 1 in synchronization with the rising edge of the TCK signal clock.
[0093]
Test-Logic-Reset → Run-Test / Idle → Select-DR-Scan → Select-IR-Scan → Captur-IR → Shift-IR →… → Shift-IR → Exit1-IR → Update-IR → Run-Test / Idle →…
[0094]
In such a state transition, the shift register stage of the instruction register 2 (each instruction register 2 shown in FIG. 3 is synchronized with the rising edge of the clock of the TCK signal while the TAP controller 1 is in the Captur-IR state. Each bit of the 5-bit fixed value b'00001 is loaded in parallel on the flip-flop 232) of the cell 200. In the next Shift-IR state, the number of times corresponding to the bit width of the instruction register 2 is repeated.
[0095]
In this embodiment, since the bit width of the instruction register 2 is 5 bits as described above, the host computer gives the TMS signal b′0 to the TAP controller 1 five times in succession so that the TAP controller 1 Performs a state transition that repeats the Shift-IR state five times. At this time, the host computer inputs the instruction code to the TAP controller 1 as a TDI signal in order from the LSB. Specifically, in FIG. 3, data serially input to the instruction register 2 as a TDI signal to the first stage cell 200 is sequentially output from the serial output via the flip flop 232 of each cell 200 to the flip flop 232 of the next stage cell 200. Is output. As a result, b'00001 is serially output from the cell 200 at the final stage as a TDO signal.
[0096]
After the above Shift-IR state has been repeated five times, the host computer outputs the b'1 TMS signal twice in succession. As a result, the TAP controller 1 transits to the Update-IR state via the Exit1-IR state. In the instruction register 2 in synchronization with the falling edge of the clock of the TCK signal while the TAP controller 1 is in the Update-IR state, the data latched in the serial latch (flip-flop 232) of each cell 200 (input as the TDI signal) The data is transferred to the parallel output latch (flip-flop 233) and latched to complete the instruction setting.
[0097]
The instruction set in the instruction register 2 in this way is sent to the instruction decoder 3 and decoded. In synchronization with the state transition of the TAP controller 1, the scan path selection, the test data registers 4, 6, 7 and the like are sent. Designation of writing / reading, selection of the TDO signal output by the multiplexer 8, and generation of signals necessary for each are performed. The operation when the above-described four private instructions are set will be specifically described below.
[0098]
When the SETDINT instruction is set in the instruction register 2, the DINT register 4 is selected as a scan path. Then, the host computer inputs the TMS signal to the TAP controller 1 while changing the value so that the TAP controller 1 performs the following state transition. In all of the following explanations, the timing of the TMS signal and the TCK signal is the same as in the case of the instruction setting described above.
[0099]
Run-Test / Idle → Select-DR-Scan → Captur-DR → Shift-DR → Exit1-DR → Update-DR → Run-Test / Idle →…
[0100]
In such a state transition, the value of the DINT input (PC break DINT input) shown in FIG. 6 is set to the DINT register in synchronization with the rising edge of the clock of the TCK signal while the TAP controller 1 is in the Captur-DR state. 4 flip-flops 432 are loaded. In the Shift-DR state, b′1 is input as a TDI signal from the host computer in order to set the DINT register 4 to the DINT state. Since the DINT register 4 is 1 bit wide, the number of transitions of Shift-DR is one. At this time, the current DINT value is output as the TDO signal.
[0101]
The DINT register is synchronized with the falling edge of the TCK signal clock while the TAP controller 1 is in the Update-DR state as the state transition proceeds from the Captur-DR state through the Shift-DR state and Exit1-DR state. 4, the data latched in the serial latch (flip-flop 432) (data input from the TDI) is transferred to the parallel output latch (flip-flop 433), and the OR gate 14 shown in FIG. Then, it is sent to the flag register 5. As a result, the DINT flag of the flag register 5 is set.
[0102]
When the RD_PC instruction is set in the instruction register 2, the program counter 7 is selected as a scan path. Then, the host computer inputs the TMS signal to the TAP controller 1 while changing its value so that the TAP controller 1 performs the following state transition.
[0103]
Run-Test / Idle → Select-DR-Scan → Captur-DR → Shift-DR (16 times) → Exit1-DR → Update-DR → Run-Test / Idle →…
[0104]
In such a state transition, the value (PC value) of the program counter 7 at that time is loaded into the serial latch in synchronization with the rising edge of the clock of the TCK signal while the TAP controller 1 is in the Captur-DR state. Specifically, in each cell 700 shown in FIG. 8, the operation in which the value of the data latch 730 is loaded into the flip-flop 732 via the multiplexer 731 is 16 bits wide because the program counter 7 is 16 bits wide. It is executed simultaneously on 16 serial registers (flip-flops 732) connected to the serial of 700 cells.
[0105]
In the next Shift-DR state after the Captur-DR state, writing to the program counter 7 is not possible, so the host computer outputs the provisional value h'ffff as the TDI signal and inputs it to the program counter 7. However, any provisional value does not affect the operation. Then, by repeating the Shift-DR state 16 times, the value of the 16-bit program counter 7 loaded in the flip-flop 732 of each cell 700 of the program counter 7 in the previous Captur-DR state is changed from the LSB side. Serial output as TDO signal. Note that nothing happens in the Update-IR state.
[0106]
When the RD_Trans instruction is set in the instruction register 2, the transfer register 6 is selected as a scan path. Then, the host computer inputs the TMS signal to the TAP controller 1 while changing the value so that the TAP controller 1 performs the following state transition.
[0107]
Run-Test / Idle → Select-DR-Scan → Captur-DR → Shift-DR (16 times) → Exit1-DR → Update-DR → Run-Test / Idle →…
[0108]
In such a state transition, the value of the transfer register 6 at that time is loaded into the serial latch in synchronization with the rising edge of the clock of the TCK signal while the TAP controller 1 is in the Captur-DR state. Specifically, in each cell 600 shown in FIG. 7, the operation in which the value of the data latch 630 is loaded into the flip-flop 632 via the multiplexer 631 is the serial number because the transfer register 6 is 16 bits wide. It is executed simultaneously on 16 serial registers connected to.
[0109]
When the RD_Trans instruction is executed, since the write to the transfer register 6 is not performed in the Shift-DR state during the state transition described above, the host computer outputs the provisional value h'ffff as the TDI signal and inputs it to the transfer register 6. . However, any provisional value does not affect the operation. Then, by repeating the Shift-DR state 16 times, the 16-bit value loaded in the flip-flop 632 of each cell 600 of the transfer register 6 in the previous Captur-DR state is serialized as a TDO signal from the LSB side. Is output. Note that nothing happens in the Update-IR state.
[0110]
Even when the WR_Trans instruction is set in the instruction register 2, the transfer register 6 is selected as the scan path as in the case of the above-described DR-Trans instruction. Then, the host computer inputs the TMS signal to the TAP controller 1 while changing the value so that the TAP controller 1 performs the following state transition.
[0111]
Run-Test / Idle → Select-DR-Scan → Captur-DR → Shift-DR (16 times) → Exit1-DR → Update-DR → Run-Test / Idle →…
[0112]
In such a state transition, the value of the transfer register 6 at that time is loaded into the serial latch in synchronization with the rising edge of the clock of the TCK signal while the TAP controller 1 is in the Captur-DR state. Specifically, in each cell 600 shown in FIG. 7, the operation in which the value of the data latch 630 is loaded into the flip-flop 632 via the multiplexer 631 is the serial number because the transfer register 6 is 16 bits wide. It is executed simultaneously on 16 serial registers connected to.
[0113]
While the state transition advances from the Captur-DR state described above and the TAP controller 1 is in the Shift-DR state, an arbitrary value can be input from the host computer to the transfer register 6 as the TDI signal. At this time, the 16-bit input value is input from the LSB side. On the other hand, by repeating the Shift-DR state 16 times, the value loaded in the flip-flop 632 of each cell 600 of the transfer register 6 in the previous Captur-DR state is serially output from the LSB side as the TDO signal. .
[0114]
The transfer register 6 enters the serial latch in synchronization with the falling edge of the TCK signal clock while the TAP controller 1 is in the Update-DR state after the state transition further proceeds from the above-mentioned Shift-DR state. Certain data (data input as a TDI signal) is transferred to the parallel output latch and set in the transfer register 6. Specifically, the data latched in the flip-flop 632 in FIG. 7 is latched in the flip-flop 633, and the output is further latched in the data latch 630 through the multiplexer 634 and the multiplexer 635. This operation is executed simultaneously for all 16-bit latches.
[0115]
The debugging apparatus of the present invention performs debugging using the above-described four private instructions, and details thereof will be described below. By the way, in general, debug devices need to set the registers in the LSI chip to be debugged, specify memory read / write, set breakpoints (PC value to stop program execution for debugging), etc. . At this time, it is necessary to perform a handshake between the LSI chip to be debugged and the host computer to be debugged.
[0116]
When the DINT flag of the flag register 5 is set during the operation of the LSI chip, the value of the program counter 7 (PC value) is set to the head address where the monitor program whose flowchart is shown in FIG. 9 is stored. The monitor program is executed. There are the following three conditions for setting the DINT flag.
[0117]
First condition: When b'1 is set to pin input DINT of LSI chip
Second condition: Breaking by PC value
Third condition: When SETDINT instruction is executed
[0118]
However, the second condition among the above three conditions is a condition for detecting and breaking when a specific address in the program memory 9 is executed (trying to execute), and is not directly related to the present invention. Therefore, the details are omitted.
[0119]
In FIG. 9, when the monitor program is executed, first, as a first procedure, context saving is performed to save in advance the register contents that may be destroyed by execution of debugging (step S11). The subsequent procedure differs depending on whether writing to the transfer register 6, reading, or end of the monitor program. In order to process this conditional branch by the monitor program, a CHCK_DINT routine (step S12) described later is used. The After execution, the start address of the program describing the desired processing is written from the host computer to the transfer register 6, and the value is transferred to the program counter (PC) 7 (step S13). As a result, the process jumps to the address describing the desired process.
[0120]
First, processing in the case of writing to the transfer register 6 will be described. This process is also used in the above-described conditional branch. Basically, a desired value may be written into the LSI chip from the host computer using the WR_Trans instruction, but it is necessary to detect the state on the LSI chip side and write it at an appropriate timing. This timing synchronization is shown in FIG.
[0121]
As shown in FIG. 11, before executing the WR_Trans instruction, the host computer issues an RD_PC instruction (step S21) and observes the execution program address of the LSI chip. On the other hand, since the monitor program as shown in FIG. 9 is executed on the LSI chip side, the process is transferred to the CHCK_DINT routine which is a temporary suspension process in the monitor program (step S14). This CHCK_DINT routine (step S100) is composed of two loops as shown in the flowchart of FIG. 10. The first loop (step S101) is waiting for DINT → b'0, and the next loop (step S100). Step S102) is waiting for DINT → b′1. Since the CHCK_DINT routine (step S100) is assigned to a fixed address in the program memory, any loop is executed by observing the PC value being executed by the RD_PC instruction from outside the LSI chip (host computer). Can be detected.
[0122]
In the monitor program, the first DINT → b′0 waiting loop is canceled when the DINT flag in the flag register 5 becomes b′0. During execution of the monitor program, the DINT flag is cleared by issuing an instruction other than the SETDINT instruction. Therefore, the DRD flag is cleared by issuing the RD_PC instruction from the host computer, and the next DINT → b'1 wait loop is entered. The DINT → b′1 waiting loop is canceled when the DINT flag in the flag register 5 becomes b′1. During execution of the monitor program, the DINT flag is set by issuing the SETDINT instruction, and the DINT → b'1 wait loop is released. In other words, the monitor program is effectively stopped by repeating the DINT → b′1 wait loop until the SETDINT instruction is issued from the host computer.
[0123]
The host computer observes the execution PC value of the LSI chip using the RD_PC instruction, confirms that the monitor program is stopped in the DINT → b'1 wait loop, and then sends the desired value to the transfer register 6 using the WR_Trans instruction (step S23). Write the value.
[0124]
After the completion of the writing of the desired value to the transfer register 6, the host computer issues a SETDINT instruction to release the loop and restart the monitor program stopped in the DINT → b'1 wait loop (step S24). ). The monitor program releases the DINT → b'1 wait loop by the SETDINT command from the host computer and continues the next processing described in the program memory. As a process of the monitor program after the writing to the transfer register 6 is completed, a process of transferring from the transfer register 6 to a register or a memory that can be transferred via a bus (internal bus 12, local bus 13) connected to the transfer register 6 is considered. (Step S15).
[0125]
A program necessary for these processes is stored in the program memory 9 in advance as a monitor program. Even if such a program is not stored in the program memory 9, if the monitor program is provided with a process for transferring the contents of the transfer register 6 to the RAM area 91 of the program memory, the program is transferred to the transfer register 6 from the host computer. It is also possible to add a monitor program by performing the writing process.
[0126]
Next, processing in the case of reading from the transfer register 6 will be described. Basically, the host computer may read the value of the transfer register 6 using the RD_Trans instruction, but it is necessary to detect the state on the LSI chip side and read it at an appropriate timing. This timing synchronization is shown in FIG.
[0127]
As shown in FIG. 12, before executing the RD_Trans instruction, the host computer issues an RD_PC instruction (step S31) and observes the execution program address of the LSI chip. On the other hand, since the monitor program as shown in FIG. 9 is executed on the LSI chip side, the process of transferring to the transfer register 6 (step S16) is executed, and then the CHCK_DINT routine (step S17) in the monitor program is executed. Processing is transferred. The process of transferring to the transfer register 6 may be a process of transferring from a register or memory that can be transferred to the transfer register 6 via a bus (internal bus 12, local bus 13) connected to the transfer register 6.
[0128]
A program necessary for these processes is stored in advance in the program memory as a monitor program. Even if such a program is not stored in the program memory 9, if the monitor program is provided with a process for transferring the contents of the transfer register 6 to the RAM area 91 of the program memory, the program is transferred to the transfer register 6 from the host computer. It is possible to add a monitor program by performing the writing process.
[0129]
The host computer observes the execution PC value of the LSI chip with the RD_PC instruction (step S31) and confirms that the monitor program is stopped in the DINT → b'1 wait loop (step S32), and then the RD_Trans instruction (step S33). ) To read the value from the transfer register 6. After the reading from the transfer register 6 is completed, the host computer issues a SETDINT instruction to release the loop and restart the monitor program stopped in the DINT → b′1 waiting loop (step S34). The monitor program releases the DINT → b'1 wait loop by the SETDINT command from the host computer and continues the next processing described in the program memory.
[0130]
Writing / reading to all registers / memory (program memory 9, internal register 10, internal memory 11, etc.) connected to transfer register 6 is possible by a combination of the above-described write / read processing to transfer register 6. It becomes. As mentioned above, in order to enable writing / reading to / from all registers / memory, it is necessary to prepare transfer processing between the transfer register 6 and all registers / memory using a monitor program. is there. However, if a process for transferring the contents of the transfer register 6 to the RAM area 91 of the program memory 9 is prepared in the monitor program, the monitor program can be added by a write process to the transfer register 6 from the host computer. Become.
[0131]
When these series of processes are completed, the monitor program ends, the register contents saved in context when the monitor program is executed are restored to the original state (step S18), and the process returns to the address before the monitor program is executed. As a method for terminating the monitor program, the start address of the context restore routine in the monitor program is written to the transfer register 6 by the writing process to the transfer register 6 from the host computer. Since the monitor program is programmed to transfer the contents of the transfer register 6 to the program counter 7 at the end of processing, the monitor program jumps to the address written in the transfer register 6. In this case, it is possible to jump to the context restore routine and return from the monitor program.
[0132]
[Embodiment 2]
The CHCK_DINT routine (FIG. 10) of the monitor program (FIGS. 9, 11, and 12) stored in the program memory 9 in the first embodiment is composed of two loops. This processing can be realized by a halt instruction for stopping the processing at a specific address in addition to a method for realizing the program by loop execution as in the first embodiment.
[0133]
In this case, two modes of releasing DINT = b′0 and releasing DINT = b′1 are necessary as modes for releasing the halt. By using the DINT = b′0 release mode halt instruction in the first loop of the CHCK_DINT routine of FIG. 10 and the DINT = b′1 release mode halt instruction in the second loop, respectively, A similar operation can be realized. FIG. 13 shows a flowchart in the case of such a halt command.
[0134]
In FIG. 13, this CHCK_DINT routine (step S200) is composed of two halt instructions. The first halt instruction (step S201) is DINT = b'0 release, and the next halt instruction (step S202) is DINT = b'1 is released. Since the CHCK_DINT routine (step S200) is assigned to a fixed address in the program memory, any halt instruction can be executed by observing the PC value being executed with the RD_PC instruction from outside the LSI chip (host computer). Can be detected.
[0135]
In the above embodiments, specific numerical values are given for the bit widths of the instruction register 2, instruction decoder 3, DINT register 4, flag register 5, transfer register 6, program counter 7, etc. It is not limited to. In each of the above embodiments, an example in which the debugging device of the present invention is connected to a host computer is shown, but the device is not limited to a host computer as long as it is a device capable of JTAG access.
[0136]
【The invention's effect】
As described above in detail, according to the debugging device of the present invention, which register or memory (program memory, internal register, internal memory, etc.) is connected to the transfer memory when writing or reading data. Since this is performed by the monitor program, there is an effect that it is possible to realize a flexible debugging device that does not require dedicated hardware and can easily change and expand the transfer source and destination.
[0137]
In addition, when reading data, it is possible to detect the end of data transfer from the register to the transfer memory and the memory (program memory to the transfer register, internal register, internal memory, etc.) by monitoring the value of the program counter. Does not require hardware.
[0138]
In addition, the program can be re-executed once execution of the program is stopped.
[0139]
Furthermore, at least a part of the contents of a plurality of storage means (internal register, internal memory) connectable to the transfer register can be output to the outside.
[0140]
In addition, any program can be externally written to the writable / readable program memory (RAM area), so the transfer program between the debug target register, memory, etc. and the transfer register can be externally written and read. It is possible to arbitrarily select a debug target by writing to a simple program memory (RAM area).
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a debugging device according to the present invention.
FIG. 2 is a state transition diagram showing a transition state of the TAP controller of the debugging device of the present invention.
FIG. 3 is a block diagram showing a configuration example of a cell of each bit constituting an instruction register of the debugging device of the present invention.
FIG. 4 is a list showing the operation of the instruction register of the debugging device of the present invention.
FIG. 5 is a list of instructions used by the debugging apparatus of the present invention.
FIG. 6 is a block diagram illustrating a configuration example of a DINT register of the debugging device according to the present invention.
FIG. 7 is a block diagram showing a configuration example of a cell of each bit constituting a transfer register of the debugging device of the present invention.
FIG. 8 is a block diagram showing a configuration example of each bit cell constituting the program counter of the debugging device of the present invention.
FIG. 9 is a flowchart of a monitor program of the debugging device of the present invention.
FIG. 10 is a flowchart of a CHCK_DINT routine according to the first embodiment of the monitor program of the debugging device of the present invention.
FIG. 11 is a flowchart of a write process to a transfer register of the debug device of the present invention.
FIG. 12 is a flowchart of a read process from a transfer register of the debug device according to the present invention.
FIG. 13 is a flowchart of a CHCK_DINT routine according to the second embodiment of the monitor program of the debugging device of the present invention.
FIG. 14 is a block diagram illustrating a configuration example of a conventional debugging device.
[Explanation of symbols]
1 TAP controller, 2 instruction register, 3 instruction decoder, 4 DINT register, 5 flag register, 6 transfer register, 7 program counter,
9 Program memory, 10 internal registers, 11 internal memory, 91 RAM area.

Claims (6)

A control circuit that operates in response to an external input signal;
An instruction register capable of inputting a predetermined instruction from the outside by controlled access to the control circuit;
An instruction decoder for decoding the contents of the instruction register;
A program counter for generating a program address to be executed, the contents of which can be output to the outside by controlled access to the control circuit;
A program memory accessed according to the value of the program counter,
The program memory stores a program including a pause process that does not execute an address after a predetermined address after the end of a specific process,
When the predetermined instruction is decoded by the instruction decoder, the control circuit accesses the program counter and outputs the value to the outside. A debugging device characterized in that the end of processing is detected. 2. The debugging apparatus according to claim 1, wherein the temporary suspension process stored in the program memory is a program that loops between predetermined addresses after the end of the specific process. 2. The debugging apparatus according to claim 1, wherein the temporary suspension process stored in the program memory is a program that waits for execution of the program at a specific address after completion of the specific process. A first register capable of holding the value of a signal input from the outside by controlled access to the control circuit;
And a second register that holds the signal value held in the first register in synchronization with an externally input signal at an arbitrary timing and releases the pause processing according to the value. The debugging device according to claim 1. It is possible to output the contents to the outside by controlled access to the control circuit, and has a transfer register that can be connected to a plurality of storage means,
The program memory stores a transfer program between at least a part of a plurality of storage means connectable to the transfer register and the transfer register,
When a predetermined instruction is decoded by an instruction decoder, the control circuit accesses the transfer register and outputs the value to the outside, so that at least a part of a plurality of storage means connectable to the transfer register 2. The debugging apparatus according to claim 1, wherein the content of the message can be output to the outside. A part of the program memory is connected to a transfer register, has an area that can be accessed by the value of the program counter, and can be written and read,
6. The debugging apparatus according to claim 5, wherein an arbitrary program can be written to the writable / readable program memory by accessing a transfer register under the control of a control circuit.

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