JP3687280B2 - Chip mounting method - Google Patents

Chip mounting method Download PDF

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Publication number
JP3687280B2
JP3687280B2 JP17674597A JP17674597A JP3687280B2 JP 3687280 B2 JP3687280 B2 JP 3687280B2 JP 17674597 A JP17674597 A JP 17674597A JP 17674597 A JP17674597 A JP 17674597A JP 3687280 B2 JP3687280 B2 JP 3687280B2
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JP
Japan
Prior art keywords
substrate
mounting
bumps
semiconductor chip
bump
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Expired - Lifetime
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JP17674597A
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Japanese (ja)
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JPH1126922A (en
Inventor
泰行 ▲高▼野
雅俊 竹田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP17674597A priority Critical patent/JP3687280B2/en
Publication of JPH1126922A publication Critical patent/JPH1126922A/en
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Publication of JP3687280B2 publication Critical patent/JP3687280B2/en
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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Description

【０００１】
【発明の属する技術分野】
本発明は、バンプ付き半導体チップを基板にフェースダウンで接続するためのチップ実装方法に関するものである。
【０００２】
【従来の技術】
バンプ付き半導体チップは、基板の小型化に有利なことから、各種コンピュータなどの多くの電子機器に多用されるようになってきている。バンプ付き半導体チップを基板に実装する方法として、従来より様々な方法が提案されている。
【０００３】
第１の方法は、ＡＣＦ（異方性導電剤）を用いる方法である。この方法は、半導体チップと基板の間にＡＣＦを介在させ、半導体チップを加熱加圧することにより、ＡＣＦに混入された導電粒子によりバンプを基板の電極に接続するものである。
【０００４】
第２の方法は、バンプを半田により形成して半田バンプとし、リフローにより半田バンプを溶融固化させて基板の電極に接続するものである。この場合、半導体チップと基板の接合力を確保するために、好ましくは半導体チップと基板の間に封止用の樹脂が封入される。
【０００５】
第３の方法は、バンプを金により形成して金バンプとし、また基板の電極上にはメッキ等により半田をプリコートする。そして上記第２の方法と同様にリフローにより半田付けし、好ましくは封止用の樹脂を封入する。
【０００６】
第４の方法は、熱圧着硬化絶縁樹脂を用いる方法である。この方法は、基板に熱圧着硬化絶縁樹脂を塗布し、半導体チップの金バンプを基板の電極上に熱圧着し、熱圧着硬化絶縁樹脂を硬化させるものである。
【０００７】
【発明が解決しようとする課題】
しかしながら上記第１の方法では、Ｎｉ粒子などの導電粒子をバンプに食い込ませるために大きな荷重を半導体チップに加える必要があり、このため基板に大きなストレスが加わって回路パターンの断線を発生しやすく、また半導体チップもダメージを受けやすい。
【０００８】
また上記第２の方法は、リフローにより半田バンプを基板の電極に接着するため、荷重ストレスはほとんどないという利点がある。しかしながら第２の方法は半田のぬれ性を確保するためにフラックスを使用する必要があり、単にフラックス塗布やフラックス洗浄等の工程が必要となるだけでなく、フラックスを使用することによる環境上の問題が発生し、さらにはマイグレーションを引き起こしやすいなどの問題点がある。また樹脂封止を行った場合には、フラックスの残査により樹脂の封入時や硬化時に樹脂の流動性が阻害されてボイドが発生しやすくなり、ボイドが発生すると熱ストレスにより半田亀裂などの問題を誘発する。
【０００９】
また上記第３の方法も半田を用いることから、第２の方法と同様の問題がある。また第４の方法は、半導体チップに大きな荷重を加えねばならないため第１の方法と同様の問題がある。以上のように、従来方法は、いずれも様々な問題点を有していた。
【００１０】
そこで本発明は、上記従来の問題点を解決するもので、低荷重実装、フラックスレス実装を可能とし接合信頼性の高いチップ実装方法を提供することを目的としている。
【００１１】
【課題を解決するための手段】
本発明は、金を材質とするバンプが形成されたチップを表面に熱圧着硬化絶縁樹脂を有する被接続母材に接続するチップ実装方法であって、前記バンプと前記被接続母材とを位置合わせした状態で前記バンプが前記被接続母材に着地する前から超音波を印加し前記熱圧着硬化絶縁樹脂を排除する加振ステップと、前記加振ステップの後に加熱して前記バンプと前記被接続母材とを接続するとともに排除された前記熱圧着硬化絶縁樹脂が硬化して前記チップと前記被接続母材とを結合する加熱ステップとを有するものである。そしてこの方法により低荷重実装、フラックスレス実装が可能となり、接合信頼性の高いチップ実装方法が得られる。
【００１２】
【発明の実施の形態】
本発明は、金を材質とするバンプが形成されたチップを表面に熱圧着硬化絶縁樹脂を有
する被接続母材に接続するチップ実装方法であって、前記バンプと前記被接続母材とを位置合わせした状態で前記バンプが前記被接続母材に着地する前から超音波を印加し前記熱圧着硬化絶縁樹脂を排除する加振ステップと、前記加振ステップの後に加熱して前記バンプと前記被接続母材とを接続するとともに排除された前記熱圧着硬化絶縁樹脂が硬化して前記チップと前記被接続母材とを結合する加熱ステップとを有する。
【００１５】
（実施の形態１）
図１は、本発明の実施の形態１のバンプ付き半導体チップの実装工程図であって、ＡＣＦによるフリップチップ実装に超音波を印加する場合の製造工程図を示すものである。
【００１６】
図１において１はＡＣＦ、２はＮｉ粒子、３は基板、４は基板３上に形成された電極、５は半導体チップ、６は半導体チップ５に形成された金バンプ、７はツールである。次に実装方法を説明する。
【００１７】
ＡＣＦ１の貼付が完了した基板３（図１（ａ））にツール７で吸着した金バンプ６の形成された半導体チップ５を位置合わせし（図１（ｂ））、ツール７に超音波とパルスヒートをかけながら加圧する（図１（ｃ））。
【００１８】
この方法によれば、Ｎｉ粒子２が金バンプ６に捕獲後、超音波を加えながら加圧していくため、超音波の振動によりＮｉ粒子２はバンプ６と基板３上に形成された電極４に食い込み易くなる。従って、従来はＮｉ粒子２を金バンプ６に食い込ませるために１バンプ当たり５０〜６０ｇの荷重を印加していたが、超音波によりＮｉ粒子２が金バンプ６及び基板３上に形成された電極４に食い込みやすくなるため、５ｇ〜６ｇ（約１／５〜１／６）の低荷重で接合が可能となる。また低荷重で半導体チップ５へのストレスも低減可能である。実際の超音波の印加方法は、超音波発信器を使用しツール７に超音波を印加し、超音波の方向はＡＣＦ１中のＮｉ粒子２を金バンプ６及び基板３上に形成された電極４に食い込ませるために各方向（Ｘ，Ｙ，Ｚ方向）併用しながら行う。
【００１９】
またこの方法はＮｉ粒子を用いたＡＣＦのみならず、樹脂ボールに金メッキ、絶縁膜を施した導電粒子を用いたＡＣＦに対しても非常に有効である。通常、このタイプのＡＣＦは実装時に高荷重をかけ絶縁膜を破り押さえつけて電気的導通をとるが、ボンディング時に超音波を併用することにより、超音波が絶縁膜を破るため低荷重化を図ることができる。
【００２０】
以上のことよりＡＣＦを用いた実装において超音波併用実装は非常に信頼性向上に有効な実装手段である。なお、超音波の印加方法はツールのみでなく、基板ステージから印加してもよく、また加熱においてもツール加熱ではなく、基板ステージからの加熱でもよい。さらに本実施の形態１ではパルスヒートツールを使用したが、常時加熱のコンスタント加熱でもよい。さらに本実施の形態１ではバンプ材質を金としているがバンプ材質に関しては金に限らず、半田、アルミ等他の金属にも適用される。
【００２１】
（実施の形態２）
図２は、本発明の実施の形態２のバンプ付き半導体チップの実装工程図であって、半田バンプを用いた実装方法を示すものである。図中、８は半導体チップ５に形成された半田バンプ、９は空気に触れることによりその表面に生じた酸化膜である。従来例で説明したように、半田バンプ８による実装では、実装荷重に関しては、基本的に基板３に低荷重（数ｇ／バンプ）で実装するため、基板３への荷重ストレスと言う点では特に大きな問題はないが、基板３上に形成された電極４への半田の濡れの向上、酸化膜９除去のために、従来はフラックスを使用していたものである。
【００２２】
本方法では、実装時にツール７に超音波とパルスヒートをかけ実装する。具体的には、半田バンプ８の形成された半導体チップ５をまず基板３の電極４と位置合わせを行い実装する（図２（ａ））。次にツール７に半導体チップ５を吸着した状態で超音波をかける（図２（ｂ））。その結果、半田バンプ８と基板３上に形成された電極４とが超音波により擦れあい、酸化膜９が除去される。酸化膜９が除去された状態でツール７をパルスヒートにて加熱することにより半田バンプ８が溶融し、酸化膜９の無い部分において基板パターンに半田８が濡れ、良好な接合が得られる（図２（ｃ））。その後、半導体チップ５と基板３の間に封止樹脂１１を封入し、接合が完了する（図２（ｄ））。
【００２３】
以上のことから半田接合においてフラックスレスが可能となり、洗浄工程が不要になる。さらにフラックス残査による封止樹脂１１の封入工程時の問題であったチップ基板間への封止樹脂１１の流れにくさによるボイドの発生の防止を図ることが可能で、信頼性が低下するといった問題が解消され、非常に信頼性の高い接合状態を得ることが可能となる。なお、この実施の形態２では封止工程を半田バンプ８と基板３との接合が完了した後行っていたが、封止樹脂１１を実装時に同時にパルスヒートで硬化させる実装方式でもよい。
【００２４】
（実施の形態３）
図３は、本発明の実施の形態３のバンプ付き半導体チップの実装工程図であって、金バンプの形成された半導体チップを半田がプリコートされた基板に実装する方法を示している。図３において、１０は基板３の電極４上にメッキ法などによる半田である。この方法においても半田を使用するという特質上、従来は半田の基板上に形成された電極への濡れの向上、酸化膜の除去のためにフラックスを使用し実装していたものである。
【００２５】
本方法では実装時にツール７に超音波とパルスヒートかけ実装する。具体的には、金バンプ６の形成された半導体チップ５をまず基板３の半田プリコートされた電極４と位置合わせを行い実装する（図３（ａ））。次にツール７に半導体チップ５を吸着した状態で超音波をかける（図３（ｂ））。その結果、金バンプ６と基板３上に形成された電極４に半田１０とが超音波により擦れあい、半田１０表面の酸化膜１１が除去される（図３（ｃ））。酸化膜９が除去された状態でツール７をパルスヒートにて加熱することにより基板３上に形成された電極４に半田１０が溶融し、酸化膜９の無い部分において金バンプ６表面に半田１０が濡れ、良好な接合が得られる。その後、封止樹脂１１で封止工程を行い接合が完了する（図３（ｄ））。
【００２６】
以上のことから実施の形態２と同様な作用効果と同等の硬化が得られる。なお、この実施の形態３では封止工程をバンプと基板との接合が完了した後行っているが（図３（ｄ））、樹脂をボンディング時に同時にパルスヒートで硬化させる実装方式でもよい。
【００２７】
（実施の形態４）
図４は、本発明の実施の形態４のバンプ付き半導体チップの実装工程図であって、金バンプの形成されたチップを熱圧着硬化絶縁樹脂を用い基板に実装する方法を示している。具体的にはツール７に吸着された金バンプ６の形成された半導体チップ５を熱圧着硬化絶縁樹脂１２が塗布された基板３上の電極４に位置合わせし実装する（図４（ａ））。次にツール７に半導体チップ５を吸着した状態で（すなわち、金バンプ６が電極４に着地する前から）超音波とパルスヒートをかける（図４（ｂ））。その結果、超音波により半導体チップ５形成された金バンプ６と基板３上に形成された電極４間の熱圧着硬化絶縁樹脂１２が周囲に排除され、金バンプ６表面と基板３上に形成された電極４の表面とが良好な接触が得られる。またパルスヒートによる加熱で熱圧着硬化絶縁樹脂１２が硬化し半導体チップ５と基板３とが固定される（図４（ｃ））。従って従来はバンプ基板の樹脂を排除するために高い荷重（約５０ｇ）をかけ実装していたが、超音波の併用により、低荷重（数ｇ／バンプ）での実装が可能であり、基板へのストレスも低減されかつチップへのストレスも低減される。
【００２８】
【発明の効果】
以上のように本発明は、バンプと前記被接続母材とを位置合わせした状態で前記バンプが前記被接続母材に着地する前から超音波を印加し前記熱圧着硬化絶縁樹脂を排除する加振ステップと、前記加振ステップの後に加熱して前記バンプと前記被接続母材とを接続するとともに排除された前記熱圧着硬化絶縁樹脂が硬化して前記チップと前記被接続母材とを結合するようにしたので、低荷重実装、フラックスレス実装が可能となり、接合信頼性の高い半導体チップの実装方法を実現できる。
【図面の簡単な説明】
【図１】本発明の実施の形態１のバンプ付き半導体チップの実装工程図
【図２】本発明の実施の形態２のバンプ付き半導体チップの実装工程図
【図３】本発明の実施の形態３のバンプ付き半導体チップの実装工程図
【図４】本発明の実施の形態４のバンプ付き半導体チップの実装工程図
【符号の説明】
１ ＡＣＦ
２ Ｎｉ粒子
３ 基板
４ 電極
５ 半導体チップ
６ 金バンプ
７ ツール
８ 半田バンプ
１０ 半田
１１ 封止樹脂
１２ 熱圧着硬化絶縁樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip mounting method for connecting a bumped semiconductor chip to a substrate face down.
[0002]
[Prior art]
Bumped semiconductor chips are advantageous in reducing the size of a substrate, and are therefore widely used in many electronic devices such as various computers. Conventionally, various methods have been proposed for mounting a bumped semiconductor chip on a substrate.
[0003]
The first method is a method using ACF (anisotropic conductive agent). In this method, an ACF is interposed between a semiconductor chip and a substrate, and the semiconductor chip is heated and pressed to connect the bumps to the electrodes of the substrate by conductive particles mixed in the ACF.
[0004]
In the second method, bumps are formed by solder to form solder bumps, and the solder bumps are melted and solidified by reflow and connected to the electrodes of the substrate. In this case, in order to ensure the bonding force between the semiconductor chip and the substrate, a sealing resin is preferably sealed between the semiconductor chip and the substrate.
[0005]
In the third method, bumps are formed of gold to form gold bumps, and solder is precoated on the electrodes of the substrate by plating or the like. In the same manner as in the second method, soldering is performed by reflow, and a sealing resin is preferably sealed.
[0006]
The fourth method is a method using a thermocompression cured insulating resin. In this method, a thermocompression-curing insulating resin is applied to a substrate, a gold bump of a semiconductor chip is thermocompression-bonded on an electrode of the substrate, and the thermocompression-curing insulating resin is cured.
[0007]
[Problems to be solved by the invention]
However, in the first method, it is necessary to apply a large load to the semiconductor chip in order to cause conductive particles such as Ni particles to bite into the bumps. Therefore, a large stress is applied to the substrate, and the circuit pattern is easily disconnected. Semiconductor chips are also susceptible to damage.
[0008]
Further, the second method has an advantage that there is almost no load stress because the solder bump is bonded to the electrode of the substrate by reflow. However, in the second method, it is necessary to use a flux in order to ensure the wettability of the solder, and not only a process such as flux application and flux cleaning is required, but also environmental problems due to the use of the flux. Occurs, and it is easy to cause migration. In addition, when resin sealing is performed, the residual resin flux prevents the fluidity of the resin during resin encapsulation or curing, and voids are likely to occur. To trigger.
[0009]
The third method also uses the solder, and therefore has the same problem as the second method. The fourth method has the same problem as the first method because a large load must be applied to the semiconductor chip. As described above, all of the conventional methods have various problems.
[0010]
SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a chip mounting method that enables low-load mounting and fluxless mounting and has high bonding reliability.
[0011]
[Means for Solving the Problems]
The present invention relates to a chip mounting method for connecting a chip on which a bump made of gold is formed to a connected base material having a thermocompression-curing insulating resin on the surface, wherein the bump and the connected base material are positioned. In the combined state, an ultrasonic wave is applied before the bumps land on the base material to be connected, and the thermocompression-cured insulating resin is removed, and heating is applied after the vibration step to heat the bumps and the substrate. wherein said chip the thermocompression bonding cured insulating resin that is eliminated with connecting the connection base material is cured is to have a heating step of combining the target connection matrix. This method enables low load mounting and fluxless mounting, and a chip mounting method with high bonding reliability can be obtained.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The present invention has a thermocompression cured insulating resin on the surface of a chip on which a bump made of gold is formed.
A chip mounting method for connecting to a base material to be connected, in which the bump and the base material to be connected are aligned and ultrasonic waves are applied before the bumps land on the base material to be connected. A vibration step for removing the pressure-curing cured insulating resin, and heating and connecting the bump and the base material to be connected after the vibration step; that having a heating step of coupling the the connected base material.
[0015]
(Embodiment 1)
FIG. 1 is a mounting process diagram of a semiconductor chip with bumps according to the first embodiment of the present invention, and shows a manufacturing process diagram when ultrasonic waves are applied to flip chip mounting by ACF.
[0016]
In FIG. 1, 1 is ACF, 2 is Ni particles, 3 is a substrate, 4 is an electrode formed on the substrate 3, 5 is a semiconductor chip, 6 is a gold bump formed on the semiconductor chip 5, and 7 is a tool. Next, the mounting method will be described.
[0017]
The semiconductor chip 5 on which the gold bump 6 adsorbed by the tool 7 is positioned is aligned with the substrate 3 (FIG. 1A) on which the ACF 1 has been attached (FIG. 1B). The pressure is applied while applying heat (FIG. 1 (c)).
[0018]
According to this method, since the Ni particles 2 are captured by the gold bumps 6 and then pressurized while applying ultrasonic waves, the Ni particles 2 are applied to the bumps 6 and the electrodes 4 formed on the substrate 3 by the vibration of the ultrasonic waves. It becomes easy to bite in. Therefore, conventionally, a load of 50 to 60 g per bump is applied to cause the Ni particles 2 to penetrate into the gold bumps 6. However, the electrodes in which the Ni particles 2 are formed on the gold bumps 6 and the substrate 3 by ultrasonic waves. Since it becomes easy to bite into 4, it becomes possible to join with a low load of 5 g to 6 g (about 1/5 to 1/6). Further, the stress on the semiconductor chip 5 can be reduced with a low load. The actual method of applying ultrasonic waves is to apply ultrasonic waves to the tool 7 using an ultrasonic transmitter. The direction of the ultrasonic waves is the Ni particles 2 in the ACF 1 and the electrodes 4 formed on the gold bumps 6 and the substrate 3. In order to bite into each other, it is performed while using each direction (X, Y, Z direction) together.
[0019]
This method is very effective not only for ACF using Ni particles but also for ACF using conductive particles in which resin balls are plated with gold and an insulating film is applied. Normally, this type of ACF applies a high load during mounting and breaks down and holds down the insulating film to establish electrical continuity. However, by using ultrasonic waves together during bonding, the ultrasonic wave breaks the insulating film, reducing the load. Can do.
[0020]
From the above, in the mounting using the ACF, the ultrasonic combined mounting is a very effective mounting means for improving the reliability. In addition, the application method of an ultrasonic wave may be applied not only from a tool but also from a substrate stage, and heating may be performed not from tool heating but from a substrate stage. Furthermore, although the pulse heat tool is used in the first embodiment, constant heating that is constantly heated may be used. Further, in the first embodiment, the bump material is gold, but the bump material is not limited to gold, but can be applied to other metals such as solder and aluminum.
[0021]
(Embodiment 2)
FIG. 2 is a mounting process diagram of the semiconductor chip with bumps according to the second embodiment of the present invention, and shows a mounting method using solder bumps. In the figure, 8 is a solder bump formed on the semiconductor chip 5, and 9 is an oxide film formed on the surface of the bump by contact with air. As described in the conventional example, in the mounting using the solder bumps 8, the mounting load is basically mounted on the substrate 3 with a low load (several g / bump). Although there is no major problem, a flux is conventionally used to improve the wetting of the solder on the electrode 4 formed on the substrate 3 and to remove the oxide film 9.
[0022]
In this method, the tool 7 is mounted by applying ultrasonic waves and pulse heat at the time of mounting. Specifically, the semiconductor chip 5 on which the solder bumps 8 are formed is first aligned with the electrode 4 of the substrate 3 and mounted (FIG. 2A). Next, ultrasonic waves are applied with the semiconductor chip 5 adsorbed to the tool 7 (FIG. 2B). As a result, the solder bumps 8 and the electrodes 4 formed on the substrate 3 are rubbed with ultrasonic waves, and the oxide film 9 is removed. When the tool 7 is heated by pulse heat in the state where the oxide film 9 is removed, the solder bumps 8 are melted, and the solder 8 is wetted to the substrate pattern in a portion where the oxide film 9 is not present, so that good bonding is obtained (FIG. 2 (c)). Thereafter, the sealing resin 11 is sealed between the semiconductor chip 5 and the substrate 3 to complete the bonding (FIG. 2D).
[0023]
From the above, fluxless is possible in solder joining, and a cleaning process is unnecessary. Furthermore, it is possible to prevent the generation of voids due to the difficulty in the flow of the sealing resin 11 between the chip substrates, which was a problem during the sealing process of the sealing resin 11 due to the flux residue, and the reliability is reduced. The problem is solved, and it is possible to obtain a very reliable bonding state. In the second embodiment, the sealing process is performed after the bonding of the solder bumps 8 and the substrate 3 is completed. However, a mounting method in which the sealing resin 11 is cured by pulse heat at the same time as mounting may be used.
[0024]
(Embodiment 3)
FIG. 3 is a mounting process diagram of a semiconductor chip with bumps according to a third embodiment of the present invention, and shows a method of mounting a semiconductor chip on which gold bumps are formed on a substrate pre-coated with solder. In FIG. 3, reference numeral 10 denotes solder on the electrode 4 of the substrate 3 by plating or the like. In this method as well, due to the use of solder, conventionally, flux has been used to improve the wetting of electrodes formed on the substrate and to remove the oxide film.
[0025]
In this method, ultrasonic waves and pulse heat are applied to the tool 7 during mounting. Specifically, the semiconductor chip 5 on which the gold bumps 6 are formed is first aligned and mounted with the solder precoated electrode 4 on the substrate 3 (FIG. 3A). Next, ultrasonic waves are applied with the semiconductor chip 5 adsorbed to the tool 7 (FIG. 3B). As a result, the solder 10 rubs against the gold bump 6 and the electrode 4 formed on the substrate 3 by ultrasonic waves, and the oxide film 11 on the surface of the solder 10 is removed (FIG. 3C). When the tool 7 is heated by pulse heat in the state where the oxide film 9 is removed, the solder 10 is melted to the electrode 4 formed on the substrate 3, and the solder 10 is applied to the surface of the gold bump 6 in a portion where the oxide film 9 is not present. Get wet and good bonding is obtained. Thereafter, a sealing process is performed with the sealing resin 11 to complete the bonding (FIG. 3D).
[0026]
From the above, the same effect and hardening as in the second embodiment can be obtained. In the third embodiment, the sealing process is performed after the bonding between the bump and the substrate is completed (FIG. 3D), but a mounting method in which the resin is cured by pulse heat at the time of bonding may be used.
[0027]
(Embodiment 4)
FIG. 4 is a mounting process diagram of a bumped semiconductor chip according to the fourth embodiment of the present invention, and shows a method of mounting a chip on which a gold bump is formed on a substrate using a thermocompression cured insulating resin. Specifically, the semiconductor chip 5 on which the gold bump 6 adsorbed by the tool 7 is formed is aligned and mounted on the electrode 4 on the substrate 3 coated with the thermocompression-curing insulating resin 12 (FIG. 4A). . Next, with the semiconductor chip 5 adsorbed on the tool 7 (that is, before the gold bumps 6 land on the electrodes 4), ultrasonic waves and pulse heat are applied (FIG. 4B). As a result, the thermocompression-curing insulating resin 12 between the gold bumps 6 formed on the semiconductor chip 5 and the electrodes 4 formed on the substrate 3 is removed to the surroundings by ultrasonic waves, and formed on the surface of the gold bumps 6 and the substrate 3. Good contact with the surface of the electrode 4 is obtained. Further, the thermocompression-curing insulating resin 12 is cured by heating by pulse heat, and the semiconductor chip 5 and the substrate 3 are fixed (FIG. 4C). Therefore, in the past, mounting was performed by applying a high load (about 50 g) in order to eliminate the resin of the bump substrate, but by using ultrasonic waves, mounting with a low load (several g / bump) is possible. The stress on the chip is also reduced, and the stress on the chip is also reduced.
[0028]
【The invention's effect】
As described above, according to the present invention , an ultrasonic wave is applied before the bumps land on the connected base material in a state where the bumps and the connected base material are aligned, and the thermocompression cured insulating resin is excluded. And after the vibration step, the bump and the to-be-connected base material are heated to connect the bump and the to-be-connected base material, and the removed thermocompression-bonding insulating resin is cured to bond the chip to the to-be-connected base material. Therefore, low-load mounting and fluxless mounting are possible, and a semiconductor chip mounting method with high bonding reliability can be realized.
[Brief description of the drawings]
FIG. 1 is a mounting process diagram of a bumped semiconductor chip according to a first embodiment of the present invention. FIG. 2 is a mounting process diagram of a bumped semiconductor chip according to a second embodiment of the present invention. 3 is a process diagram for mounting a semiconductor chip with bumps. FIG. 4 is a process diagram for mounting a semiconductor chip with bumps according to a fourth embodiment of the present invention.
1 ACF
2 Ni particle 3 Substrate 4 Electrode 5 Semiconductor chip 6 Gold bump 7 Tool 8 Solder bump 10 Solder 11 Sealing resin 12 Thermocompression cured insulating resin

Claims (1)

金を材質とするバンプが形成されたチップを表面に熱圧着硬化絶縁樹脂を有する被接続母材に接続するチップ実装方法であって、
前記バンプと前記被接続母材とを位置合わせした状態で前記バンプが前記被接続母材に着地する前から超音波を印加し前記熱圧着硬化絶縁樹脂を排除する加振ステップと、前記加振ステップの後に加熱して前記バンプと前記被接続母材とを接続するとともに排除された前記熱圧着硬化絶縁樹脂が硬化して前記チップと前記被接続母材とを結合する加熱ステップとを有することを特徴とするチップ実装方法。A chip mounting method for connecting a chip on which a bump made of gold is formed to a connected base material having a thermocompression-curing insulating resin on the surface,
An excitation step of applying ultrasonic waves before the bumps land on the connected base material in a state where the bumps and the connected base material are aligned, and excluding the thermocompression-cured insulating resin; Heating after the step to connect the bump and the base material to be connected and to cure the removed thermocompression cured insulating resin to bond the chip and the base material to be connected. A chip mounting method characterized by the above.
JP17674597A 1997-07-02 1997-07-02 Chip mounting method Expired - Lifetime JP3687280B2 (en)

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