JP3681146B2 - Television receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a television receiver. The present invention also relates to a television receiver having a diversity function.
[0002]
[Prior art]
Today, various television systems have been put into practical use, but generally commercialized television receivers are configured as receivers dedicated to the television system corresponding to a specific television system. It is. Therefore, for example, while PAL television receivers are commercialized and shipped to European countries adopting the PAL system, NTSC television receivers are commercialized and shipped to Japan and the United States adopting the NTSC system. From the beginning, television receivers are manufactured and provided for each system.
[0003]
However, such a configuration in which a television receiver is provided for each system often causes an increase in cost, and is disadvantageous for suppressing the product price. Therefore, it is important to share the components or manufacturing processes of each system receiver as much as possible.
On the other hand, an in-vehicle television receiver or the like installed or used in a mobile body, for example, a vehicle has a function of performing diversity as an anti-multipath method, and realizes an automatic tracking operation to the reception environment.
[0004]
However, since the video format signals to be received are different between the PAL television receiver and the NTSC television receiver, and the processing for performing the diversity operation must be changed accordingly, the television reception having the diversity function is required. It is not easy to share parts and the like between the systems as described above.
[0005]
More specifically, the field frequency of the PAL video format signal is 50 [Hz] and the horizontal frequency is 15.625 [kHz], whereas the field frequency of the NTSC video format signal is 59.94 [Hz], Since the horizontal frequency is 15.734 [kHz], the conditions for synchronizing the received video format signal and the diversity operation are different.
[0006]
In particular, since the duration length of the vertical synchronization signal of the PAL video format signal differs from that of the NTSC video format signal to a degree that cannot be ignored, a general timing for generating a diversity operation based on detection of the vertical synchronization signal is generally used. In the processing, it is difficult to perform the diversity operation at a constant timing in either method.
[0007]
[Problems to be solved by the invention]
Therefore, the present invention has been made in view of the above points, and the object of the present invention is to make it possible to share parts and manufacturing processes and to easily adapt to video format signals of each television system. It is an object of the present invention to provide a television receiver capable of performing the above operation.
[0008]
[Means for Solving the Problems]
A receiver according to the present invention comprises: Diversity operation according to reception status A television receiver for demodulating a composite video signal from a received signal; a designating means for designating one of the television systems; and detecting a vertical sync signal from the composite video signal and detecting a detection signal Detection means for outputting, delay means for delaying a detection signal output from the detection means, setting means for setting a delay time in the delay means according to the television system designated by the designation means, Control means for starting antenna selection processing based on the detection signal delayed by the delay means; It is characterized by having.
[0009]
In the receiver, the detection unit includes a low-pass filter that passes a low-frequency component of a signal obtained by synchronous separation from the composite video signal, and a comparison unit that compares an output of the low-pass filter with a reference value. Can be.
In the receiver, the television system specified by the specifying unit includes an NTSC system and a PAL system, and the setting unit uses the delay time when the NTSC system is specified. It may be set longer by 1 / (2fH) (fH is the horizontal synchronizing frequency of the composite video signal) than the designated case.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a schematic configuration of a diversity television receiver according to an embodiment of the present invention.
In FIG. 1, this receiver can be used, for example, for in-vehicle use, and includes four receiving antennas ANT1 to ANT4 for realizing space diversity. Each antenna is electrically connected to a switch (RF-SW) 1. Are combined.
[0012]
The switch 1 selects any one of the four antennas, and supplies an RF (Radio Frequency) signal from the selected antenna to the video signal reproduction system 2 as a received signal.
The video signal reproduction system 2 serves as a demodulating means, and a front end tuner (not shown) that converts a received signal from the switch 1 into an intermediate frequency signal, and a video intermediate frequency signal amplifier 21 that amplifies the intermediate frequency signal. And an AM detection circuit 22 that reproduces a composite video signal by demodulating the intermediate frequency signal amplified by the amplifier 21 with AM (Amplitude Modulation).
[0013]
The composite video signal is supplied to a CRT (Cathode-Ray Tube) 2x as a display device through various reproduction circuits and amplification circuits (not shown). The CRT 2x displays an image corresponding to the composite video signal. As the display device, a liquid crystal display or the like can be applied in addition to the CRT.
The received signal supplied to the video intermediate frequency signal amplifier 21 includes an audio signal in addition to the video signal. The audio intermediate frequency signal is extracted by the video intermediate frequency signal amplifier 21 and supplied to the audio signal reproduction system 3. Is done.
[0014]
The audio signal reproduction system 3 includes an audio intermediate frequency signal amplifier 31 that amplifies the audio intermediate frequency signal, and an FM detection circuit 32 that reproduces a composite audio signal by demodulating the intermediate frequency signal amplified by the amplifier 31 by FM (Frequency Modulation). Including.
The composite audio signal is supplied to a speaker 3x as an acoustic output device through various reproduction circuits and amplification circuits (not shown). The speaker 3x outputs a sound corresponding to the composite sound signal.
[0015]
The composite video signal from the video signal reproduction system 2 is controlled by the clamp circuit 40 so that the direct current (DC) potential of the sink chip becomes constant. The clamped signal is compared with a predetermined reference voltage by the waveform shaping circuit 41. A synchronizing signal is separated from the composite video signal by the clamp circuit 40 and the waveform shaping circuit 41 and is output as a composite synchronizing signal.
[0016]
The composite sync signal subjected to the sync separation is supplied to a low-pass filter (LPF) 60. The LPF 60 is provided to eliminate a component of 2fH (fH is a horizontal synchronization frequency) due to the equalization pulse. Therefore, the frequency component of fH is obtained from the output of the LPF 60.
The component of fH output from the LPF 60 is supplied to one input terminal of the phase comparator 61 that constitutes a part of the phase locked loop (PLL). The phase comparator 61 compares one input signal with the other input signal and outputs a phase difference signal corresponding to the phase difference between the two to a low-pass filter (LPF) 62. The phase difference signal that has passed through the LPF 62 is supplied to a VCO (Voltage-Controlled Oscillator) 63 as a control signal. Here, it is assumed that the VCO 63 oscillates with a center frequency of 32 fH and is deviated from the center frequency in accordance with the supplied control signal. The oscillation output signal is supplied to the control unit 5 as a master clock. On the other hand, this oscillation output signal is also supplied to the frequency divider 64. The frequency divider 64 divides the oscillation output signal from the VCO 63 by 1/32 and supplies a signal having a frequency of fH to the control unit 5 and the other input terminal of the phase comparator 61. The phase comparator 61, the LPF 62, the VCO 63, and the frequency divider 64 form a so-called phase locked loop (PLL), and generate a clock signal synchronized with the horizontal sync signal of the received composite video signal.
[0017]
Further, the composite synchronization signal output from the waveform shaping circuit 41 is also supplied to the inverting circuit 81. The composite synchronizing signal inverted by the inverting circuit 81 is supplied to one input terminal of the level comparator 83 through a low pass filter (LPF) 82.
The output signal of the LPF 82 is compared with a predetermined reference voltage level Vr by the comparator 83. The comparator 83 generates a signal that becomes a high level only when the input signal is higher than the reference voltage level Vr, and supplies this to the control unit 5. Since the LPF 82 is set to pass the vertical synchronization signal fv, the high level signal generated by the comparator 83 has a period equivalent to that of the vertical synchronization signal fv. Thus, the vertical synchronizing signal of the received signal is detected by the inverting circuit 81, the LPF 82, and the comparator 83 (hereinafter, the output signal of the comparator 83 is referred to as an equivalent vertical synchronizing signal).
[0018]
Further, the control unit 5 is given external input switching information, PAL / NTSC identification information, and the like. The external input switching information is obtained from a system operation unit (not shown). For example, when the receiver is incorporated in an in-vehicle navigation system as one source, the map information from another source, for example, a CD-ROM player is used. This corresponds to information indicating that the display is switched to the display of the television broadcast image by the receiver or vice versa.
[0019]
The PAL / NTSC identification information is for setting whether the receiver handles a PAL television signal or an NTSC television signal, and can be set by a switch 5s having a configuration as shown in the figure, for example. More specifically, one terminal of the switch 5s is connected to the other end of the resistor that is fed to one end, and the other terminal of the switch 5s is grounded. From the common connection point of the resistor and the switch, a high level signal is obtained when the switch 5s is opened, and a low level signal is obtained when the switch 5s is closed. Therefore, by using these two states as PAL / NTSC identification information, the control unit 5 can detect which method should be handled. In this embodiment, such a high level signal is defined as a PAL setting signal, and a low level signal is defined as an NTSC setting signal.
[0020]
The control unit 5 controls each unit of the receiver based on the supplied signal and given information. Such control includes a reception antenna selection process in the vertical blanking period of the composite video signal, a QV pulse generation process for generating a QV pulse for starting this antenna selection process, and the like.
1. QV pulse generation processing
FIG. 2A shows a composite synchronization signal when an NTSC television signal is received, and FIG. 2B shows a composite synchronization signal when a PAL television signal is received. In both figures, the vertical synchronization signal particularly related to the diversity operation and a portion before and after the vertical synchronization signal are shown.
[0021]
When (a) and (b) are compared, the duration of the vertical synchronization signal when the NTSC signal is received is equal to the equalization pulse 1 than the duration of the vertical synchronization signal when the PAL television signal is received. It can be seen that the period is longer by 1 / (2fH).
This means that when a diversity operation capable of supporting both types is performed, it is necessary to perform control in consideration of the difference in duration of the vertical synchronization signal.
[0022]
This point will be described in detail. In television diversity, an antenna switching operation is performed during a vertical blanking period so as not to disturb a displayed image. In this case, an antenna that exhibits the best reception state is often selected by detecting the pedestal level corresponding to the reception level (reception electric field strength) for each antenna and comparing the detection levels with each other.
[0023]
On the other hand, as shown in the figure, it has been studied to insert a multiplex broadcast signal within a vertical blanking period.
If so, the so-called receiving antenna selection process that detects and compares the pedestal level by sequentially switching the antennas and selects a good antenna is performed from the end of the vertical synchronization signal if the compatibility of both types is not considered. This may be performed within the period A in the figure before the generation of the multiplex broadcast signal.
[0024]
If compatibility between both systems is to be guaranteed without adding special control, the receiving antenna selection process may be performed within the period B in the figure, but synchronization is disturbed by random noise, multipath, etc. If an area C (hereinafter referred to as a guard area) C that is preliminarily used with a margin is arranged in consideration of the case of the antenna selection process before and after the antenna selection process, the common processing time is further shortened.
[0025]
For example, if the sampling period of each antenna reception level is 1 / (2 fH) and the guard area is provided only 1 / (2 fH) from both sides of the antenna selection processing period, synchronization of ± 1 sample is achieved by providing the guard area. Since reception level sampling can be performed even if disturbance occurs, there is no inconvenience in antenna selection processing.
[0026]
However, in order to perform a diversity operation with four standard antennas for in-vehicle use, four 1 / (2fH) periods are required, so the antenna selection process must be started at least at the point of the black triangle in the figure. In other words, the start point of the antenna selection process cannot be made common in both systems.
On the other hand, when the detection of the vertical synchronizing signal in the figure is detected by a common detection circuit for both systems, it is detected at almost the same point, for example, at the time of the white triangle in the figure, regardless of the system. Therefore, the time from the detection of the vertical synchronization signal to the start of the actual antenna selection process is not constant.
[0027]
Therefore, in this embodiment, the television system to be handled can be set. Further, when handling the NTSC signal, the timing for starting the antenna selection process is delayed by 1 / (2fH) than when the PAL signal is handled. Yes. FIG. 3 shows a configuration according to the operation principle. The QV pulse generation circuit 50 for detecting the arrival of the vertical synchronization signal from the equivalent vertical synchronization signal fv and generating a QV pulse indicating the starting point for starting the receiving antenna selection processing is obtained by the equivalent vertical synchronization signal fv and the switch 5s. PAL / NTSC identification information is provided.
[0028]
The QV pulse generation circuit 50 includes a vertical synchronization signal detection circuit 51, a selection circuit 52, and delay circuits 53 and 54.
The vertical synchronization signal detection circuit 51 detects the arrival of the vertical synchronization signal from the input equivalent vertical synchronization signal fv and generates a detection signal.
The selection circuit 52 operates as selection means for selecting whether or not to delay the generated detection signal by 1 / (2fH). This selection is made based on the PAL / NTSC identification information obtained from the switch 5s. That is, when a high level signal indicating the PAL system is input to the selection circuit 52 as a selection signal, the detection signal is output as a QV pulse without passing through the delay circuit 53, and a low level signal indicating the NTSC system is selected as the selection signal. Is input to the selection circuit 52, the detection signal is output as a QV pulse delayed by 1 / (2fH) by the delay circuit 53.
[0029]
Thereafter, the output (Q pulse) that has passed through the selection circuit 52 or the delay circuit 53 is delayed by an amount of time until the antenna selection process is actually started in the delay circuit 54, and is output as a QV pulse.
Next, FIG. 4 shows a specific circuit example. The QV pulse generation circuit 50 includes four D-type flip-flops 500 to 503, a predetermined number of D-type flip-flop groups 509, an AND circuit 504, an EXOR circuit 505, a NAND circuit 506, NOT circuits 507 and 508. Consists of.
[0030]
The clock generator 65 divides the 32 fH master clock input from the VCO 63 to generate a clock signal having a period of 1 / (2 fH). The equivalent vertical synchronizing signal fv input to the QV pulse generation circuit 50 is sampled by the D flip-flops 500 to 503 at the cycle of the 2fH clock signal. At this time, since the equivalent vertical synchronizing signal fv is already binarized by the comparison means 83, each D flip-flop samples either a signal indicating a low level (L) or a high level (H). Will be.
[0031]
The D flip-flops 500 to 502 and the AND circuit 504 operate as the vertical synchronization signal detection circuit 51 and generate a vertical synchronization signal using continuous sample data in order to suppress erroneous detection of the vertical synchronization signal due to noise or the like. To detect.
The D flip-flop 503 is for operating as the delay circuit 53. Furthermore, the EXOR circuit 505, the NAND circuit 506, and the NOT circuit 507 are for operating as the selection circuit 52.
[0032]
The operation will be described below. First, a case where the received signal is set as a PAL system will be described. A high level signal is input to one input terminal of the EXOR circuit 505 and a low level signal passed through the NOT circuit 507 is one of the NAND circuits 506. Is input to the input terminal. As a result, when the PAL system is set, when the output of the D flip-flops 502, 501, and 500 becomes L, H, and H, respectively, a high level Q pulse that indicates detection of the vertical synchronization signal is output from the AND circuit 504. Is done.
[0033]
On the other hand, when the received signal is set to be of the NTSC system, a low level signal is inputted to one input terminal of the EXOR circuit 505 and a high level signal passed through the NOT circuit 507 is inputted to one input of the NAND circuit 506. Input at the end. As a result, when the NTSC system is set, when the outputs of the D flip-flops 503, 502, 501, and 500 become L, H, H, and H, respectively, the high level indicating the detection of the vertical synchronization signal from the AND circuit 504. Q pulse is output. That is, the Q pulse is generated with a delay of 1 / (2fH) from the time when the PAL system is set.
[0034]
This is shown in the waveform diagram of FIG.
When the PAL system is selected, each input of the AND circuit 504 becomes high level and a Q pulse is output during the period of the period length of the 2fH clock signal corresponding to the circle in the figure. At this time, the output of the NAND circuit 506 is always at a high level, and in the case of the PAL system, the D flip-flop 503 is not used for detecting the vertical synchronization signal fv.
[0035]
On the other hand, when the NTSC system is selected, each input of the AND circuit 504 becomes high level and a Q pulse is output during the period of the period length of the 2fH clock signal corresponding to the triangle mark in the figure. At this time, the D flip-flop 503 is also used for the detection of the vertical synchronizing signal fv, and as a result, the detection of the vertical synchronizing signal is delayed by one clock period, that is, 1 / (2fH). .
[0036]
Therefore, when the NTSC system is selected, the Q pulse indicating the generation of the vertical synchronizing signal is delayed by one D flip-flop (1 / (2fH)) than when the PAL system is selected. It becomes possible.
The generated Q pulse is delayed by a predetermined time in the D flip-flop group 509 and output as a QV pulse. This predetermined time corresponds to the time from the detection of the Q pulse until the antenna selection process is actually started. In this example, the predetermined time is 3.5 periods of the 2fH clock signal.
[0037]
In the present embodiment, as an example, a configuration in which D flip-flops 500 to 503 are used and four D flip-flops are used is shown. However, if it is desired to further suppress false detection, the D flip-flop used here is used. It is effective to further increase the number.
In the embodiment of FIG. 4, the Q pulse is generated with a delay of one clock. However, in the case of the NTSC system, the QV pulse is 1 / (2fH compared to the PAL system. For example, the D flip-flop to be used is not to apply the delay according to the method when generating the Q pulse, but to apply the delay according to the method when generating the QV pulse. The same effect can be obtained by changing the number of groups.
[0038]
The QV pulse obtained in this way indicates the starting point of the antenna selection process described below.
2. Antenna selection process
FIG. 6 shows the configuration of the antenna selection processing circuit. This circuit bears the function of performing the diversity operation in response to the above-described QV pulse. The circuit is formed in the control unit 5 and is supplied with the composite video signal from the AM detection circuit 22 and digitalized at every sampling timing. An A / D (analog / digital) converter 510 for conversion, an evaluation circuit 511 that takes in the digital output and evaluates a digital value at each sampling timing, and an A / D conversion based on the QV pulse supplied thereto A timing generation / antenna designating circuit 512 for generating sampling timing and generating antenna switching signals SEL1 to SEL4 for the generator 510 and receiving an evaluation output of the evaluation circuit 511 and generating an antenna switching signal based on the evaluation output. Composed.
[0039]
The operation waveform of each part of this circuit is shown in FIG. First, when the QV pulse is supplied, the timing generation / antenna designating circuit 512 responds to the sampling timing signals corresponding to the four antennas with respect to the A / D converter 510 as shown in FIG. The occurrence of
In this example, it is assumed that the antenna ANT1 is selected before the QV pulse is generated. First, as shown in FIG. 7, the first sampling timing signal is the timing generation / antenna designating circuit 512 in a state where the switching signal SEL1 supplied to the switch 1 is on and the switching signals SEL2 to SEL4 are off. It is emitted from. The sampling timing signal is always issued at such a timing that the pedestal level of the received composite video signal by the selected antenna can be sampled.
[0040]
At this time, the A / D converter 510 is continuously supplied with the composite video signal received by the antenna ANT1, and the A / D converter 510 samples the pedestal level of the composite video signal received by the antenna ANT1. Therefore, the corresponding digital signal is output (see * 1). The evaluation circuit 511 takes in the digital signal output from the A / D converter 510 by the antenna ANT1, and stores the value in the internal memory in association with the antenna identification data.
[0041]
Following this level capture, the timing generation / antenna designation circuit 512 turns off the short-time switching signal SEL1, turns on the switching signal SEL2, turns off the switching signal SEL3, and turns off the switching signal SEL4 at a predetermined timing. 1 and the received output of ANT2 is supplied to the video signal reproduction system 2. In synchronization with this, a sampling timing signal is generated, and the A / D converter 510 samples the composite video signal received by the antenna ANT2. Therefore, the A / D converter 510 samples the pedestal level of the composite video signal received by the antenna ANT2, and outputs a corresponding digital signal (see * 2). The evaluation circuit 511 takes in the output digital signal of the A / D converter 510 by the antenna ANT2, and compares it with the value of the digital signal by the antenna ANT1 stored previously. As a result of the comparison, the evaluation circuit 511 discriminates a digital signal having a large value, and stores only the value of the digital signal having the large value in the internal memory in association with the corresponding antenna identification data.
[0042]
When the evaluation of the antenna ANT2 is completed, the timing generation / antenna designation circuit 512 selects the switching signal SEL1 on, the switching signal SEL2 off, the switching signal SEL3 off, and the switching signal SEL4 off before the QV pulse is generated. Return to the selected state of the antenna (ANT1 in this case).
Thereafter, the timing generation / antenna designation circuit 512 similarly turns off the short-time switching signal SEL1, turns off the switching signal SEL2, turns on the switching signal SEL3, turns off the switching signal SEL4, and switches the switch 1 at the next switching timing. Thus, the reception output of the antenna ANT3 is supplied to the video signal reproduction system 2. In synchronization with this, a sampling timing signal is generated, and the A / D converter 510 samples the composite video signal received by the antenna ANT3. Therefore, the A / D converter 510 samples the pedestal level of the composite video signal received by the antenna ANT3 and outputs a corresponding digital signal (see * 3). The evaluation circuit 511 takes in the digital signal output from the A / D converter 510 by the antenna ANT3 and compares it with the value of the digital signal stored previously. As a result of the comparison, the evaluation circuit 511 discriminates a digital signal having a large value, and stores only the value of the digital signal having the large value in the internal memory in association with the corresponding antenna identification data.
[0043]
When the evaluation of the antenna ANT3 is completed, the timing generation / antenna designating circuit 512 selects the switching signal SEL1 on, the switching signal SEL2 off, the switching signal SEL3 off, and the switching signal SEL4 off before the output QV pulse is generated. Return to the selected antenna again.
The sampling process of the ANT4 pedestal level is performed in the same manner. Similarly, at the next switching timing, the timing generation / antenna designating circuit 512 turns off the short-time switching signals SEL1 to SEL4 respectively off, off, off, and on and switches the switch 1 to reproduce the received output of the antenna ANT4 as a video signal. Supply to system 2. In synchronization with this, a sampling timing signal is generated, and the A / D converter 510 samples the composite video signal received by the antenna ANT4. Therefore, the A / D converter 510 samples the pedestal level of the composite video signal received by the antenna ANT4 and outputs a corresponding digital signal (see * 4). The evaluation circuit 511 takes in the digital signal from the antenna ANT4 and compares it with the value of the previously stored digital signal. As a result, the evaluation circuit 511 discriminates the larger value, and the value of the digital signal having the larger value is determined. Are stored in the internal memory in association with the corresponding antenna identification data.
[0044]
When the evaluation based on the digital signal by the antenna ANT4 is completed, the timing generation / antenna designating circuit 512 turns on the switching signal SEL1, turns off the switching signal SEL2, turns off the switching signal SEL3, and turns off the switching signal SEL4, before the output QV pulse is generated. Return the selected antenna to the selected state.
Thus, when the sampling processing of the pedestal level of each of the four antennas is completed, the internal memory of the evaluation circuit 511 stores the value of the pedestal level of the composite video signal received by the antenna having the highest reception level among the antennas ANT1 to ANT4. Are stored together with the corresponding antenna identification data.
[0045]
The evaluation circuit 511 refers to the contents of the internal memory, and gives an instruction to the timing generation / antenna designation circuit 512 to select the antenna corresponding to the stored antenna identification data. For example, when the final evaluation shows that the antenna with the highest reception level is the antenna ANT3, the evaluation circuit 511 sends the identification data of the antenna ANT3 to the timing generation / antenna designation circuit 512, The timing generation / antenna designating circuit 512 turns on only the switching signal SEL3 at the next switching timing. As a result, the switch 1 supplies the reception output of the antenna ANT3 to the video signal reproduction system 2 to complete the antenna selection processing, and thereafter continues to select the antenna ANT3 unless the next QV pulse is input.
[0046]
When the QV pulse is generated again, the above four sampling processes are performed from the antenna ANT3 as a starting point to perform antenna selection.
In the example described above, the internal memory of the evaluation circuit 511 is updated with the digital signal having the largest value at each sampling process. However, all the digital signal values obtained in each sampling process are stored. Of course, it is possible to compare the values stored so far after the end of the last sampling process, and to determine the value of the digital signal having the largest value among them.
[0047]
Thus, in this embodiment, even if the designated television system is changed, the QV pulse as the start signal of the antenna selection process can be always generated at a constant timing with respect to the vertical synchronizing signal end of the composite video signal. . Therefore, each process after the QV pulse generation can be shared.
In the above embodiment, the spatial diversity operation for switching the receiving antenna based on the level detection of the composite video signal has been described, but the present invention may be applied to other diversity operations.
[0048]
Further, in the above embodiment, the configurations shown in FIGS. 3 and 4 are based on hardware. However, the present invention is not limited to this, and equivalent configurations can also be realized by software executed by a microcomputer.
In addition to the above, various means have been described in a limited manner in the above embodiment, but can be appropriately modified within a range that can be designed by those skilled in the art.
[0049]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to easily provide a television receiver capable of performing an operation suitable for a video format signal of each television system, and to share components and manufacturing processes. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a diversity television receiver according to an embodiment of the present invention.
FIG. 2 is a time chart showing schematic forms of NTSC and PAL composite sync signals obtained by synchronizing and separating from composite video signals in the receiver of FIG. 1;
3 is a block diagram showing a schematic configuration of a QV pulse generation circuit 50 in the receiver of FIG. 1; FIG.
4 is a circuit diagram showing a detailed configuration of the QV pulse generation circuit 50 of FIG. 3; FIG.
5 is a time chart showing operation waveforms of respective parts of the circuit for explaining the circuit operation of FIG. 4; FIG.
6 is a block diagram showing a basic configuration of an antenna selection processing circuit formed in a control unit in the receiver of FIG. 1. FIG.
7 is a time chart showing the operation of each part of the circuit for explaining the circuit operation of FIG. 6; FIG.
[Explanation of symbols]
ANT1-ANT2 receiving antenna
1 switch
2 Video signal playback system
21 Video intermediate frequency amplifier
22 AM detector circuit
2x CRT
3 Audio signal playback system
31 Audio intermediate frequency amplifier
32 FM detector circuit
3A distortion detection circuit
3x speaker
40 Clamp circuit
41 Waveform shaping circuit
5 Control unit
5s DIP switch
60 LPF
61 Phase comparator
62 LPF
63 VCO
64 divider
81 Inversion circuit
82 LPF
83 level comparator
50 QV pulse generation circuit
51 Vertical synchronization signal detection circuit
52 selection circuit
53, 54 delay circuit
500-503 D-type flip-flop
504 AND circuit
505 EX-OR circuit
506 NAND circuit
507,508 NOT circuit
509 D-type flip-flop stage
510 A / D converter
511 Evaluation circuit
512 Timing generation / antenna designation circuit

Claims (3)

A television receiver that performs a diversity operation according to a reception state ,
Demodulation means for demodulating the composite video signal from the received signal;
A designation means for designating one of the television systems;
Detection means for detecting occurrence of a vertical synchronization signal from the composite video signal and outputting a detection signal;
Delay means for delaying a detection signal output from the detection means;
Setting means for setting a delay time in the delay means according to the television system designated by the designation means;
Control means for starting antenna selection processing based on the detection signal delayed by the delay means;
A television receiver comprising: The detection means includes
A low-pass filter that passes a low-frequency component of a signal obtained by synchronizing and separating from the composite video signal;
A comparison means for comparing the output of the low-pass filter with a reference value;
The television receiver according to claim 1, further comprising: Television systems specified by the specifying means include NTSC system and PAL system,
The setting means sets the delay time longer by 1 / (2fH) (fH is the horizontal synchronization frequency of the composite video signal) when the NTSC system is specified than when the PAL system is specified. The television receiver according to claim 1 or 2.

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