JP3678972B2 - Receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving apparatus, and more particularly, to a receiving apparatus used for OFDM mobile communication and a synchronization acquisition method thereof.
[0002]
[Prior art]
Conventionally, in a synchronization acquisition method in OFDM mobile communication, a method of averaging and using symbol synchronization timing detected from a plurality of frames has been proposed as a method for reducing an error in symbol synchronization timing.
[0003]
Hereinafter, a receiving apparatus and a synchronization acquisition method thereof in conventional OFDM mobile communication will be described with reference to FIGS. FIG. 13 is a schematic diagram showing an example of a frame format in OFDM mobile communication, and FIG. 14 is a principal block diagram showing a schematic configuration of a conventionally proposed receiving apparatus.
[0004]
In FIG. 13, (a) and (b) are examples of frame formats. The frame format shown in FIG. 13 (a) is an AGC symbol 11, a phase reference symbol 12, a guard interval 13, and an effective symbol. 14. Here, the phase reference symbol 12 is, for example, a pilot symbol.
[0005]
The frame format shown in FIG. 13B includes an AGC symbol 11, a synchronization symbol 15, a phase reference symbol 12, a guard interval 13, and an effective symbol 14. Here, the first half of the AGC symbol 11 is the same signal as the first half of the synchronization symbol 15, and the second half of the AGC symbol 11 is a signal obtained by inverting the polarity of the second half of the synchronization symbol 15.
[0006]
In FIG. 14, the antenna 21 receives a radio signal, and the A / D unit 22 performs A / D conversion processing on the received signal.
[0007]
The symbol synchronizer 23 A) a method of calculating a correlation value between a known symbol in a received signal and a known symbol held in advance and detecting a timing for obtaining a maximum correlation value (hereinafter referred to as “first scheme”) B) Using any one of methods for calculating the correlation value between the received signal and the signal obtained by delaying the received signal by one symbol and detecting the timing for obtaining the maximum correlation value (hereinafter referred to as “second scheme”), The timing at which the integrated value of the correlation values is maximized, that is, the symbol synchronization timing is detected and output to the counter unit 24.
The symbol synchronization unit 23 will be described in detail later.
[0008]
Here, since the first method calculates the correlation value between the received signal and the known symbol, the synchronization pull-in can be performed with higher accuracy than the second method when the channel quality is good. On the other hand, since the second method calculates the correlation value between the received signals, when the line quality is poor, the synchronization pulling can be performed with higher accuracy than the first method. In view of this, the symbol synchronization unit 23 calculates the correlation value using the second method when the channel quality is poor, and calculates the correlation value using the first method when the channel quality is good. Thus, the first method and the second method may be switched and used. Note that when the channel quality is poor, for example, when the frequency offset is not sufficiently compensated immediately after the start of communication and phase rotation occurs in the received signal, and when the channel quality is good, for example, When the frequency offset is sufficiently compensated for a while after the start of communication and no phase rotation occurs in the received signal.
[0009]
The counter unit 24 is a counter that circulates a count value at an arbitrary interval with a period corresponding to one frame length, for example, starting from the beginning of the frame of the received signal, and integrates correlation values output from the symbol synchronization unit 23. The count value is latched at the timing when the value becomes maximum, and the count value is output to the counter averaging unit 25.
[0010]
The counter averaging unit 25 calculates an average value of the count values latched by the counter unit 24 at a predetermined time interval that is arbitrarily set, and outputs the average value to the timing generation unit 26.
[0011]
The timing generation unit 26 generates a control signal indicating symbol synchronization timing based on the average value of the count values output from the counter average unit 25 and outputs the control signal to the FFT unit 27.
[0012]
The FFT unit 27 performs FFT (fast Fourier transform) processing on the received signal after the A / D conversion processing in synchronization with the symbol synchronization timing output from the timing generation unit 26. Thereafter, the demodulator 28 performs demodulation processing, and the determination unit 29 performs determination to obtain a demodulated signal.
[0013]
Next, the symbol synchronization unit 23 will be described in detail with reference to FIGS. 15 to 17. First, the symbol synchronizer 23 using the conventionally proposed first method will be described. FIG. 15 is a principal block diagram showing a schematic configuration of the symbol synchronization unit 23 using the conventionally proposed first method. In FIG. 15, an IFFT (Inverse Fast Fourier Transform) unit 31 performs IFFT processing on a known symbol held in advance.
[0014]
The hard decision unit 32 performs a hard decision on each signal after IFFT processing, and outputs a decision result consisting of 1 bit to a multiplier 34 described later.
[0015]
The hard decision unit 32 is provided to reduce the amount of calculation in a multiplier 34 described later, and the output of the IFFT unit 31 may be output to the multiplier 34 described later as it is.
[0016]
A plurality of delay units 33 are provided, and these are cascade-connected. The input received signal after A / D conversion processing is delayed for a predetermined time and output to the delay unit 33 of the next stage. It outputs to the multiplier 34 provided correspondingly.
[0017]
Each of the multipliers 34 receives a signal corresponding to the delay time in the delay unit 33 among the signals of the known symbol portion in the received signal, and multiplies the output bits of the hard decision unit 32.
[0018]
The adder 35 is provided corresponding to the delay unit 33 and the multiplier 34, calculates the sum of correlation results output from the multipliers 34, and outputs the result to the maximum value detection unit 36.
[0019]
The maximum value detection unit 36 detects a timing at which the calculated integrated value of the correlation values is maximum, that is, a symbol synchronization timing, and outputs it to the counter unit 24. Note that, according to the first method, the integrated value of the correlation values between the known symbols in the received signal and the known symbols held in advance is maximized at the head of the guard interval.
[0020]
Next, another symbol synchronization unit 23 using the conventionally proposed first method will be described. FIG. 16 is a principal block diagram showing another schematic configuration of the symbol synchronization unit 23 using the conventionally proposed first method. However, components having the same configuration as the symbol synchronization unit 23 in FIG.
[0021]
In FIG. 16, the hard decision result in the hard decision unit 32 is output to each correlation value calculation unit 41. Each correlation value calculation unit 41 includes a polarity inverter 42 and a selector unit 43 that uses the output of the hard decision unit 32 as a switching control signal.
[0022]
Each correlation value calculation unit 41 receives a signal corresponding to the delay time in the delay unit 33 among the signals of the known symbol portion in the received signal, and calculates the correlation value by multiplying the output bit of the hard decision unit 32. Output the equivalent value.
[0023]
That is, based on the hard decision result output from the hard decision unit 32, the selector unit 43 outputs the input signal to the correlation value calculation unit 41 as a correlation value as it is when the hard decision result is “1”. When the determination result is “−1”, a signal obtained by inverting the polarity of the input signal to the correlation value calculation unit 41 that is the output of the polarity inverter 42 is output as a correlation value.
[0024]
In this way, in the conventionally proposed first method, the symbol synchronization timing used as the FFT processing start timing is obtained by taking a correlation between the known symbol in the received signal and the known symbol held in advance.
[0025]
In addition, by performing a hard decision on the known symbol held in advance after IFFT processing and outputting it to the multiplier, only one bit representing the hard decision result is used in the multiplier instead of the known symbol after the IFFT processing consisting of a plurality of bits. Since it is used for multiplication processing, the amount of calculation can be reduced.
[0026]
Further, by adopting the configuration as shown in FIG. 16, the circuit scale can be reduced and the processing speed can be improved.
[0027]
Next, the symbol synchronization unit 23 using the conventionally proposed second method will be described. FIG. 17 is a principal block diagram showing a schematic configuration of the symbol synchronization unit 23 using the conventionally proposed second method.
[0028]
In FIG. 17, the delay unit 51 delays the received signal after A / D conversion processing by one symbol, and the multiplying unit 52 is the received signal that is the output of the A / D unit 22 and the output of the delay unit 51. The received signal delayed by one symbol is multiplied and a correlation value is calculated.
[0029]
The integrating unit 53 integrates the outputs of the multiplying unit 52, and the maximum value detecting unit 54 detects the timing at which the integrated value of the calculated correlation value is maximum, that is, the symbol synchronization timing, and outputs it to the counter unit 24. Note that, according to the second method, the integration result of the correlation value between the received signal and the signal obtained by delaying the received signal by one symbol is maximized at the head of the guard interval.
[0030]
Thus, in the conventionally proposed second method, the symbol synchronization timing used as the FFT processing start timing is obtained by taking a correlation between the received signal and the signal obtained by delaying the received signal by one symbol.
[0031]
In the above two systems, a pilot symbol can be used as a known symbol, and a dedicated synchronization symbol provided in the previous stage of the pilot symbol can also be used.
[0032]
As described above, according to the conventionally proposed receiving apparatus, it is possible to reduce the symbol synchronization timing error to some extent by averaging and using the symbol synchronization timing detected from a plurality of frames.
[Problems to be solved by the invention]
However, in the conventionally proposed receiving apparatus, all symbol synchronization timings detected from a plurality of frames are averaged and used without considering the influence of delayed waves in a multipath environment. There is a problem that the synchronization timing error becomes large. In other words, in a multipath environment, there is a case where a backward error becomes large with respect to the symbol synchronization timing detected from the delayed wave frame. As for the symbol synchronization timing after conversion, the backward error becomes large, and there is a problem that good symbol synchronization acquisition characteristics (synchronization acquisition accuracy) cannot be obtained.
[0033]
The present invention has been made in view of such a point, and an object thereof is to provide a receiving apparatus having improved symbol synchronization pull-in characteristics.
[0034]
[Means for Solving the Problems]
In the multipath environment, the present inventor has the reason that the error behind the averaged symbol synchronization timing becomes large regardless of the magnitude of the error behind the symbol synchronization timing of each frame. Focusing on the fact that averaging is performed using all symbol synchronization timings detected from the frame, averaging is performed by excluding symbol synchronization timings with large backward errors and averaging. The present inventors have found that the backward error of the symbol synchronization timing can be reduced.
[0035]
  That is,In the present inventionThe symbol synchronization timing is averaged using only the symbol synchronization timing within a specific time range, excluding the ones with large backward errors detected from multiple frames.To do.
[0058]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0059]
(Embodiment 1)
The receiving apparatus according to the first embodiment of the present invention averages the symbol synchronization timing by excluding the symbol synchronization timing having a large backward error that exceeds an arbitrary threshold value.
[0060]
Hereinafter, the receiving apparatus according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a principal block diagram showing a schematic configuration of the receiving apparatus according to the first embodiment of the present invention.
[0061]
In FIG. 1, an antenna 101 receives a radio signal, and an A / D unit 102 performs A / D conversion processing on the received signal.
[0062]
Symbol synchronization section 103 calculates a correlation value between a known symbol in the received signal and a known symbol held in advance, and detects the timing for obtaining the maximum correlation value, that is, the first method described above or the received signal A method of calculating a correlation value with a signal obtained by delaying a received signal by one symbol and detecting a timing for obtaining a maximum correlation value, that is, a timing at which an integrated value of correlation values becomes maximum using the above-described second method. Detect and output to the counter unit 104.
[0063]
The counter unit 104 is a counter that circulates a count value at an arbitrary interval with a period corresponding to one frame length starting from the beginning of the frame of the received signal, for example, and integrates the correlation values output from the symbol synchronization unit 103 The count value is latched at the timing when the value becomes maximum.
[0064]
The switch 105 is connected and controlled so that only a specific count value among the count values latched by the counter unit 104 is output to the counter averaging unit 107.
[0065]
The comparison unit 106 compares the count value latched by the counter unit 104 with an arbitrary threshold value stored in advance, and controls connection of the switch 105 based on the comparison result. That is, the comparison unit 106 disconnects the switch 105 when the count value exceeds the arbitrary threshold value. The comparison unit 106 may connect the switch 105 when the count value is equal to or less than the arbitrary threshold value.
As a result, it is possible to exclude symbol synchronization timing with a large backward error. That is, only the symbol synchronization timing (symbol synchronization timing with a small backward error) within a specific time range is selected.
[0066]
The counter average unit 107 calculates an average value for count values equal to or less than an arbitrary threshold value that has passed through the switch 105 at a predetermined time interval that is arbitrarily set, and outputs the average value to the timing generation unit 108. That is, the counter averaging unit 107 calculates an average value of the symbol synchronization timing using only the symbol synchronization timing (symbol synchronization timing with a small backward error) within a specific time range.
[0067]
Timing generation section 108 generates a control signal indicating symbol synchronization timing based on the average value of the count values output from counter averaging section 107 and outputs the control signal to FFT section 109.
[0068]
The FFT unit 109 performs FFT (Fast Fourier Transform) processing on the received signal after A / D conversion processing in synchronization with the symbol synchronization timing output from the timing generation unit 108. Thereafter, the demodulation unit 110 performs demodulation processing, and the determination unit 111 performs determination to obtain a demodulated signal.
[0069]
Next, the operation of the receiving apparatus having the above configuration will be described.
The OFDM signal received by the antenna 101 is converted into a digital signal by the A / D unit 102.
[0070]
For the received signal, the symbol synchronization unit 103 calculates the correlation value using the first method or the second method, detects the timing at which the accumulated correlation value takes the maximum value, and outputs it to the counter unit 104. The counter unit 104 latches the count value at the detection timing.
[0071]
Of the latched count value, only a count value equal to or smaller than an arbitrary threshold value passes through the switch 105, thereby eliminating a symbol synchronization timing with a large backward error. Then, the counter averaging unit 107 calculates an average value of the symbol synchronization timing using only the symbol synchronization timing with a small backward error.
[0072]
Thereafter, the timing generation unit 108 generates a control signal indicating the symbol synchronization timing based on the average value, and outputs the control signal to the FFT unit 109, which is used as the FFT processing start timing for the received signal.
[0073]
Thus, according to the present embodiment, symbol synchronization timing is excluded by using only symbol synchronization timing with small backward error, excluding symbol synchronization timing with large backward error exceeding an arbitrary threshold. Since the timing is averaged, it is possible to prevent a backward error from becoming large with respect to the symbol synchronization timing after the averaging, and it is possible to improve symbol synchronization pull-in characteristics.
[0074]
(Embodiment 2)
The receiving apparatus according to the second embodiment of the present invention has substantially the same configuration as that of the first embodiment, and differs in that the threshold value is variable according to the line quality.
[0075]
When the channel quality is deteriorated, the symbol synchronization timing with a large backward error that exceeds an arbitrary threshold value increases. Therefore, if the threshold value is fixed, the number of symbol synchronization timings used for averaging the symbol synchronization timings decreases, and therefore the backward error increases for the symbol synchronization timings after averaging. It may end up.
[0076]
Hereinafter, the receiving apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a principal block diagram showing a schematic configuration of the receiving apparatus according to the second embodiment of the present invention. However, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0077]
In FIG. 2, the selector unit 201 uses the channel quality information detected by a detection unit (not shown) as a switching control signal, and outputs a threshold value A to the comparison unit 106 when the channel quality is poor. The threshold value B is output to the comparison unit 106.
[0078]
Here, as threshold values, two values of threshold value A and threshold value B (threshold value A> threshold value B) are provided, and threshold value A is set when the line quality is poor. The number of count values input to the counter average unit 107 is increased, and when the line quality is good, the number of count values input to the counter average unit 107 is decreased using the threshold value B. .
[0079]
Since various methods have already been proposed for obtaining channel quality information, detailed description thereof is omitted here. For example, a difference between an input signal and an output signal of the determination unit 111, that is, a determination error is used. Alternatively, a determination result of a so-called CRC check or the like may be used.
[0080]
Thus, according to the present embodiment, when the channel quality is poor, the number of symbol synchronization timings used for the averaging process is increased by increasing the threshold value. Symbol synchronization pull-in characteristics can be improved.
[0081]
Here, a case has been described in which a large and small binary value is provided as a threshold value that is stored in advance and used selectively. However, the present invention is not limited to this, and the counter average unit 107 increases as the line quality deteriorates. If the number of count values input to can be increased, the number of threshold values and each value can be arbitrarily determined.
[0082]
(Embodiment 3)
The receiving apparatus according to the third embodiment of the present invention has substantially the same configuration as that of the second embodiment, and is different in that the line quality information is used after averaging for a plurality of frames.
[0083]
Hereinafter, the receiving apparatus according to the third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a principal block diagram showing a schematic configuration of the receiving apparatus according to the third embodiment of the present invention. However, the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0084]
In FIG. 3, the quality information averaging unit 301 averages the line quality information detected for each frame by a detection unit (not shown) for a plurality of frames, and outputs the averaged quality information to the selector unit 201.
[0085]
As described above, according to the present embodiment, since channel quality information detected in a plurality of frames is averaged before use, channel quality estimation accuracy is improved, threshold setting is performed more appropriately, and symbol synchronization is performed. The pull-in characteristics can be improved.
[0086]
(Embodiment 4)
The receiving apparatus according to the fourth embodiment of the present invention has substantially the same configuration as that of the first embodiment, and the count value output from the counter unit 104 this time is used to calculate the average value of the count values in the counter average unit 107. And the point that the weighted average with the average count value output from the previous counter average unit 107 is performed.
[0087]
Hereinafter, the receiving apparatus according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a principal block diagram showing a schematic configuration of the counter averaging unit 107 of the receiving apparatus according to the fourth embodiment of the present invention.
[0088]
Increasing the number of count values for averaging processing can reduce the backward error in symbol synchronization timing, but increases the required memory capacity. Thus, in the present embodiment, the count value is averaged using the following equation.
ave {C (n)} = (l−α) × ave {C (n−1)} + α × C (n) (1)
Here, C (n) is the count value output from the current counter unit 104, ave {C (n)} is the average count value output from the current counter average unit 107, and ave {C (n-1). } Represents the average count value output from the previous counter averaging unit 107, and α represents a coefficient (for example, 0.1) used for the weighted averaging process. Note that n is an integer value of 0, 1, 2,.
[0089]
The configuration and operation of the counter averaging unit 107 for realizing the above equation (1) will be described. The multiplier 401 multiplies the count value C (n) output from the counter unit 104 this time by α (for example, 0.1). This corresponds to α × C (n) in the above formula (1).
[0090]
The memory 402 is a memory for storing the average count value ave {C (n−1)} output from the previous counter average unit 107. The average count value ave {C (n−1)} output from the previous counter averaging unit 107 is multiplied by l−α (for example, 0.9) by the multiplier 403. This corresponds to (l−α) × ave {C (n−1)} in the above formula (1).
[0091]
The adder 404 adds the output of the multiplier 401 and the output of the multiplier 403, and outputs an average count value ave {C (n)}.
[0092]
Thus, according to the present embodiment, the count value C (n) output from the current counter unit 104 and the average count value ave {C (n−1)} output from the previous counter averaging unit 107 When the weighted average is performed, it is only necessary to store the average count value ave {C (n−1)} output from the previous counter average unit 107 in the memory. Therefore, averaging is performed using a plurality of count values. When performing processing, it is possible to improve the symbol synchronization pull-in characteristics without increasing the memory capacity.
[0093]
(Embodiment 5)
The receiving apparatus according to the fifth embodiment of the present invention has substantially the same configuration as that of the fourth embodiment, and is different in that the coefficient used for the weighted average is variable.
[0094]
Hereinafter, the receiving apparatus according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a principal block diagram showing a schematic configuration of the counter averaging unit 107 of the receiving apparatus according to the fifth embodiment of the present invention. However, the same components as those in the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0095]
The smaller the value of the coefficient used for the weighted averaging process, the smaller the backward error in the symbol synchronization timing after the averaging process, but the convergence speed becomes slower. Further, the larger the value of the coefficient, the faster the convergence speed, but the larger the error. Therefore, in the present embodiment, the value of the coefficient is set to a large value α (for example, 0.5) for the first few count values, and to a small value β (for example, 0.1) thereafter. .
[0096]
The switch 501 outputs a large value α (for example, 0.5) to the first few count values and a small value β (for example, 0.1) to the multiplier 401 thereafter. Similarly, the switch 502 outputs 1-α (for example, 0.5) to the multiplier 403 for the first few count values and 1-β (for example, 0.9) thereafter. To.
[0097]
As described above, according to the present embodiment, since the coefficient used for the weighted average is made variable, both the reduction of the symbol synchronization timing error after the averaging process and the increase of the convergence speed are achieved as compared with the fourth embodiment. be able to.
[0098]
(Embodiment 6)
The receiving apparatus according to the sixth embodiment of the present invention has substantially the same configuration as that of the fourth embodiment, and differs in that the coefficient used for the weighted average is a value that can be realized by a bit shift and an adder.
[0099]
Hereinafter, the receiving apparatus according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a principal block diagram showing a schematic configuration of the counter averaging unit 107 of the receiving apparatus according to the sixth embodiment of the present invention. However, the same components as those in the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0100]
If the bit shift operation is used, the count value can be halved by shifting the count value to the right by 1 bit, and by shifting the count value to the right by 2 bits, the value can be increased by 0.25 times and to the right by 3 bits. By shifting, the value can be increased by 0.125 times. Therefore, by using this, the value of the coefficient α used for the weighted averaging process in the above equation (1) is set to a value that can be realized by bit shift and addition (for example, 0.25). Multipliers can be omitted.
[0101]
The 2-bit shifter 601 shifts the count value output from the counter unit 104 this time to the right by 2 bits, and multiplies the count value by 0.25. The 2-bit shifter 602 and the 1-bit shifter 603 shift the average count value output from the previous counter averaging unit 107, which is the output of the memory 402, by 2 bits to the right and 1 bit to the right, respectively. 25 times and 0.5 times.
[0102]
The adder 604 adds the outputs of the 2-bit shifter 602 and the 1-bit shifter 603 to generate a count value that is 0.75 times the average count value output from the previous counter averaging unit 107. Finally, the adder 404 adds the output of the 2-bit shifter 601 and the output of the adder 604, whereby the above equation (1) when α = 0.25 can be realized on the circuit. .
[0103]
As described above, according to the present embodiment, when the weighted average is performed in the counter average unit 107, the weighted average can be performed only by the bit shift and the adder without using the multiplier. Compared with the fourth embodiment and the fifth embodiment, the circuit scale can be reduced.
[0104]
The receiving apparatus according to the first to sixth embodiments can be applied to a communication terminal apparatus such as a mobile station apparatus or a base station apparatus in a wireless communication system. In this case, since the communication terminal apparatus and the base station apparatus are equipped with a receiving apparatus that can improve the symbol synchronization pull-in characteristics, errors during communication can be reduced and communication quality can be improved.
[0105]
In the first to sixth embodiments, a pilot symbol can be used as a known symbol, and a dedicated synchronization symbol provided in the previous stage of the pilot symbol can also be used.
[0106]
In the first to sixth embodiments, the configuration of the symbol synchronization unit 103 may be a configuration using the first scheme or a configuration using the second scheme. Further, in Embodiments 1 to 6 above, the configuration of symbol synchronization section 103 is such that the correlation value is calculated using the second method when the channel quality is poor, and the first value is used when the channel quality is good. A configuration may be adopted in which the first method and the second method are switched and used such that the correlation value is calculated using the method.
[0107]
(Embodiment 7)
In Embodiments 1 to 6 described above, symbol synchronization timing (count value) exceeding a certain upper limit value (threshold value) is not used for averaging of symbol synchronization timing. However, in this case, the averaging parameter decreases. For example, when averaging using 16 frames, if the number of frames for which the symbol synchronization timing exceeds the threshold is 6, the averaging parameter is 10. In order to improve the accuracy of the symbol synchronization timing (and hence the accuracy of the symbol synchronization acquisition characteristic), it is preferable that the averaging parameter is large.
[0108]
Therefore, in the present embodiment, for symbol synchronization timing exceeding a certain upper limit value, this upper limit value is used as the symbol synchronization timing. Hereinafter, the receiving apparatus according to the present embodiment will be described with reference to FIG. FIG. 7 is a block diagram showing a configuration of a receiving apparatus according to the seventh embodiment of the present invention. 7 that are the same as those in the first embodiment (FIG. 1) are denoted by the same reference numerals as those in FIG. 1 and will not be described in detail.
[0109]
In Embodiments 1 to 6 described above, the case of excluding symbol synchronization timing having a large backward error has been described. However, in the present embodiment, symbol synchronization timing having a large backward error is excluded. A case will be described in which not only the symbol synchronization timing with a large forward error is excluded.
Referring to FIG. 7, the count value latched by the counter unit 104 is sent to the comparison unit 701 and the selection unit 702. A first upper limit value is input to the comparison unit 701 and the selection unit 702.
[0110]
First, the comparison unit 701 subtracts the reference count value (reference value) from the count value latched by the counter unit 104. Hereinafter, the absolute value of this result is referred to as “timing error”. The reference count value can be changed as appropriate.
[0111]
Second, the comparison unit 702 compares the timing error with the first upper limit value, and controls the output operation of the counter value to the counter averaging unit 107 by the selection unit 702 based on the comparison result. That is, the comparison unit 702 outputs the counter value for which the timing error is equal to or less than the first upper limit value to the counter averaging unit 107 as it is, and conversely, for the counter value for which the timing error exceeds the first upper limit value, Instead, the selection unit 702 is controlled to output the first upper limit value to the counter averaging unit 107.
[0112]
The selection unit 702 outputs either the count value latched by the counter unit 104 or the first upper limit value to the counter averaging unit 702 according to the control by the comparison unit 702 as described above. However, when the selection unit 702 outputs the first upper limit value to the counter average unit 702 and the count value is smaller than the reference count value, the selection unit 702 sets the first upper limit value to a negative value.
[0113]
A specific example of the value output from the selection unit 702 to the counter averaging unit 107 is as follows. Here, the first upper limit value is “3” as an example, but the first upper limit value is not limited.
(1) When count value−reference count value ≦ −3; −3
(2) When count value-reference count value = -2: -2
(3) Count value−reference count value = −1; −1
(4) Count value−reference count value = 0; 0
(5) Count value−reference count value = 1; 1
(6) When count value-reference count value = 2: 2
(7) Count value−reference count value ≧ 3; 3
Here, (1) to (3) correspond to the case where the symbol synchronization timing has shifted forward, and (5) to (7) correspond to the case where the symbol synchronization timing has shifted backward.
[0114]
Thereafter, the counter averaging unit 107 calculates the average value using the count value or the first upper limit value from the selection unit 702 at an arbitrarily set fixed time interval, as in the first to sixth embodiments. The calculated average value is output to the timing generation unit 108.
[0115]
Thus, according to the present embodiment, when a symbol synchronization timing exceeding a certain upper limit value occurs, this symbol synchronization timing is not used for averaging, but instead of this symbol synchronization timing, the above symbol synchronization timing is used. By performing averaging using the upper limit value, it is possible to prevent the averaging parameter from decreasing. As a result, the accuracy of the symbol synchronization timing, and hence the accuracy of the symbol synchronization pull-in characteristics, can be improved.
[0116]
(Embodiment 8)
In the present embodiment, a case will be described where, in the seventh embodiment, different upper limit values are used when the symbol synchronization timing is shifted backward and when shifted forward.
[0117]
Under a multipath environment, in general, the probability that the symbol synchronization timing is shifted backward is higher than the probability that the symbol synchronization timing is shifted forward. Further, when the symbol synchronization timing is shifted backward, the value shifted becomes large.
[0118]
Therefore, different upper limit values should be prepared for each of the case where the symbol synchronization timing is shifted backward and forward (specifically, the upper limit value when the symbol synchronization timing is shifted backward). By setting the value to a large value, the accuracy of the averaged symbol synchronization timing can be further improved.
[0119]
Hereinafter, the receiving apparatus according to the present embodiment will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration of a receiving apparatus according to the eighth embodiment of the present invention. In addition, about the structure similar to Embodiment 7 (FIG. 7) in FIG. 8, the code | symbol same as the thing in FIG. 7 is attached | subjected, and detailed description is abbreviate | omitted.
[0120]
Referring to FIG. 8, the count value latched by the counter unit 104 is sent to the first comparison unit 801, the second comparison unit 802, and the selection unit 803. The first upper limit value is input to the first comparison unit 801 and the selection unit 803, and the second upper limit value is input to the second comparison unit 802 and the selection unit 803.
[0121]
First, the first comparison unit 801 first subtracts the count value latched by the counter unit 104 from the reference count value. Hereinafter, this result is referred to as “front timing error”.
[0122]
Second, the first comparison unit 801 compares the forward timing error with the first upper limit value, and controls the output operation of the counter value to the counter averaging unit 107 by the selection unit 803 based on the comparison result. That is, the first comparison unit 801 outputs the counter value whose forward timing error is a positive number equal to or less than the first upper limit value to the counter averaging unit 107 as it is, and conversely, the front timing error exceeds the first upper limit value. For the counter value, the selection unit 803 is controlled to output the first upper limit value to the counter averaging unit 107 instead of the counter value.
[0123]
First, the second comparison unit 802 subtracts the reference count value from the count value latched by the counter unit 104. Hereinafter, this result is referred to as “rear timing error”.
[0124]
Secondly, the second comparison unit 802 compares the backward timing error with the second upper limit value, and controls the output operation of the counter value to the counter averaging unit 107 by the selection unit 803 based on the comparison result. In other words, the second comparison unit 802 outputs the counter value whose positive timing error is a positive number equal to or smaller than the second upper limit value to the counter averaging unit 107 as it is, and conversely, the rear timing error exceeds the second upper limit value. For the counter value, the selection unit 803 is controlled to output the second upper limit value to the counter averaging unit 107 instead of the counter value.
[0125]
As described above, in a multipath environment, the probability that the symbol synchronization timing is shifted backward is high and the shifted value is also increased. Therefore, it is preferable to set the second upper limit value large.
[0126]
According to the control by the first comparison unit 801 and the second comparison unit 802 as described above, the selection unit 803 selects the counter value latched by the counter unit 104 with respect to the counter average unit 107, the first upper limit value, or the second upper limit value. Output one of the upper limit values.
[0127]
A specific example of the value output from the selection unit 803 to the counter averaging unit 107 is as follows. Here, as an example, the first upper limit value and the second upper limit value are “3” and “5”, respectively, but the first upper limit value and the second upper limit value are not limited.
(1) When count value−reference count value ≦ −3; −3
(2) When count value-reference count value = -2; -2
(3) Count value−reference count value = −1; −1
(4) Count value−reference count value = 0; 0
(5) Count value−reference count value = 1; 1
(6) When count value-reference count value = 2: 2
(7) Count value−reference count value = 3; 3
(8) Count value−reference count value = 4; 4
(9) Count value−reference count value ≧ 5; 5
Here, (1) to (3) correspond to the case where the symbol synchronization timing is shifted forward, and (5) to (9) correspond to the case where the symbol synchronization timing is shifted backward.
[0128]
Thereafter, the counter averaging unit 107, as in the seventh embodiment, calculates any one of the count value from the selection unit 803, the first upper limit value, or the second upper limit value at a fixed time interval set arbitrarily. The average value is calculated using this, and the calculated average value is output to the timing generation unit 108.
[0129]
As described above, according to the present embodiment, different upper limit values are prepared for each of the case where the symbol synchronization timing is shifted backward and the case where it is shifted forward, compared with Embodiment 7. Thus, the accuracy of the averaged symbol synchronization timing can be further improved.
[0130]
(Embodiment 9)
In the present embodiment, a case will be described in which the upper limit value is changed according to the channel quality in the seventh embodiment or the eighth embodiment.
In general, the symbol synchronization error increases as the line quality deteriorates. Therefore, in the present embodiment, when the line quality is good, the upper limit value is set to a small value, and when the line quality is bad, the upper limit value is set to a large value. Thereby, the accuracy of the averaged symbol synchronization timing can be improved.
[0131]
Hereinafter, the receiving apparatus according to the present embodiment will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of the receiving apparatus according to the ninth embodiment of the present invention. In addition, about the structure similar to Embodiment 8 (FIG. 8) in FIG. 9, the code | symbol same as the thing in FIG. 8 is attached | subjected, and detailed description is abbreviate | omitted.
[0132]
Referring to FIG. 9, the comparison unit 901 determines whether or not the line quality is good by comparing the line quality information and the first threshold value. The determination result is sent to the selection unit 902 and the selection unit 903. In order to obtain channel quality information, for example, a method using reception level information or the method described in the second embodiment can be used.
[0133]
For example, the first upper limit value and the first ′ upper limit value (where the first upper limit value <the first ′ upper limit value) are input to the selection unit 902, and the second upper limit value and the first upper limit value are input to the selection unit 903, for example. 2 ′ upper limit value (where 2nd upper limit value <2 ′ ′ upper limit value) is input.
When the result of determination by the comparison unit 901 indicates that “the line quality is good”, the selection unit 902 sets the first upper limit value as the upper limit value to be output. When indicating that the quality is “poor”, the first upper limit value is set as the upper limit value to be output. Further, the selection unit 902 outputs the upper limit value set in this way to the first comparison unit 801 and the selection unit 803.
[0134]
When the result of determination by the comparison unit 901 indicates that “the line quality is good”, the selection unit 903 sets the second upper limit value as the upper limit value to be output. When indicating that the quality is bad, the second 'upper limit value is set as the upper limit value to be output. The selection unit 903 outputs the upper limit value set in this way to the second comparison unit 802 and the selection unit 803.
The operations of the first comparison unit 801, the second comparison unit 802, and the selection unit 803 are the same as those described in the eighth embodiment.
[0135]
Thus, according to the present embodiment, the accuracy of the averaged symbol synchronization timing is further improved as compared with the seventh and eighth embodiments by changing the upper limit value according to the channel quality. be able to.
[0136]
In the present embodiment, the case where two different upper limit values are prepared for each of the first comparison unit 801 and the second comparison unit 802 has been described as an example. However, the present invention is not limited to this. Needless to say, the present invention can also be applied to cases where three or more types of upper limit values corresponding to the degree of line quality are prepared.
[0137]
In the present embodiment, the case where one threshold value is used in the comparison unit 901 to determine whether the channel quality is good has been described. However, the present invention is not limited to this, and the comparison unit 901 is used. The present invention can also be applied to a case where the line quality is judged more finely using two or more threshold values in FIG.
[0138]
Furthermore, in the present embodiment, the case has been described in which the upper limit values in both the selection unit 902 and the selection unit 903 are changed according to the line quality. However, the present invention is not limited to this, and according to the line quality. The present invention can also be applied to a case where the upper limit value in either the selection unit 902 or the selection unit 903 is changed.
[0139]
(Embodiment 10)
In the present embodiment, a case will be described where, in the ninth embodiment, information related to the delay time of a delayed wave is used as channel quality information in addition to reception level information.
[0140]
When the delay time of the delayed wave is large, the symbol synchronization timing is shifted backward and the shifted value is also increased. Conversely, when the delay time of the delayed wave is small, the backward shift of the symbol synchronization timing is small. That is, the delay time of the delayed wave can be used as an index indicating the line quality.
[0141]
The delay time of the delayed wave can be estimated as follows. FIG. 10 is a schematic diagram illustrating an example of a period (when the delay time of the delay wave is small) in which the reception level varies in OFDM communication. FIG. 11 is a schematic diagram illustrating an example of a cycle (in the case where the delay time of the delay wave is large) in which the reception level varies in OFDM communication.
[0142]
The fluctuation cycle of the reception level in the frequency axis direction due to multipath fading is determined by the delay time of the delay wave. That is, when the delay time of the delay wave is small, as shown in FIG. 10, the fluctuation period of the reception level in the frequency direction becomes long, and conversely, when the delay time of the delay wave is large, it is shown in FIG. As described above, the fluctuation period of the reception level in the frequency direction is shortened.
[0143]
Therefore, it is possible to estimate the delay time of the delayed wave by calculating the absolute value of the difference in reception level between adjacent subcarriers. That is, when the absolute value is small, it can be estimated that the delay time of the delayed wave is small, and conversely, when the absolute value is large, it can be estimated that the delay time of the delayed wave is large.
[0144]
Hereinafter, the receiving apparatus according to the present embodiment will be described with reference to FIG. FIG. 12 is a block diagram showing a configuration of the receiving apparatus according to the tenth embodiment of the present invention. In addition, about the structure similar to Embodiment 9 (FIG. 9) in FIG. 12, the code | symbol same as the thing in FIG. 9 is attached | subjected, and detailed description is abbreviate | omitted.
[0145]
Referring to FIG. 12, demodulation section 110 sends a signal transmitted by each subcarrier after demodulation processing to delay section 1201 and subtraction section 1202. The delay unit 1201 delays the signal from the demodulation unit 110 by a time corresponding to one subcarrier and sends the signal to the subtraction unit 1202. The subtractor 1202 calculates a difference in reception level between adjacent subcarriers by subtracting the signal from the demodulator 110 and the signal from the delay unit 1202 and outputs the calculation result to the absolute value detector 1203. To do.
[0146]
The absolute value detection unit 1203 detects the absolute value of the difference in reception level between adjacent subcarriers by calculating the absolute value of the calculation result from the subtraction unit 1202. The detected absolute value is sent to the comparison unit 1204. Note that the detected absolute values may be averaged and then sent to the comparison unit 1204. Thereby, the estimation accuracy of the delay time of the delayed wave can be further improved.
[0147]
The comparison unit 1204 determines whether the delay time of the delayed wave is large or small by comparing the absolute value from the absolute value detection unit 1203 with a threshold value. That is, when the absolute value is larger than the threshold value, the comparison unit 1204 determines that “the delay time of the delayed wave is large”, and when the absolute value is smaller than the threshold value, It is determined that the delay time is small. The result of the determination is sent to the logical product unit 1205.
[0148]
The logical product unit 1205 receives the determination result from the comparison unit 1204 and the determination result from the comparison unit 901. Note that the determination result from the comparison unit 901 is as described in the ninth embodiment.
[0149]
The logical product unit 1205 indicates that the determination result from the comparison unit 901 indicates that “the line quality is good” and the determination result from the comparison unit 1204 indicates that “the delay time of the delayed wave is small”. Sends the determination result indicating that “the line quality is good” to the selection unit 902 and the selection unit 903 described above. Also, in the cases other than the above, the logical product unit 1205 finally sends the determination result indicating that “the line quality is bad” to the selection unit 902 and the selection unit 903 described above.
The operations of the selection unit 902, the selection unit 903, the first comparison unit 801, the second comparison unit 802, and the selection unit 803 are the same as those described in the ninth embodiment.
[0150]
Note that although a case where one threshold value is used in the comparison unit 1204 has been described in this embodiment in order to determine the magnitude of the delay time of the delayed wave, the present invention is not limited to this. The present invention can also be applied to the case where the comparison unit 1204 further determines the delay time of the delay wave using two or more threshold values.
[0151]
As described above, according to the present embodiment, the information regarding the delay time of the delayed wave is used as the channel quality information in addition to the reception level information, so that the averaged symbol synchronization timing is compared with the ninth embodiment. Accuracy can be further improved.
[0152]
In this embodiment, the case where both the reception level information and the delay time of the delay wave are used as the line quality information has been described. However, the present invention is not limited to this, and the delay quality of the delay wave is used as the line quality information. Needless to say, the present invention can also be applied when only the delay time is used.
[0153]
【The invention's effect】
As described above, according to the present invention, the symbol synchronization pull-in characteristics can be improved.
[Brief description of the drawings]
FIG. 1 is a principal block diagram showing a schematic configuration of a receiving apparatus according to a first embodiment of the present invention;
FIG. 2 is a principal block diagram showing a schematic configuration of a receiving apparatus according to a second embodiment of the present invention.
FIG. 3 is a principal block diagram showing a schematic configuration of a receiving apparatus according to a third embodiment of the present invention;
FIG. 4 is a principal block diagram showing a schematic configuration of a counter averaging unit of the receiving apparatus according to the fourth embodiment of the present invention;
FIG. 5 is a principal block diagram showing a schematic configuration of a counter averaging unit of the receiving apparatus according to the fifth embodiment of the present invention;
FIG. 6 is a principal block diagram showing a schematic configuration of a counter averaging unit of the receiving apparatus according to the sixth embodiment of the present invention;
FIG. 7 is a block diagram showing a configuration of a receiving apparatus according to a seventh embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a receiving apparatus according to an eighth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a receiving apparatus according to a ninth embodiment of the present invention.
FIG. 10 is a schematic diagram illustrating an example of a period (when a delay time of a delay wave is small) in which a reception level fluctuates in OFDM communication.
FIG. 11 is a schematic diagram illustrating an example of a period (when a delay time of a delay wave is large) in which a reception level varies in OFDM communication.
FIG. 12 is a block diagram showing a configuration of a receiving apparatus according to the tenth embodiment of the present invention;
FIG. 13A is a schematic diagram illustrating an example of a frame format in OFDM mobile communication.
(B) Schematic diagram showing another example of frame format in OFDM mobile communication
FIG. 14 is a principal block diagram showing a schematic configuration of a conventionally proposed receiving apparatus.
FIG. 15 is a principal block diagram showing a schematic configuration of a symbol synchronization unit of a conventionally proposed receiving apparatus;
FIG. 16 is a principal block diagram showing another schematic configuration of a symbol synchronization unit of a conventionally proposed receiving apparatus;
FIG. 17 is a principal block diagram showing still another schematic configuration of a symbol synchronization unit of a conventionally proposed receiving apparatus;
[Explanation of symbols]
103 Symbol synchronization unit
104 Counter section
105 switches
106 Comparison part
107 Average counter
108 Timing generator
201 Selector section
301 Quality information average part

Claims (13)

Receiving means for receiving an OFDM signal;
Detecting means for detecting symbol synchronization timing in a plurality of frames;
A selection means for selecting and outputting a symbol synchronization timing in which the time from the beginning of the frame is within a threshold value among the detected symbol synchronization timings;
Averaging means for obtaining an average value of the outputs of the selection means ;
Fourier transform means for performing Fourier transform processing on the OFDM signal using the average value as processing start timing ;
A receiving apparatus comprising: The selection means outputs the threshold value instead of the symbol synchronization timing for the symbol synchronization timing at which the time exceeds the threshold value.
The receiving device according to claim 1. It said selection means changes the threshold value according to the channel quality,
The receiving device according to claim 1 . The selection means changes the threshold according to the line quality averaged over a plurality of frames.
The receiving device according to claim 1 . It said averaging means obtains the previous average value, and the symbol synchronization timing which is selected this time by the selecting means, the weighted average performed by the current average value using,
The receiving device according to claim 1 . Receiving means for receiving an OFDM signal;
Detecting means for detecting symbol synchronization timing in a plurality of frames;
Selecting means for selecting and outputting a symbol synchronization timing whose error from a reference value is within a threshold value among detected symbol synchronization timings;
Averaging means for obtaining an average value of the outputs of the selection means ;
Fourier transform means for performing Fourier transform processing on the OFDM signal using the average value as processing start timing ;
A receiving apparatus comprising: The selection means outputs the threshold value instead of the symbol synchronization timing for the symbol synchronization timing at which the error exceeds the threshold value.
The receiving device according to claim 6. The selection means uses different threshold values when the error occurs in front of and behind the reference value.
The receiving device according to claim 6. The selection means sets a threshold value when the error occurs behind the reference value to a value larger than a threshold value when the error occurs in front of the reference value,
The receiving device according to claim 8. The selection means changes the threshold according to line quality .
The receiving device according to claim 6. The selection means changes the threshold according to a delay time of a delay wave .
The receiving device according to claim 6. A synchronization acquisition method for performing a Fourier transform process on an OFDM signal using an average value of symbol synchronization timings detected in a plurality of frames as a process start timing,
A synchronization acquisition method for obtaining the average value using only the symbol synchronization timing whose time from the beginning of the frame is within a threshold value among the symbol synchronization timings detected in a plurality of frames . A synchronization acquisition method for performing a Fourier transform process on an OFDM signal using an average value of symbol synchronization timings detected in a plurality of frames as a process start timing Because
A synchronization acquisition method for obtaining the average value using only symbol synchronization timings whose error from a reference value is within a threshold value among symbol synchronization timings detected in a plurality of frames.

Images