JP3673598B2 - Image processing method and image processing apparatus - Google Patents

Description

スキュー値を求める（２）式において分母部分は画像全体の分散値であり、分子は各画素の輝度値と、その平均値との差分を３乗することにより算出されるが、奇数乗であれば３乗に限定されるものではない。
【００６７】
ステップＳ７０５では、１つの処理ブロックにおける閾値決定処理ループ回数ｉの判断（ｉ＝１、つまり最初のループかどうかの判断）を行う。ｉが「１」であればステップＳ７０６へ、ｉが「１」以外であればステップＳ７０９へ進む。ステップＳ７０６では、処理中のブロックが「文字ブロック」かどうかの画像特徴判別を行い、ステップＳ７１８へ進む。画像特徴判別の詳細（Ｓ７２８〜Ｓ７２９、Ｓ７０７〜Ｓ７０８）は後述するが文字ブロックであると判断された場合はＭＦが「ＯＮ」に設定される。
【００６８】
ステップＳ７０９では（３）式に示す様にヒストグラムの偏りの大きさを判断する。
【００６９】
｜ＳＫ｜＜０．１２５ …（３）
つまり、スキュー値ＳＫの絶対値が「０．１２５」未満かの判断を行う。ステップＳ７０９が真ならばステップＳ７１９へ、偽ならばステップＳ７１０へ進む。
【００７０】
ステップＳ７１０ではかすれ文字処理を行う。Ｓ７１０の条件が成立した場合はＳ７１９へ、成立しなかった場合はＳ７１１へ進む。かすれ文字処理の詳細（Ｓ７１０、Ｓ７３０〜Ｓ〜７３１、Ｓ７１２〜Ｓ７１３）は後述する。
【００７１】
ステップＳ７１１では、閾値決定処理ループ回数ｉの判定を行い、ｉが「２」ならばステップＳ７１２へ、「２」以外ならステップＳ７１６へ進む。ｉが「２」の場合に進むステップＳ７１４では、処理中のブロックが「つぶれ文字ブロック」かどうの判断と処理を行いステップＳ７１６で合流する。つぶれ文字処理の詳細（Ｓ７１４、Ｓ７３２〜Ｓ７３３、Ｓ７１５）は後述するがつぶれ文字ブロックであると判断された場合はつぶれ文字フラグＴＦが「ＯＮ」に設定される。
【００７２】
ステップＳ７１６では、以下に示す（４）式によりヒストグラムの偏りの方向を判断する。
【００７３】
ＳＫ＞＝０ …（４）
【００７４】
ステップＳ７１６において（４）式が真（ヒストグラムの偏りが平均値ＡＶよりも大きい値の範囲にある事を意味する）ならばステップＳ７１７へ進み、偽（ヒストグラムの偏りが平均値ＡＶよりも小さい値の範囲にある事を意味する）ならばステップＳ７１８へ進む。
【００７５】
ステップＳ７１７では、ＳＴＡＲＴに平均値ＡＶをセットし、ＥＮＤは変化させない。そして、ステップＳ７３４へ進む。ステップＳ７１８では、ＳＴＡＲＴは変化させず、ＥＮＤに平均値ＡＶをセットする。そして、ステップＳ７３４へ進む。ステップＳ７３４では、閾値決定処理ループ回数ｉに「１」を加え、そしてステップＳ７０２に戻り、再びＳＴＡＲＴ値からＥＮＤ値までの平均値ＡＶを算出する。この様にスキュー値ＳＫが所定値まで収束する様にして２値化閾値を設定することで、下地を除去し、鮮明な２値画像を得ることができる。
【００７６】
ステップＳ７１９では平均値ＡＶを、２値化閾値ＴＨとして設定する。ステップＳ７２０からＳ７２７は得られた二値化閾値ＴＨの制限処理であり、詳細は後述する。この閾値制限の処理を行うと閾値決定処理が終了する。
【００７７】
以上説明したようにして本実施例における２値化処理が行われるが、式（３）、（４）で示した範囲は、これに限定されるものではない。
【００７８】
このフローチャートにより説明した二値化閾値決定処理を図９における回路で実行するのであるが、演算精度を確保するために以下の様に変形する。
【００７９】
輝度値ｋの範囲は０から２５５であるため平均値ＡＶも０から２５５の範囲の値となる。しかしスキューＳＫを演算する場合、輝度ｋは平均値ＡＶの差分（ｋ−ＡＶ）の値が基本となっている。１０回の演算の繰り返しにおいて演算領域であるＳＴＡＲＴ、ＥＮＤ間が狭くなるため、その差分の値が次第に小さくなり、またΣＰｉも同様に小さくなる。よって（２）式における分母および分子部分の値が小さくなっていくためスキューＳＫの有効桁数を１回目のループと同程度確保する場合に分母／分子の演算桁を大きくすることが必要となる。即ち小数点以下の桁数を増やしていくしかない。
【００８０】
（１）式においてＸを（１４−（（ＥＮＤ−ＳＴＡＲＴ）のビット数））とすると、

となり、本来の平均値ＡＶとの関係は、
ＡＶ＝ＡＶ′÷２^X ＋ＳＴＡＲＴ （４）
となる。
【００８１】
初回のループのＳＴＡＲＴ＝０、ＥＮＤ＝２５５の時（ＥＮＤ−ＳＴＡＲＴが８ビット範囲で収まる）に平均値ＡＶを整数部分８ビット、小数部分を７ビットで求められるとすると、２回目以降において（ＥＮＤ−ＳＴＡＲＴ）が７ビット範囲であれば整数部分は７ビットであるため小数点部分を８ビットまで求めても同じ演算器で処理が可能になる。説明すると（３）式において（ｋ−ＳＴＡＲＴ）によってオフセット処理してＸによってスケーリングを行っているために同じ除算部分は２７ビット割る１３ビットで演算されても小数点以下の桁数が７から１４まで変化する。小数点以下の桁数が大きくなるのは（２）の分母／分子の値が小さくなるのと歩調があっている。
【００８２】
同じようにＹを（１２−（Σｐ（ｉ）のビット数））（ただしＹがマイナス値の場合は０）として（２）式は
ｔｍｐＡ＝（ｋ−ＳＴＡＲＴ）×２^X −ＡＶ′ （５）
ｔｍｐＢ＝（（ｔｍｐＡ×ｔｍｐＡ）÷２⁷ ）×（ｐ（ｋ）×２^Y ） （６）
ｔｍｐＣ＝Σ（ｔｍｐＡ×（ｔｍｐＢ÷２³ ）） （７）
Ｄ＝（ΣｔｍｐＢ）÷２⁷ （８）
Ｅ＝｜ｔｍｐＣ｜÷２^X+5 （９）
Ｓ…ｔｍｐＣの符号 （１０）
ＳＫ′＝Ｅ÷Ｄ （１１）
と変形される。ここでＳＫ′は｜ＳＫ｜に等しい。
【００８３】
図９の各部の内部構成を説明する前に図１０〜１４の閾値算出の処理フローを図１５に示す。大きく分けて平均値演算部６０２とスキュー演算部６０３と判定部６０４の動作の流れを示しているが、同時に動作する部分は横並びで表し、時間経過を上下で図示している。
【００８４】
最初にｎ回目の平均値、スキューをそれぞれＡＶｎ、ＳＫｎ（その前段階がＤｎ、Ｅｎ、Ｓｎ）として説明を行う。まずフェーズＰ８０１としてＳＴＡＲＴ＝０、ＥＮＤ＝２５５と初期化される。フェーズＰ８０２としてＥＮＤ〜ＳＴＡＲＴの範囲のデータが輝度頻度記憶ＲＡＭ３０４／３０５から読み出されて平均値演算部６０２に入力される。これにより輝度２５５から０までの輝度の平均値ＡＶ′１が算出される。次にフェーズＰ８０３でやはり２５５から０の範囲のデータが輝度頻度記憶ＲＡＭ３０４／３０５から読み出されてスキュー演算部６０３に入力されてＤ１、Ｅ１、Ｓ１が演算される。この時同時に０からＡＶ１の範囲の平均輝度ＡＶ′２が平均演算部６０２によって演算される。次のフェーズＰ８０４でＥＮＤをＡＶ１に設定し、フェーズＰ８０５においてＡＶ２−ＥＮＤ間の平均値ＡＶ′３ｂとＳＴＡＲＴ−ＡＶ２間の平均値ＡＶ′３ａが平均値演算部６０２によって演算され、ＥＮＤ−ＳＴＡＲＴ間のスキューＤ２、Ｅ２、Ｓ２がスキュー演算部６０３によって算出される。このフェーズＰ８０４からＰ８０５の間に同時に判定部６０４によってＤ１／Ｅ１の演算を行って得られたＳＫ′１を用いて画像特徴判別が行われる。
【００８５】
フェーズＰ８０５ではＡＶ３としてＡＶ３ａとＡＶ３ｂの二つが求められるが、続くフェーズＰ８０６で次の演算範囲を決定するのにＳＫ２の符号すなわちＳ２が正であればＡＶ３ａがＡＶ３となり負であればＡＶ３ｂがＡＶ３となる。本来であればＳ２すなわちＳＫ２の演算が終了するまでＡＶ３を求めるための領域がＳＴＡＲＴ−ＡＶ２間であるかＡＶ２−ＥＮＤ間であるかが決定されていないが、ＳＫ２（Ｄ２、Ｅ２、Ｓ２）の演算にＳＴＡＲＴ−ＡＶ２−ＥＮＤ間のデータをアクセスするため、平均値演算部６０２においてＳＴＡＲＴ−ＡＶ２間の平均値ＡＶ３ａとＡＶ２−ＥＮＤ間の平均値ＡＶ３ｂの二つの値を求めておく。輝度頻度記憶ＲＡＭ３０４／３０５のデータはＳＴＡＲＴ−ＡＶ２、ＡＶ２−ＥＮＤのように時間的にずれて入力されるため平均値演算部６０２を複数持つ必要はない。このＡＶ′３ａ、ＡＶ′３ｂ、Ｄ２、Ｅ２、Ｓ２が判定部６０４に入力され、Ｓ２の符号によりＡＶ３を決定して制御部に出力する。制御部６０５は受けた平均値によりＳＴＡＲＴとＥＮＤの再設定を行って次の演算範囲を決定し次の平均値とスキュー（ＡＶ４、Ｄ３、Ｅ３、Ｓ３）の演算を行わせる。それと平行して判定部６０４ではＤ２／Ｅ２の演算がなされ、｜ＳＫ２｜＜０．１の終了判定やつぶれ文字処理またはかすれ文字処理が行われる。詳しくは後述するがつぶれ文字とかすれ文字は相対する性質であるためどちらか一方の処理が行われる。これらの処理により終了条件が成立した場合はＡＶ２を閾値ＴＨとして出力し、制御部６０５は演算中の平均値演算部６０２とスキュー演算部６０３の動作を停止させて全処理を終了する。
【００８６】
終了条件が成立しなかった場合は同様の処理を続行していき、最後に１０回目の平均値ＡＶ１０の演算が終わってＳＫ９に対する終了判定をして終了条件が成立した場合はＡＶ９を閾値ＴＨとして成立しなかった場合はＡＶ１０を閾値ＴＨとして終わる。
【００８７】
このように平均値演算部６０２、スキュー演算部６０３、判定部６０４が同時に動作して演算を行っており、判定部６０４がｎ回目の演算を行っているとするとスキュー演算部６０３は（ｎ＋１）回目の演算であり、平均値演算部６０２は（ｎ＋２）回目の演算をパイプラインで行っていることになる。しかし単純なパイプライン動作ではなく、平均値演算部６０２とスキュー演算部６０３の演算は同期を取って行われるため輝度頻度記憶ＲＡＭ３０４／３０５は一つで処理することができる。
【００８８】
ところで平均値演算部６０２においてＳＴＡＲＴ、ＡＶｎ、ＥＮＤの三つの値が与えられた場合、ＳＴＡＲＴ−ＡＶｎ間とＡＶｎ−ＥＮＤ間の平均値を求めるためにＡＶｎに該当する箇所の輝度データを２度アクセスしなければならないが、例として図１６に示すような構成にすれば１回のアクセスですむ。
【００８９】
図１６は平均値演算部６０２の詳細な構成を示したブロック図である。
【００９０】
輝度頻度記憶ＲＡＭ３０４／３０５のデータは２５５から０へアクセスされる。９０１は入力されたＳＴＡＲＴとＥＮＤの値からＥＮＤ−ＳＴＡＲＴとＸの値を求める演算器である。この平均値演算部６０２では平均値を２つ演算するため、入力ＡとＢにはＳＴＡＲＴ、ＡＶｎ、ＥＮＤの値が実際には入力される。
【００９１】
９０２はＥＮＤ−ＳＴＡＲＴの値を入力して０までダウンカウントするカウンタ、９０３は入力Ａ、Ｂの乗算を行う乗算器であり、乗算器９０３の入力Ａには輝度すなわち輝度頻度記憶ＲＡＭ３０４／３０５のデータを読み出す時のアドレスの値−ＳＴＡＲＴの値即ちカウンタ９０２の出力が入力され、入力Ｂにはその読み出された頻度データが入力される。この乗算器９０３によって（ｋ−ＳＴＡＲＴ）×Ｐ（ｋ）の演算が行われる。９０４は加算器でありΣ（ｋ−ＳＴＡＲＴ）×Ｐ（ｋ）の演算を行う。９０５はレジスタであり、加算器９０４の出力を２つ分保持する。９０６はシフタであり、演算器９０１によって得られたＸの値によってレジスタ９０５の出力をシフトさせる。このシフト量によってＡＶ′ｎの小数点以下の桁数が決定される。９０７はテンポラリのレジスタであり、輝度がＡＶｎに相当する箇所のデータを一時的に保持するものである。９０８はマルチプレクサであり、９０９は加算器である。マルチプレクサ９０８は加算器９０９への入力をレジスタ９０７のデータにするか加算器９０９の出力をフィードバックさせるかを選択するもので、通常は出力をフィードバックさせるように選択されている。加算器９０９によりΣＰ（ｋ）が演算される。
【００９２】
９１０はレジスタであり、加算器９０９のデータが確定したところでその値を保持するものである。平均値は二つ求めなければならないためその出力を２つ分記憶する容量を持つ。９１１は除算器でありレジスタ９０５、９１０からデータを入力し、平均値を求める。
【００９３】
レジスタ９０７はＰ（ｋ）のデータをディレイさせるものである。最初に加算器９０４と９０９は初期化され０に設定されｋ＝ＥＮＤから演算を開始し、ｋ＝ＡＶｎのデータを演算したところで加算器９０４と９０９の出力をレジスタ９０５、９１０にセーブする。ｋ＝ＡＶｎ＋１の演算時にマルチプレクサ９０８はレジスタ９０７のデータを選択することにより、加算器５０７ではＰ（ＡＶｎ）＋Ｐ（ＡＶｎ＋１）の演算を行う。加算器９０４においては重複するデータの値は入力Ａ側が０であるためディレイ目的のテンポラリのレジスタは必要ない。その後ｋ＝ＳＴＡＲＴまでの演算が終わるとその結果をまたレジスタ９０５、９１０に出力する。
【００９４】
このようにすることによってデータに読み出しが各１回になるので平均値演算部６０２とスキュー演算部６０３が動作を始めてから、同期をとるためにスキュー演算部６０３を止める必要はなくなる。
【００９５】
図１７はスキュー演算部６０３の構成図である。
【００９６】
１００１はカウンタであり、ＥＮＤ−ＳＴＡＲＴの値をロードして０までカウントダウンを行う。１００２はシフタであり、平均値演算部６０２で演算されたＸを受けて（ｋ−ＳＴＡＲＴ）×２Ｘの演算を行う。１００３は減算器であり、（ｋ−ＳＴＡＲＴ）×２Ｘ−ＡＶ′すなわちｔｍｐＡの演算を行う。１００４は乗算器でありｔｍｐＡ×ｔｍｐＡの演算を行う。１００５は演算器であり平均値演算部６０２で演算されたΣＰ（ｋ）の値からＹを求める。１００６はシフタでありＹの値で輝度分布量Ｐ（ｋ）から（Ｐ（ｋ）×２^Y ）の演算を行う。１００７は乗算器であり、（ｔｍｐＡ×ｔｍｐＡ÷２⁷ ）×（Ｐ（ｋ）×２^Y ）即ちｔｍｐＢの演算を行う。１００８はディレイであり、減算器１００３の出力を乗算器１００４と１００７の演算クロック数分遅れさせる。１００９は乗算器であり、ｔｍｐＡ×（ｔｍｐＢ÷２² ）の演算を行う。１０１０は加算器であり、ΣｔｍｐＢの演算をしてＤの結果を出力する。１０１１は加算器であり、ΣｔｍｐＡ×（ｔｍｐＢ÷２² ）の演算を行う。１０１２は演算器であり、｜ΣｔｍｐＡ×（ｔｍｐＢ÷２² ）｜÷２^X+5 の演算をしてＥとその符号Ｓの出力を行う。
【００９７】
図１８は閾値算出の終了条件を判定する判定部６０４の詳細を示したブロック図である。
【００９８】
１１０１は比較器であり、スキュー演算部６０３で得られたＤ、Ｅの値からＥ×８＜Ｄ即ち｜ＳＫ｜＜０．１２５の判定を行う。１１０２は除算器であり、同じくＤ＜Ｅの値からＥ÷Ｄを演算してＳＫ′ｎ即ち｜ＳＫｎ｜の値を求める。１１０３は画像特徴判定部であり、１１０４はかすれ文字処理部であり、１１０５はつぶれ文字処理部である。１１０３、１１０４、１１０５内には図１０〜図１４のＭＦ、ＫＦ、ＴＦ、ＳＫ１があって共通に管理されている。
【００９９】
では、画像特徴判別部１１０３について、図１０、図１２に戻って説明する。ステップＳ７０１では、動作開始時に処理中のブロックが「文字ブロック」かどうかを示す、文字フラグＭＦに「０」をセットし、ステップＳ７０４にて一回目のスキュー値の演算がなされるのを待つ。一回目のスキュー値（この段階ではＤ１、Ｅ１）が演算されると画像特徴判別Ｓ７０６に入り、そのスキュー値の符号Ｓが負である場合（Ｓ７２８）、ステップＳ７２９へ進み符号Ｓが負でない場合ステップＳ７１８へ進み画像特徴判別を終了する。ステップＳ７２９では除算器１１０２によって演算されるスキュー値ＳＫ′１を用い、処理中のブロックが「文字ブロック」かどうかの判断を（１２）式により行う。
【０１００】
ＳＫ′＞ＭＨ …（１２）
ここで、ＭＨは処理中のブロックが「文字ブロック」かどうかを示す値であり、制御部２０８にＣＰＵ部７が設定した値である。ここでは、「ＭＨ＝２０」とする。ステップＳ７２９において（１２）式が真ならばステップＳ７０７へ、偽ならばこの画像特徴判別処理を終える。ステップＳ７０７では、処理中のブロックが「文字ブロック」であることを示す、文字フラグＭＦに「１」をセットし、次のステップＳ７０８で得られたスキュー値をＳＫ１に保持してこの画像特徴判別処理を終える。
【０１０１】
以上説明したようにして本実施の形態における画像特徴判別処理が行われるが、式（１２）で示した条件は、これに限定されるものではない。
【０１０２】
次に、つぶれ文字処理部について、同じく図１０、図１４を用い詳細に説明する。
【０１０３】
ここで、つぶれ文字とは、１文字の画数が多い等のため、つぶれている文字のことであり、つぶれ文字と判断されるとそれを良好に再現できる閾値を割り当てる。
【０１０４】
ステップＳ７０１では、処理中のブロックが「つぶれ文字ブロック」かどうかを示す、つぶれ文字フラグＴＦに「ＯＦＦ」をセットする。２回目のスキュー演算（Ｄ２、Ｅ２）が終わるとステップＳ７１４に進み、文字フラグＭＦが「ＯＮ」であり符号Ｓが正である場合、ステップＳ７０８で保持されたＳＫ１と除算器１１０２によって演算されるスキュー値ＳＫ′２を用い、ステップＳ７３３では、処理中のブロックが「つぶれ文字ブロック」かどうかの判断を（１３）式により行う。
【０１０５】
ＳＫ１＞＝ＳＲ×ＳＫ′２ …（１３）
ここで、ＳＲは処理中のブロックが「つぶれ文字ブロック」かどうかを示す値であり、ここでは、「ＳＲ＝３．０」とする。ステップＳ７３３において（１３）式が真ならばステップＳ７１５へ、偽ならばこのつぶれ文字処理を終える。ステップＳ７１５では、処理中のブロックが「つぶれ文字ブロック」であることを示す、つぶれ文字フラグＴＦに「ＯＮ」をセットし、このつぶれ文字処理を終える。
【０１０６】
以上説明したようにして本実施の形態における、つぶれ文字処理が行われるが、式（１３）で示した条件は、これに限定されるものではない。
【０１０７】
さらに、かすれ文字処理について、図１０、図１３を用い詳細に説明する。かすれ文字とはうすくなってしまった文字のことであるが、本例ではこのうすれ文字にも最適な閾値を割り当てる。ステップＳ７０１では、処理中のブロックが「かすれ文字ブロック」かどうかを示す、かすれ文字フラグＫＦに「ＯＦＦ」をセットする。２回目以降のスキュー値に対して文字フラグＭＦが「ＯＮ」で符号Ｓが負である場合、ステップＳ７０８で保持されたＳＫ１と除算器１１０２によって演算されるスキュー値ＳＫ′ｎを用い、ステップＳ７３１では、処理中のブロックが「かすれ文字ブロック」かどうかの判断を（１３）式により行う。ここで、ＳＲは処理中のブロックが「かすれ文字ブロック」かどうかを示す値であり、ここでは、「ＳＲ＝３．０」とする。ステップＳ７１０において（１３）式が真ならばステップＳ７１９へ進む。偽ならばステップＳ７１１へ進み、ループ回数が２の場合のみＳ７１２へ進む。ステップＳ７１２において符号Ｓが正の場合はかすれ文字フラグＫＦを「ＯＦＦ」にする。
【０１０８】
ＳＲは処理中のブロックが「かすれ文字ブロック」かどうかを示す値であり、ここでは、「ＳＲ＝３．０」とする。
【０１０９】
以上説明したようにして本実施の形態における、かすれ文字処理が行われるが、式（６）で示した条件は、これに限定されるものではない。
【０１１０】
図１０の２回目のループにおいて、かすれ文字処理とつぶれ文字処理が重なるが処理の本体であるＳ７３１とＳ７３３は同じ処理であり、Ｓ７３０とＳ７３２から分かるように２回目のスキューの符号によってどちらが実行されるか決まる。よって２つの処理は排他的でありかつ同一処理であるため回路規模や実行時間に対する影響は小さい。
【０１１１】
終了判定が行われると判定部６０４から閾値制限部６０６に平均値ＡＶが出力され、閾値制限部６０６ではその時の平均値ＡＶを閾値ＴＨに設定してＳ７２０に進む。処理ブロックが文字ブロックでない場合すなわち文字フラグＭＦが「ＯＦＦ」の時は閾値ＴＨを下限値Ｌと上限値Ｈによる制限を行う。つまり、ステップＳ７１９で決定された閾値ＴＨが、下限値Ｌよりも小さいときは閾値ＴＨをＬで代表させ、上限値Ｈよりも大きいときは閾値ＴＨをＨで代表させるような制限処理を行う。尚、この下限値Ｌと上限値Ｈは、画像入力装置２の特性により決定される値である。文字ブロックである場合、ステップＳ７２５へ進んでつぶれ文字フラグＴＦが「ＯＮ」かどうかの判断（処理中のブロックがつぶれ文字ブロックかどうかの判断）をする。その結果が、つぶれ文字ブロックであればステップＳ７２６へ行く。ステップＳ７２６において閾値ＴＨが上限値Ｈに達しない場合はＳ７２７へ進み閾値ＴＨに文字つぶれ防止用の定数ＴＰをかけるような制限処理を行う。定数ＴＰは０．８７５としているが画像入力装置２の特性により決定される値である。
【０１１２】
図１９は図２の結果記憶部２０４と画像変換処理部２０３の詳細を示したブロック図である。
【０１１３】
結果記憶部２０４は二値化閾値演算部２０５で決定された各ブロックの閾値とそのブロックが文字ブロックであるかどうかを示す文字フラグＭＦを受け取り内部に格納する。二値化閾値演算部２０５からは６４×６４＝４０９６画素入力の時間間隔で閾値が入力される。内部のメモリ容量は扱う画像の１ラインの最大画素数を８１９２画素とすると１２８×２×９ビット（８１９２÷６４＝１２８）である。メモリ制御部２０６からは二値化する画像がライン順次で入力されるため結果記憶部２０４から画像変換処理部２０３（後述の１２０１から１２１１）への出力は６４画素分の時間間隔があり入出力の競合を調停する。画像変換処理部２０３の内部は１２０１から１２１１である。１２０１は１６ビットレジスタであり、メモリ制御部２０６より読み出された２画素分のデータを一時的に記憶する。１２０２、１２０３は比較器であり、２画素データを同時に閾値と大小比較を行い出力する。１２０４は２ビット→４ビット変換レジスタであり、１２０５は４ビット幅のＦＩＦＯメモリである。レジスタ１２０４は比較器１２０２、１２０３からの２画素分の二値化データ（２ビット）を２回受け取り４ビットそろったところでＦＩＦＯメモリ１２０５へ出力する。１２０１から１２０４は内部動作クロックに同期し１２０６から１２１１は画像の入出力クロックに同期して動作するのであるがＦＩＦＯメモリ１２０５はこのクロック速度の違いを吸収するものである。１２０６は二値画像を２ライン分ディレイさせるメモリで２ｋ×８ｂｉｔの容量を持つ。働きは８ｋ×２ｂｉｔのＦＩＦＯメモリと等価であるがバス幅を４倍の８ビット幅にしていることにより１ポートＲＡＭで処理している。画像のクロックにして２クロックに１回アクセスされる。１２０７、１２０８、１２０９はシフトレジスタであり、３画素×３画素のウインドウを作る。１２１０は文字フラグのディレイメモリであり、１２８＋αビットの容量を持つ。１２１１は孤立点除去部であり、シフトレジスタ１２０８の注目画素即ち３×３画素の中心画素のまわりの画素を調べて、孤立点であれば白画素「１」に変換して出力する。ディレイメモリ１２１０から孤立点除去部１２１１への出力はこの注目画素が含まれたブロックの文字フラグＭＦの値であり、文字フラグが「１」であれば孤立点除去を働かせ、「０」であれば休止させて注目画素をスルー出力させる。
【０１１４】
尚、６４×６４の処理ブロックからはずれる部分の二値化閾値はその近傍の６４×６４のブロックの二値化閾値を用いる。
【０１１５】
前述の実施の形態ではブロックのサイズを６４×６４としたが、画像の解像度が倍になった場合は１２８×１２８であり、１／２の場合は３２×３２とする。ブロックサイズが小さくなった場合でも（５）式から（１１）式にある全画素数によって変化するＹによって同じハードで演算精度を確保できる。ブロックサイズを大きくする場合は、輝度頻度記憶ＲＡＭのビット幅（容量）を大きくしてかつ閾値を演算する平均値演算部とスキュー演算部の演算器のビット数も大きくする。即ち、演算系は処理する画像の解像度の最大値によって設計される。
【０１１６】
しかし、十分なサンプリング数（輝度頻度を構成する画素数）が必要であれば、データを間引いて処理できる。例えば４０９６画素で十分であれば、１２８×１２８の領域から輝度頻度は飛び飛びに４０９６画素でとるのである。この場合は閾値演算部の構成は変わらない。また、輝度頻度記憶ＲＡＭのビット幅を２ビット増やして、閾値を演算する平均値演算部とスキュー演算部には輝度頻度記憶ＲＡＭの下位２ビットを除いて入力しても閾値演算部の構成は変わらない。
【０１１７】
この必要とするサンプリング数は画像入力装置の特性等によって決定される。
【０１１８】
また、前記実施の形態ではブロックの大きさを縦横同じにしたが長方形でもよい。
【０１１９】
また、前記実施の形態ではブロックと判定されたブロックのみ孤立点除去を行うとしたが、全ブロックに行ってもよく、全ブロックに対して処理をスルーさせてもよい。
【０１２０】
また、動作周波数に余裕がある場合は輝度頻度記憶ＲＡＭを１ポートＲＡＭで構成してもよい。輝度値に対応するメモリデータの読み出し、＋１加算、メモリデータの書き込みの一連の動作をすることになるので処理クロック数が３倍程度になるが、パイプラインの不整合を監視する回路が不要になる。
【０１２１】
また、同じく輝度頻度を記憶するものをカウンタで構成してもよい。回路規模は大きくなるが１画素を１クロックで処理できるので動作周波数を高くできる。
【０１２２】
以上説明したように、本実施の形態によれば、各処理ごとに必要であったバンドメモリが１ブロックに統一されるため、メモリ制御信号が１組ですみ信号の数を少なくできるためＩＣ化しやすい。また各処理バッファが物理的に分離されていないため各処理の開始のタイミングを自由に設定できる。
【０１２３】
また、輝度頻度記憶メモリを多ポートＲＡＭで構成することによって輝度頻度累計のための周波数を低減することができ、より高速動作が可能になる。
【０１２４】
また、二値化閾値を演算する平均値演算部とスキュー演算部の演算の同期をとってパイプライン化されているため、本来であればシーケンシャルに実行するか、平均値演算部とスキュー演算部のそれぞれに必要な輝度頻度記憶ＲＡＭが１個ですむため、処理の高速化と回路規模増加の回避を同時に実現できる。
【０１２５】
また、画像の文字及び線画部分の孤立点が除去されるため見やすくなり、かつ文字認識の認識率が向上する。また、圧縮効率も向上するので画像の格納スペースとＦＡＸ等の転送速度の向上がなされる。
【０１２６】
また、本実施の形態によれば、数値演算の演算式と演算に用いる数値データにより演算値のとり得る値の予測から、演算の小数点位置を決定して演算値の桁数を切り捨て及び繰り上げを行い、最終演算値を予め設定した有効桁数内に収めることを特徴とする。
【０１２７】
更に、演算の小数点位置は、処理単位ごとに決定することを特徴とする。
【０１２８】
更に、前記決定処理単位は、前記画像の輝度頻度の平均値を求め、前記画像の輝度頻度の偏りを求める単位を処理単位とする決定手段を有することを特徴とする。
【０１２９】
例えば、有効桁数は演算値の必要精度によって決定されることを特徴とする。
【０１３０】
以上の構成により、多値画像の画像処理の演算において、限られたコンピュータの扱える整数の有効数値内で一定の精度を保ち、特に、大きな数値から小さい数値まで収束させるような繰り返し演算の高速化ができるという特有の作用効果が得られる。
【０１３１】
即ち全計算を複数に分割してそれを処理単位とし、演算処理単位毎にデータ範囲を調べて必要とする演算精度を得られる桁数を決定する。この決定した桁数によって整数演算の小数点位置を移動させて演算するのである。このことにより各処理範囲中は整数演算で行うためハード演算の場合はハード量を少なくできる。かつ処理単位毎に最適な小数点位置にするため桁数を少なくして精度を高めることができる。
【０１３２】
【発明の効果】
以上説明した如く本発明によれば、多値画像を２値化するための２値化閾値を決定して２値化処理を行う際に、処理を極めて高速化することができる。
【０１３３】
また、多値画像の画像処理の演算において、限られたコンピュータの扱える整数の有効数値内で一定の精度を保ち、特に、大きな数値から小さい数値まで収束させるような繰り返し演算を高速化ができる。
【図面の簡単な説明】
【図１】本実施の形態における画像処理装置の全体構成を示した図である。
【図２】閾値演算二値化部の構成を示したブロック図である。
【図３】二値化閾値演算部２０５の内部構成を示した図である。
【図４】二値化閾値演算部におけるパイプライン処理を説明するための図である。
【図５】二値化閾値演算部におけるパイプライン処理を説明するための図である。
【図６】画像入力に対するバッファメモリの入出力を示す図である。
【図７】輝度頻度演算部の構成を示した図である。
【図８】輝度頻度演算部における処理タイミングを示した図である。
【図９】閾値演算部の構成を示したブロック図である。
【図１０】閾値演算処理を示したフローチャート図である。
【図１１】閾値演算処理を示したフローチャート図である。
【図１２】閾値演算処理を示したフローチャート図である。
【図１３】閾値演算処理を示したフローチャート図である。
【図１４】閾値演算処理を示したフローチャート図である。
【図１５】閾値演算部におけるタイミングチャート図である。
【図１６】平均値演算部の構成を示したブロック図である。
【図１７】スキュー演算部の構成を示したブロック図である。
【図１８】判定部の構成を示したブロック図である。
【図１９】結果記憶部と画像変換処理部の構成を示したブロック図である。
【図２０】閾値決定処理を説明するための図である。
【図２１】閾値決定処理を説明するための図である。
【図２２】閾値決定処理を説明するための図である。
【符号の説明】
１ 画像処理装置
２ 画像入力装置
３ 画像表示装置
４ 入力Ｉ／Ｆ部
５ 閾値演算二値化部
６ 記憶部
７ ＣＰＵ部
８ 文字認識部
９ 画像処理部
１０ 出力Ｉ／Ｆ部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing method and an image processing apparatus, for example, an image processing method and an image processing apparatus that perform binarization by determining a binarization threshold value from a multi-valued image.
[0002]
[Prior art]
The development of image processing technology in recent years is remarkable, and image processing apparatuses capable of processing multi-value images such as full-color images, character recognition processing in multi-value images, and the like have become widespread.
[0003]
In such an image processing technique, binarization processing of a multi-valued image has become an indispensable technique. Conventional binarization methods include a simple binarization method using a preset fixed threshold, and a threshold when the inter-class variance is maximum when the histogram is divided into two classes with a certain threshold. Otsu method as a threshold value (Otsu, “Automatic threshold selection method based on discrimination and least square criterion”, IEICE Transactions, vol. J63-D, no. 4, pp. 349-356, 1980 In addition, there is a binarization method for setting a threshold according to a local density for an image having gradation.
[0004]
[Problems to be solved by the invention]
However, the binarization method in the conventional image processing apparatus as described above has the following problems.
[0005]
In the simple binarization method using the fixed threshold value, it is difficult to set an appropriate threshold value between the object density and the background density in the image, and as a result, the entire image is crushed in black or on the contrary white. I was sorry. In the Otsu method, when the distributions of the two classes are extremely different, there is a property that the threshold is shifted to the larger class, and therefore a noisy binary image is generated.
[0006]
Therefore, the present applicant has filed an application in Japanese Patent Application No. 7-22895 for a method capable of automatically setting an appropriate binarization threshold between the object density and the background density in the image.
[0007]
The flow of threshold determination in the application will be described below.
[0008]
In FIG. 20, first, in step S1, an 8-bit multi-value image is input. The multivalued image is input by an image input device such as a scanner. In step S2, a histogram of the entire input image is calculated. Here, using all the pixels in the image, the frequency for each digital value from 8 bits, that is, “0” to “255” is calculated. Thereby, for example, a histogram shown in FIG. 21 is obtained.
[0009]
In step S3, “0” and “255” are set in the parameters START and END, respectively. START and END correspond to the start point and end point of the statistical value of the luminance value obtained in the subsequent steps S4 and S5, respectively.
[0010]
In step S4, the average value AV of the pixels corresponding to the digital values from START to END is calculated. For example, if START = 0 and END = 255, the average value AV of pixels having values from “0” to “255” (in this case, all pixels) is calculated. If START = 0 and END = 177, “ An average value AV of pixels having values from “0” to “177” is calculated.
[0011]
In step S5, the skew value SK of the pixel corresponding to the luminance value from START to END is calculated. The skew value is a statistic indicating the bias of the histogram distribution. The following formula is used for calculating the skew value.
[0012]
SK = (Σ (Xi−AV) ^ 3) / D
(Note that R ^ 3 indicates the third power of R.)
[0013]
Here, Xi is the luminance value of the pixel. D is a dispersion value of the entire image, and is calculated by the following equation.
[0014]
D = Σ (Xi-AV) ^ 2
(Note that the square of R is indicated by the notation of R ^ 2.)
[0015]
In the above formula, the skew value is calculated by raising the difference between the luminance value of each pixel and the average value to the third power. However, the skew value is not limited to the third power as long as it is an odd power.
[0016]
Subsequently, in steps S6 and S7, the direction of histogram bias is determined. First, in step S6, the bias direction of the histogram is determined by the following equation. This is a determination as to whether or not the histogram bias is in the range of values smaller than the average value AV.
[0017]
SK <−1.0
[0018]
If the above formula is true in step S6, the process proceeds to step S10, and if false, the process proceeds to step S7. In step S10, START is not changed, and average value AV is set to END. Then, returning to step S4, the average value AV from the START value to the END value is calculated again.
[0019]
On the other hand, in step S7, the direction of bias of the histogram is determined by the following equation. This is a determination as to whether or not the histogram bias is in the range of values greater than the average value AV.
[0020]
SK> 1.0
[0021]
If the above formula is true in step S7, the process proceeds to step S11, and if false, the process proceeds to step S8. In step S11, the average value AV is set to START, and END is not changed. Then, returning to step S4, the average value AV from the START value to the END value is calculated again.
[0022]
On the other hand, in step S8, the average value AV when the conditions in steps S6 and S7 are both false is set as the binarization threshold TH. In step S9, simple binarization processing using the binarization threshold TH is performed.
[0023]
Hereinafter, the binarization processing in Japanese Patent Application No. 7-22895 will be described in more detail with reference to specific image examples.
[0024]
The binarization threshold value TH determination process will be described using the example of the histogram shown in FIG.
[0025]
FIG. 21 shows a histogram of an image (8-bit input). In FIG. 21, the horizontal axis represents the digital value of luminance representing “0”, that is, black, and the right end represents “255”, that is, white, and the vertical axis represents the frequency of each digital value. FIG. 22 is a diagram showing changes in the values of parameters in the process shown in steps S4 and S5 in the binarization process shown in FIG. 20 described above for an image having a histogram as shown in FIG. It is. In addition, each parameter value shown in FIG. 22 is each shown by the frequency | count of passing through step S4 and S5.
[0026]
First, in the first process that passes through steps S4 and S5, the average value AV and the statistic SK are calculated with START = 0 and END = 255, and values of “177” and “−78.9” are obtained, respectively. In this case, since the statistic SK is less than “−1.0”, START = 0 and END = 177 are set in step S10.
[0027]
Subsequently, in the second process, the average value AV and the statistic SK at START = 0 and END = 177 are calculated to obtain values “91” and “−8.6”, respectively. Again, since the statistic SK is less than “−1.0”, START = 0 and END = 91 are set in step S10.
[0028]
Subsequently, in the third processing, the average value AV and the statistic SK at START = 0 and END = 91 are calculated, and the values “43” and “9.6” are obtained, respectively. In this case, since the statistic SK exceeds “1.0”, START = 43 and END = 91 are set in step S11.
[0029]
Subsequently, in the fourth processing, the average value AV and the statistic SK at START = 43 and END = 91 are calculated, and the values “72” and “−7.0” are obtained, respectively. Again, since the statistic SK is less than “−1.0”, START = 43 and END = 72 are set in step S10.
[0030]
Subsequently, in the fifth processing, the average value AV and the statistic SK at START = 43 and END = 72 are calculated, and values of “58” and “−2.2” are obtained, respectively. Again, since the statistic SK is less than “−1.0”, START = 43 and END = 58 are set in step S10.
[0031]
In the sixth processing, the average value AV and the statistical quantity SK at START = 43 and END = 58 are calculated, and values of “50” and “−0.4” are obtained, respectively. Here, since the statistic SK is not less than “−1.0” and not more than “1.0”, the condition of Steps S6 and S7 is not satisfied, and the process proceeds to Step S8 to set the binarization threshold TH as “50”. Is set. In step S9, simple binarization processing using the binarization threshold TH is performed.
[0032]
In this way, the binarization threshold is determined so that the skew value converges to a predetermined value, and binarization is performed. That is, in the input multi-valued image, an area having a threshold most suitable for separating the background and the object in the image is identified based on the luminance frequency and its bias, and then the average of the specific area The luminance value is used as a threshold value.
[0033]
According to the threshold value determination method of Japanese Patent Application No. 7-22895, an appropriate threshold value can be set between the object density and the background density. However, when the processing flow of FIG. Since the method of convergence of the range varies depending on the input image, the range of calculation for the threshold value calculation differs greatly between the minimum and maximum cases. Therefore, in order to perform this calculation in a predetermined time, the processing frequency has to be increased, which has been a bottleneck for speeding up.
[0034]
Conventional numerical computation methods on computers include integer arithmetic and floating point arithmetic. Integer operations are performed at high speed within integer valid values that can be handled by computers (32767 to -32768 with 16-bit integers), and even faster within integer valid values inside computers (depending on the processing environment such as the CPU and system). Calculated. Floating-point operations are performed with numbers that have a numeric part and an exponent part, so it can be expressed from large numbers to numbers below the decimal point.
[0035]
There are a method of using a floating point arithmetic unit and a method of using an integer arithmetic unit in constructing a block to be calculated by an arithmetic unit, not by a computer program.
[0036]
However, the binarization threshold value determination method in the image processing numerical calculation device as described above has the following problems.
[0037]
When performing numerical processing of image processing with integer arithmetic, it is overwhelmingly faster than floating-point arithmetic, but errors occur due to truncation of the decimal part due to division, etc., and division is included in repetitive arithmetic In some cases, the error tends to increase and the accuracy cannot be maintained. In addition, there was a limit on the width of integers, and it was not possible to handle large numbers exceeding the limit or numbers after the decimal point.
[0038]
When performing numerical processing of image processing by floating point arithmetic, high accuracy can be maintained, but arithmetic processing is slow and processing time is long. In addition, there are not a few CPUs that do not have a floating-point arithmetic unit, and in this case, further processing time is required.
[0039]
In the calculation by hardware, the calculation speed is slow and the circuit scale is large when it is configured with a floating point arithmetic unit, and the calculation error due to truncation increases when it is configured with an integer arithmetic unit.
[0040]
In the case of floating-point arithmetic, there is always an operation for updating the value of the exponent part by normalizing the mantissa part for each arithmetic operation. Although this operation is not so much in multiplication and division, it requires a considerable number of clocks in addition and subtraction, and there is a disadvantage that the amount of hardware becomes large when trying to execute this with a small number of clocks. On the other hand, in integer arithmetic or fixed decimal arithmetic, there is a risk of overflow and a risk of deterioration in arithmetic accuracy due to rounding error. In order to obtain an arithmetic accuracy equivalent to that of floating point arithmetic in integer arithmetic, the number of digits of the arithmetic unit must be increased. In this case, an increase in hardware amount or a decrease in operable frequency is inevitable.
[0041]
The present invention has been made in view of the above-described technology, and when performing a binarization process by determining a binarization threshold value for binarizing a multilevel image, the process can be extremely speeded up. An object is to provide an image processing method.
[0042]
In addition, the present invention provides a high-speed repetitive operation that maintains a certain precision within a limited number of effective integer values that can be handled by a limited number of computers in image processing operations for multi-valued images, and in particular, converges from a large numerical value to a small numerical value. An object of the present invention is to provide an image processing method.
[0043]
[Means for Solving the Problems]
In order to achieve the above-described object, an image processing method according to the present invention includes a plurality of pixels in an image processing method for performing binarization processing by determining a binarization threshold value for binarizing a multilevel image. When performing binarization processing in units of blocks of a predetermined size, it is determined by input of multi-valued images in line sequential, binarization threshold determination processing in block sequential, and binarization threshold determination processing The binarization processing in line sequential is performed by pipeline processing using the threshold value, and the binarization threshold determination processing calculates the frequency for each luminance in the block in units of the predetermined size. The binarization threshold value is determined by calculating and calculating the luminance average value and the skew value from the luminance frequency, and each calculation is executed while being synchronized by pipeline processing.
[0044]
In order to achieve the above-described object, an image processing apparatus according to the present invention determines a binarization threshold value for binarizing a multi-valued image and performs binarization processing. An input means for inputting a multi-valued image in a line sequence and a binarization threshold value determining means for determining a binarization threshold value in the block order. And binarization means for performing binarization processing in line order using the threshold value determined by the binarization threshold value determination means, input of a multi-valued image by the input means, and the binarization threshold value Determining means for determining a binarization threshold value, and control means for executing binarization processing by the binarization means in a pipeline process, wherein the binarization threshold value determining means has the predetermined magnitude. For each block, calculate the frequency for each luminance in the block, and Determining the binarization threshold value by calculating an average luminance value and the skew value from the luminance frequency, further said control means executes while synchronizing the operation of the brightness average value and the skew value in the pipeline processing.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a system configuration for executing binarization processing in the present embodiment. In FIG. 1, 1 is an image processing apparatus that performs binarization processing, character recognition processing, and the like, 2 is an image input apparatus such as a scanner that inputs an image, and 3 is an image display apparatus that displays the processed image. It is.
[0046]
In the image processing apparatus 1, 4 is an input interface unit serving as an interface with the image input apparatus 2, 5 is a threshold value calculation for calculating a binarization threshold value from the input multi-valued image and binarizing the multi-valued image. It is a binarization part. A storage unit 6 stores image data, and a CPU unit 7 controls the entire image processing apparatus, and includes a CPU, a ROM, a RAM, and the like. 8 is a character recognition unit that performs character recognition processing on an area extracted as a character region, 9 is an image processing unit that performs various image processing and image layout processing on regions separated into regions other than the character region, An output interface unit serving as an interface with the image display device 3 (the processing of the character recognition unit 8 and the image processing unit 9 may be executed by the CPU unit 7 by a program).
[0047]
Multi-valued image data input from the image input device 2 through the input interface unit 4 is input to the threshold calculation binarization unit 5. The threshold calculation binarization unit 5 calculates a binarization threshold for each predetermined area (64 × 64 pixels) and converts multi-value image data of 64 × 64 pixels into a binary image. Details of the inside 5 of the threshold calculation binarization unit will be described later. The converted binary image data is stored in the storage unit 6. Of the images stored in the storage unit 6, an image identified as a character region is subjected to character recognition processing and converted into a character code.
[0048]
FIG. 2 is a diagram showing the inside of the threshold calculation binarization unit 5.
[0049]
In the threshold calculation binarization unit 5, 201 is an input unit for inputting multivalued image data, and 207 is a buffer memory for storing image data from the input unit 201 for the number of lines in a predetermined area. Reference numeral 206 denotes a memory control unit that controls data input / output of the buffer memory 207. Reference numeral 205 denotes a binarization threshold value calculation unit that calculates a luminance frequency for each predetermined area of the input image and a binarization threshold value corresponding thereto. 204 is a result storage unit capable of storing a plurality of bands of threshold data obtained by the binarization threshold value calculation unit 205, 203 is an image conversion processing unit that creates a binary image from a multi-valued image, An output unit 202 outputs the converted binary image. A control unit 208 receives an instruction from the CPU unit 7 and controls the threshold calculation binarization unit 5 as a whole. The threshold calculation binarization unit 5 handles multi-valued images with luminance. Therefore, what is meant by 8-bit luminance data is 0 for the darkest black and 255 for the lightest white. Although this meaning may be different between the image input device 2 and the image display device 3, in this case, the input unit 201 and the output unit 202 perform inversion processing.
[0050]
FIG. 3 is a diagram showing details of the binarization threshold value calculation unit 205.
[0051]
Reference numeral 301 denotes a luminance frequency calculation unit, 302 denotes a threshold value calculation unit, 303 denotes a multiplexer, and 304 and 305 denote luminance frequency storage RAMs. The luminance frequency storage RAMs 304 and 305 are constituted by a two-port RAM, one port is read-only, and the other port is write-only, and both are connected to the multiplexer 303. The RAMs 304 and 305 are alternately connected to the luminance frequency calculation unit 301 and the threshold value calculation unit 302 via the multiplexer 303.
[0052]
FIG. 4 is a diagram showing these operation timings. First, in FIG. 2, multivalued image data input in raster order through the input unit 201 is written into the buffer memory 207 via the memory control unit 206. When data for 64 lines is input, 64 × 64 block data is sequentially read from the buffer memory 207 and input to the binarization threshold value operation unit 205 via the memory control unit 206. The luminance frequency calculation unit 301 counts the frequency for each luminance in the block of 64 × 64 pixels from the memory control unit 206. The frequency of each luminance is counted at a location having the luminance value of the luminance frequency storage RAM as an address. If the luminance frequency of the first block is generated in the luminance frequency storage RAM 304, the next luminance frequency is generated in the luminance frequency storage RAM 305. The threshold calculation unit 302 operates with a delay of one block with respect to the processing of the luminance frequency calculation unit 301. That is, during the time when the luminance frequency calculation unit 301 is processing the Nth block, the threshold value calculation unit 302 processes the N-1th block. Details of the luminance frequency calculation unit 301 and the threshold value calculation unit 302 will be described later. The threshold value calculated by the threshold value calculation unit 302 is stored in the result storage unit 204. The binarization process is started from a position delayed by about 128 lines with respect to the multi-value image input.
[0053]
FIG. 5 shows a flow of data input / output in the buffer memory 207. The flow from the input unit to the buffer memory (multi-valued image input) is line sequential, and the output from the buffer memory to the binarization threshold value calculating unit is 64 pixel × 64 line block sequential, from the buffer memory to the image conversion processing unit Multi-valued images flow in line sequential. Accordingly, a binary image output is also output line by line from the image conversion processing unit 203.
[0054]
FIG. 6 is a diagram showing input / output of the buffer memory 207 in response to image input. Each process of input, calculation, and output is accessed by subdividing. To explain, when accessing 32 pixels (32 bytes) unit, input / output of 32 bytes of input, 32 bytes of operation and 32 bytes of output within the time with the input clock of 32 pixels of multi-valued image as the unit of processing. (When 3 accesses compete).
[0055]
The input / output rate of the buffer memory is 3 times the image input rate, but if the data width of the buffer memory is 16 bits, it becomes 1.5 times. By adjusting the data width of the buffer memory in this way, an input / output rate suitable for the memory speed can be obtained. The memory control unit 206 has a small buffer (FIFO memory) that absorbs the difference between the image input speed and the input / output speed of the buffer memory in about 64 bytes (32 bytes × 2). In addition, when the input, calculation, and output processing buffers are divided into banks, switching cannot be performed unless the processing of each bank is completed, but since the processing is not separated, the start of each processing can be freely performed. Referring to FIG. 6, the input, calculation, and output start intervals must be equal, but the output process start is slightly advanced as can be seen from the figure. This makes it possible to reduce the output time difference with respect to the input of each line.
[0056]
FIG. 7 is a diagram showing the relationship between the configuration of the luminance frequency calculation unit 301 and the luminance frequency storage RAM 304/305, and FIG. 8 is a diagram showing the calculation processing timing of the luminance frequency.
[0057]
Reference numeral 501 denotes a value check unit that checks whether or not the same luminance data is continuously input. Reference numeral 502 denotes a RAM read unit that reads out data of the luminance frequency storage RAMs 304 and 305 corresponding to the input luminance value. A +1 addition unit that adds +1 to the read data, 504 is a RAM write unit that writes back the added data to the luminance frequency storage RAMs 304 and 305, and 505 is a data multiplexer that avoids inconsistency in pipeline processing. . As shown in FIG. 8, the luminance frequency calculation unit 301 performs the same address (luminance value) check, memory read, +1 addition process, and write process in a pipeline. However, if the same luminance data is input while the data read from the luminance frequency storage RAM is subjected to +1 addition processing and written back, the luminance frequency cannot be counted correctly because the data before the +1 addition is processed as it is. . Therefore, the check unit 501 with the same address checks whether there is the same data within the number of stages of the pipeline. For example, when the value check unit 501 processes the Nth data, the value is compared with the values of the previous N-1 and N-2th data to check for the same value. If there is the same luminance data, the data is fed back by the multiplexer 505, and the data reading means ignores the data from the luminance frequency storage RAM so that the luminance frequency can be counted correctly. In addition, when the pattern is such that the read operation and the write operation are simultaneously performed on the same address, the read operation is prohibited. If the processing block is 64 × 64 pixels, the luminance frequency is 0 to 4096, and a 13-bit width memory is required, but it is limited to 4095. In addition to the 12 bits, 1 bit is used as an initialization flag. The initialization flag is set to 1 at the start of operation, and the data with the initialization flag of 1 is treated as 0 regardless of the other 12 bits. The initialization flag is set by the next threshold value calculation unit 302.
[0058]
FIG. 9 is a diagram showing the configuration of the threshold value calculation unit 302 and the relationship with the luminance frequency storage RAM 304/305. Reference numeral 304/305 denotes a luminance frequency storage RAM which is a RAM having a luminance value ranging from 0 to 255 as an address value.
[0059]
Reference numeral 601 denotes a clear processing unit that processes the initialization flag in the luminance frequency storage RAMs 304 and 305. Reference numeral 602 denotes an average value calculation unit that calculates the average luminance from the luminance frequency in the designated range, and 603 denotes a skew calculation unit that calculates the skew from the luminance frequency in the designated range. The output of the luminance frequency storage RAM 304/305 is connected to the average value calculation unit 602 and the skew calculation unit 603, and the read data is input in parallel. Reference numeral 604 denotes a determination unit that receives the outputs of the average value calculation unit 602 and the skew calculation unit 603 and determines whether or not to end. A control unit 605 performs overall control, and mainly manages a range. Reference numeral 606 denotes a threshold value calculation unit that performs upper and lower threshold processing.
[0060]
Next, the flow of binarization threshold value determination processing in the present embodiment will be described in detail with reference to the flowcharts of FIGS.
[0061]
In step S701, “0” and “255” are set in the parameters START and END, respectively. At the same time, the MF, KF, and TF flags used in image feature discrimination, blurred character processing, and collapsed character processing, which will be described later, are initialized to “OFF, ON, OFF”, and “1” is set to the threshold determination processing loop count i. set. START and END correspond to the start point and end point of the statistics (average value and skew value) of the luminance values obtained in steps S702 and S704 in the subsequent stage, respectively.
[0062]
In step S702, an average value AV of pixels corresponding to digital values from START to END is calculated. For example, if START = 0 and END = 255, an average value AV of pixels having values from “0” to “255” is calculated. If START = 0 and END = 109, “0” to “109” are calculated. An average value AV of pixels having values up to “is calculated.
[0063]
When k is a luminance value from 0 to 255 and Pk or P (k) is a distribution amount corresponding to the luminance value, the average value AV is
AV = Σ (k × P (k)) ÷ ΣP (k) (k = START... END) (1)
It becomes.
[0064]
In S703, the threshold determination processing loop count i is determined. If i is "10", the process proceeds to step S718, and if other than "10", the process proceeds to step S704.
[0065]
In step S704, the skew value SK of the pixel corresponding to the luminance value from START to END is calculated. The skew value is a statistic indicating the bias of the histogram distribution. The following equation (2) is used to calculate the skew value.
[0066]

In equation (2) for obtaining the skew value, the denominator is the variance value of the entire image, and the numerator is calculated by raising the difference between the luminance value of each pixel and its average value to the third power. It is not limited to the third power.
[0067]
In step S705, a determination is made of the number i of threshold value determination processing loops in one processing block (i = 1, that is, whether the first loop). If i is “1”, the process proceeds to step S706. If i is other than “1”, the process proceeds to step S709. In step S706, image feature determination is performed to determine whether the block being processed is a “character block”, and the process advances to step S718. Details of the image feature determination (S728 to S729, S707 to S708) will be described later, but if it is determined to be a character block, MF is set to “ON”.
[0068]
In step S709, the magnitude of the histogram bias is determined as shown in equation (3).
[0069]
| SK | <0.125 (3)
That is, it is determined whether the absolute value of the skew value SK is less than “0.125”. If step S709 is true, the process proceeds to step S719, and if false, the process proceeds to step S710.
[0070]
In step S710, blurred character processing is performed. If the condition of S710 is satisfied, the process proceeds to S719, and if not, the process proceeds to S711. Details of the blurred character processing (S710, S730 to S731, and S712 to S713) will be described later.
[0071]
In step S711, the threshold determination process loop count i is determined. If i is "2", the process proceeds to step S712, and if other than "2", the process proceeds to step S716. In step S714 that proceeds when i is “2”, it is determined whether or not the block being processed is a “collapsed character block”, and merges in step S716. Although details of the collapsed character processing (S714, S732 to S733, S715) will be described later, if it is determined that the block is a collapsed character block, the collapsed character flag TF is set to “ON”.
[0072]
In step S716, the direction of the histogram bias is determined by the following equation (4).
[0073]
SK> = 0 (4)
[0074]
In step S716, if the expression (4) is true (means that the histogram bias is in a range of values larger than the average value AV), the process proceeds to step S717, and false (a value in which the histogram bias is smaller than the average value AV). If it is within the range, the process proceeds to step S718.
[0075]
In step S717, the average value AV is set in START, and END is not changed. Then, the process proceeds to step S734. In step S718, START is not changed, and average value AV is set in END. Then, the process proceeds to step S734. In step S734, “1” is added to the threshold value determination processing loop count i, and the process returns to step S702 to calculate the average value AV from the START value to the END value again. Thus, by setting the binarization threshold value so that the skew value SK converges to a predetermined value, the background can be removed and a clear binary image can be obtained.
[0076]
In step S719, the average value AV is set as the binarization threshold TH. Steps S720 to S727 are the obtained binarization threshold TH limiting process, and details will be described later. When this threshold value limiting process is performed, the threshold value determining process ends.
[0077]
As described above, the binarization processing in the present embodiment is performed, but the ranges shown by the equations (3) and (4) are not limited to this.
[0078]
The binarization threshold value determination process described with reference to this flowchart is executed by the circuit in FIG. 9 but is modified as follows in order to ensure calculation accuracy.
[0079]
Since the range of the luminance value k is 0 to 255, the average value AV is also a value in the range of 0 to 255. However, when calculating the skew SK, the luminance k is basically based on the difference value (k−AV) of the average value AV. Since the area between START and END, which are the operation areas, becomes narrower after 10 repetitions, the difference value gradually decreases, and ΣPi similarly decreases. Therefore, since the values of the denominator and the numerator part in the expression (2) become smaller, it is necessary to increase the denominator / numerator arithmetic digit when the number of significant digits of the skew SK is secured to the same extent as the first loop. . In other words, there is no choice but to increase the number of digits after the decimal point.
[0080]
In the equation (1), if X is (14− (number of bits of (END-START))),

The relationship with the original average value AV is
AV = AV ′ ÷ 2 ^X + START (4)
It becomes.
[0081]
When the initial loop START = 0 and END = 255 (END-START fits within the 8-bit range), if the average value AV is obtained with an integer part of 8 bits and a decimal part of 7 bits, the second and subsequent times ( If (END-START) is in the 7-bit range, the integer part is 7 bits, so that even if the decimal part is obtained up to 8 bits, processing can be performed by the same arithmetic unit. To explain, since the offset processing is performed by (k-START) in equation (3) and scaling is performed by X, even if the same division part is calculated by 13 bits divided by 27 bits, the number of digits after the decimal point is from 7 to 14 Change. The increase in the number of digits after the decimal point is in step with the decrease in the denominator / numerator value in (2).
[0082]
Similarly, assuming that Y is (12− (the number of bits of Σp (i))) (however, if Y is a negative value, 0), equation (2) is
tmpA = (k-START) × 2 ^X -AV '(5)
tmpB = ((tmpA × tmpA) / 2 ⁷ ) × (p (k) × 2 ^Y (6)
tmpC = Σ (tmpA × (tmpB ÷ 2 ^Three )) (7)
D = (ΣtmpB) ÷ 2 ⁷ (8)
E = | tmpC | ÷ 2 ^{X + 5} (9)
S: Symbol of tmpC (10)
SK ′ = E ÷ D (11)
And transformed. Here, SK ′ is equal to | SK |.
[0083]
Before explaining the internal configuration of each part in FIG. 9, the processing flow of the threshold calculation in FIGS. The operation flow of the average value calculation unit 602, the skew calculation unit 603, and the determination unit 604 is roughly shown, but the portions that operate simultaneously are shown side by side, and the passage of time is illustrated vertically.
[0084]
First, description will be made assuming that the n-th average value and the skew are AVn and SKn (the previous stage is Dn, En, and Sn). First, as phase P801, START = 0 and END = 255 are initialized. As phase P 802, data in the range of END to START is read from the luminance frequency storage RAM 304/305 and input to the average value calculation unit 602. Thus, an average value AV′1 of luminance from luminance 255 to 0 is calculated. Next, in phase P803, data in the range of 255 to 0 is read from the luminance frequency storage RAM 304/305 and input to the skew calculation unit 603 to calculate D1, E1, and S1. At the same time, an average luminance AV′2 in the range of 0 to AV1 is calculated by the average calculation unit 602. In the next phase P804, END is set to AV1, and in phase P805, the average value AV'3b between AV2 and END and the average value AV'3a between START-AV2 are calculated by the average value calculation unit 602, and between END-START Skews D2, E2, and S2 are calculated by the skew calculation unit 603. During this phase P804 to P805, image feature discrimination is performed using SK′1 obtained by calculating D1 / E1 by the determination unit 604 simultaneously.
[0085]
In phase P805, two AV3a and AV3b are obtained as AV3. In the following phase P806, the next calculation range is determined. That is, if the sign of SK2, that is, S2 is positive, AV3a is AV3. Become. Originally, it is not determined whether the area for obtaining AV3 is between START-AV2 or AV2-END until the calculation of S2, that is, SK2, is completed, but SK2 (D2, E2, S2) In order to access data between START-AV2 and END for the calculation, the average value calculation unit 602 obtains two values of an average value AV3a between START-AV2 and an average value AV3b between AV2 and END. Since the data in the luminance frequency storage RAM 304/305 is input with a time shift such as START-AV2 and AV2-END, it is not necessary to have a plurality of average value calculation units 602. AV′3a, AV′3b, D2, E2, and S2 are input to the determination unit 604, and AV3 is determined by the sign of S2 and output to the control unit. The control unit 605 resets START and END based on the received average value, determines the next calculation range, and calculates the next average value and skew (AV4, D3, E3, S3). At the same time, the determination unit 604 calculates D2 / E2, and performs an end determination of | SK2 | <0.1, a collapsed character process, or a blurred character process. For more characters blurred character collapse will be described later in one process either because it is opposing properties is performed. When the end condition is satisfied by these processes, AV2 is output as the threshold value TH, and the control unit 605 stops the operations of the average value calculation unit 602 and the skew calculation unit 603 that are being calculated and ends all the processes.
[0086]
If the end condition is not satisfied, the same process is continued. Finally, when the calculation of the average value AV10 for the tenth time is completed and the end determination is made for SK9, AV9 is set as the threshold value TH. If not established, AV10 ends with the threshold value TH.
[0087]
As described above, when the average value calculation unit 602, the skew calculation unit 603, and the determination unit 604 operate simultaneously to perform calculation, and the determination unit 604 performs n-th calculation, the skew calculation unit 603 has (n + 1). The average value calculation unit 602 performs the (n + 2) th calculation in the pipeline. However, it is not a simple pipeline operation, and the operations of the average value calculation unit 602 and the skew calculation unit 603 are performed in synchronization, so that the luminance frequency storage RAM 304/305 can be processed by one.
[0088]
By the way, when three values of START, AVn, and END are given in the average value calculation unit 602, the luminance data at a location corresponding to AVn is accessed twice in order to obtain an average value between START-AVn and AVn-END. However, if it is configured as shown in FIG. 16 as an example, only one access is required.
[0089]
FIG. 16 is a block diagram showing a detailed configuration of the average value calculation unit 602.
[0090]
Data in the luminance frequency storage RAM 304/305 is accessed from 255 to 0. Reference numeral 901 denotes an arithmetic unit that obtains the END-START and X values from the input START and END values. Since the average value calculation unit 602 calculates two average values, the values of START, AVn, and END are actually input to the inputs A and B.
[0091]
Reference numeral 902 denotes a counter that inputs an END-START value and counts down to 0. Reference numeral 903 denotes a multiplier that multiplies the inputs A and B. The input A of the multiplier 903 has a luminance, that is, a luminance frequency storage RAM 304/305. The address value at the time of reading data-the value of START, that is, the output of the counter 902 is inputted, and the read frequency data is inputted to the input B. The multiplier 903 calculates (k−START) × P (k). Reference numeral 904 denotes an adder that calculates Σ (k−START) × P (k). A register 905 holds two outputs of the adder 904. Reference numeral 906 denotes a shifter that shifts the output of the register 905 according to the value of X obtained by the arithmetic unit 901. This shift amount determines the number of digits after the decimal point of AV′n. Reference numeral 907 denotes a temporary register that temporarily holds data at a location corresponding to a luminance of AVn. Reference numeral 908 denotes a multiplexer, and 909 denotes an adder. The multiplexer 908 selects whether the input to the adder 909 is the data of the register 907 or the output of the adder 909 is fed back, and is normally selected to feed back the output. The adder 909 calculates ΣP (k).
[0092]
Reference numeral 910 denotes a register which holds the value when the data of the adder 909 is determined. Since two average values must be obtained, it has a capacity to store two outputs. Reference numeral 911 denotes a divider which inputs data from the registers 905 and 910 and obtains an average value.
[0093]
The register 907 delays the data of P (k). First, the adders 904 and 909 are initialized and set to 0, and the calculation is started from k = END. When the data of k = AVn is calculated, the outputs of the adders 904 and 909 are saved in the registers 905 and 910. In the operation of k = AVn + 1, the multiplexer 908 selects the data in the register 907, so that the adder 507 performs the operation of P (AVn) + P (AVn + 1). In the adder 904, since the value of the overlapping data is 0 on the input A side, a temporary register for delay purposes is not necessary. Thereafter, when the calculation up to k = START is completed, the result is output to the registers 905 and 910 again.
[0094]
By doing so, data is read once, so that it is not necessary to stop the skew calculation unit 603 for synchronization after the average value calculation unit 602 and the skew calculation unit 603 start operating.
[0095]
FIG. 17 is a configuration diagram of the skew calculation unit 603.
[0096]
A counter 1001 loads the value of END-START and counts down to zero. A shifter 1002 receives the X calculated by the average value calculation unit 602 and performs a calculation of (k-START) × 2X. Reference numeral 1003 denotes a subtractor, which performs an operation of (k-START) × 2X-AV ′, that is, tmpA. Reference numeral 1004 denotes a multiplier that performs an operation of tmpA × tmpA. An arithmetic unit 1005 calculates Y from the value of ΣP (k) calculated by the average value calculation unit 602. Reference numeral 1006 denotes a shifter, which is a value of Y, and the luminance distribution amount P (k) to (P (k) × 2 ^Y ). Reference numeral 1007 denotes a multiplier, and (tmpA × tmpA ÷ 2 ⁷ ) × (P (k) × 2 ^Y ) That is, tmpB is calculated. Reference numeral 1008 denotes a delay, which delays the output of the subtracter 1003 by the number of operation clocks of the multipliers 1004 and 1007. Reference numeral 1009 denotes a multiplier, which is tmpA × (tmpB ÷ 2 ² ). Reference numeral 1010 denotes an adder that calculates ΣtmpB and outputs the result of D. Reference numeral 1011 denotes an adder, and ΣtmpA × (tmpB ÷ 2 ² ). Reference numeral 1012 denotes an arithmetic unit. | ΣtmpA × (tmpB ÷ 2 ² ) | ÷ 2 ^{X + 5} And E and its code S are output.
[0097]
FIG. 18 is a block diagram illustrating details of the determination unit 604 that determines the threshold calculation end condition.
[0098]
Reference numeral 1101 denotes a comparator which determines E × 8 <D, that is, | SK | <0.125 from the values of D and E obtained by the skew calculation unit 603. Reference numeral 1102 denotes a divider, which similarly calculates E ÷ D from the value of D <E to obtain the value of SK′n, that is, | SKn |. Reference numeral 1103 denotes an image feature determination unit, 1104 denotes a blurred character processing unit, and 1105 denotes a collapsed character processing unit. 1103, 1104, and 1105 include MF, KF, TF, and SK1 shown in FIGS. 10 to 14 and are managed in common.
[0099]
Now, the image feature discrimination unit 1103 will be described with reference to FIGS. 10 and 12 again. In step S701, “0” is set to the character flag MF indicating whether or not the block being processed is “character block” at the start of operation, and the process waits for the first skew value calculation in step S704. When the first skew value (D1 and E1 at this stage) is calculated, the image feature determination S706 is entered. When the sign S of the skew value is negative (S728), the process proceeds to step S729, and the sign S is not negative. Proceeding to step S718, the image feature determination is terminated. In step S729, the skew value SK′1 calculated by the divider 1102 is used to determine whether or not the block being processed is a “character block” according to equation (12).
[0100]
SK ′> MH (12)
Here, MH is a value indicating whether the block being processed is a “character block”, and is a value set by the CPU unit 7 in the control unit 208. Here, “MH = 20”. In step S729, if the expression (12) is true, the process proceeds to step S707, and if it is false, the image feature determination process is terminated. In step S707, the character flag MF indicating that the block being processed is a “character block” is set to “1”, and the skew value obtained in the next step S708 is held in SK1 to determine this image feature. Finish the process.
[0101]
As described above, the image feature determination processing according to the present embodiment is performed, but the condition shown in Expression (12) is not limited to this.
[0102]
Next, the collapsed character processing unit will be described in detail with reference to FIGS. 10 and 14.
[0103]
Here, the collapsed character is a collapsed character because of the large number of strokes of one character, and a threshold value that can be favorably reproduced when it is determined to be a collapsed character is assigned.
[0104]
In step S <b> 701, “OFF” is set in the collapsed character flag TF indicating whether the block being processed is a “collapsed character block”. When the second skew calculation (D2, E2) is completed, the process proceeds to step S714. When the character flag MF is “ON” and the sign S is positive, the calculation is performed by the SK1 and the divider 1102 held in step S708. In step S733, the skew value SK'2 is used to determine whether or not the block being processed is a "collapsed character block" according to equation (13).
[0105]
SK1> = SR × SK′2 (13)
Here, SR is a value indicating whether the block being processed is a “collapsed character block”, and here, “SR = 3.0”. In step S733, if the expression (13) is true, the process proceeds to step S715. In step S715, “ON” is set in the collapsing character flag TF indicating that the block being processed is a “collapsed character block”, and the collapsing character processing ends.
[0106]
As described above, the collapsed character processing in the present embodiment is performed, but the condition shown in Expression (13) is not limited to this.
[0107]
Further, the blurred character processing will be described in detail with reference to FIGS. A faint character is a faint character, but in this example, an optimum threshold is assigned to the faint character. In step S701, “OFF” is set in the blurred character flag KF indicating whether the block being processed is a “blurred character block”. When the character flag MF is “ON” and the sign S is negative for the second and subsequent skew values, the SK1 held in step S708 and the skew value SK′n calculated by the divider 1102 are used, step S731. Then, whether or not the block being processed is a “blurred character block” is determined by the equation (13). Here, SR is a value indicating whether the block being processed is a “blurred character block”, and here, “SR = 3.0”. If the expression (13) is true in step S710, the process proceeds to step S719. If it is false, the process proceeds to step S711, and the process proceeds to S712 only when the number of loops is 2. If the code S is positive in step S712, the blurred character flag KF is set to “OFF”.
[0108]
SR is a value indicating whether the block being processed is a “blurred character block”, and here, “SR = 3.0”.
[0109]
As described above, the blurred character processing in the present embodiment is performed, but the condition shown in the equation (6) is not limited to this.
[0110]
In the second loop of FIG. 10, the blurred character processing and the collapsed character processing overlap, but S731 and S733, which are the main bodies of the processing, are the same processing, and as can be seen from S730 and S732, which is executed depending on the sign of the second skew. It will be decided. Therefore, since the two processes are exclusive and the same process, the influence on the circuit scale and execution time is small.
[0111]
When the end determination is made, the determination unit 604 outputs the average value AV to the threshold limiting unit 606, and the threshold limiting unit 606 sets the average value AV at that time to the threshold TH and proceeds to S720. When the processing block is not a character block, that is, when the character flag MF is “OFF”, the threshold TH is limited by the lower limit L and the upper limit H. That is, a restriction process is performed in which the threshold value TH is represented by L when the threshold value TH determined in step S719 is smaller than the lower limit value L, and is represented by H when the threshold value TH is larger than the upper limit value H. The lower limit value L and the upper limit value H are values determined by the characteristics of the image input device 2. If it is a character block, the process advances to step S725 to determine whether or not the collapsed character flag TF is “ON” (determination of whether or not the block being processed is a collapsed character block). If the result is a collapsed character block, the process proceeds to step S726. If the threshold value TH does not reach the upper limit value H in step S726, the process proceeds to step S727, and restriction processing is performed such that the threshold value TH is multiplied by a constant TP for preventing character collapse. The constant TP is 0.875, but is a value determined by the characteristics of the image input apparatus 2.
[0112]
FIG. 19 is a block diagram showing details of the result storage unit 204 and the image conversion processing unit 203 of FIG.
[0113]
The result storage unit 204 receives the threshold value of each block determined by the binarization threshold value calculation unit 205 and the character flag MF indicating whether or not the block is a character block, and stores it inside. A threshold value is input from the binarization threshold value calculation unit 205 at a time interval of 64 × 64 = 4096 pixels input. The internal memory capacity is 128 × 2 × 9 bits (8192 ÷ 64 = 128) when the maximum number of pixels in one line of the handled image is 8192 pixels. Since the image to be binarized is input line-sequentially from the memory control unit 206, the output from the result storage unit 204 to the image conversion processing unit 203 (1201 to 1211 described later) is input / output with a time interval of 64 pixels. Mediate conflicts. The inside of the image conversion processing unit 203 is 1201 to 1211. Reference numeral 1201 denotes a 16-bit register that temporarily stores data for two pixels read from the memory control unit 206. Reference numerals 1202 and 1203 denote comparators that simultaneously compare the two pixel data with the threshold value and output the result. Reference numeral 1204 denotes a 2-bit → 4-bit conversion register, and reference numeral 1205 denotes a 4-bit FIFO memory. The register 1204 receives the two-pixel binarized data (2 bits) from the comparators 1202 and 1203 twice, and outputs them to the FIFO memory 1205 when 4 bits are ready. Although 1201 to 1204 operate in synchronization with the internal operation clock and 1206 to 1211 operate in synchronization with the image input / output clock, the FIFO memory 1205 absorbs the difference in clock speed. Reference numeral 1206 denotes a memory for delaying a binary image by two lines and has a capacity of 2k × 8 bits. The function is equivalent to an 8k × 2 bit FIFO memory, but the processing is performed by a 1-port RAM by making the bus width four times as large as 8 bits. The image clock is accessed once every two clocks. Reference numerals 1207, 1208, and 1209 denote shift registers, which create a window of 3 pixels × 3 pixels. A character flag delay memory 1210 has a capacity of 128 + α bits. Reference numeral 1211 denotes an isolated point removing unit which examines a pixel around a target pixel of the shift register 1208, that is, a central pixel of 3 × 3 pixels, and if it is an isolated point, converts it into a white pixel “1” and outputs it. The output from the delay memory 1210 to the isolated point removing unit 1211 is the value of the character flag MF of the block including the pixel of interest. If the character flag is “1”, isolated point removal is performed. If it is stopped, the target pixel is output through.
[0114]
It should be noted that the binarization threshold value of the 64 × 64 block in the vicinity thereof is used as the binarization threshold value of the portion deviating from the 64 × 64 processing block.
[0115]
In the above-described embodiment, the block size is 64 × 64, but is 128 × 128 when the image resolution is doubled, and 32 × 32 when the resolution is ½. Even when the block size is reduced, the calculation accuracy can be secured with the same hardware by Y that changes depending on the total number of pixels in the equations (5) to (11). When the block size is increased, the bit width (capacity) of the luminance frequency storage RAM is increased and the number of bits of the arithmetic unit of the average value calculation unit and the skew calculation unit for calculating the threshold value is also increased. That is, the arithmetic system is designed with the maximum value of the resolution of the image to be processed.
[0116]
However, if a sufficient number of samplings (the number of pixels constituting the luminance frequency) is necessary, data can be thinned out and processed. For example, if 4096 pixels are sufficient, the luminance frequency jumps from the 128 × 128 region to 4096 pixels. In this case, the configuration of the threshold calculation unit does not change. Even if the bit width of the luminance frequency storage RAM is increased by 2 bits and the low-order 2 bits of the luminance frequency storage RAM are input to the average value calculation unit and the skew calculation unit for calculating the threshold value, the configuration of the threshold value calculation unit is does not change.
[0117]
The required number of samplings is determined by the characteristics of the image input device.
[0118]
In the above embodiment, the size of the block is the same in the vertical and horizontal directions, but it may be rectangular.
[0119]
In the above-described embodiment, isolated points are removed only for blocks determined to be blocks, but may be performed for all blocks, or processing may be performed for all blocks.
[0120]
Further, when there is a margin in the operating frequency, the luminance frequency storage RAM may be configured with a 1-port RAM. A series of operations of reading out memory data corresponding to the luminance value, adding +1, and writing in the memory data is performed, so the number of processing clocks is about three times, but a circuit for monitoring pipeline mismatch is unnecessary. Become.
[0121]
Similarly, a device that stores the luminance frequency may be constituted by a counter. Although the circuit scale is large, one pixel can be processed with one clock, so that the operating frequency can be increased.
[0122]
As described above, according to the present embodiment, the band memory required for each process is unified into one block, so that only one set of memory control signals is required, and the number of signals can be reduced. Cheap. In addition, since each processing buffer is not physically separated, the start timing of each processing can be freely set.
[0123]
In addition, by configuring the luminance frequency storage memory with a multi-port RAM, the frequency for the luminance frequency accumulation can be reduced, and higher-speed operation becomes possible.
[0124]
In addition, since the calculation of the average value calculation unit for calculating the binarization threshold and the calculation of the skew calculation unit are synchronized with each other, it is pipelined so that it is originally executed sequentially or the average value calculation unit and the skew calculation unit Since only one luminance frequency storage RAM is required for each of these, it is possible to simultaneously realize high-speed processing and avoiding an increase in circuit scale.
[0125]
Further, since the isolated points of the characters and line drawing parts of the image are removed, it is easy to see and the recognition rate of character recognition is improved. Further, since the compression efficiency is also improved, the storage space for images and the transfer speed such as FAX are improved.
[0126]
Further, according to the present embodiment, the decimal point position of the calculation is determined, and the number of digits of the calculation value is rounded down and raised from the prediction of the value that the calculation value can take based on the numerical expression and the numerical data used for the calculation. And the final calculated value is stored within a preset effective number of digits.
[0127]
Furthermore, the decimal point position of the operation is determined for each processing unit.
[0128]
Further, the determination processing unit includes a determination unit that obtains an average value of luminance frequencies of the image and uses a unit for obtaining a bias of luminance frequency of the image as a processing unit.
[0129]
For example, the number of significant digits is determined by the required accuracy of the calculated value.
[0130]
With the above configuration, in multi-valued image processing operations, it is possible to maintain constant accuracy within a limited number of integers that can be handled by a limited number of computers, especially speeding up repeated operations that converge from large numbers to small numbers. It is possible to obtain a unique effect of being able to
[0131]
That is, all the calculations are divided into a plurality of processing units, and the number of digits that can obtain the required calculation accuracy is determined by examining the data range for each processing unit. The calculation is performed by moving the decimal point position of the integer operation according to the determined number of digits. As a result, integer processing is performed during each processing range, so that the amount of hardware can be reduced in the case of hardware calculations. In addition, since the decimal point position is optimal for each processing unit, the number of digits can be reduced to increase the accuracy.
[0132]
【The invention's effect】
As described above, according to the present invention, when performing a binarization process by determining a binarization threshold value for binarizing a multi-valued image, the process can be extremely speeded up.
[0133]
Further, in the calculation of image processing of multi-valued images, it is possible to maintain a certain accuracy within a limited number of effective numerical values that can be handled by a limited computer, and in particular, it is possible to speed up repeated operations that converge from a large numerical value to a small numerical value.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an overall configuration of an image processing apparatus according to an embodiment.
FIG. 2 is a block diagram showing a configuration of a threshold calculation binarization unit.
FIG. 3 is a diagram illustrating an internal configuration of a binarization threshold value calculation unit 205;
FIG. 4 is a diagram for explaining pipeline processing in a binarization threshold value calculation unit;
FIG. 5 is a diagram for explaining pipeline processing in a binarization threshold value calculation unit;
FIG. 6 is a diagram illustrating input / output of a buffer memory for image input.
FIG. 7 is a diagram illustrating a configuration of a luminance frequency calculation unit.
FIG. 8 is a diagram showing processing timing in a luminance frequency calculation unit.
FIG. 9 is a block diagram showing a configuration of a threshold value calculation unit.
FIG. 10 is a flowchart showing threshold value calculation processing.
FIG. 11 is a flowchart showing threshold value calculation processing;
FIG. 12 is a flowchart showing threshold value calculation processing.
FIG. 13 is a flowchart showing threshold calculation processing.
FIG. 14 is a flowchart showing threshold value calculation processing.
FIG. 15 is a timing chart in the threshold value calculation unit.
FIG. 16 is a block diagram showing a configuration of an average value calculation unit.
FIG. 17 is a block diagram illustrating a configuration of a skew calculation unit.
FIG. 18 is a block diagram illustrating a configuration of a determination unit.
FIG. 19 is a block diagram illustrating a configuration of a result storage unit and an image conversion processing unit.
FIG. 20 is a diagram for explaining threshold determination processing;
FIG. 21 is a diagram for explaining threshold determination processing;
FIG. 22 is a diagram for explaining threshold determination processing;
[Explanation of symbols]
1 Image processing device
2 Image input device
3 Image display device
4 Input I / F section
5 threshold calculation binarization unit
6 storage unit
7 CPU part
8 Character recognition part
9 Image processing unit
10 Output I / F section

Claims (8)

In an image processing method for determining a binarization threshold for binarizing a multi-valued image and performing binarization processing,
When performing binarization processing in units of a block having a predetermined size composed of a plurality of pixels, input of a multi-valued image in line sequence, binarization threshold value determination processing in block sequence, and binarization threshold value Using the threshold value determined in the determination process, the binarization process in line sequential is performed in the pipeline process,
The binarization threshold value determination process calculates a frequency for each luminance in the block for each block of the predetermined size, and calculates a luminance average value and a skew value from the luminance frequency to obtain a binarization threshold value. An image processing method characterized by determining and executing each operation while synchronizing with pipeline processing.   A processing buffer used in the input of the multi-valued image, the binarization threshold value determination process, and the binarization process is configured by a single memory block, and the single memory block is set for each predetermined processing unit. The image processing method according to claim 1, wherein time division is accessed.   In the binarization threshold value determination process, a memory for calculating the luminance frequency and a memory for calculating the average luminance value and the skew value are switched and used, and the calculation of the luminance frequency and the luminance 3. The image processing method according to claim 2, wherein the average value and the skew value are operated in a pipeline.   In the calculation of the skew value, a value that can be taken by the skew value is predicted from the information of the histogram range for calculating the skew value, the decimal point position of the calculation of the skew value is determined from the predicted value, and the digit of the calculated value 2. The image processing method according to claim 1, wherein the number is rounded down and rounded up, and the final calculation value is stored within a preset effective number of digits. In an image processing apparatus that performs a binarization process by determining a binarization threshold for binarizing a multi-valued image,
An input means for inputting a multi-valued image in a line sequence when performing binarization processing in units of a block of a predetermined size composed of a plurality of pixels;
Binarization threshold value determining means for determining the binarization threshold value in block order;
Binarization means for performing binarization processing in line order using the threshold value determined by the binarization threshold value determination means;
Control means for executing multi-level image input by the input means, determination of a binarization threshold by the binarization threshold determination means, and binarization processing by the binarization means by pipeline processing;
Have
The binarization threshold value determining means calculates a frequency for each luminance in the block for each block of the predetermined size, and calculates a luminance average value and a skew value from the luminance frequency to obtain a binarization threshold value. Further, the control means executes the calculation of the luminance average value and the skew value while synchronizing with the pipeline processing.   A processing buffer configured by a single memory block used for input of the multi-valued image, the binarization threshold value determination process, and the binarization process; and the control means includes the single memory block. 6. The image processing apparatus according to claim 5, wherein control is performed so that access is performed in a time division manner for each predetermined processing unit.   The control means controls to switch between a memory for calculating the luminance frequency and a memory for calculating the luminance average value and the skew value, and calculates the luminance frequency and the luminance average. 7. The image processing apparatus according to claim 6, wherein the value and the skew value are operated in a pipeline.   In the calculation of the skew value, the binarization threshold value determining means predicts a value that can be taken from the range of the histogram for calculating the skew value, and uses the predicted value to calculate a decimal point of the skew value. 6. The image processing apparatus according to claim 5, wherein the position is determined, the number of digits of the calculation value is rounded down and carried up, and the final calculation value is stored within a preset effective number of digits.

Images