JP3672758B2 - Debugging support device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
This invention makes it possible to debug a program on a sequencer peripheral device even if the units of the sequencer are not ready. Debugging support device It is about.
[0002]
[Prior art]
A conventional example will be described with reference to FIGS. FIG. 12 is a block diagram of a device configuration when debugging a program operating on a conventional sequencer peripheral device, and FIG. 13 is a flowchart showing a conventional debugging procedure. In FIG. 12, 1 is a sequencer peripheral device on which a debug target program 6z described later operates, 2 is a CRT, 3 is a keyboard, 4 is a sequencer, 4a is a CPU unit of the sequencer 4, 4b is a network unit of the sequencer 4, and 4c is a sequencer 4, 4 d is a sequence program that operates on the sequencer 4, 5 is a CPU, 6 is a memory, 6 z is a debug target program to be debugged, 7 a is a CRT interface with the CRT 2, and 7 b is a keyboard with the keyboard 3 An interface 7 c is a network interface that is an interface with the sequencer 4.
The sequencer 4 normally uses a combination of a plurality of units such as a power supply unit (not shown), a CPU unit, and various functional units. In the sequencer 4 of FIG. 12, a CPU unit 4a and a network unit 4b having a network function are combined.
[0003]
Next, a procedure for debugging a program on a conventional sequencer peripheral device will be described with reference to the flowchart of FIG. First, in step S5101, the process starts from preparing a debugging environment. In step S5102, a CPU unit 4a (hereinafter referred to as a target CPU unit) of the sequencer 4 to be connected to the sequencer peripheral device 1 is prepared. If the target CPU unit 4a cannot be prepared in step S5103, a CPU unit compatible with the target CPU unit 4a (hereinafter referred to as a compatible CPU unit) is prepared in step S5104. If a compatible CPU unit cannot be prepared in step S5105, the debugging operation is interrupted in step S5106.
[0004]
If the target CPU unit 4a has been prepared in step S5103 or a compatible CPU unit has been prepared in step S5105, a network unit 4b of the sequencer 4 for network connection with the sequencer peripheral device 1 is prepared in step S5107. If the network unit 4b cannot be prepared in step S5108, the debugging operation is interrupted in step S5106. If the network unit 4b is prepared, the sequencer peripheral device 1 and the sequencer 4 are connected in step S5109. In step S5110, the sequencer 4 is activated to execute the sequence program 4d.
[0005]
In step S5111, the debug target program 6z is executed in accordance with the start command input from the keyboard 3 of the sequencer peripheral device 1. If the debug target program 6z transmits / receives data to / from the sequence program 4d running on the sequencer 4 in step S5112, the debug operation is terminated in step S5114. If the debug target program 6z does not operate correctly, such as data cannot be transmitted / received or there is an error in the transmitted / received data, the debug target program 6z is stopped by a stop command input from the keyboard 3 in step S5113. The process proceeds to the modification work of the debug target program 6z, and after the modification, the process returns to step S5111, and the operation confirmation work is repeated.
[0006]
FIG. 14 shows a block diagram of a device configuration when debugging a program that operates on a conventional sequencer peripheral device as in FIG. 12, but here, especially when debugging a program in the communication portion between the sequencer peripheral device and the network unit. The equipment configuration of is shown. In the figure, reference numeral 19 denotes a dedicated decryption device (hereinafter referred to as a message analysis device) for decrypting a message passing through a communication line.
[0007]
Conventionally, after installing a message analysis device 19 which is a dedicated debugging device on a communication line, the debug target program 6z and the sequence program 4d are started, and while the message transmitted and received by the message analysis device 19 is monitored and confirmed. I was debugging.
[0008]
[Problems to be solved by the invention]
In the debugging procedure when debugging a program operating on a conventional sequencer peripheral device, all the necessary sequencer units, that is, in the above example, the sequencer CPU unit and network unit connected to the sequencer peripheral device must be prepared. Could not do debugging work. In addition, when a compatible CPU unit is used, a rough operation can be confirmed, but the operation may differ from that when the target CPU unit is used due to a difference from the target CPU unit, for example, a difference in the number of usable devices. Yes, I could not debug with high accuracy. In addition, every time the configuration of the system to be debugged changes, a CPU unit and a network unit must be prepared, which is troublesome.
[0009]
Further, in the case of the configuration using the message analysis device, there is a trouble of preparing and installing the message analysis device. In addition, when installing a message analysis device, it is necessary to temporarily stop the sequencer peripheral device and the sequencer, so it is impossible to install / remove the message analysis device during debugging.
[0010]
Further, in the conventional debugging procedure, a sequencer connected to the sequencer peripheral device and the sequencer peripheral device are required. Therefore, the debugging operation cannot be performed unless both devices are prepared.
[0011]
The present invention has been made to solve the above-described problems. In debugging a program operating on a device connected to a sequencer and a network (hereinafter referred to as a sequencer peripheral device), the sequencer is connected to a personal computer (hereinafter referred to as a personal computer). ), And by selecting each sequencer unit on the personal computer, the sequencer with various system configurations can be emulated and debugged. Debugging support device The purpose is to obtain.
[0012]
In addition, the present invention enables debugging of a communication program in an application on the sequencer peripheral device by monitoring the message transmitted from the sequencer peripheral device to the personal computer and the response message on the personal computer. Debugging support device The purpose is to obtain.
[0013]
In addition, the present invention makes it possible to realize a program running on a sequencer peripheral device and a sequencer emulation on a single personal computer. Debugging support device The purpose is to obtain.
[0014]
[Means for Solving the Problems]
In view of the above object, the present invention is directed to debugging a program operating on a sequencer peripheral device connected to a sequencer via a network. A debugging support device that supports Emulate sequencers in sequencer peripherals Built-in sequence program Connect a personal computer, Personal computer Select on personal computer According to the sequencer CPU unit name and network unit name A debugging support apparatus emulating a sequencer having a system configuration.
[0015]
In addition, the present invention further enables monitoring of a communication program in an application on the sequencer peripheral device by monitoring the message transmitted from the sequencer peripheral device to the personal computer and the response message on the personal computer. The feature is in the debugging support device.
[0016]
The present invention also relates to debugging a program operating on a sequencer peripheral device connected to the sequencer via a network. Is a debugging support device that supports a system, and includes a sequence program, emulates a sequencer, and also includes a program to be debugged. The sequencer has a system configuration according to the CPU unit name of the selected sequencer and the name of the network unit through Emulate The present invention is in a debugging support apparatus comprising a single personal computer.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
A debugging support apparatus according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a debugging support apparatus according to this embodiment, FIG. 2 is a flowchart showing a debugging procedure when the debugging support apparatus is used, and FIG. 3 is a CPU unit name and network of a sequencer emulated by a personal computer 4 is a flowchart showing virtual sequencer setting means for setting a unit name, FIG. 4 is a screen for inputting a CPU unit name and a network unit name, and FIG. 5 is a simulation means for simulating a sequence program operating on the sequencer on a personal computer. FIG. 6 is a flowchart showing data communication means for performing data communication with the sequencer peripheral device. In the figure, the same reference numerals as in the conventional example indicate the same or corresponding parts.
[0021]
In FIG. 1, 11 is a personal computer emulating a sequencer, 12 is a CRT, 13 is a keyboard, 15 is a CPU, 16 is a memory, 16a is a simulation means for simulating a sequence program, and 16b is data for data communication with a sequencer peripheral device. Communication means, 16c is a virtual sequencer setting means for inputting the CPU unit name and network unit name of the sequencer to be emulated, 16d is an area for storing the simulated state of the sequence program (hereinafter referred to as simulation area), and 17a is a CRT with the CRT 12 Interface 17b, a keyboard interface with the keyboard 13, 17c a network interface with the sequencer peripheral device 1, 18 an auxiliary storage device, 18a a sequence program, b is a virtual PLC configuration file that stores the CPU unit name and the network unit name set in the virtual PLC setting unit 16c. The debug support device is composed of everything shown in Fig. 1.
[0022]
Next, a debugging procedure when the debugging support apparatus according to the present invention is used will be described based on the flowchart of FIG. First, in step S201, the process starts by preparing a debugging environment. In step S202, the sequencer peripheral device 1 and the personal computer 11 are connected. In step S203, the CPU unit name and network unit name of the sequencer to be emulated are input using the virtual sequencer setting unit 16c. In step S204, the simulation unit 16a and the data communication unit 16b are activated, and the sequence program 18a (same as the conventional sequence program 4d in FIGS. 12 and 13) is simulated on the personal computer 11 to start emulation.
As will be described later, when a network unit name is input as shown in FIG. 3, the information is held in the virtual sequencer setting file 18b. As shown in FIG. 6, the data communication unit 16b reads the network unit name from the virtual sequencer setting file 18b, and performs a network pseudo operation by analyzing the corresponding message. A specific example of emulation will be described later.
[0023]
In step S205, the debug target program 6z is executed in accordance with the start command input from the keyboard 3 of the sequencer peripheral device 1. If the debug target program 6z transmits and receives data to and from the personal computer 11 emulating the sequencer and operates correctly in step S206, the debugging operation is terminated in step S208. If the debug target program 6z does not operate correctly, such as data cannot be transmitted / received or there is an error in the transmitted / received data, the debug target program 6z is stopped by a stop command input from the keyboard 3 in step S207. After correcting the debug target program 6z, the process returns to step S205 to repeat the operation check operation.
[0024]
Next, the virtual sequencer setting means 16c will be described based on the flowchart of FIG. First, in step S301, the virtual sequencer setting means 16c developed in the memory 16 is started by an activation command input from the keyboard 13 by the debug operator. In step S302, this means displays a screen for inputting the CPU unit name and network unit name (connection method with peripheral devices) as shown in FIG. The screen of FIG. 4 can display a list of CPU unit model names and a list of connection methods with peripheral devices. The operator can use the keyboard 13 to emulate the CPU unit model names and peripherals of the system to be emulated. Select the connection method with the device from the list.
If the cancel button is pressed in step S303 after the CPU and network unit names are input by the debug operator, the process jumps to step S311 and the virtual sequencer setting unit 16c is terminated. If the OK button is pressed, input data is checked in step S304. That is, it is checked whether the CPU unit name and the network unit name are correctly selected. If the input data is not correct, that is, if the CPU unit name or network unit name is not selected, an error message is displayed in step S305, and then the process returns to step S302 to repeat the process. If the input data is correct, the input CPU unit name (A3U, etc. in FIG. 4) and network unit name (C24, E71, etc. in FIG. 4) are stored in the virtual sequencer setting file 18b of the auxiliary storage device 18 in step S306. .
[0025]
Since the CPU unit name to be simulated is set, the simulation unit 16a developed in the memory 16 is activated in step S307. In step S308, it is checked whether an end command has been input from the keyboard 13. If not, in step S309, after waiting for a predetermined time, the process returns to step S308 and the end command check is repeated. When the end command is input, the simulation unit 16a is terminated in step S310, and the virtual sequencer setting unit 16c is terminated in step S311.
[0026]
Next, the simulation means 16a will be described based on the flowchart of FIG. First, in step S501, the virtual sequencer setting unit 16c activates the simulation unit 16a developed in the memory 16. In step S502, this means reads the CPU unit name from the virtual sequencer setting file 18b. In step S503, the sequence program 18a in the auxiliary storage device 18 is read. In step S504, a simulation area 16d, which is an area for storing the simulated state of the sequence program, is secured on the memory 16, and in step S505, the simulation area 16d is initialized. In step S506, the data communication means 16b for performing data communication with the sequencer peripheral device 1 is activated.
[0027]
In step S507, the simulation area 16d is read out and set as the initial state of the simulation. In step S508, a simulation of the sequence program 18a corresponding to the specification of the CPU unit name is executed. That is, since the sequence program 18a of the auxiliary storage device 18 is read in step S503, the simulation can be performed by analyzing the instructions in the program. For example, in the case of a data transfer command from the device D to the device W, the simulation is realized by transferring (copying) the data from the address corresponding to the device D in the simulation area 16d to the address corresponding to the device W.
In step S509, the simulation result is stored in the simulation area 16d. That is, the simulation result of copying data from the device D equivalent address to the device W equivalent address is stored in the simulation area 16d.
In step S308 of FIG. 3, the virtual sequencer setting unit 16c is waiting for an end command. To end the virtual sequencer setting means 16c, the operator needs to input an end command from the keyboard 13. When the end command is input, an end request is generated to the simulation means 16a in step S310. This request is received in step S510.
In step S510, it is checked whether an end request has been received from the virtual sequencer setting means 16c. If no request has been received, the process returns to step S507 to repeat the simulation. If there is a request for termination, the data communication unit 16b is terminated in step S511, the simulation area 16d is released in step S512, and the simulation unit 16a is terminated in step S513.
[0028]
Next, the data communication means 16b will be described based on the flowchart of FIG. As shown in FIG. 3, the simulation unit 16a and the data communication unit 16b in FIG. 5 start / end are activated by the simulation unit 16a, and then the simulation unit 16a activates the data communication unit 16b. The simulation unit 16a ends the data communication unit 16b, and finally the simulation unit 16a ends. At the time of emulation, the simulation unit 16a and the data communication unit 16b operate simultaneously (for example, Word and Excel operate simultaneously on Windows).
First, in step S601, the simulation means 16a activates the data communication means 16b developed in the memory 16. In step S602, this means reads the network unit name from the virtual sequencer setting file 18b.
[0029]
In step S603, it is checked whether a message from the debug target program 6z of the sequencer peripheral device 1 has been received. If no message is received, it is checked in step S604 if there is an end request from the simulation means 16a. If there is, a data communication process 16b is ended in step S614. If there is no termination request, in step S605, after waiting for a certain period of time, the process returns to step S603 to check message reception. If a message is received in step S603, message analysis corresponding to the network unit is performed in step S606. Message analysis is necessary because the message format varies depending on the network communication protocol.
[0030]
If the message content is a read request in step S607, the simulation area 16d is read in step S611. The read data creates an answer message corresponding to the network unit in step S612, and transmits it to the debug target program 6z of the sequencer peripheral device 1 in step S613. The response message is created, for example, with a configuration of “communication destination address + result + response content”. The communication destination address is a 4-digit value indicating to which device / apparatus the response is received, the result is a 2-digit character indicating the execution result for the request in OK / NG, and the response content is 8 digits indicating the data to be answered Is the value of For example, when replying the data 123 read from the simulation area 16d to the sequencer peripheral device with the communication destination address 0001, a message 0001OK00000013 is created and transmitted. When reading of the simulation area 16d fails due to some abnormality, a message 0001NG00000000 is transmitted.
If the message content is not a read request in step S607, it is checked in step S608 if it is a write request. If it is a write request, in step S609, the received data is written in the simulation area 16d, and the process returns to step S612. In the case of a write request, the content of the response message “communication destination address + result + response content” is always 0, and a message is created by setting OK / NG for writing to the simulation area 16d in the result. In the case of writing OK, it becomes 0001KO00000000.
If the message content is not a write request in step S608, an error response message corresponding to the network unit is created in step S610, and the process returns to step 613. In step S613, after transmitting the message, the process returns to step S603 to repeat the process.
[0031]
As a specific example of emulation, for example, consider a system for controlling the amount of water in a tank as shown in FIG. 7 (conventional) and FIG. 8 (present invention). The sequence program 4d is a program for controlling the amount of water in the tank by controlling the amount of water in the tank and the amount of water discharged from the tank. The amount of water in the tank is stored in the memory 4c of the sequencer 4, and when the water is poured into the tank, the increased amount is added to the value (hereinafter referred to as the amount of water) and held, and when the water is drained from the tank And hold. In this example, when the sequence program 4d is executed, the water volume value changes from 10 → 20 → 25 (the tank water volume also changes in accordance with the realization of the water volume value).
[0032]
The debug target program 6z is a program for reading the water amount value held in the memory 4c of the sequencer 4 onto the memory 6 of the personal computer 1 corresponding to the sequencer peripheral device via the communication line and displaying the value on the CRT 2. However, as the name of the program to be debugged indicates, this program is a program to be debugged, that is, a program whose operation is to be confirmed now.
[0033]
Conventionally, after preparing each unit of the sequencer 4 and the tank, the personal computer 1 and the PLC 4 must be connected to debug the debug target program 6z (see FIGS. 7 and 12). The debugging in the present invention is an operation for confirming that the display on the CRT 2 changes in the same manner as the water amount value on the memory 4c changes from 10 → 20 → 25. When debugging is completed, the program is completed and the amount of water in the tank can be monitored by the personal computer 1.
[0034]
In the present invention, the sequencer 4 is emulated by the personal computer 11 and debugging of the debug target program 6z is enabled without preparing the sequencer 4 and the tank (see FIGS. 8 and 1).
[0035]
A specific example of emulation using a system that controls the amount of water in the tank is shown below. The simulation means 16a is means for simulating (simulating) the sequence program 4d on the personal computer 11. Accordingly, when the sequence program 4d is operated using the simulation means 16a, the water amount value changes from 10 → 20 → 25 in the same manner as when the sequencer 4 is operated, and the value is held in the simulation region 16d. That is, the simulation means 16a analyzes and simulates the instruction of the sequence program 4d, and stores the result in the simulation area 16d, so that the sequencer 4 can be emulated.
[0036]
The debug target program 6z reads the water amount value from the simulation area 16d via the communication line and the data communication means 16b, and displays the value on the CRT 12. If there is an error in the program, the water volume value will not be displayed correctly, so correct the program and debug again. This is repeated to complete the program (see FIG. 2).
[0037]
As described above, according to the present invention, since the sequencer setting operation is faithfully emulated by the personal computer 11 by selecting the unit of the sequencer 4 on the personal computer 11, the debug target program 6z is changed to the case of the actual system. There is no need to change in the case of an emulated system, and debugging can be performed efficiently. It is also an advantage that it is not necessary to prepare each PLC unit.
[0038]
Embodiment 2. FIG.
A debugging support apparatus according to another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a flowchart showing the operation of the data communication means in the debugging support apparatus according to this embodiment. Steps S701 and S702 of “message display on CRT” are added to the flowchart shown in FIG. A process (message display function) for displaying the message received by the data communication means 16b and the message to be transmitted on the CRT 12 is added. 9, the same numbers as those in FIG. 6 indicate the same processes. The message display function is basically configured by driving hardware (in this case, a personal computer, a CRT I / F, and a CRT) depending on software, as in other means.
[0039]
The operation of adding the message display function to the data communication means of FIG. 6 will be described with reference to FIG. Steps different from those in FIG. 6 will be described. In step S701, the message received in step S603 is displayed on the CRT 12. In step S702, the reply message created in step S612 or step S610 is displayed on the CRT 12.
An example of the display is shown in FIG. FIG. 10 shows the answer message described above as an example.
[0040]
By displaying the message to be transmitted / received on the CRT 12, it is possible to confirm what kind of message has been received and what kind of response message has been transmitted, which is useful for finding unauthorized transmission / reception data. For example, when an error reply message is created in step S610, it can be easily determined why the error reply is made by looking at the received message displayed in step S701.
[0041]
In the present embodiment, the message is displayed on the CRT in step S701 and step S702. However, by displaying the message and recording it in a file in the auxiliary storage device, a history of the message can be left in the past. The cause of abnormal communication that has occurred can be easily pursued.
[0042]
Embodiment 3 FIG.
A debugging support apparatus according to still another embodiment of the present invention will be described with reference to FIG. FIG. 11 is a block diagram showing the configuration of the debugging support apparatus. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. In this embodiment, the sequencer peripheral device 1 (the personal computer 1 in FIG. 8) in the above embodiment is incorporated on the personal computer 11 side, and the debugging support device is configured by one personal computer 11X.
[0043]
In FIG. 11, 11X is a program running on a sequencer peripheral device and a personal computer emulating the sequencer, 17cX is a network interface on the sequencer emulation side, and 7cX is a network interface on the program side running on the sequencer peripheral device. is there.
[0044]
Next, a debugging procedure when using the debugging support apparatus according to this embodiment will be described based on the flowchart of FIG. In this embodiment, since the debugging support device is configured by one personal computer 11X, the configuration is exactly the same except that it is not necessary to connect the sequencer peripheral device 1 and the personal computer 11 as in step S202 of FIG.
[0045]
In this embodiment, the connection between the program running on the sequencer peripheral device and the emulation of the sequencer is implemented inside the personal computer, but the same can be achieved by using a return cable.
[0046]
【The invention's effect】
As explained above, according to the present invention, A debugging support device that supports debugging of a program that operates on a sequencer peripheral device connected to the sequencer via a network, and a personal computer with a sequence program that emulates the sequencer is connected to the sequencer peripheral device with the debug target program. Then, the personal computer emulates a sequencer having a system configuration according to the CPU unit name of the sequencer selected on the personal computer and the name of the network unit via Since it did in this way, the effort which prepares an actual CPU unit and a network unit can be saved, and there exists an effect which shortens a debugging work time.
[0047]
In addition, since messages sent to the personal computer from the sequencer peripheral device and their response messages are monitored on the personal computer, the message can be confirmed without the need for a message analysis device, etc. This has the effect of facilitating program debugging.
[0048]
In addition, by emulating the program and the sequencer operating on the sequencer peripheral device with a single personal computer, it is possible to save time for preparing an actual CPU unit and network unit and to shorten the debugging work time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a debugging support apparatus according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a debugging procedure using a debugging support apparatus according to an embodiment of the present invention.
FIG. 3 is a flowchart showing the operation of the virtual sequencer setting means of the personal computer of the debugging support apparatus according to the embodiment of the present invention.
FIG. 4 is a diagram showing an example of a virtual sequencer setting screen of a personal computer of the debugging support apparatus according to the embodiment of the present invention.
FIG. 5 is a flowchart showing the operation of the simulation means of the personal computer of the debugging support apparatus according to the embodiment of the present invention.
FIG. 6 is a flowchart showing the operation of the data communication means of the personal computer of the debugging support apparatus according to the embodiment of the present invention.
FIG. 7 is a diagram of a conventional case for explaining a specific example of emulation according to the present invention.
FIG. 8 is a diagram in the case of the present invention for explaining a specific example of emulation according to the present invention;
FIG. 9 is a flowchart showing an operation when a message display function is added to data communication means in a debugging support apparatus according to another embodiment of the present invention;
FIG. 10 is a diagram showing an example of display of an answer message.
FIG. 11 is a block diagram showing a configuration of a debugging support apparatus according to still another embodiment of the present invention.
The response message is displayed on the CRT 12.
FIG. 12 is a block diagram showing a device configuration when debugging a program operating on a conventional sequencer peripheral device.
FIG. 13 is a flowchart showing a conventional debugging procedure.
FIG. 14 is a block diagram showing a device configuration when debugging a program operating on a conventional sequencer peripheral device using a message analysis device.
[Explanation of symbols]
1 sequencer peripheral device, 2,12 CRT, 3,13 keyboard, 5,15 CPU, 6,16 memory, 6z program to be debugged, 7a, 17a CRT interface, 7b, 17b keyboard interface, 7c, 17c, 7cX, 17cX Network interface, 11, 11X personal computer, 16a simulation means, 16b data communication means, 16c virtual sequencer setting means, 16d simulation area, 18 auxiliary storage device, 18a sequence program, 18b virtual sequencer setting file.

Claims (3)

A debugging support device for supporting a debugging programs running sequencer peripheral device connected with the sequencer and networks, connecting a personal computer with a built-in sequence program that emulates the programmable controller PLC peripheral device with a built-in program to be debugged A debugging support device, wherein the personal computer emulates a sequencer having a system configuration in accordance with the CPU unit name of the sequencer selected on the personal computer and the network unit name through which the personal computer is selected.   The communication program in the application on the sequencer peripheral device can be debugged by monitoring the message transmitted from the sequencer peripheral device to the personal computer and the response message on the personal computer. The debugging support device according to 1. A debugging support device that supports debugging of a program that operates on a sequencer peripheral device connected to the sequencer via a network. A debugging support apparatus comprising a personal computer emulating a sequencer having a system configuration in accordance with a CPU unit name and a network unit name via .

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