JP3665575B2 - Display control device and display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a display control device and a display device related to a display such as a liquid crystal display (LCD) and a plasma display panel (PDP) and its application devices.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, portable personal computers and word processors called so-called laptop computers generally have an openable / closable flat display unit, and medium and large-sized liquid crystal display devices mounted thereon are shown in FIG. As described above, the liquid crystal display control unit 10 built in the apparatus main body side and the flat liquid crystal display module unit 20 provided on the inner side of the opening / closing lid are separated and independently arranged. The liquid crystal display controller 10 includes a liquid crystal module controller 12 and a micro processor unit (MPU) (not shown). The liquid crystal module controller 12 supplies various control signals and clocks to the liquid crystal display module unit 20 side. Supply signal.
[0003]
The liquid crystal display module unit 20 includes, for example, a simple matrix type liquid crystal display panel (matrix liquid crystal display element) 22, a signal electrode driving circuit (X driver) 24 mounted on the periphery (frame) region of the panel 22, and scanning electrodes. Drive circuit (Y driver) 26 and high-voltage liquid crystal drive voltage (reference voltage) V₀  ~ V₅  And a liquid crystal power supply circuit 28 for generating. The signal electrode drive circuit 24 includes a plurality of signal electrode driver semiconductor integrated circuits 24.₁  ~ 24_m  For example, the driver output is supplied for each line of the screen for the total number M of signal electrodes. That is, the data signals D0 to D7 are successively taken into the shift register in the signal electrode drive circuit 24 by the pixel clock (shift clock pulse) XSCL, and scanning is performed when the signal (M bit) for one line of the screen is taken. The data signal in the shift register is sent in parallel to the data latch circuit by the line synchronization signal YSCL (data signal latch clock LP), and the data signal is subjected to direct / parallel conversion. In the data latch circuit, the signal voltage for one line is held for one scanning period, and the selection switch circuit sets the driver output voltage connected to the signal electrode based on the signal voltage to either the selected state or the non-selected state. To do. The AC clock FR is a clock that makes each of the above voltages an AC waveform in order to prevent deterioration of the liquid crystal element due to DC driving. The forced blank display signal DF (bar) is a signal for forcibly setting the liquid crystal screen to a blank display state. The scan electrode driving circuit 26 includes a plurality of scan electrode driver semiconductor integrated circuits 26.₁  ~ 26_n  For example, the selection voltage is applied to only one of the N scanning electrodes in total, and the non-selection voltage is applied to the other (N-1) scanning electrodes. One scanning line period is started by the scanning start pulse (frame start signal) SP, and the selection voltage is supplied from the scanning electrode of the first row to the Nth row every time the scanning line synchronization signal YSCL (data signal latch clock LP) comes in. It is sequentially applied to the scanning electrode of the eye (line order display). The liquid crystal power supply circuit 28 disposed on the liquid crystal display module unit 20 side has a plurality of liquid crystal drive voltages V to be selected by the selection switches of the signal electrode drive circuit 24 and the scan electrode drive circuit 26.₀  ~ V₅  Is set to a power-on / off state by a forced blank display signal DF (bar).
[0004]
[Problems to be solved by the invention]
By the way, the liquid crystal display control unit 10 built in the apparatus main body side and the flat liquid crystal display module unit 20 provided inside the opening / closing lid are generally connected by a flexible cable 30 via a hinged movable part. Yes. Therefore, every time the opening / closing lid on the flat liquid crystal display module unit 20 side is opened / closed, the cable 30 itself is bent, and the signal lines of the cable 30 are inevitably damaged or disconnected due to physical factors. If a part of the signal line is disconnected, for example, a state in which the AC voltage is not applied to the liquid crystal display panel 22 while the DC voltage (DC component) is applied is generated, which is more expensive and difficult to replace than other components. The liquid crystal display panel 22 may be deteriorated. Such liquid crystal deterioration is an impediment to life and display quality, and is an important problem for display devices based on visibility.
[0005]
Of the signals supplied from the liquid crystal module controller 12 to the liquid crystal display module unit 20 side, the signals that may cause the DC drive deterioration of the liquid crystal display panel 22 include the scan start pulse SP and the scan line synchronization signal YSCL. (Data signal latch clock LP), AC clock FR and logic side power supply voltage V_CCIt is. Further, even if some abnormal operation occurs in the liquid crystal module controller 12 and the microprocessor unit (MPU), the above-mentioned signals may be abnormal, and the same situation as described above may occur.
[0006]
By the way, if the problem of the DC drive of such a liquid crystal display is spread, it can be generalized to the problem of signal abnormality on the liquid crystal module unit side. In addition, assuming a wall-mounted television, the display control unit and the display panel are remotely located, so the problem of display quality degradation due to signal level attenuation and noise effects has been raised as well as signal suspension. The Further, not only a liquid crystal display but also a plasma display becomes a problem.
Furthermore, if a means for realizing a predetermined sequence is not provided at the start of display such as when the power is turned on, rush current is concentrated and abnormal panel driving becomes a problem.
[0007]
Therefore, in view of the above problems, the problem of the present invention is as follows.A display control device and a display device capable of preventing concentration of rush current at the start of display such as power-on and abnormal driving of the panelIt is to provide.
[0008]
[Means for Solving the Problems]
A display control apparatus for controlling a flat display body as one means for solving the problem is a display controller that operates by a supplied logic power supply. When the logic power supply is turned on (t0), a forced blank display signal is displayed. (/ DFF) is held in an active state and the logic power supply is turned on. 1 When the delay time elapses (t1), the display controller that outputs the forced blank display signal (/ DFF) as an inactive state and the forced blank display when the logic power supply is turned on (t0) In response to the signal (/ DFF) being in the active state, the flat display body is set to the blank display state, and after the forced blank display signal (/ DFF) is changed from the active state to the inactive state, After the elapse of the delay time (t3), a display power supply control signal (/ POFF) instructing the start of power supply output generation is output to the display body power supply circuit, and the third delay time is output after the display power supply control signal is output. After the elapse of time (t4), a display drive circuit for canceling the blank display state, selecting a predetermined potential supplied from the display power supply circuit, and outputting it to the flat display is provided. And wherein the Rukoto.
[0011]
  In the display control apparatus described above,,flatThe display body may be composed of a liquid crystal display panel or a plasma display panel.Also,In the display control apparatus described above,flatThe display control device is constituted by a semiconductor integrated circuit. A display control device as described above;flatA display device using a display body can also be configured.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
FIG. 1 shows a first embodiment of the present invention.InvolvedIt is a block diagram which shows the whole structure of a liquid crystal display device. 1 that are the same as those shown in FIG. 9 are given the same reference numerals, and descriptions thereof are omitted.
[0017]
The scan driver semiconductor integrated circuit (LSI) 46 constituting the scan electrode drive circuit (Y driver) 46 of the liquid crystal display module section 40 in this embodiment.₁  ~ 46_n  Has a signal management control unit 47.
[0018]
First scan driver semiconductor integrated circuit 46₁  Signal management controller 47 of₁  Detects the stop of the scanning line synchronization signal YSCL (data signal latch clock LP) applied to the terminal CKB1. Second scan driver semiconductor integrated circuit 46₂  Signal management controller 47 of₂  Detects the stop of the scan start pulse (frame start signal) SP applied to the terminal CKB2. Nth (for example, third) scan driver semiconductor integrated circuit 46_n  Signal management controller 47 of_n  Detects the stop of the AC clock FR applied to the terminal CKBn. Each signal management control unit 47₁  ~ 47_n  Is the signal stop detection control terminal S₁  ~ S_n  And signal stop detection terminal T₁  ~ T_n  have. First scan driver semiconductor integrated circuit 46₁  Signal management controller 47 of₁  Signal stop detection control terminal S₁  Is normally supplied with a forced blank display signal DFF (bar) of a high level voltage from the control circuit 10 side, and its signal stop detection terminal T₁  The second scan driver semiconductor integrated circuit 46₂  Signal management controller 47 of₂  Signal stop detection control terminal S₂  It is connected to the. The second scan driver semiconductor integrated circuit 46₂  Signal management controller 47 of₂  Signal stop detection terminal T₂  Is a signal stop detection terminal at the next stage (for example, the nth signal management control unit 47)._n  Signal stop detection control terminal S_n  )It is connected to the. The nth signal management control unit 47_n  Signal stop detection terminal T_n  Scan driver 46₁  ~ 46_n  And signal driver 24₁  ~ 24_n  Are connected to the forced blank control terminal DF (bar).
[0019]
Signal management control unit 47 of each scanning driver₁  ~ 47_n  As shown in FIG. 2, the signal management control units 47 are cascade-connected.₁  ~ 47_n  The configuration is the same. Signal management control unit 47₁  The signal to be detected is the terminal CKB₁  The data signal latch clock LP applied to the signal management control unit 47₂  The signal to be detected is the terminal CKB₂  A signal management control unit 47 with a scan start pulse (frame start signal) SP applied to_n  The signal to be detected is the terminal CKB_n  The AC clock FR applied to.
[0020]
Here, the signal management control unit 47₁  The structure will be described by paying attention to. Signal management control unit 47₁  Has a signal stop detection circuit 48 as signal detection means for detecting stop of the detected signal, and a sequence processing circuit 51 including a signal delay circuit 49 and a logic circuit 50.
[0021]
The signal stop detection circuit 48 is switched by a latch clock LP as a detected signal, and is configured to be a first N-type MOS transistor Tr that forms a transfer gate.₁  , Inverter INV for inverting the phase of the latch clock LP₁, A second N-type MOS transistor Tr that is switched by an antiphase signal of the latch clock LP to form a transfer gate₂  , First N-type MOS transistor Tr₁  The first capacitor C that is charged and discharged by the opening / closing operation of₁₁, Second N-type MOS transistor Tr₂  The second capacitor C that is charged and discharged by the opening / closing operation of₁₂, This capacitor C₁₂Discharge resistor R that discharges₁  , And second capacitor C₁₂Charging voltage and threshold V_THAnd inverter INV that outputs a charge level determination signal₂  It is composed of First N-type MOS transistor Tr₁  And inverter INV₁  And the second N-type MOS transistor Tr₂  Constitutes a series exclusive switching circuit. The first N-type MOS transistor Tr₁  Is the first capacitor C₁₁And a second N-type MOS transistor Tr.₂  Is the first capacitor C₁₁Of the second capacitor C₁₂A selective charging switch that distributes and forwards to the network is configured.
[0022]
The signal delay circuit 49 is connected to the inverter INV₂  A D-type flip-flop 49a having a reset terminal R (bar) connected to the output of the output terminal and a grounded input terminal D (bar) and using the frame start signal SP as a clock input CK, and an inverter INV₂  A D-type flip-flop having a reset terminal R (bar) connected to the output of the output terminal and an input terminal D (bar) connected to the output Q (bar) of the flip-flop 49a and using the frame start signal SP as a clock input. And a flop 49b. The logic circuit 50 includes an AND circuit AND having two inputs, the forced blank signal DFF (bar) from the control circuit 10 and the Q output of the flip-flop 49b.
[0023]
FIG. 3 shows the scan driver 46.₁  Signal management controller 47 of₁  It is a circuit diagram which shows the normal scanning electrode drive circuit (logic part) except for FIG. This logic section includes a multi-bit scan electrode driving cell 46 that applies a voltage in line order corresponding to a large number of scan electrodes.₁₁, 46₁₂... are built in an array. In FIG. 3, the scan electrode driving cell 46 of the first bit and the second bit.₁₁, 46₁₂And its peripheral circuitry.
[0024]
Here, scan electrode driving cell 46₁₁The structure of the scan electrode driving cell 46 will be described by paying attention to FIG.₁₁The D-type flip-flop 46a in the shift register that is activated by the frame start signal SP and transfers the frame start signal SP to the next stage every time the scan synchronization signal YSCL arrives, and the nth scan to the bit selection output Q Driver 46_n  Terminal T_n  The unit-by-line forced blank display control circuit 46b that performs a logical operation in consideration of the forced blank display signal DF (bar) supplied from the power supply circuit, and outputs the logic system power supply voltage (V_CC= 5v) to a row unit voltage level shift circuit 46c for converting to a logical amplitude of a high voltage system, and a total row forced blank display control circuit 46d for performing a logical operation by adding a forced blank display signal DF (bar) to the AC clock FR. And the AC clock FR is changed to the logic power supply voltage (V_CC= 5v) to high voltage AC clock FR with high voltage system logic amplitude_HVoltage level shift circuit 46e for AC clock to be converted into a high voltage AC clock FR_H  High-frequency AC clock FR with reverse phase_H  The forward / reverse two-phase clock generation circuit 46f to be inverted to (bar) and the high-voltage AC clock FR_H  , Reverse phase high voltage AC clock FR_H  Four selection control signals C in an alternating combination from a pair of (bar) and a pair of outputs O and O (bar) of the row unit voltage level shift circuit 46c.₁  ~ C₄  A selection control signal generation circuit 46g for generating each selection control signal C₁  , C₂  , C₃  , C₄  By means of scan electrode drive voltage V₅  , V₁  , V₀  , V₄  This is composed of a selection switch 46h that selectively transmits to the scanning electrode. Here, the line-by-line forced blank display control circuit 46b and the total line forced blank display control circuit 46d constitute a forced blank display control circuit. INV₃  Is an inverter that matches the logic to the row-by-line forced blank display control circuit 46b of the forced blank display control signal DF (bar).
[0025]
Next, the operation of this embodiment will be described with reference to FIG. When the logic power supply VCC of the liquid crystal display device is turned on at time t0, a reset signal having a pulse width of several μs to several ms is supplied to the power-on reset terminal RS of the liquid crystal module controller 12 as in the conventional case. The liquid crystal module controller 12 is initialized from the side. During this initialization period, various signals output from the liquid crystal module controller 12 are generally in a stopped state. During this period, since the forced blank display signal DFF (bar) is at a low voltage level (hereinafter referred to as L level), the liquid crystal power supply circuit 28 is in a power-off state and the liquid crystal drive power supply voltages V0 to V5 are not generated. It is. Therefore, no DC component is applied between the liquid crystal electrodes during this initialization period, preventing deterioration of the liquid crystal element.In addition, abnormal driving of the liquid crystal panel is also suppressed.
[0026]
After this period, as shown in FIG.₁  The forced blank display signal DFF (bar) changes from the L level to the high voltage level (hereinafter referred to as the H level), and the liquid crystal module controller 12 receives the frame start signal SP, the data signal latch clock LP, and the AC clock FR. Occur. Here, first, the scanning driver 46₁  Signal management controller 47 of₁  The operation of the signal delay circuit 49 will be described.₁  Is supplied with a frame start signal SP and a detection terminal CKB of the signal stop detection circuit 48.₁  Is supplied with a data signal latch clock LP.
[0027]
During the H level period of the data signal latch clock LP, the transistor Tr of the signal stop detection circuit 48₁  Is on and transistor Tr₂  Is in the off state. Therefore, during this period, the capacitor C₁₁Is charged. During the L level period of the data signal latch clock LP, the transistor Tr of the signal stop detection circuit 48₂  Is on and transistor Tr₁  Is in the off state. Therefore, during this period, the capacitor C₁₁A part of the electric charge charged in the capacitor C₁₂Charged into the. As the repetitive pulse of the data signal latch clock LP is generated, the capacitor C₁₂Since the charging voltage of the inverter INV increases₂  Input voltage is threshold V_THAt time t₂  Inverter INV₂  Output INV_OUT  Becomes H level. Time t₂  Previously inverter INV₂  Output INV_OUT  Is at the L level, the output Q of the D flip-flop 49a of the signal delay circuit 49 is at the L level.₁  Is L level. Where the output INV_OUT  Even if becomes H level, the time t₂  Then, the output Q does not become H level. One frame period (T) of the frame start signal SP by the delayed storage action of the input signals of the D flip-flops 49b and 49a._F  ) To 2 frame periods (2T_F  ), The output Q is maintained at the L level, and the time t₃
The output T of the logic circuit 50₁  Becomes H level.
[0028]
Scan driver 46₂  Signal management control unit 47 in₂  Signal stop detection circuit 48₂  Detection terminal CKB₂  Is supplied with a frame start signal SP and a signal delay circuit 49.₂Input terminal CKA₂  In the scan driver 46₁  Cascade input DI coming from the cascade output terminal DO₂  A frame start signal SP is supplied. And the scanning driver 46₁  Output T of the logic circuit 50₁  Scan driver 46₂  The logic circuit 50 is cascade-connected. Signal stop detection circuit 48₂  Capacitor C₂₁Is charged by a repetitive pulse of the frame start signal SP. Similarly, the scanning driver 46_n  Signal management control unit 47 in_n  Signal stop detection circuit 48_n  Detection terminal CKB_n  Is supplied with an alternating signal FR and a signal delay circuit 49._nInput terminal CKA_n  There is a scan driver 46₂  Cascade input DI coming from the cascade output terminal DO_n  A frame start signal SP is supplied. And the scanning driver 46₂  Output T of the logic circuit 50₂  Scan driver 46_n  The logic circuit 50 is cascade-connected. Signal stop detection circuit 48_n  Capacitor C_n2Is charged by a repetitive pulse of the alternating signal FR. Since the cycle and duty ratio of the data signal latch clock LP, the frame start signal SP, and the alternating signal FR as the detected signals are different, the inverter INV in each scan driver₁  ~ INV_nComparison judgment time t₃In order to match these, the capacitor C₁₁~ C_n1, C₁₂~ C_n2And discharge resistance R₁  ~ R_n  It is desirable to be able to mutually adjust the value of (time constant). For this purpose, in this embodiment, as shown in FIG. 1, an external capacitor and an external connection terminal of a resistor are provided in the scan driver.
[0029]
Thus, the logic power supply V_CCTime t₀  To logic circuit output T₁  ~ T_n  When t becomes H level₃  In the period up to this time, the L level output T is supplied to the forced display blank control terminal DF (bar) of each scanning driver and signal driver._n  Therefore, the liquid crystal display panel 22 is in a blank display state. That is, when the forced display blank control signal DF (bar) is at the L level, the transistor F of the selection switch 46h of the scan electrode drive cell 46 is controlled by the forced blank display control circuits 46b and 46d shown in FIG.₁  Only in the on state, the voltage V₅  (0v) is applied, and the voltage between the liquid crystal electrodes (liquid crystal applied voltage) is 0v. Time t₀  ~ Time t₃  This period corresponds to the liquid crystal drive prohibition period. Time t₁  As a result, the liquid crystal power supply circuit 28 is powered on and the liquid crystal drive voltage V₀  ~ V₅These voltages are supplied to the scanning and signal driver, but the shift register and the like in the scanning and signal driver are in an indefinite state when the power is turned on. However, at time t₃  Since the liquid crystal display is blank-controlled, abnormal driving of the liquid crystal panel can be avoided.
[0030]
Next, when the output Tn becomes H level at time t3, since the H level voltage is supplied to the forced display blank control terminal DF (bar) of each scan driver and signal driver, normal operation of the scan driver and signal driver is performed. As a result, the liquid crystal display panel 22 is AC driven, and a display screen is drawn on the liquid crystal panel 22. B shown in FIG. 4 represents a liquid crystal driving period. At time t1, the liquid crystal power supply circuit 28 and the logic unit of the scanning and signal driver are powered on, and at time t3 later than this, the liquid crystal display panel 22 is driven. Therefore, since power supply power-on does not occur simultaneously, an excessive power supply rush current is suppressed. This is because, in addition to the delay operation of the signal stop detection circuit 48 itself, the delay action of the signal delay circuit 49 having a delay time of 1 to 2 frame periods functions effectively.
From the viewpoint of a sequence at the start of display such as when power is turned on, FIG. 0 With logic power Vcc And the MPU detecting this generates a power-on reset signal (not shown), and in response to this, the time t 1 The DFF (bar) is set to H level, that is, the liquid crystal power supply circuit 28 is turned on and the liquid crystal drive power supply voltage V is turned on. 0 ~ V Five At a time t after a predetermined period has elapsed Three At T 1 , T 2 , T Three That is, it is described that DF (bar) is set to the H level, that is, the forced display blank control signal is canceled and display is started. By configuring the means for realizing such a sequence, it is possible to disperse the rush current and avoid abnormal driving of the liquid crystal panel.
[0031]
Now, at time t in this liquid crystal driving period B₄  Assume that the output of the data signal latch clock LP sent from the liquid crystal module controller 12 side is stopped, for example. During output of the data signal latch clock LP, the scan driver 46₁  Signal stop detection circuit 48₁  Second capacitor C₁₂Is fully charged, but when its clock LP stops, the second capacitor C₁₂To the first capacitor C₁₁The second capacitor C₁₂Is the discharge resistance R₁  Begins to discharge rapidly with a predetermined time constant through the inverter INV₂  The input voltage gradually increases. Its input voltage is its threshold V_THExceeds the output voltage INV_OUT  Is time t₅  Becomes L level. By this logical change, the signal delay circuit 49₁  Is reset, and its output Q becomes L level, so that the logic circuit 50 is controlled even though the forced display blank control signal DF (bar) is at L level.₁  Output T₁  Is the time t₅  Becomes L level. This output T₁Scan driver 46₂  Logic circuit 50₂  Since the frame start signal SP is being output, its logic circuit 50₂  Output T₂  Becomes L level. In addition, output T₂  Scan driver 46_n  Logic circuit 50_n  Since the AC input signal FR is being output, the logic circuit 50_n  Output T_n  Becomes L level. This output T_n  Corresponds to the forced display blank control signal DF (bar) on the liquid crystal display module unit 46 side, so that the liquid crystal display panel 22 is in a blank display state using the forced display blank circuits 46b and 46d. That is, the transistor F of the selection switch 46h of the scan electrode driving cell 46 shown in FIG.₁  Only in the on state, the voltage V₅  Since (0v) is fed, the voltage between the liquid crystal electrodes is maintained at 0v. For this reason, even when the data signal latch clock LP is stopped for some reason, the liquid crystal element is not driven with a direct current component, so that deterioration of the liquid crystal is prevented in advance. Also, when the frame start signal SP or the AC signal FR is stopped for some reason, the output T_n  Since it becomes L level, liquid crystal deterioration is prevented in the same manner. In the liquid crystal drive inhibition period A, as long as the frame start signal SP and the alternating signal FR continue, the second capacitor C₂₂And C_n1Is in a charged state and the inverter INV₂  , INV_n  Is at the H level.
[0032]
Time t₆  When the data signal latch clock LP begins to appear again at, as described above, the second capacitor C₁₂Is charged and the inverter INV₁  Output INV_OUT  Becomes H level. Output INV_OUT  A signal delay circuit 49 functioning as a timer after one to two frame periods from the time when becomes H level.₁Output Q at time t₇  Becomes H level. Thus, the logic circuit 50₁  Output T₁  Goes to H level and in conjunction with this, the logic circuit 50₂  , 50_n  Output T₂  , T_n  Becomes H level. Accordingly, since the forced display blank control signal DF (bar) on the liquid crystal display module unit 22 side changes to H level, the liquid crystal display panel 22 enters the liquid crystal driving period B.
[0033]
Finally, at time t₈  When the forced display blank control signal DFF (bar) on the liquid crystal display controller 12 side becomes L level, the logic circuit 50₁  Output T₁  Changes to L level, so that the logic circuit 50₂  , 50_n  Output T₂  , T_n  Becomes L level. Therefore, the forced display blank control signal DF (bar) on the liquid crystal display module unit 20 side becomes L level, and the liquid crystal display panel 22 enters the display off period C.
[0034]
[Example 2]
FIG. 5 shows a second embodiment of the present invention.InvolvedIt is a block diagram which shows a liquid crystal display device. 5 that are the same as those shown in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted.
[0035]
A plurality of scan drivers 76 constituting the scan electrode drive circuit (X driver) 76 of the liquid crystal display module unit 70 of this embodiment.₁  ~ 76_n  Is a signal management control unit 77 similar to the signal management control unit of the first embodiment.₁  ~ 77_n  However, as shown in FIG.₁  ~ 77_n  There is a liquid crystal drive voltage V₀  ~ V₅  A power supply power on / off control circuit 78 for controlling the power on / off timing of the liquid crystal power circuit 28 to generate the power₁  ~ 78_n  Is added.
[0036]
Power supply power on / off control circuit 78₁  ~ 78_n  The logic circuit 50₁  Input terminal S₁  ~ S_n  Inverter INV that inverts the signal coming in₃  A two-stage D flip-flop 78a, 78b, its output Q and terminal P₁  ~ P_n  And a logic circuit 78c that takes the logic of the signal coming from. The signal delay circuit 79 of each signal management control unit 77 has a configuration in which a third stage D flip-flop 79c is additionally connected to the two-stage D flip-flops 49a and 49b of the signal delay circuit 49 according to the first embodiment. It is.
[0037]
First scan driver 76₁  The input terminal P of the logic circuit 78c₁  The logic side power supply voltage V_CCAre supplied with the power on / off signal of the second scan driver 76.₂  Terminal P₂  Includes a first scan driver 76.₁  Power supply on / off control circuit 78 in FIG.₁  Output PF₁Are supplied in cascade. The nth scan driver 76_n  Terminal P_n  Includes a second scanning driver 76 which is a preceding stage.₂  Power supply on / off control circuit 78 in FIG.₂  Output PF₂Are supplied in cascade. The nth scan driver 76_n  Power supply power on / off control circuit 78_n  Output PF_n  Is supplied to the power-off terminal POFF (bar) of the liquid crystal power circuit 28.
[0038]
The liquid crystal power supply circuit 28 has the same configuration as the conventional one, and as shown in FIG._CC(5v) A voltage conversion circuit 28a that generates a high voltage (20 to 40v) boosted based on the power supply voltage, and an npn for control that is turned on / off depending on the voltage value supplied to the power-off terminal POFF (bar) Type transistor 28b, a pnp type transistor 28c of a power switch that is turned on / off in conjunction with the on / off operation of the transistor 28b, a smoothing capacitor 28d interposed between the collector and the ground, and the charge voltage Drive voltage V₀  ~ V₅  And a voltage dividing circuit 28e for outputting.
[0039]
Next, the operation of the above embodiment will be described with reference to FIG. When the power switch SW is closed at time t0 and the logic power supply VCC of the liquid crystal display device is turned on, the pulse width of several μs to several ms is applied to the power-on reset terminal RS of the liquid crystal module controller 12 as in the first embodiment. The reset signal is supplied from the MPU side, and the liquid crystal module controller 12 is initialized. Therefore, the output signal from the liquid crystal module controller 12 is generally in a stopped state. During this period, the logic power supply voltage VCC is supplied to one input of the logic circuit 78c, which is the AND circuit of the first scan driver 761, but the data signal latch clock LP has not appeared, so that the output PF1 is at the L level. Is in a state. As a result, the output PF2 of the second scan driver 762 is also at the L level, and the output PFn of the nth scan driver 76n is also at the L level, so that the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 is in the L level state. Is maintained. Therefore, since the base potential of the transistor 28b shown in FIG. 7 is L level (0v), the boosted voltage is not supplied to the smoothing capacitor 28d, and therefore the liquid crystal drive voltages V0 to V5 are not generated. As in Example 1, no direct current component is applied between the liquid crystal electrodes during this initialization period, preventing deterioration of the liquid crystal element.In addition, abnormal driving of the liquid crystal panel is also suppressed.
[0040]
Next, as shown in FIG.₁  Thus, various signals are generated from the liquid crystal module controller 12. The forced blank display signal DFF (bar) changes from the L level to the H level, and the frame start signal SP, the data signal latch clock LP, and the AC clock FR are generated. As described in the first embodiment, the inverter INV is started by the appearance of the data signal latch clock LP.₂  Output INV_OUTIs time t₂  Becomes H level. Therefore, the output Q of the power on / off control circuit 78b is at the time t.₂  Time t delayed by one to two frame periods₃So that the output PF of the logic circuit 78c.₁  Becomes H level. As a result, the second and nth scan drivers 76 are provided.₂  , 76_n  Output PF of logic circuit 78c₁  , PF are linked to the H level, so that the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 is energized to the H level. As a result, the transistor 28b is turned on, so that the transistor 28c is also turned on by the voltage drop of the base-emitter resistance of the transistor 28c, the smoothing capacitor 28d is charged, and the liquid crystal drive voltage V₀  ~ V₅  Will occur. Time t₃  From time t when the next frame start signal SP arrives₄  Until then, the output Q of the D flip-flop 79c remains at the L level. Signal delay circuit 79 in this embodiment₁  The number of stages of the D flip-flop is the power on / off control circuit 78.₁  Therefore, the output Q of the D flip-flop 79c is one frame period T than that of the D flip-flop 78b._F  This is because it becomes the H level after a delay. As a result, the output T₁  , T₂  , T_n  Since both are at the H level, as in the first embodiment, the forced blank display signal DF (bar) on the liquid crystal display module unit side changes from the L level to the H level. And the signal electrode has a drive voltage V₀  ~ V₅  Is supplied with power and enters the liquid crystal display mode.
[0041]
For example, when the liquid crystal display panel 22 is driven simultaneously with the generation of the liquid crystal drive voltages V0 to V5, a large charge rush current is induced in the power supply unit of the liquid crystal display panel and the scanning and signal drivers. However, in this embodiment, since the liquid crystal drive is started after one frame period TF after the liquid crystal drive voltages V0 to V5 are generated at the time t3, the rush current can be dispersed by the time difference energization of the power supply unit. It is possible to prevent the down and reduce the power capacity, which contributes to the protection of the liquid crystal display panel and the driver.
Further, from the viewpoint of a display start sequence at power-on or the like, FIG. 0 With logic power Vcc And the MPU detecting this generates a power-on reset signal (not shown), and in response to this, the time t 1 To set DFF (bar) to H level and time t 2 And after the first period TF, Three PF1, PF2, PFn, that is, POFF (bar) is set to the H level, that is, the liquid crystal power supply circuit 28 is turned on, and the liquid crystal drive power supply voltage V 0 ~ V Five At the time t after starting the generation of the second period TF Four T1, T2, Tn, that is, DF (bar) is set to H level, that is, the forced display blank control signal is canceled and display is started. By configuring the means for realizing such a sequence, it is possible to disperse the rush current and avoid abnormal driving of the liquid crystal panel.
Furthermore,The power control described above reduces the development cost burden on the system side, and does not increase the signal wiring between the conventional system side and the LCD module. Further, since the power capacity is reduced, an inexpensive power source can be used.
Next, assuming that the oscillation of the data signal latch clock LP sent from the liquid crystal module controller 12 side stops at the time t5 in the liquid crystal driving period B, the input voltage of the inverter INV2 increases as in the first embodiment. The output voltage INVOUT becomes L level at time t6, and the outputs T1, T2, Tn also become L level. As a result, since the forced display blank control signal DF (bar) on the liquid crystal display module side becomes L level, the liquid crystal display panel 22 is in a blank display state. The same effect as Example 1 is exhibited. When the output voltage INVOUT of the inverter INV2 becomes L level, the outputs PF1, PF2, and PFn simultaneously become L level, the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 changes to L level, and the liquid crystal drive voltage V0 to. Generation of V5 stops.
[0042]
Time t₇  When the data signal latch clock LP starts to appear again in FIG. 2, similarly to the first embodiment, the inverter INV₂  Output voltage INV_OUT  Is time t₈  At H level, and as described above, at this time t₈  Time t 1 to 2 frames after₉  Output PF at₁  , PF₂  , PF_n  Becomes H level. As a result, since the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 changes to the H level, the liquid crystal driving voltage V₀  ~ V₅  Are generated and applied to the driver side. And as mentioned above, the output T₁  , T₂  , T_n  Is the time t₉  1 frame period T_F  Is delayed by t₁₀Becomes the H level, and the liquid crystal driving voltage V is applied to the scanning electrodes and signal electrodes of the liquid crystal display panel 22.₀  ~ V₅  Is supplied and the liquid crystal display mode is resumed.
[0043]
Time t₁₁When the forced display blank control signal DFF (bar) on the liquid crystal display controller 12 side becomes L level, the output T₁  , T₂  , T_n  Therefore, the forced display blank control signal DF (bar) on the liquid crystal display module unit 70 side also becomes L level, and the liquid crystal display panel 22 enters the display off period C. At this time t₁₁Time t 1 to 2 frames after₁₂Power on / off control circuit 78₁  The output Q of the D flip-flop 78b changes to L level, and the output PF₁  , PF₂, PF_n  Becomes L level. As a result, since the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 is also at the L level, the liquid crystal driving voltage V₀  ~ V₅  Stops occurring. As described above, when the forced display blank control signal DFF (bar) on the liquid crystal display controller 12 side becomes the L level, the liquid crystal voltage is not applied to the driver after a certain period of time has elapsed after the liquid crystal driving is stopped. By such a power-off sequence, the logic power supply V_CCAnd LCD drive power supply V₀  ~ V₅  Thus, the parasitic bipolar current and the through current in the driver are suppressed, so that the liquid crystal display panel and the driver can be protected.
[0044]
In this embodiment, the power of the liquid crystal power supply circuit 28 is turned on after the clock is supplied to the liquid crystal module side, and the power of the liquid crystal power supply circuit 28 is also turned off by stopping the output of the clock. Since the rush current is distributed or time-difference by such an auto-sequence of power supply energization, the liquid crystal panel, the driver and the liquid crystal power circuit constituting the liquid crystal display module can be protected as described above.
Further, after the signal DFF (bar) instructing the start of the display on sequence is supplied, the power of the liquid crystal power supply circuit 28 is turned on, and then the forced display blank control signal is canceled to start the display. By configuring the means for realizing such a sequence, it is possible to disperse the rush current and avoid the abnormal driving of the liquid crystal panel.
[0045]
In each of the above embodiments, the signal management control unit is built in the scan driver LSI. This is because the number of input / output signal lines is smaller than that of the signal driver LSI and the display frame area is wide. This is because the area margin of the circuit board on which the signal management control unit is mounted is large. In this embodiment, the display device of the simple matrix liquid crystal panel has been described. However, the present invention is not limited to this and can be applied to an active matrix liquid crystal display device. In such a case, it is preferable to incorporate a signal management control unit on the gate driver LSI side. In that case, when the clock is stopped, the gate driver LSI is controlled so that all the gates are turned on, and the source driver is controlled so that the same potential is output on the data side as that on the common side. It is set to be in the added state. Furthermore, the present invention can be applied not only to a display but also to a display device whose display quality deteriorates due to direct current driving, such as an electronic device or a plasma display using a wide range of liquid crystal devices, such as a liquid crystal optical arithmetic device. is there.
[0046]
In each of the above embodiments, means for detecting an abnormality of a signal supplied from the liquid crystal module controller 12 side and means for removing the abnormal state of the signal in advance or afterwards are provided on the liquid crystal module side. However, it is also possible to employ a shared configuration in which some components of these means are provided on the liquid crystal module side and the remaining components are provided on the system (controller) side. For example, a plurality of signals (SP, LP, FR) that may cause a direct current drive of a liquid crystal panel have different frequencies and pulse duties. Therefore, these signals are simply converted using an anti-match gate (Exclusive OR gate). It is converted into a single composite signal, which is sent back to the system side, the abnormal state is monitored by the judgment circuit, the abnormal state is removed by the output, and an indicator is displayed using a display body different from the LCD module side. Such a configuration can be adopted. Further, the scanning driver 46 of the embodiment shown in FIG._n  Terminal T_n  It is also possible to adopt a method in which the output of the above is returned to the system side, and the logic and liquid crystal power supplies are controlled to be turned on / off in a certain sequence.
[0047]
Another cause of deterioration of the liquid crystal panel is the liquid crystal driving voltage V due to the abnormality of the voltage dividing circuit 28e in the liquid crystal power supply circuit 28 shown in FIG.₀  ~ V₅  It is conceivable that the liquid crystal panel is driven by an effective direct current component and deteriorates due to a voltage value shift or an output failure of a specific driver. Since these abnormalities can also be detected as fluctuations in the power supply current or the power supply voltage, the abnormal state can be removed by the above-described abnormality removing means.
[0048]
【The invention's effect】
As described above, the present inventionIn the display control device and the display device, after the signal for instructing the start of the display on sequence is supplied, the power of the liquid crystal power supply circuit 28 is turned on, and then the forced display blank control signal is canceled to start the display. . By configuring the means for realizing such a sequence, it is possible to disperse the rush current and avoid the abnormal driving of the liquid crystal panel.
The present invention is applicable not only to liquid crystal display devices but also to plasma display devices.AlsoApplicable.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to Embodiment 1 of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a signal management control unit of each scanning driver and a connection relationship between drivers in the same embodiment.
FIG. 3 is a circuit diagram showing a scan electrode drive cell of the scan driver in the same embodiment.
FIG. 4 is a timing chart showing the relationship between various signals in the liquid crystal display module for explaining the operation of the embodiment;
FIG. 5 is a block diagram showing an overall configuration of a liquid crystal display device according to Embodiment 2 of the present invention.
FIG. 6 is a circuit diagram illustrating a configuration of a signal management control unit of each scanning driver and a connection relationship between drivers in the same embodiment.
FIG. 7 is a circuit diagram showing a configuration of a liquid crystal power supply circuit in the same example.
FIG. 8 is a timing chart showing the relationship between various signals in the liquid crystal display module for explaining the operation of the embodiment;
FIG. 9 is a block diagram showing a configuration of a conventional liquid crystal display device.
[Explanation of symbols]
10 ... Liquid crystal display controller
12, 40, 70 ... Liquid crystal module controller
20 ... Flat liquid crystal display module
22 ... Liquid crystal display panel (matrix liquid crystal display element)
24₁  ~ 24_m  ... Signal electrode driver semiconductor integrated circuits
24 ... Signal electrode drive circuit (X driver)
26, 46, 76 ... scan electrode drive circuit (Y driver)
26₁  ~ 26_n  , 46₁  ~ 46_n  , 76₁  ~ 76_n  ... Scan electrode driver semiconductor integrated circuits
28 ... Liquid crystal power circuit
28a ... Voltage conversion circuit
28b... Npn transistor
28c... Pnp type transistor
28d ... Smoothing capacitor
28e ... Voltage divider circuit
30 ... Cable
46₁₁, 46₁₂... Scanning electrode drive cells
46a, 49a, 49b, 78a, 78b, 79c ... D-type flip-flop
46b ... Line-by-line forced blank display control circuit
46c... Row unit voltage level shift circuit
46d ... Total line forced blank display control circuit
46e ... Voltage level shift circuit
46f: Forward / reverse two-phase clock generation circuit
46g... Selection control signal generation circuit
46h ... selection switch
47, 47₁  ~ 47_n  , 77₁  ~ 77_n  ... Signal management control unit
48 ... Signal stop detection circuit
49, 79... Signal delay circuit
50 ... Logic circuit
51. Sequence processing circuit
78₁  ~ 78_n  ... Power supply power on / off control circuit
78c ... logic circuit
Tr₁  ... First N-type MOS transistor
Tr₂  ... Second N-type MOS transistor
INV₁, INV₂  , INV₃  ... Inverters
C₁₁... First capacitor
C₁₂... Second capacitor
R₁  ... Discharge resistance
AND ... AND circuit
CKB1 to CKBn ... terminals
S₁  ~ S_n  ... Signal stop detection control terminal
T₁  ~ T_n  ... Signal stop detection terminal
V₀  ~ V₅  ... Liquid crystal drive voltage (reference voltage)
D0 to D7 ... Data signal
XSCL: Pixel clock (shift clock pulse)
YSCL ... Scanning line synchronization signal
LP: Data signal latch clock
FR: AC clock
DF (bar) Display-off signal (forced blank display signal)
SP: Scan start pulse (frame start signal)
POFF (bar): Power-off terminal

Claims (5)

A display control device for controlling a flat display body,
  A display controller that operates with a supplied logic power supply. When the logic power supply is turned on, the forced blank display signal is held in an active state, and the first power supply is turned on after the logic power supply is turned on. 1 The display controller that outputs the forced blank display signal as an inactive state after a delay time of
When the logic power supply is turned on, the flat display body is set to a blank display state in response to the forced blank display signal being in an active state,
After the second delay time has elapsed since the forced blank display signal has changed from the active state to the inactive state, a display power control signal instructing the start of power output generation is output to the display power circuit,
After the third delay time has elapsed since the display power supply control signal was output, the blank display state is canceled, and a predetermined potential supplied from the display body power supply circuit is selected and output to the flat display body A body drive circuit;
The display control apparatus comprising: The display control apparatus according to claim 1 , wherein the flat display body is a liquid crystal display panel. The display control apparatus according to claim 1 , wherein the flat display body is a plasma display panel. The display control apparatus according to any one of claims 1 to 3, wherein the display control device, wherein the display control device is a semiconductor integrated circuit. The display control apparatus in any one of Claims 1 thru | or 4, and the display apparatus which has the said flat display body.

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