JP3660516B2 - Code synchronization acquisition apparatus and radio - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio apparatus employing a direct spread spectrum spread spectrum communication system (DS-SS) and a code synchronization acquisition apparatus applied to the radio apparatus.
[0002]
[Prior art]
In recent years, wireless communication technology has been remarkably improved, and various communication systems and wireless devices used in this system have been developed and operated. A direct spread spectrum spread communication system exists as a communication system having excellent interference resistance and noise resistance.
[0003]
In the direct spread spectrum spread communication system, the information signal to be transferred is band-spread with a wider band spread code than the signal and transmitted. Therefore, when receiving, it is necessary to synchronize this spreading code sequence.
[0004]
As a conventional code synchronization acquisition technique, there is a method in which a correlation output is obtained using a matched filter corresponding to a spread code, and the code timing is obtained by storing the output in a memory and selecting the largest one among them. . However, this method has a drawback that the circuit scale, memory, and the like increase because the output for each sample is handled.
[0005]
As another code synchronization acquisition technique, there is a method of obtaining synchronization by instantaneously comparing the output of a matched filter with a threshold value. However, this method has a drawback that the synchronization acquisition characteristic is deteriorated when there is a change in the transmission path such as fading.
[0006]
For this reason, as a code synchronization acquisition technology that can cope with fluctuations in the transmission path without increasing the circuit scale, memory, etc., the result of integrating the output of the matched filter for a certain period is used for determining the code timing. A method has been proposed (Japanese Patent Application No. 10-124924). FIG. 7 shows functional blocks of this method.
[0007]
In this method, first, the baseband signal obtained by the RF receiving unit 101 is sampled by the AD converter 102 and converted into a discrete signal. Subsequently, the discrete signal is passed through the matched filter 103 and despread with a spreading code, and the signal power integrator 104 divides the square value of the output signal of the matched filter 103 into the period of the spreading code (block). ) Integrate every time. The timing generator 105 instructs the signal power integrator 104 to indicate the timing of the integration period.
[0008]
Next, the integration block which is the integration result of the signal power integrator 104 is held in the memory 106, and the peak determination unit 107 detects the peak of the integration block. Then, all the samples in one or a plurality of blocks whose integration values are detected as peaks are detected in the memory 108 by the peak determination unit 107, and peak detection is performed from the samples acquired in the memory 108 by the peak determination unit 109. And get synchronization timing. The flow of this process will be described in detail with reference to FIG.
[0009]
The output (d1) of the matched filter is integrated and stored for each block. The block has a period obtained by equally dividing the spreading code period T (d2). Next, one or a plurality of large values are specified from the integrated values (d3) for each block, and all sample values included in the specified block positions are captured and stored (d4). Then, a sample showing a peak is selected from these samples (d5) and used as a code timing.
[0010]
As described above, in the method of performing the determination by integrating the output of the matched filter for a certain period in order to acquire the code synchronization, as described in Japanese Patent Application No. 10-124924, a circuit smaller than the conventional method is used. Processing is possible with scale and computational complexity. Moreover, it is possible to avoid performance degradation of synchronization acquisition due to transmission path fluctuations such as fading by cumulatively adding the integration results for each divided block over a plurality of cycles of the spread code sequence.
[0011]
[Problems to be solved by the invention]
However, in this method, when the true correlation value when trying to acquire synchronization exists at the boundary of the block to be integrated, the timing of the true correlation value is moved to the next period due to clock drift between transmission and reception. Therefore, there is a problem that synchronization acquisition may fail. For example, the case shown in FIG. 9 can be considered.
[0012]
When integration is performed for each block and a block having a peak is specified (e1), the peak of the sample is assumed to be at the position of e2 in block A as shown in FIG. Therefore, when the signals in the block are added, the block A shows a larger integrated value than the block B, and the block A is selected. However, when the sample of block A is taken in next time (e3), the peak of the sample at the position of e2 may be moved to the position of e4 of block B due to clock drift. In other words, in this case, if only the samples in the original block are taken, a sample showing a peak cannot be detected.
[0013]
The present invention has been made in consideration of such a situation, and an object thereof is to provide a code synchronization acquisition apparatus and a radio device that enable highly accurate code synchronization without being affected by clock drift.
[0014]
[Means for Solving the Problems]
In order to achieve the above-described object, the present invention is designed so that when integrating the output of the matched filter, the integration block is moved back and forth in order to avoid missing the correlation value near the boundary of the integration block due to clock drift. The blocks are divided so that they overlap each other.
[0015]
According to the present invention, when there is a true correlation value in the vicinity of a block boundary, it is possible to avoid the fact that the correlation value is moved to the adjacent block due to clock drift and is not missed.
[0016]
In addition, the present invention adds several samples before and after a sample to be a candidate block when the largest sample is detected after detecting one or a plurality of integration blocks showing a large integration value. What was used was used.
[0017]
According to the present invention, after detecting an integration block, when samples showing peaks are detected, several samples before and after the candidate block are added to the detection target, and the correlation value near the boundary is not missed. It is possible to detect.
[0018]
Further, according to the present invention, when block integration is performed on the output of the matched filter, the integration block is divided into blocks so that the integration block overlaps with the preceding and succeeding blocks, and the integration value indicates a large value. When a maximum sample is detected from a plurality of integration blocks after detecting a plurality of integration blocks, a sample obtained by adding several samples before and after the sample to be a candidate block is used.
[0019]
According to the present invention, it is avoided that the correlation value is moved to the adjacent block due to clock drift, and the correlation value near the boundary is acquired by adding several samples before and after the candidate block to the detection target. Since spilling is avoided, more accurate code synchronization can be performed as compared with the above-described invention.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 is a diagram showing the configuration of the code synchronization acquisition apparatus according to the first embodiment.
[0022]
As shown in FIG. 1, this code synchronization acquisition apparatus includes an RF receiver 101 that converts a DS-SS signal received by an antenna into a baseband signal, and a discrete reception baseband by sampling the baseband signal. AD converter 102 that generates a signal, matched filter 103 that despreads the discrete reception signal output from AD converter 102 with a spreading code, and signal power that integrates the power value of the correlation output from matched filter 103 An integrator 201, a timing generator 202 that generates a timing signal of an integration period (block) of the signal power integrator 201, a memory 106 that holds an integration block that is an integration result of the signal power integrator 201, and this memory 106, a peak detector 107 for detecting the peak of the integration block held in 106, and a peak determination unit 1 Only a memory 108 for taking samples of the detected integrated block 7, and a peak judging unit 109 for determining the sign timing contents held in the memory 108 to determine the timing of the correlation peak based on.
[0023]
The configuration of this code synchronization acquisition apparatus is basically the same as the conventional configuration shown in FIG. 7, but a signal power integrator is used to overlap the integration range of the output of the matched filter 103 between two adjacent blocks. The difference is that 201 and the timing generation unit 202 operate.
[0024]
FIG. 2 is a diagram for explaining a method of overlapping the integration range between two adjacent blocks when performing this block integration.
[0025]
As a result of the signal power integrator 201 and the timing generation unit 202 operating to overlap the integration range of the output of the matched filter 103 by two adjacent blocks, the integration ranges of the blocks A and B overlap each other by several samples. (A1). Here, it is assumed that the sample (a2) indicating the peak in the block A when the block is specified moves out of the range of the block A (a3) when the sample is taken in due to clock drift. However, because the integration ranges overlap, block B also contains samples that show this peak at a particular block, and block B is selected along with block A. That is, a sample showing a peak that is missed in block A can be detected in block B.
[0026]
Thus, in the code synchronization acquisition apparatus of the first embodiment, it is possible to perform highly accurate code synchronization without being affected by clock drift.
[0027]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the code synchronization acquisition apparatus according to the second embodiment.
[0028]
As shown in FIG. 3, this code synchronization acquisition apparatus includes an RF receiver 101 that converts a DS-SS signal received by an antenna into a baseband signal, and a discrete reception baseband by sampling the baseband signal. AD converter 102 that generates a signal, matched filter 103 that despreads the discrete reception signal output from AD converter 102 with a spreading code, and signal power that integrates the power value of the correlation output from matched filter 103 An integrator 104; a timing generator 105 that generates a timing signal of an integration period (block) of the signal power integrator 104; a memory 106 that holds an integration block that is an integration result of the signal power integrator 201; 106, a peak detector 107 for detecting the peak of the integration block held in 106, and a peak determination unit 1 7, a timing generator 203 that generates a timing signal for taking a sample of the memory 108 according to the detection result 7, a memory 108 that takes a sample based on the timing signal from the timing generator 203, and the contents held in the memory 108 A peak determination unit 109 that determines the code timing by determining the timing of the correlation peak is provided.
[0029]
The configuration of this code synchronization acquisition apparatus is obtained by adding a timing generator 203 to the conventional configuration shown in FIG. 7. This timing generator 203 is added to the integration block sample detected by the peak detector 107. Then, the operation is performed so that several samples before and after are taken into the memory.
[0030]
FIG. 4 is a diagram for explaining a method of adding several samples before and after the detected block when the samples are taken.
[0031]
In the code synchronization acquisition apparatus of the second embodiment, the process up to the point where the output of the matched filter 103 is divided into blocks and integrated is the same as in the prior art, and the period of the spreading code is also divided equally. Referring to FIG. 4, when a block is specified, there is a sample (b1) showing a peak in the block A, and the block A is selected by specifying the block (unlike the first embodiment, the block B is selected). Not) Next, the sample included in the block A is taken in, but there is a possibility that the sample is out of the range of the block A due to clock drift. In this case, a sample showing a peak cannot be detected. Therefore, here, in addition to the sample capture range included in the range of the block A, as shown in FIG. 4, several samples before and after are captured together to increase the number of sample selection candidates (b2). By doing in this way, it becomes possible to detect the sample (b3) which has deviated from the specified block.
[0032]
Thus, in the code synchronization acquisition apparatus of the second embodiment, it is possible to perform highly accurate code synchronization without being affected by clock drift.
[0033]
(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the code synchronization acquisition apparatus according to the third embodiment.
[0034]
As shown in FIG. 5, the code synchronization acquisition apparatus includes an RF receiver 101 that converts a DS-SS signal received by an antenna into a baseband signal, and a discrete reception baseband by sampling the baseband signal. AD converter 102 that generates a signal, matched filter 103 that despreads the discrete reception signal output from AD converter 102 with a spreading code, and signal power that integrates the power value of the correlation output from matched filter 103 An integrator 201, a timing generator 202 that generates a timing signal of an integration period (block) of the signal power integrator 201, a memory 106 that holds an integration block that is an integration result of the signal power integrator 201, and this memory 106, a peak detector 107 for detecting the peak of the integration block held in 106, and a peak determination unit 1 7, a timing generator 203 that generates a timing signal for taking a sample of the memory 108 according to the detection result 7, a memory 108 that takes a sample based on the timing signal from the timing generator 203, and the contents held in the memory 108 A peak determination unit 109 that determines the code timing by determining the timing of the correlation peak is provided.
[0035]
The configuration of this code synchronization acquisition apparatus is obtained by adding a timing generator 203 to the conventional configuration shown in FIG. 7. This timing generator 203 is added to the integration block sample detected by the peak detector 107. Then, the operation is performed so that several samples before and after are taken into the memory 108. Further, the signal power integrator 201 and the timing generation unit 202 operate so that the integration range of the output of the matched filter 103 is overlapped by two adjacent blocks.
[0036]
FIG. 6 is a diagram for explaining a method of overlapping the integration range between two adjacent blocks when performing this block integration and adding several samples before and after the detected block when taking in the samples.
[0037]
As a result of the signal power integrator 201 and the timing generation unit 202 operating to overlap the integration range of the output of the matched filter 103 by two adjacent blocks, the integration ranges of the blocks A and B overlap each other by several samples. However, here, the sample (c1) indicating the peak that exists in the block A at a specific position of the block and does not overlap with the block B is out of the range of the block A when the sample is taken in due to clock drift. Suppose that it moved to (c2).
[0038]
Even in this case, in addition to the sample capturing range included in the range of the block A, in order to increase the number of sample selection candidates (C2), the samples are overlapped. It is also possible to detect the sample (c3) that is out of the specified block beyond the range.
[0039]
Thus, in the code synchronization acquisition apparatus of the third embodiment, it is possible to perform code synchronization with higher accuracy than the code synchronization acquisition apparatuses of the first and second embodiments.
[0040]
【The invention's effect】
As described in detail above, according to the present invention, the integration block is overlapped by two adjacent integration blocks, or after the integration block is specified, several samples before and after the block are added to the candidate samples, Even if clock drift occurs, accurate code synchronization can be performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a code synchronization acquisition apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a method of overlapping an integration range between two adjacent blocks when performing block integration according to the first embodiment;
FIG. 3 is a diagram showing a configuration of a code synchronization acquisition apparatus according to the second embodiment.
FIG. 4 is a diagram for explaining a method of adding several samples before and after a detected block when taking a sample according to the second embodiment;
FIG. 5 is a diagram showing a configuration of a code synchronization acquisition apparatus according to the third embodiment.
FIG. 6 is a diagram for explaining a method of overlapping the integration range between two adjacent blocks when performing block integration according to the third embodiment and adding several samples before and after the detected block when taking samples; Figure.
FIG. 7 is a diagram for explaining a method of using a result obtained by integrating the output of a conventional matched filter for a certain period for determination of code timing.
FIG. 8 is a diagram for explaining in detail a processing flow of a method in which a result of integrating a conventional matched filter output for a certain period is used for determination of code timing.
FIG. 9 is a diagram for explaining a problem included in a method of using a result obtained by integrating an output of a conventional matched filter for a certain period for determination of code timing.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... RF receiver 102 ... AD converter 103 ... Matched filter 104 ... Signal power integrator 105 ... Timing generator (block)
106: Memory (block)
108 ... Memory (sample)
107: Peak detector (block)
109 ... Peak detector (sample)
201 ... Signal power integrator 202 ... Timing generator (block)
203 ... Timing generator (sample)

Claims (6)

Integration of the output value of the matched filter for each of a plurality of periods cut out from the cycle of the spread code sequence, and determining the code timing using the result of integration, thereby performing synchronization acquisition of the spread code in direct spread spectrum spread communication In the code synchronization acquisition device,
A code synchronization acquisition apparatus comprising means for cutting out the period so that a part of the integration range overlaps between two adjacent periods. Integrate the output value of the matched filter for each period obtained by dividing the spreading code sequence into multiple periods, specify one or more periods from the result of integration, and then include the samples included in the specified period In a code synchronization acquisition apparatus that performs synchronization acquisition of a spread code in direct spread spectrum spread communication by determining the code timing as a candidate,
A code synchronization acquisition apparatus comprising: means for acquiring a predetermined number of samples before and after the specified period as candidates. After integrating the output value of the matched filter for each of a plurality of periods cut out from the cycle of the spread code sequence, and specifying one or a plurality of periods from the result of the integration, samples included in the specified period are selected as candidates. In a code synchronization acquisition apparatus that performs synchronization acquisition of a spread code in direct spread spectrum spread communication by determining the code timing,
Means for cutting out the period so that a part of the integration range overlaps between two adjacent periods;
A code synchronization acquisition apparatus comprising: means for acquiring a predetermined number of samples before and after the specified period as candidates. Integration of the output value of the matched filter for each of a plurality of periods cut out from the cycle of the spread code sequence, and determining the code timing using the result of integration, thereby performing synchronization acquisition of the spread code in direct spread spectrum spread communication In the radio,
A wireless device comprising means for cutting out the period so that a part of the integration range overlaps between two adjacent periods. Integrate the output value of the matched filter for each period obtained by dividing the spreading code sequence into multiple periods, specify one or more periods from the result of integration, and then include the samples included in the specified period In a radio that performs synchronization acquisition of a spread code in direct spread spectrum spread communication by determining the code timing as a candidate,
A wireless device comprising means for taking a predetermined number of samples before and after the specified period as candidates. After integrating the output value of the matched filter for each of a plurality of periods cut out from the cycle of the spread code sequence, and specifying one or a plurality of periods from the result of the integration, samples included in the specified period are selected as candidates. In a radio that performs synchronization acquisition of a spread code in direct spread spectrum spread communication by determining the code timing,
Means for cutting out the period so that a part of the integration range overlaps between two adjacent periods;
Means for capturing a predetermined number of samples before and after the specified period as candidates.

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