JP3659007B2 - Test jig inspection method - Google Patents

Description

【００５１】
ここに、検査１は、試験治具２０の配線３５−１〜３５−ｎ、３８−１〜３８−ｍ、４１−１〜４１−ｐ、４４のうち、受信可能な試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐに接続されている配線（以下、受信可能配線という）３５−１〜３５−ｎ、４１−１〜４１−ｐの電源／グラウンド短絡故障を検査するものである。
【００５２】
また、検査２は、受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの断線故障、受信可能配線間の短絡故障および誤配線を検査するものである。
【００５３】
また、検査３は、試験治具２０の配線３５−１〜３５−ｎ、３８−１〜３８−ｍ、４１−１〜４１−ｐ、４４のうち、送信専用の試験チャネル２６−１〜２６−ｍに接続されている配線（以下、送信専用配線という）３８−１〜３８−ｍと受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間の短絡故障を検査するものである。
【００５４】
また、検査４は、送信専用配線３８−１〜３８−ｍの電源／グラウンド短絡故障、断線故障、送信専用配線間の短絡故障および誤配線を検査するものである。
【００５５】
図３は本発明の一実施形態の内容を概略的に示すフローチャートであり、本発明の一実施形態は、検査１〜検査４を図３に示すような手順で行うというものである。
【００５６】
即ち、本発明の一実施形態においては、まず、作業者は、図２に示すように、試験機２２の接続ピン２５−１〜２５−ｎ、２７−１〜２７−ｍ、２９−１〜２９−ｐ、３１に試験治具２０の接続ピン３４−１〜３４−ｎ、３７−１〜３７−ｍ、４０−１〜４０−ｐ、４３を接続し、試験治具２０を試験機２２に装着する（ステップＳ１）。
【００５７】
続いて、同じく、図２に示すように、作業者は、試験機２２の接続ピン３３にプローブ装置２３の接続ピン４８を接続して、プローブ装置２３を試験機２２に装着し（ステップＳ２）、制御コンピュータ２１に検査開始の指示を与える（ステップＳ３）。
【００５８】
制御コンピュータ２１に対する検査開始の指示（ステップＳ３）は、例えば、図４に示すように、検査実行コマンド名、配線情報ファイル名（試験治具２０の配線情報［ネットリスト］のファイル名）、プローブ接続チャネル番号（プローブ装置２３を接続した試験チャネルのチャネル番号［本発明の一実施形態の場合は、試験チャネル３２のチャネル番号］）を入力することにより行うことができる。
【００５９】
ここに、制御コンピュータ２１は、検査開始指示を受けると、試験治具２０の配線情報の読み込みを行い（ステップＳ４）、検査の種類に応じて検査対象配線の決定を行う（ステップＳ５）。
【００６０】
なお、配線情報の読み込み（ステップＳ４）は、配線情報のファイル情報を読出し、全ての配線の試験チャネルおよび被試験体側の接続ピン名を求めることにより行われる。
【００６１】
図５は配線情報例を示す図であり、１行で１配線分の情報が記述されるが、各行のレコード形式は、図６に示すように、「被試験体の接続ピン名／試験機との接続ピン名、試験チャネル番号」を記述することにより行われる。
【００６２】
例えば、図５に示す配線情報例において、２行目に示す「ＬＡ０１−０１」は被試験体の接続ピン名であり、「ＬＡ０１」はコネクタ名、「０１」はコネクタＬＡ０１内のピン番号である。また、「ＥＸ１」は試験機２２との接続ピン名、「１」は試験チャネル番号を示している。
【００６３】
制御コンピュータ２１において、検査対象配線の決定（ステップＳ５）が行われると、検査の種類からして、プローブ４７を試験治具２０の接続ピンにコンタクトさせる必要があるか否かが判断され（ステップＳ６）、プローブ４７を試験治具２０の接続ピンにコンタクトさせる必要がない場合（検査１又は検査３を行う場合）には、制御コンピュータ２１は、試験機２２に検査の種類に応じた試験信号の送受を行わせることになる（ステップＳ９）。
【００６４】
これに対して、プローブ４７を試験治具２０の接続ピンにコンタクトさせる必要がある場合（検査２又は検査４を行う場合）には、制御コンピュータ２１は、プローブ４７のコンタクト指示を出すことになる（ステップＳ７）。
【００６５】
プローブ４７のコンタクト指示は、試験治具２０の被試験体との接続ピン名と、プローブ４７をコンタクトする旨のメッセージを表示装置面に表示することにより行われる。
【００６６】
図７はプローブ４７のコンタクト指示のメッセージ例を示す図であり、図７中、「contact to」はプローブ４７をコンタクトする旨のメッセージ、「JA33-01」はプローブ４７をコンタクトすべき接続ピン名であり、「JA33」はコネクタ名、「01」はコネクタＪＡ３３内のピン名である。また、「(129)」は、これから検査する配線がチャネル番号１２９の試験チャネルに接続されているべき配線であることを示している。
【００６７】
制御コンピュータ２１は、プローブ４７のコンタクト指示を出した後、プローブ４７が指示した接続ピンにコンタクトされたか否かを確認し（ステップＳ８）、コンタクトされた場合には、試験機２２に対して検査の種類に応じた試験信号の送受を行わせることになる（ステップＳ９）。
【００６８】
試験信号の送信は、試験チャネル２６−１〜２６−ｍから直接又は試験チャネル３２からプローブ装置２３を介して試験治具２０に対して試験信号の送出を行うことにより行われ、試験信号の受信は、試験治具２０から出力される試験信号を試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐで直接受信するか又はプローブ装置２３を介して試験チャネル３２で受信することにより行われる。
【００６９】
試験機２２において、試験信号の送受（ステップＳ９）が終了すると、制御コンピュータ２１で検査対象配線の故障の解析が行われ（ステップＳ１０）、故障解析結果が通知される（ステップＳ１１）。
【００７０】
そして、作業者からの検査を続行するか否かの指示を待ち、検査を終了するか否かを判断し（ステップＳ１２）、作業者から検査を続行する場合の指示があった時は、ステップＳ５に戻り、作業者から検査終了の指示があった時は、試験を終了させることになる。
【００７１】
なお、故障解析（ステップＳ１０）は、試験信号の送受結果を解析し、故障の有無を調べることにより行われ、故障を検出した場合には、故障個所の特定と故障モードが分類され、故障解析結果の通知（ステップＳ１１）は、表示装置面に故障解析結果を表示することにより行われる。
【００７２】
図８は故障解析結果の通知例を示す図であり、図８中、「Test2 : wiring verify check」は試験項目を示し、「contact to JA33-11(138)」はプローブ４７をチャネル番号１３８の試験チャネルに接続されているべきコネクタＪＡ３３の接続ピン１１にコンタクトさせる指示を示し、「ＯＫ」は検査した配線に故障がなかったことを示している。
【００７３】
また、「contact to JA33-12 (139)」はプローブ４７をチャネル番号１３９の試験チャネルに接続されているべきコネクタＪＡ３３の接続ピン１２にコンタクトさせる指示を示し、「ＯＫ」は検査した配線に故障がなかったことを示している。
【００７４】
また、「contact to JA33-13 (140)」はプローブ４７をチャネル番号１４０の試験チャネルに接続されているべきコネクタＪＡ３３の接続ピン１３にコンタクトさせる指示を示し、「ＮＧ」は検査した配線に故障があったことを示している。
【００７５】
そして、「Shorted JA34-45 (441)」はプローブ４７をコンタクトさせた接続ピン（コネクタＪＡ３３の接続ピン１３）に接続されている配線と、チャネル番号４４１の試験チャネルとコネクタＪＡ３４の接続ピン４５とを接続している配線との間に短絡故障が存在していることを示している。
【００７６】
また、「contact to JA33-14 (141)」はプローブ４７をチャネル番号１４１の試験チャネルに接続されているべきコネクタＪＡ３３の接続ピン１４にコンタクトさせる指示を示し、「ＮＧ」は検査した配線に故障があったことを示している。
【００７７】
そして、「Unexpect JA33-15 (142)」はプローブ４７をコンタクトさせた接続ピン（コネクタＪＡ３３の接続ピン１５）がチャネル番号１４２の試験チャネルに接続されており、コネクタＪＡ３３の接続ピン１５に接続されるべき配線と誤配線されていることを示している。
【００７８】
図９は検査１（試験治具２０の受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの電源／グラウンド短絡故障の検査）の手順を示すフローチャート、図１０〜図１２は検査１を説明するための回路図である。
【００７９】
検査１を実行する場合には、まず、試験機２２の電源３０の出力を論理０とするか、又は、接続ピン３１を接地して、図１０に示すように、接続ピン３１に論理０が出力される状態とする（ステップＮ１−１）。
【００８０】
次に、送信専用の試験チャネル２６−１〜２６−ｍの出力状態をハイインピーダンス状態とするか、又は、図１０に示すように、送信専用の試験チャネル２６−１〜２６−ｍの出力を論理１に設定する（ステップＮ１−２）。
【００８１】
次に、送受可能な試験チャネル２４−１〜２４−ｎおよび受信専用の試験チャネル２８−１〜２８−ｐを受信状態に設定し（ステップＮ１−３）、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号の論理値を判定する（ステップＮ１−４）。
【００８２】
ここに、受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐが配線４４と短絡していなければ、図１１に示すように、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号は、全て論理１となる。
【００８３】
これに対して、受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの中に配線４４又はグラウンドと短絡しているものがあると、配線４４又はグラウンドに短絡している受信可能配線に接続されている試験チャネルの受信信号は論理０となる。
【００８４】
例えば、図１２に示すように、試験チャネル２４−１の受信信号＝論理０、試験チャネル２４−２〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１の場合には、受信可能配線３４−１は配線４４に短絡していることになる。
【００８５】
このように、検査１を実行する場合には、試験治具２０の受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの電源／グラウンド短絡故障を検出することができる。
【００８６】
また、図１３は検査２（受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの断線故障、受信可能配線間の短絡故障および誤配線の検査）の手順を示すフローチャート、図１４〜図１７は検査２を説明するための回路図である。
【００８７】
検査２を実行する場合には、まず、送受可能な試験チャネル２４−１〜２４−ｎおよび受信専用の試験チャネル２８−１〜２８−ｐを受信状態とし（ステップＮ２−１）、プローブ４７を試験治具２０の接続ピン３６−１〜３６−ｎ、４２−１〜４２−ｐの中の指示された接続ピンにコンタクトさせる（ステップＮ２−２）。
【００８８】
そして、試験チャネル３２から論理０の信号を送信し（ステップＮ２−３）、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号の論理値を判定する（ステップＮ２−４）。以下、検査を終了させない限り、プローブ４７をコンタクトさせるべき接続ピンを変えながら、ステップＮ２−２〜Ｎ２−４を繰り返す。
【００８９】
ここに、プローブ４７をコンタクトさせた接続ピンに接続されている受信可能配線に接続されている試験チャネルのみでプローブ４７からの送信信号を受信した場合には、その受信可能配線には、断線故障、受信可能配線間の短絡故障、誤配線は存在しないと判断することができる。
【００９０】
例えば、図１４に示すように、プローブ４７を接続ピン３６−１にコンタクトさせて、試験チャネル３２から論理０の信号を送信した場合、試験チャネル２４−１の受信信号＝論理０、試験チャネル２４−２〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合には、受信可能配線３５−１には、断線故障、受信可能配線間の短絡故障、誤配線は存在しないと判断することができる。
【００９１】
これに対して、試験チャネル２４−２〜２４−ｎ、２８−１〜２８−ｐのいずれにおいても、プローブ４７からの送信信号が受信されなかった場合には、コンタクトさせた接続ピンに接続されている受信可能配線に断線故障があると判断することができる。
【００９２】
例えば、図１５に示すように、プローブ４７を接続ピン３６−１にコンタクトさせて、試験チャネル３２から論理０の信号を送信した場合、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合、受信可能配線３５−１に断線故障が存在すると判断することができる。
【００９３】
また、プローブ４７をコンタクトさせた接続ピンに接続されている受信可能配線に接続されている試験チャネルと、他の試験チャネルとで同時にプローブ４７からの送信信号を受信した場合には、プローブ４７をコンタクトさせた接続ピンに接続されている受信可能配線と、送信信号を受信した他の試験チャネルに接続されている受信可能配線との間に短絡故障が存在すると判断することができる。
【００９４】
例えば、図１６に示すように、プローブ４７を接続ピン３６−１にコンタクトさせて、試験チャネル３２から論理０の信号を送信した場合、試験チャネル２４−１、２８−１の受信信号＝論理０、試験チャネル２４−２〜２４−ｎ、２８−２〜２８−ｐの受信信号＝論理１であった場合には、受信可能配線３５−１、４１−１間に短絡故障が存在すると判断することができる。
【００９５】
また、プローブ４７をコンタクトさせた接続ピンに接続されているべき配線に接続されている試験チャネルでは送信信号が受信されず、他の試験チャネルでプローブ４７からの送信信号を受信した場合には、受信可能配線に誤りがあると判断することができる。
【００９６】
例えば、図１７に示すように、プローブ４７を接続ピン３６−１にコンタクトして、試験チャネル３２から論理０の信号を送信した場合、試験チャネル２４−１の受信信号＝論理１、試験チャネル２４−２の受信信号＝論理０、試験チャネル２４−３（図示せず）〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合には、配線３５−１、３５−２は、誤配線されていると判断することができる。
【００９７】
このように、検査２を実行する場合には、試験治具２０の受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの断線故障、受信可能配線間の短絡故障および誤配線を検出することができる。
【００９８】
また、図１８は検査３（送信専用配線３８−１〜３８−ｍと受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間の短絡故障の検査）の手順を示すフローチャート、図１９、図２０は検査３を説明するための回路図である。
【００９９】
検査３を実行する場合には、まず、送受可能な試験チャネル２４−１〜２４−ｎおよび受信専用の試験チャネル２８−１〜２８−ｐを受信状態とする（ステップＮ３−１）。
【０１００】
次に、プローブ４７をコンタクトさせない状態で、送信専用の試験チャネル２６−１〜２６−ｍの中の１個の試験チャネルの出力を論理０とし、他の試験チャネルの出力を論理１とする（ステップＮ３−２）。
【０１０１】
そして、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号の論理値を判定する（ステップＮ３−３）。以下、検査を終了させない限り、論理０を出力させる試験チャネルを変えながら、ステップＮ３−２、Ｎ３−３を繰り返す。
【０１０２】
ここに、試験チャネル２６−１〜２６−ｍの中の１個の試験チャネルの出力を論理０、他の試験チャネルの出力を論理１とした場合において、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合には、論理１を送信した試験チャネルに接続されている送信専用配線と受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間に短絡故障は存在しないと判断することができる。
【０１０３】
たとえば、図１９に示すように、試験チャネル２６−１の送信信号＝論理０、試験チャネル２６−２〜２６−ｍの送信信号＝論理１とした場合、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合には、送信専用配線３８−１と受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間には短絡故障は存在しないと判断することができる。
【０１０４】
これに対して、試験チャネル２６−１〜２６−ｍの中の１個の試験チャネルの出力を論理０、他の試験チャネルの出力を論理１とした場合において、試験チャネル２４−１〜２４−ｎ、２８−１〜２８−ｐの受信信号のいずれかが論理０であった場合には、論理０の信号を送信した送信専用配線と、論理０の信号を受信した試験チャネルに接続されている受信可能配線との間に短絡故障が存在すると判断することができる。
【０１０５】
例えば、図２０に示すように、試験チャネル２６−１の送信信号＝論理０、試験チャネル２６−２〜２６−ｍの送信信号＝論理１とした場合、試験チャネル２４−１の受信信号＝論理０、試験チャネル２４−２〜２４−ｎ、２８−１〜２８−ｐの受信信号＝論理１であった場合には、送信専用配線３８−１と受信可能配線３５−１との間に短絡故障が存在すると判断することができる。
【０１０６】
このように、検査３を実行する場合には、試験治具２０の送信専用配線３８−１〜３８−ｍと受信可能な配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間の短絡故障を検出することができる。
【０１０７】
また、図２１は検査４（送信専用配線３８−１〜３８−ｍの電源／グラウンド短絡故障、断線故障、送信専用配線間の短絡故障および誤配線の検査）の手順を示すフローチャート、図２２〜図２６は検査４を説明するための回路図である。
【０１０８】
検査４を実行する場合には、試験チャネル３２を受信状態とし（ステップＮ４−１）、続いて、電源３０の出力を論理０とし（ステップＮ４−２）、プローブ４７を接続ピン３９−１〜３９−ｍの中の指示された接続ピンにコンタクトする（ステップＮ４−３）。
【０１０９】
次に、試験チャネル２６−１〜２６−ｍから表２に示すような第１パターン〜第ｍパターンの試験信号を順に送信する。即ち、試験チャネル２６−１、２６−２、・・・２６−ｍからそれぞれ信号［０１１１・・・１］、［１０１１・・・１］、・・・［１１１１・・・０］を同時に送信する（ステップＮ４−４）。
【０１１０】
そして、試験チャネル３２の受信信号の論理値を判定する（ステップＮ４−５）。以下、検査を終了させない限り、プローブ４７をコンタクトさせる接続ピンを変えながら、ステップＮ４−３〜Ｎ４−５を繰り返す。
【０１１１】
【表２】

【０１１２】
ここに、試験チャネル２６−１〜２６−ｍから表２に示すような第１パターン〜第ｍパターンを順に送信した場合において、試験チャネル３２の受信信号がプローブ４７をコンタクトさせた接続ピンに期待される受信信号であった場合には、プローブ４７をコンタクトさせた送信専用配線には、電源／グラウンド短絡故障、断線故障、送信専用配線間の短絡故障および誤配線は存在しないと判断することができる。
【０１１３】
例えば、図２２に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合において、試験チャネル３２の受信信号が［０１１１・・・１］であった場合には、送信専用配線３８−１には、電源／グラウンド短絡故障、断線故障、送信専用配線間の短絡故障および誤配線は存在しないと判断することができる。
【０１１４】
これに対して、試験チャネル３２の受信信号が全ビットを論理０とする信号［００００・・・０］であった場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線は、配線４４又はグラウンドに短絡していると判断することができる。
【０１１５】
例えば、図２３に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合、試験チャネル３２の受信信号が［００００・・・０］であった場合には、送信専用配線３８−１には電源／グラウンド短絡故障が存在すると判断することができる。
【０１１６】
また、試験チャネル３２の受信信号が全ビットを論理１とする信号［１１１１・・・１］であった場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線に断線故障が存在すると判断することができる。
【０１１７】
例えば、図２４に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合、試験チャネル３２の受信信号＝［１１１１・・・１］であった場合には、送信専用配線３８−１に断線故障が存在すると判断することができる。
【０１１８】
また、試験チャネル３２の受信信号の中の期待されたビットと期待されないビットに論理０が含まれていた場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線は、期待されないビットに論理０を含む試験信号を出力する試験チャネルに接続されている送信専用配線と短絡故障していると判断することができる。
【０１１９】
例えば、図２５に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合において、試験チャネル３２の受信信号＝［００１１・・・１］であった場合には、送信専用配線３８−１、３８−２間に短絡故障が存在すると判断することができる。
【０１２０】
また、試験チャネル３２の受信信号が、プローブ４７をコンタクトさせた接続ピンに接続されている試験チャネル以外の試験チャネルから送信された試験信号であった場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線と、受信した試験信号を送信した試験チャネルに接続されている送信専用配線とが誤配線されていると判断することができる。
【０１２１】
例えば、図２６に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合、試験チャネル３２の受信信号＝［１０１１・・・１］であった場合には、送信専用配線３８−１、３８−２は、誤配線されていると判断することができる。
【０１２２】
このように、検査４を実行する場合には、試験治具２０の送信専用配線３８−１〜３８−ｍの電源／グラウンド短絡故障、断線故障、送信専用配線間の短絡故障および誤配線を検出することができる。
【０１２３】
なお、送信専用配線３８−１〜３８−ｍの断線故障の検査は、図２７に示す手順で行うこともできる。即ち、まず、試験チャネル３２を受信状態とし（ステップＮ５−１）、試験チャネル２６−１〜２６−ｍから論理０の送信信号が送出されるように設定する（ステップＮ５−２）。
【０１２４】
次に、プローブ４７を接続ピン３９−１〜３９−ｍの中の指示された接続ピンにコンタクトさせ（ステップＮ５−３）、試験チャネル３２の受信信号の論理値を判定する（ステップＮ５−４）。以下、検査を終了させない限り、プローブ４７をコンタクトさせる接続ピンを変えながら、ステップＮ５−３、Ｎ５−４を繰り返す。
【０１２５】
ここに、試験チャネル３２の受信信号が論理０であった場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線に断線故障は存在しないと判断することができる。
【０１２６】
例えば、図２８に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合、試験チャネル３２の受信信号が論理０であった場合には、送信専用配線３８−１に断線故障は存在しないと判断することができる。
【０１２７】
これに対して、試験チャネル３２の受信信号が論理１であった場合には、プローブ４７をコンタクトさせた接続ピンに接続されている送信専用配線に断線故障が存在すると判断することができる。
【０１２８】
例えば、図２９に示すように、プローブ４７を接続ピン３９−１にコンタクトさせた場合、試験チャネル３２の受信信号が論理１であった場合には、送信専用配線３８−１に断線故障が存在すると判断することができる。
【０１２９】
このように、図２７に示す手順を実行することによっても、送信専用配線３８−１〜３８−ｍの断線故障の検出を行うことができる。
【０１３０】
なお、図３０（Ａ）に示すように、試験治具２０の配線５０、５１がドライバ（バッファ）５２を介在させている場合において、配線５０が試験機２２内の送受可能な試験チャネル５３に接続された場合には、送受可能な試験チャネル５３を送信専用の試験チャネルとして扱うことで、配線５０、５１を送信専用配線として検査することができる。
【０１３１】
これに対して、図３０（Ｂ）に示すように、試験治具２０の配線５４、５５がレシーバ（レベル変換回路）５６を介在させている場合において、配線５５が試験機２２内の送受可能な試験チャネル５７に接続された場合には、試験チャネル５７をそのまま送受可能な試験チャネルとして扱うことができ、配線５４、５５を受信可能配線として検査することができる。
【０１３２】
以上のように、本発明の一実施形態によれば、試験治具２０について、▲１▼受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの電源／グラウンド短絡故障、▲２▼受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐの断線故障、受信可能配線間の短絡故障および誤配線、▲３▼送信専用配線３８−１〜３８−ｍと受信可能配線３５−１〜３５−ｎ、４１−１〜４１−ｐとの間の短絡故障、▲４▼送信専用配線３８−１〜３８−ｍの断線故障、送信専用配線間の短絡故障および誤配線を検出することができるので、試験治具２０の不良による被試験体の試験時の障害を防止することができる。
【０１３３】
しかも、本発明の一実施形態によれば、試験治具２０を使用する試験機２２を使用して検査を行うとしているので、プローブ装置２３を容易すれば足り、フライングプローバ等の特別な配線検査装置を必要としない。
【０１３４】
また、試験治具２０の配線情報を使用して試験治具２０の検査を行うとしているので、プローブ４７のコンタクト指示を確実に行うことができ、検査もれを防止し、試験治具２０の検査を確実に行うことができる。また、プローブ４７のコンタクト指示を制御コンピュータ２１により行うとしているので、試験治具２０の検査を容易に行うことができる。
【０１３５】
また、試験機２２内に送信専用の試験チャネルおよび受信専用の試験チャネルが存在する場合であっても試験治具２０の検査を行うことができるので、試験治具２０に内蔵させたバッファやレシーバにより試験信号の送受方向が限定された場合でも試験治具２０の検査を行うことができる。
【０１３６】
なお、本発明の一実施形態においては、プローブ４７を作業者が扱うようにした場合について説明したが、自動プローバを使用するように構成しても良く、このようにする場合には、試験治具２０の検査をより容易に行うことができる。
【０１３７】
【発明の効果】
以上のように、本発明によれば、試験機に試験治具を装着し、試験機を利用して試験治具の配線を検査するとしているので、制御コンピュータを使用することにより、フライングプローバ等のような特別な配線検査装置を必要とせず、試験治具の配線検査を確実、かつ、容易に行うことができる。
【図面の簡単な説明】
【図１】本発明の一実施形態を説明するための回路図である。
【図２】本発明の一実施形態を説明するための回路図である。
【図３】本発明の一実施形態の内容を概略的に示すフローチャートである。
【図４】本発明の一実施形態を説明するための図である。
【図５】本発明の一実施形態で使用される配線情報例を示す図である。
【図６】本発明の一実施形態で使用される配線情報例で使用される各行のレコード形式を示す図である。
【図７】本発明の一実施形態で使用されるプローブのコンタクト指示のメッセージ例を示す図である。
【図８】本発明の一実施形態で使用される故障解析結果の通知例を示す図である。
【図９】本発明の一実施形態で行われる検査１の手順を示すフローチャートである。
【図１０】本発明の一実施形態で行われる検査１を説明するための回路図である。
【図１１】本発明の一実施形態で行われる検査１を説明するための回路図である。
【図１２】本発明の一実施形態で行われる検査１を説明するための回路図である。
【図１３】本発明の一実施形態で行われる検査２の手順を示すフローチャートである。
【図１４】本発明の一実施形態で行われる検査２を説明するための回路図である。
【図１５】本発明の一実施形態で行われる検査２を説明するための回路図である。
【図１６】本発明の一実施形態で行われる検査２を説明するための回路図である。
【図１７】本発明の一実施形態で行われる検査２を説明するための回路図である。
【図１８】本発明の一実施形態で行われる検査３の手順を示すフローチャートである。
【図１９】本発明の一実施形態で行われる検査３を説明するための回路図である。
【図２０】本発明の一実施形態で行われる検査３を説明するための回路図である。
【図２１】本発明の一実施形態で行われる検査４の手順を示すフローチャートである。
【図２２】本発明の一実施形態で行われる検査４を説明するための回路図である。
【図２３】本発明の一実施形態で行われる検査４を説明するための回路図である。
【図２４】本発明の一実施形態で行われる検査４を説明するための回路図である。
【図２５】本発明の一実施形態で行われる検査４を説明するための回路図である。
【図２６】本発明の一実施形態で行われる検査４を説明するための回路図である。
【図２７】試験治具の送信専用配線の断線故障検査の他の方法を示すフローチャートである。
【図２８】試験治具の送信専用配線の断線故障検査の他の方法を説明するための回路図である。
【図２９】試験治具の送信専用配線の断線故障検査の他の方法を説明するための回路図である。
【図３０】本発明の一実施形態を説明するための回路図である。
【図３１】試験機と被試験体とを電気的に接続する試験治具の概念を示す図である。
【符号の説明】
２４−１〜２４−ｎ 送受可能な試験チャネル
２６−１〜２６−ｍ 送信専用の試験チャネル
２８−１〜２８−ｐ 受信専用の試験チャネル
３２ 送受可能な試験チャネル[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test jig inspection method for inspecting a wiring of a test jig for electrically connecting a test machine such as a printed circuit board test machine, an in-circuit test machine, a logic circuit test machine and the like to a device under test. .
[0002]
For example, when testing an electronic circuit component such as LSI or an electronic circuit unit on which the component is mounted, the tester and the device under test are electrically connected, and the test signal is transmitted from the tester to the device under test. And a test jig for transmitting signals from the device under test to the testing machine.
[0003]
If there is a defect such as disconnection, short circuit, or incorrect wiring in the wiring of the test jig, a normal test cannot be performed on the device under test. Therefore, it is necessary to inspect the wiring of the test jig.
[0004]
[Prior art]
FIG. 31 is a diagram showing the concept of a test jig for electrically connecting a test machine and a device under test. In FIG. 31, 1 is a test machine, 2 is a test jig, and 3 is a device under test.
[0005]
In the testing machine 1, 4 is a test channel group for transmitting a test signal to the device under test 3 and receiving a signal from the device under test 3, 5 is a power supply device for supplying a power supply voltage to the device under test 6, Reference numeral 7 denotes a connector for connection to the test jig 2.
[0006]
In the test jig 2, 8 and 9 are connectors for connecting to the testing machine 1, 10 is a wiring group, and 11 and 12 are connectors for connecting to the device under test 3. Reference numeral 13 denotes a circuit portion, and reference numerals 14 and 15 denote connectors for connection to the test jig 2.
[0007]
By the way, the device under test 3 has various types, and the shape, the specification of the connector, and the allocation pattern of signals and power to the connection pins in the connector differ depending on the type. Signals assigned to the internal connection pins and the allocation pattern to the power supply are fixed.
[0008]
For this reason, it is interposed between the testing machine 1 and the device under test 3 to transmit a test signal from the testing machine 1 to the device under test 3 and to transmit a signal from the device under test 3 to the testing machine 1. The test jig 2 is required.
[0009]
A test jig 2 shown in FIG. 31 includes connectors 8 and 9 corresponding to the connectors 6 and 7 of the testing machine 1 and connectors 11 and 12 corresponding to the connectors 14 and 15 of the device under test 3. However, there is a type of test jig in which the connection to the device under test 3 is not performed by a connector but by a large number of probes.
[0010]
Conventionally, as an inspection method for such a test jig, a multimeter or a buzzer is used to manually check the electrical continuity of the wiring based on the manufacturing information of the test jig such as a netlist, and the operator makes a pass / fail judgment. And an inspection method using a wiring inspection device such as a flying prober have been employed.
[0011]
[Problems to be solved by the invention]
The test jig inspection method using a multimeter or buzzer uses paper-based information, so there may be a problem that inspection may be lost due to misreading of information, etc., and short-circuit failure detection However, there is a problem that it takes much time and effort to detect a short-circuit fault.
[0012]
The test jig inspection method using a wiring inspection device such as a flying prober can be used to create data for the wiring inspection device. program However, there is a problem that it takes a lot of labor and time to create them, and a lot of money is required to purchase and maintain the wiring inspection apparatus.
[0013]
In view of the above, the present invention provides a test jig inspection method capable of reliably and easily performing a wiring inspection of a test jig without requiring a special wiring inspection apparatus such as a flying prober. The purpose is to do.
[0014]
[Means for Solving the Problems]
In the present invention, the first invention is a test for electrically connecting a device under test having an electronic circuit and a testing machine for testing the device under test by transmitting and receiving signals between the device under test. A test jig inspection method for inspecting the wiring of a jig, which includes a step of mounting the test jig on a testing machine and inspecting the wiring of the testing jig using the testing machine. .
[0015]
In the present invention, according to the first aspect of the present invention, the method includes the steps of mounting the test jig on the test machine and inspecting the wiring of the test jig using the test machine. Therefore, it is not necessary to use a special wiring inspection device such as a flying prober, and the wiring inspection of the test jig can be performed reliably and easily.
[0016]
In the present invention, the second aspect of the present invention is the first aspect of the present invention, wherein the step of inspecting the wiring of the test jig using the testing machine is the wiring connected to the power source in the testing machine during the wiring of the testing jig. The process of setting the potential to a logical value that can detect a short-circuit fault, Inside Determining the logical value of the output of the receivable test channel connected to the wiring of the test jig among the test channels.
[0017]
In the present invention, according to the second invention, it is possible to detect a power supply / ground short-circuit failure in wiring connected to a receivable test channel in the testing machine during wiring of the test jig.
[0018]
In the present invention, the third invention is the wiring of the test jig in the second invention, when the test channel in the testing machine has a test channel dedicated for transmission connected to the wiring of the test jig. Set the output state of the transmission-only test channel connected to the high impedance state, or set the output of the transmission-only test channel connected to the test fixture wiring to a logical value that can detect a short-circuit fault. It includes the step of setting the opposite logical value.
[0019]
In the present invention, according to the third aspect, between the wiring of the test jig connected to the test channel dedicated for transmission in the testing machine and the wiring connected to the receivable test channel in the testing machine. Even if there is a short-circuit fault, it can be hidden and a power / ground short-circuit fault in the wiring connected to the receivable test channel in the tester can be detected.
[0020]
In the present invention, the fourth invention relates to the second invention, in the case where the test channel in the testing machine has a test channel that can be transmitted and received that is connected to a wiring dedicated to the transmission of the test jig. The test channel that can be transmitted and received is treated as a test channel dedicated to transmission.
[0021]
According to the fourth aspect of the present invention, when the test jig is provided with a buffer for amplifying a test signal to be transmitted to the device under test, the wiring connected to the buffer and dedicated to transmission is provided. Even if there is a short-circuit fault between the wire connected to the receivable test channel in the tester, this is hidden and the wire connected to the receivable test channel in the tester is hidden. A power / ground short circuit fault can be detected.
[0022]
In the present invention, the fifth aspect of the present invention is the first aspect of the present invention, wherein the step of inspecting the wiring of the test jig using the test machine is performed in the connection pins of the test jig with the DUT in the test machine. Selecting connection pins connected to possible test channels one by one, transmitting a signal of a predetermined logic value from the selected connection pins to the tester, and in the test channel in the tester, And determining the logical value of the output of the receivable test channel connected to the wiring.
[0023]
In the present invention, according to the fifth aspect, during the wiring of the test jig, the disconnection failure of the wiring connected to the receivable test channel in the testing machine, the short-circuit failure between the same type wirings, and the incorrect wiring are detected. Can do.
[0024]
Among the present inventions, the sixth invention is the 5 In the present invention, one of the connection pins connected to the receivable test channel in the testing machine is selected one by one from the connection pins of the test jig to the DUT, and a signal of a predetermined logic value is selected from the selected connection pin. The step of transmitting to the tester is performed via a probe from a probe dedicated test channel in the tester.
[0025]
Among the present inventions, the seventh invention is the 5 In the present invention, one of the connection pins connected to the receivable test channel in the testing machine is selected one by one from the connection pins of the test jig to the DUT, and a signal of a predetermined logic value is selected from the selected connection pin. The step of transmitting to the tester is performed from a free test channel in the tester via a probe.
[0026]
In the present invention, the eighth invention is the first invention, wherein the step of inspecting the wiring of the test jig using the testing machine is connected to the wiring of the testing jig in the test channel in the testing machine. Select a test channel dedicated to transmission one by one, send a signal of a predetermined logic value from the selected test channel dedicated to transmission to the test jig, and wire the test jig in the test channel in the tester Determining the logical value of the output of the connected receivable test channel.
[0027]
In the present invention, according to the eighth invention, during the wiring of the test jig, the wiring connected to the test channel dedicated for transmission in the testing machine, and the wiring connected to the receivable test channel in the testing machine It is possible to detect a short-circuit fault during.
[0028]
In the present invention, the ninth invention is the first invention, wherein the step of inspecting the wiring of the test jig using the testing machine is connected to the wiring of the testing jig in the test channel in the testing machine. A process of transmitting different parallel logic pattern signals from a plurality of test channels dedicated to transmission to the test jig one by one in sequence, and a test channel dedicated to transmission in the testing machine in the connection pins of the test jig to the DUT And a step of determining a logical value of a signal output to a connection pin connected to.
[0029]
In the present invention, according to the ninth invention, during the wiring of the test jig, the disconnection failure of the wiring connected to the test channel dedicated for transmission in the testing machine, the short-circuit failure between the same type wirings and the incorrect wiring are detected. Can do.
[0030]
In the present invention, the tenth invention is the first invention, wherein the step of inspecting the wiring of the test jig using the testing machine is connected to the wiring of the testing jig in the test channel in the testing machine. A process of transmitting a signal of a predetermined logical value from the test channel dedicated to transmission to the test jig and a connection connected to the test channel dedicated to transmission in the testing machine in the connection pins of the test jig to the DUT And determining the logical value of the signal output to the pin.
[0031]
According to the tenth aspect of the present invention, it is possible to detect a disconnection failure in the wiring connected to the test channel dedicated for transmission in the testing machine during wiring of the test jig.
[0032]
In the present invention, the eleventh invention is output to the connection pin connected to the test channel dedicated for transmission in the testing machine in the connection pin with the device under test of the test jig in the ninth or tenth invention. The process of determining the logic value of the signal to be tested is to test the signal output to the connection pin connected to the test channel dedicated for transmission in the tester through the probe. This is performed by transmitting to an in-machine probe dedicated test channel or an empty test channel.
[0033]
In the present invention, a twelfth aspect of the present invention is the ninth, tenth or eleventh aspect of the present invention, wherein a test that can be transmitted and received is connected to a wiring dedicated to the transmission of the test jig in the test channel in the testing machine. When there is a channel, a test channel that can be transmitted and received is treated as a test channel dedicated to transmission.
[0034]
According to the twelfth aspect of the present invention, when the test jig includes a buffer for amplifying a test signal to be transmitted to the device under test, the wiring connected to this buffer and dedicated to transmission In addition, it is possible to detect disconnection failure, short-circuit failure, and miswiring.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram for explaining an embodiment of the present invention. In FIG. 1, reference numeral 20 denotes a test jig to be inspected. In one embodiment of the present invention, a control computer 21, a testing machine 22, and a probe device 23 are prepared.
[0036]
In the test machine 22, 24-1 to 24-n are test channels that can be transmitted and received so that a test signal can be transmitted to a device under test (not shown) and a signal can be received from the device under test. Reference numerals 25-1 to 25-n denote connection pins provided corresponding to the test channels 24-1 to 24-n.
[0037]
In addition, reference numerals 26-1 to 26-m denote test channels dedicated to transmission that can transmit only test signals to the device under test, and 27-1 to 27-m denote test channels 26-1 to 26-1. It is a connection pin provided corresponding to 26-m.
[0038]
Reference numerals 28-1 to 28-p are dedicated reception channels for receiving only signals from the device under test, and 29-1 to 29-p are test channels 28-1 to 28-p. It is a connection pin provided corresponding to p.
[0039]
Reference numeral 30 denotes a power supply for supplying a power supply voltage to the device under test. Reference numeral 31 denotes a connection pin provided corresponding to the power supply 30. Reference numeral 32 denotes transmission of a test signal to the device under test and reception of a signal from the device under test. The transmission / reception test channel 33, which is configured to be able to perform the test, is a connection pin provided corresponding to the test channel 32.
[0040]
For example, the logic function tester for printed wiring boards has several hundred test channels that can be sent and received for general signals, and tens of test channels dedicated to transmission for clock and scan test inputs, and scan test outputs. There are dozens of test channels dedicated to reception.
[0041]
Here, the transmission units of the test channels 24-1 to 24-n, 26-1 to 26-m, and 32 can transmit signals of logic 0 (L level) or logic 1 (H level). However, when the transmission signal of logic 0 and the transmission signal of logic 1 are short-circuited, the transmission signal of logic 0 is stronger and the wiring from which the transmission signal of logic 1 is output is logic 0. The transmission signal is output.
[0042]
In addition, the receiving units of the test channels 24-1 to 24-n, 28-1 to 28-p, and 32 are configured to be able to identify whether the received signal is logic 0 or logic 1. However, when there is no received signal, it is configured to be in the same state as when a logical 1 received signal is received.
[0043]
Therefore, in one embodiment of the present invention, as described later, a logic 0 signal is used as a test signal for performing a wiring inspection of the test jig 20.
[0044]
In the test jig 20, 34-1 to 34-n, 37-1 to 37-m, 40-1 to 40-p, and 43 are connection pins connected to the testing machine 22.
[0045]
35-1 to 35-n, 38-1 to 38-m, 41-1 to 41-p, 44 are connection pins 34-1 to 34-n, 37-1 to 37-m, 40-1 to 40-p, 43 is connected to the wiring.
[0046]
Further, 36-1 to 36-n, 39-1 to 39-m, 42-1 to 42-p, 45 are wirings 35-1 to 35-n, 38-1 to 38-m, 41-1 to 41, respectively. -P, 44 is a connection pin with the device under test to which it is connected.
[0047]
In the probe device 23, 46 is a cable, 47 is a probe connected to one end of the cable 46, and 48 is a connection pin with the testing machine 22 provided at the other end of the cable 46.
[0048]
As described above, the control computer 21, the testing machine 22, and the probe device 23 are prepared for the test jig 20 to be inspected, and the test jig 20 and the probe device 23 are tested as shown in FIG. When mounted on the machine 22, inspection 1 to inspection 4 as shown in Table 1 can be performed.
[0049]
This example is an example in which the test channel 32 is an empty channel. However, when using a tester having a probe function or a tester having a probe-dedicated test channel, the tester 32 may be The provided probe can be used.
[0050]
[Table 1]

[0051]
Here, the inspection 1 is a test channel 24-1 that can be received among the wirings 35-1 to 35 -n, 38-1 to 38 -m, 41-1 to 41 -p, 44 of the test jig 20. Inspecting power supply / ground short circuit failure of wirings connected to 24-n, 28-1 to 28-p (hereinafter referred to as receivable wirings) 35-1 to 35-n, 41-1 to 41-p It is.
[0052]
The inspection 2 is for inspecting the disconnection failure of the receivable wirings 35-1 to 35-n and 41-1 to 41-p, the short-circuit failure between the receivable wirings, and the erroneous wiring.
[0053]
Further, the inspection 3 is performed in the test channels 26-1 to 26 dedicated for transmission among the wirings 35-1 to 35-n, 38-1 to 38-m, 41-1 to 41-p, 44 of the test jig 20. -Check for short-circuit faults between wires connected to -m (hereinafter referred to as transmission-only wires) 38-1 to 38-m and receivable wires 35-1 to 35-n, 41-1 to 41-p To do.
[0054]
The inspection 4 is for inspecting a power supply / ground short-circuit failure, a disconnection failure, a short-circuit failure between transmission-dedicated wires, and miswiring of the transmission-dedicated wires 38-1 to 38-m.
[0055]
FIG. 3 is a flowchart schematically showing the contents of an embodiment of the present invention. In the embodiment of the present invention, inspection 1 to inspection 4 are performed according to the procedure shown in FIG.
[0056]
That is, in one embodiment of the present invention, first, as shown in FIG. 2, the worker connects the connection pins 25-1 to 25 -n, 27-1 to 27 -m, 29-1 of the testing machine 22. The connection pins 34-1 to 34-n, 37-1 to 37-m, 40-1 to 40-p, 43 of the test jig 20 are connected to 29-p and 31, and the test jig 20 is connected to the testing machine 22. (Step S1).
[0057]
Subsequently, similarly, as shown in FIG. 2, the operator connects the connection pin 48 of the probe device 23 to the connection pin 33 of the test machine 22 and attaches the probe device 23 to the test machine 22 (step S <b> 2). The control computer 21 is instructed to start inspection (step S3).
[0058]
As shown in FIG. 4, for example, an inspection start command name, a wiring information file name (a wiring information [net list] file name of the test jig 20), and a probe are sent to the control computer 21 as shown in FIG. This can be done by inputting the connection channel number (the channel number of the test channel to which the probe device 23 is connected [the channel number of the test channel 32 in one embodiment of the present invention)].
[0059]
Here, when receiving the inspection start instruction, the control computer 21 reads the wiring information of the test jig 20 (step S4), and determines the inspection target wiring according to the type of inspection (step S5).
[0060]
The wiring information is read (step S4) by reading the wiring information file information and obtaining the test channels of all wirings and the names of connection pins on the DUT.
[0061]
FIG. 5 is a diagram showing an example of wiring information, and information for one wiring is described in one line. The record format of each line is, as shown in FIG. "Connecting pin name and test channel number" are described.
[0062]
For example, in the wiring information example shown in FIG. 5, “LA01-01” shown in the second row is the connection pin name of the DUT, “LA01” is the connector name, and “01” is the pin number in the connector LA01. is there. “EX1” indicates the name of the connection pin with the test machine 22, and “1” indicates the test channel number.
[0063]
When the control computer 21 determines the wiring to be inspected (step S5), it is determined from the type of inspection whether the probe 47 needs to contact the connection pin of the test jig 20 (step S5). S6) When it is not necessary to contact the probe 47 with the connection pin of the test jig 20 (when performing inspection 1 or inspection 3), the control computer 21 sends a test signal corresponding to the type of inspection to the testing machine 22 Are sent and received (step S9).
[0064]
On the other hand, when it is necessary to contact the probe 47 to the connection pin of the test jig 20 (when the inspection 2 or the inspection 4 is performed), the control computer 21 issues a contact instruction for the probe 47. (Step S7).
[0065]
The contact instruction of the probe 47 is performed by displaying a name of a connection pin of the test jig 20 with the device under test and a message for contacting the probe 47 on the display device surface.
[0066]
FIG. 7 is a diagram showing an example of a contact instruction message of the probe 47. In FIG. 7, “contact to” is a message to contact the probe 47, and “JA33-01” is the name of the connection pin to which the probe 47 should be contacted. “JA33” is a connector name, and “01” is a pin name in the connector JA33. Also, “(129)” indicates that the wiring to be inspected from now on is the wiring that should be connected to the test channel of channel number 129.
[0067]
After issuing the contact instruction of the probe 47, the control computer 21 confirms whether or not the connection pin instructed by the probe 47 has been contacted (step S8). The test signal is transmitted / received according to the type (step S9).
[0068]
The test signal is transmitted by transmitting the test signal directly from the test channels 26-1 to 26-m or from the test channel 32 to the test jig 20 via the probe device 23. The test signal output from the test jig 20 is directly received by the test channels 24-1 to 24-n and 28-1 to 28-p, or is received by the test channel 32 through the probe device 23. Done.
[0069]
When the test machine 22 finishes sending and receiving the test signal (step S9), the control computer 21 analyzes the failure of the inspection target wiring (step S10) and notifies the failure analysis result (step S11).
[0070]
And it waits for the instruction | indication of whether to continue the test | inspection from a worker, it is judged whether a test | inspection is complete | finished (step S12), and when there exists an instruction | indication in the case of continuing a test | inspection from a worker, Returning to S5, when the operator gives an instruction to end the inspection, the test is ended.
[0071]
The failure analysis (step S10) is performed by analyzing the transmission / reception result of the test signal and checking the presence / absence of the failure. When a failure is detected, the failure location is identified and the failure mode is classified, and the failure analysis is performed. The notification of the result (step S11) is performed by displaying the failure analysis result on the display device surface.
[0072]
FIG. 8 is a diagram showing an example of failure analysis result notification. In FIG. 8, “Test2: wiring verify check” indicates a test item, and “contact to JA33-11 (138)” indicates the probe 47 with channel number 138. An instruction to contact the connection pin 11 of the connector JA33 to be connected to the test channel is indicated, and “OK” indicates that there is no failure in the inspected wiring.
[0073]
“Contact to JA33-12 (139)” indicates an instruction to cause the probe 47 to contact the connection pin 12 of the connector JA33 to be connected to the test channel of channel number 139, and “OK” indicates a failure in the inspected wiring. Indicates that there was no.
[0074]
“Contact to JA33-13 (140)” indicates an instruction to contact the probe 47 to the connection pin 13 of the connector JA33 to be connected to the test channel of channel number 140, and “NG” indicates a failure in the inspected wiring. Indicates that there was.
[0075]
And " Shorted JA34-45 (441) "is a wire connected to the connection pin (connection pin 13 of connector JA33) with which the probe 47 is contacted, and a wire connecting the test channel of channel number 441 and the connection pin 45 of connector JA34. Indicates that a short-circuit fault exists between the two.
[0076]
“Contact to JA33-14 (141)” indicates an instruction to contact the probe 47 to the connection pin 14 of the connector JA33 to be connected to the test channel of channel number 141, and “NG” indicates a failure in the inspected wiring. Indicates that there was.
[0077]
“Unexpect JA33-15 (142)” is a connection pin with which the probe 47 is contacted (a connection pin of the connector JA33). 15 ) Is connected to the test channel of channel number 142, indicating that the wiring to be connected to the connection pin 15 of the connector JA33 is miswired.
[0078]
FIG. 9 is a flowchart showing the procedure of inspection 1 (inspection of the power receivable wirings 35-1 to 35-n, 41-1 to 41-p of the test jig 20/41 to 41-p), and FIGS. 6 is a circuit diagram for explaining an inspection 1; FIG.
[0079]
When the inspection 1 is executed, first, the output of the power supply 30 of the testing machine 22 is set to logic 0, or the connection pin 31 is grounded, and as shown in FIG. An output state is set (step N1-1).
[0080]
Next, the output state of the test channels 26-1 to 26-m dedicated to transmission is set to the high impedance state, or the output of the test channels 26-1 to 26-m dedicated to transmission as shown in FIG. Set to logic 1 (step N1-2).
[0081]
Next, the test channels 24-1 to 24 -n that can be transmitted and received and the test channels 28-1 to 28 -p dedicated to reception are set to the reception state (step N 1-3), and the test channels 24-1 to 24 -n are set. , 28-1 to 28-p are determined (step N1-4).
[0082]
If the receivable wirings 35-1 to 35-n and 41-1 to 41-p are not short-circuited to the wiring 44, the test channels 24-1 to 24-n and 28-, as shown in FIG. All of the received signals from 1 to 28-p are logic one.
[0083]
On the other hand, if any of the receivable wirings 35-1 to 35 -n and 41-1 to 41 -p is short-circuited to the wiring 44 or the ground, the receiving is short-circuited to the wiring 44 or the ground. The received signal of the test channel connected to the possible wiring is logic 0.
[0084]
For example, as shown in FIG. 12, when the received signal of the test channel 24-1 = logic 0, the received signals of the test channels 24-2 to 24-n and 28-1 to 28-p = logic 1, the reception is performed. The possible wiring 34-1 is short-circuited to the wiring 44.
[0085]
As described above, when the inspection 1 is executed, it is possible to detect the power supply / ground short circuit failure of the receivable wirings 35-1 to 35 -n and 41-1 to 41 -p of the test jig 20.
[0086]
FIG. 13 is a flowchart showing the procedure of inspection 2 (inspection of disconnection failure of receivable wires 35-1 to 35-n and 41-1 to 41-p, short-circuit failure between receivable wires and incorrect wiring). 14 to 17 are circuit diagrams for explaining the inspection 2.
[0087]
When the inspection 2 is executed, first, the test channels 24-1 to 24-n and the test channels 28-1 to 28-p that can be transmitted and received are set in the reception state (step N2-1), and the probe 47 is set. Contact is made to the designated connection pin among the connection pins 36-1 to 36-n and 42-1 to 42-p of the test jig 20 (step N2-2).
[0088]
Then, a logic 0 signal is transmitted from the test channel 32 (step N2-3), and the logic values of the received signals of the test channels 24-1 to 24-n and 28-1 to 28-p are determined (step N2- 4). Hereinafter, unless the inspection is terminated, Steps N2-2 to N2-4 are repeated while changing the connection pin with which the probe 47 is to be contacted.
[0089]
Here, when the transmission signal from the probe 47 is received only by the test channel connected to the receivable wiring connected to the connection pin with which the probe 47 is contacted, the receivable wiring has a disconnection failure. Therefore, it can be determined that there is no short-circuit failure between the receivable wirings and incorrect wiring.
[0090]
For example, as shown in FIG. 14, when the probe 47 is contacted to the connection pin 36-1 and a signal of logic 0 is transmitted from the test channel 32, the received signal of the test channel 24-1 = logic 0, test channel 24 When the reception signals of −2 to 24-n and 28-1 to 28-p = logic 1, the receivable wiring 35-1 has a disconnection failure, a short-circuit failure between receivable wirings, and incorrect wiring. It can be determined that it does not exist.
[0091]
On the other hand, in any of the test channels 24-2 to 24-n and 28-1 to 28-p, when the transmission signal from the probe 47 is not received, it is connected to the contacted connection pin. It can be determined that there is a disconnection failure in the receivable wiring.
[0092]
For example, as shown in FIG. 15, when the probe 47 is contacted to the connection pin 36-1 and a signal of logic 0 is transmitted from the test channel 32, the test channels 24-1 to 24-n and 28-1 to 28-28 are transmitted. When the received signal of −p = logic 1, it can be determined that a disconnection failure exists in the receivable wiring 35-1.
[0093]
When a transmission signal from the probe 47 is received simultaneously on the test channel connected to the receivable wiring connected to the connection pin with which the probe 47 is contacted and another test channel, the probe 47 is It can be determined that a short-circuit fault exists between the receivable wiring connected to the contact pin that has been contacted and the receivable wiring connected to another test channel that has received the transmission signal.
[0094]
For example, as shown in FIG. 16, when the probe 47 is brought into contact with the connection pin 36-1 and a signal of logic 0 is transmitted from the test channel 32, the received signals of the test channels 24-1 and 28-1 = logic 0. When the reception signals of the test channels 24-2 to 24-n and 28-2 to 28-p = logic 1, it is determined that a short-circuit fault exists between the receivable wires 35-1 and 41-1. be able to.
[0095]
Further, when a transmission signal is not received in the test channel connected to the wiring to be connected to the connection pin with which the probe 47 is contacted, and a transmission signal from the probe 47 is received in another test channel, It can be determined that there is an error in the receivable wiring.
[0096]
For example, as shown in FIG. 17, when the probe 47 is contacted to the connection pin 36-1 and a signal of logic 0 is transmitted from the test channel 32, the received signal of the test channel 24-1 = logic 1, test channel 24 -2 received signal = logic 0, test channels 24-3 (not shown) to 24-n, 28-1 to 28-p received signals = logic 1, wirings 35-1, 35 -2 can be determined to be miswired.
[0097]
As described above, when the inspection 2 is executed, the receivable wirings 35-1 to 35 -n and 41-1 to 41 -p of the test jig 20 are disconnected, the receivable wiring is short-circuited, and the wiring is erroneously connected. Can be detected.
[0098]
FIG. 18 shows the procedure of inspection 3 (inspection of short-circuit failure between the transmission-dedicated wirings 38-1 to 38-m and the receivable wirings 35-1 to 35-n and 41-1 to 41-p). The flowcharts, FIGS. 19 and 20 are circuit diagrams for explaining the inspection 3.
[0099]
When the inspection 3 is executed, first, the test channels 24-1 to 24-n that can be transmitted and received and the test channels 28-1 to 28-p dedicated to reception are set in the reception state (step N 3-1).
[0100]
Next, in the state where the probe 47 is not contacted, the output of one of the test channels 26-1 to 26-m dedicated for transmission is set to logic 0, and the output of the other test channel is set to logic 1 ( Step N3-2).
[0101]
Then, the logical values of the received signals of the test channels 24-1 to 24-n and 28-1 to 28-p are determined (step N3-3). Hereinafter, unless the inspection is finished, the logic 0 Steps N3-2 and N3-3 are repeated while changing the test channel for outputting.
[0102]
When the output of one test channel among the test channels 26-1 to 26-m is logic 0 and the output of the other test channels is logic 1, the test channels 24-1 to 24-n, When the received signals of 28-1 to 28-p = logic 1, transmission-only wiring and receivable wirings 35-1 to 35-n, 41-1 connected to the test channel that has transmitted logic 1 It can be determined that there is no short-circuit fault between ˜41-p.
[0103]
For example, as shown in FIG. 19, when the transmission signal of the test channel 26-1 = logic 0 and the transmission signal of the test channels 26-2 to 26-m = logic 1, the test channels 24-1 to 24-n, When the received signals of 28-1 to 28-p = logic 1, between the transmission-dedicated wiring 38-1 and the receivable wirings 35-1 to 35-n and 41-1 to 41-p, It can be determined that there is no short circuit fault.
[0104]
On the other hand, when the output of one test channel among the test channels 26-1 to 26-m is logic 0 and the output of the other test channels is logic 1, the test channels 24-1 to 24- If any of the n, 28-1 to 28-p received signals is logic 0, it is connected to the dedicated transmission line that transmitted the logic 0 signal and the test channel that received the logic 0 signal. It can be determined that there is a short-circuit fault with the receivable wiring.
[0105]
For example, as shown in FIG. 20, when the transmission signal of the test channel 26-1 is logic 0 and the transmission signal of the test channels 26-2 to 26-m is logic 1, the reception signal of the test channel 24-1 is logic. 0, when the received signals of the test channels 24-2 to 24-n and 28-1 to 28-p = logic 1, short-circuit between the transmission-dedicated wiring 38-1 and the receivable wiring 35-1. It can be determined that a fault exists.
[0106]
As described above, when the inspection 3 is executed, the transmission dedicated wirings 38-1 to 38 -m of the test jig 20 and the receivable wirings 35-1 to 35 -n and 41-1 to 41 -p are connected. A short circuit fault can be detected.
[0107]
FIG. 21 is a flowchart showing the procedure of inspection 4 (inspection of power supply / ground short-circuit fault, disconnection fault, short-circuit fault between transmission-dedicated wirings and miswiring of transmission-dedicated wirings 38-1 to 38-m), and FIGS. FIG. 26 is a circuit diagram for explaining the inspection 4.
[0108]
When the test 4 is executed, the test channel 32 is set in the receiving state (step N4-1), and then the output of the power supply 30 is set to logic 0 (step N4-2), and the probe 47 is connected to the connection pins 39-1 to 39-1. Contact the designated connection pin in 39-m (step N4-3).
[0109]
Next, first to m-th pattern test signals as shown in Table 2 are sequentially transmitted from the test channels 26-1 to 26-m. That is, signals [0111 ... 1], [1011 ... 1], ... [1111 ... 0] are simultaneously transmitted from the test channels 26-1, 26-2, ... 26-m, respectively. (Step N4-4).
[0110]
Then, the logical value of the received signal of the test channel 32 is determined (step N4-5). Hereinafter, unless the inspection is terminated, Steps N4-3 to N4-5 are repeated while changing the connection pin with which the probe 47 is contacted.
[0111]
[Table 2]

[0112]
Here, when the first pattern to the m-th pattern as shown in Table 2 are sequentially transmitted from the test channels 26-1 to 26-m, the received signal of the test channel 32 is expected to the connection pin with which the probe 47 is contacted. In the case of the received signal, it can be determined that there is no power supply / ground short circuit failure, disconnection failure, short circuit failure between transmission dedicated wires, and miswiring in the transmission dedicated wiring contacted with the probe 47. it can.
[0113]
For example, as shown in FIG. 22, when the probe 47 is brought into contact with the connection pin 39-1, if the received signal of the test channel 32 is [0111. 1, it can be determined that there are no power supply / ground short-circuit fault, disconnection fault, short-circuit fault between transmission-dedicated wirings, and miswiring.
[0114]
On the other hand, when the received signal of the test channel 32 is a signal [0000... 0] in which all bits are logic 0, the dedicated transmission line connected to the connection pin with which the probe 47 is contacted. Can be determined to be short-circuited to the wiring 44 or the ground.
[0115]
For example, as shown in FIG. 23, when the probe 47 is brought into contact with the connection pin 39-1, if the received signal of the test channel 32 is [0000. Can be determined to have a power / ground short circuit fault.
[0116]
In addition, when the received signal of the test channel 32 is a signal [1111... 1] having all bits as logic 1, a disconnection failure occurs in the dedicated transmission line connected to the connection pin with which the probe 47 is contacted. Can be determined to exist.
[0117]
For example, as shown in FIG. 24, when the probe 47 is brought into contact with the connection pin 39-1, if the received signal of the test channel 32 = [1111. It can be determined that a disconnection fault exists.
[0118]
When the expected bit and the unexpected bit in the received signal of the test channel 32 include logic 0, the transmission-dedicated wiring connected to the connection pin with which the probe 47 is contacted is expected. It can be determined that there is a short-circuit failure with the transmission-dedicated wiring connected to the test channel that outputs a test signal including a logic 0 in the bit that is not set.
[0119]
For example, as shown in FIG. 25, when the probe 47 is brought into contact with the connection pin 39-1, if the reception signal of the test channel 32 = [0011... 1 and 38-2 can be determined to exist.
[0120]
When the received signal of the test channel 32 is a test signal transmitted from a test channel other than the test channel connected to the connection pin with which the probe 47 is contacted, the connection pin with which the probe 47 is contacted It can be determined that the dedicated transmission line connected to the transmission line and the dedicated transmission line connected to the test channel that transmitted the received test signal are miswired.
[0121]
For example, as shown in FIG. 26, when the probe 47 is brought into contact with the connection pin 39-1, if the received signal of the test channel 32 = [1011... , 38-2 can be determined to be miswired.
[0122]
As described above, when the inspection 4 is executed, the power / ground short-circuit fault, the disconnection fault, the short-circuit fault between the transmission-dedicated wirings and the miswiring of the transmission-dedicated wirings 38-1 to 38-m of the test jig 20 are detected. can do.
[0123]
Note that the inspection of the disconnection failure of the transmission-dedicated wirings 38-1 to 38-m can also be performed according to the procedure shown in FIG. That is, first, the test channel 32 is set in a reception state (step N5-1), and setting is made so that a transmission signal of logic 0 is transmitted from the test channels 26-1 to 26-m (step N5-2).
[0124]
Next, the probe 47 is brought into contact with the designated connection pin among the connection pins 39-1 to 39-m (step N5-3), and the logical value of the received signal of the test channel 32 is determined (step N5-4). ). Hereinafter, unless the inspection is terminated, Steps N5-3 and N5-4 are repeated while changing the connection pin with which the probe 47 is contacted.
[0125]
Here, when the received signal of the test channel 32 is logic 0, it can be determined that there is no disconnection failure in the dedicated transmission line connected to the connection pin with which the probe 47 is contacted.
[0126]
For example, as shown in FIG. 28, when the probe 47 is brought into contact with the connection pin 39-1, if the reception signal of the test channel 32 is logic 0, there is a disconnection failure in the transmission dedicated wiring 38-1. It can be determined not to.
[0127]
On the other hand, when the received signal of the test channel 32 is logic 1, it can be determined that a disconnection fault exists in the transmission dedicated wiring connected to the connection pin with which the probe 47 is contacted.
[0128]
For example, as shown in FIG. 29, when the probe 47 is brought into contact with the connection pin 39-1, if the reception signal of the test channel 32 is logic 1, there is a disconnection failure in the transmission dedicated wiring 38-1. It can be determined.
[0129]
As described above, the disconnection failure of the transmission-dedicated wirings 38-1 to 38-m can also be detected by executing the procedure shown in FIG.
[0130]
As shown in FIG. 30A, when the wirings 50 and 51 of the test jig 20 are provided with a driver (buffer) 52, the wiring 50 is connected to the test channel 53 that can be transmitted and received in the testing machine 22. When connected, the wiring 50 and 51 can be inspected as a transmission-only wiring by treating the test channel 53 that can be transmitted and received as a transmission-only test channel.
[0131]
On the other hand, as shown in FIG. 30B, when the wirings 54 and 55 of the test jig 20 are provided with a receiver (level conversion circuit) 56, the wiring 55 can be transmitted and received in the testing machine 22. When the test channel 57 is connected, the test channel 57 can be handled as a test channel that can be transmitted and received as it is, and the wires 54 and 55 can be inspected as receivable wires.
[0132]
As described above, according to one embodiment of the present invention, for the test jig 20, (1) Receivable wirings 35-1 to 35 -n, 41-1 to 41 -p, power supply / ground short circuit failure, 2) Receivable wiring 35-1 to 35-n, disconnection failure of 41-1 to 41-p, short-circuit failure and erroneous wiring between receivable wirings, and (3) reception dedicated wiring 38-1 to 38-m and reception Short circuit failure between possible wirings 35-1 to 35-n, 41-1 to 41-p, (4) Disconnection failure of transmission dedicated wirings 38-1 to 38-m, short circuit failure between transmission dedicated wirings and errors Since the wiring can be detected, it is possible to prevent a failure during the test of the device under test due to a defect in the test jig 20.
[0133]
Moreover, according to one embodiment of the present invention, since the inspection is performed using the testing machine 22 that uses the test jig 20, it is sufficient to facilitate the probe device 23, and a special wiring inspection such as a flying prober is sufficient. Does not require equipment.
[0134]
Further, since the test jig 20 is inspected using the wiring information of the test jig 20, the contact instruction of the probe 47 can be surely performed, and the test jig 20 can be prevented from being leaked. Inspection can be performed reliably. Further, since the contact instruction of the probe 47 is performed by the control computer 21, the test jig 20 can be easily inspected.
[0135]
In addition, since the test jig 20 can be inspected even when a test channel dedicated to transmission and a test channel dedicated to reception exist in the test machine 22, a buffer or receiver built in the test jig 20 can be used. Thus, the test jig 20 can be inspected even when the direction in which the test signal is transmitted and received is limited.
[0136]
In the embodiment of the present invention, the case where the operator handles the probe 47 has been described. However, an automatic prober may be used. The tool 20 can be inspected more easily.
[0137]
【The invention's effect】
As described above, according to the present invention, a test jig is mounted on a testing machine and the wiring of the testing jig is inspected by using the testing machine. Therefore, by using a control computer, a flying prober, etc. Thus, the wiring inspection of the test jig can be performed reliably and easily without the need for such a special wiring inspection device.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining an embodiment of the present invention.
FIG. 2 is a circuit diagram for explaining an embodiment of the present invention.
FIG. 3 is a flowchart schematically showing the contents of an embodiment of the present invention.
FIG. 4 is a diagram for explaining an embodiment of the present invention.
FIG. 5 is a diagram showing an example of wiring information used in an embodiment of the present invention.
FIG. 6 is a diagram showing a record format of each line used in an example of wiring information used in an embodiment of the present invention.
FIG. 7 is a diagram showing an example of a message for instructing a probe contact used in an embodiment of the present invention.
FIG. 8 is a diagram illustrating a notification example of a failure analysis result used in an embodiment of the present invention.
FIG. 9 is a flowchart showing a procedure of inspection 1 performed in an embodiment of the present invention.
FIG. 10 is a circuit diagram for explaining an inspection 1 performed in an embodiment of the present invention.
FIG. 11 is a circuit diagram for explaining an inspection 1 performed in an embodiment of the present invention.
FIG. 12 is a circuit diagram for explaining inspection 1 performed in an embodiment of the present invention.
FIG. 13 is a flowchart showing a procedure of inspection 2 performed in an embodiment of the present invention.
FIG. 14 is a circuit diagram for explaining inspection 2 performed in an embodiment of the present invention.
FIG. 15 is a circuit diagram for explaining inspection 2 performed in an embodiment of the present invention.
FIG. 16 is a circuit diagram for explaining inspection 2 performed in an embodiment of the present invention;
FIG. 17 is a circuit diagram for explaining inspection 2 performed in an embodiment of the present invention.
FIG. 18 is a flowchart showing a procedure of inspection 3 performed in an embodiment of the present invention.
FIG. 19 is a circuit diagram for explaining inspection 3 performed in an embodiment of the present invention.
FIG. 20 is a circuit diagram for explaining inspection 3 performed in an embodiment of the present invention.
FIG. 21 is a flowchart showing a procedure of inspection 4 performed in an embodiment of the present invention.
FIG. 22 is a circuit diagram for explaining inspection 4 performed in an embodiment of the present invention;
FIG. 23 is a circuit diagram for explaining inspection 4 performed in an embodiment of the present invention.
FIG. 24 is a circuit diagram for explaining inspection 4 performed in an embodiment of the present invention.
FIG. 25 is a circuit diagram for explaining inspection 4 performed in an embodiment of the present invention.
FIG. 26 is a circuit diagram for explaining inspection 4 performed in an embodiment of the present invention;
FIG. 27 is a flowchart showing another method for inspecting a disconnection fault of a transmission-only wiring of a test jig;
FIG. 28 is a circuit diagram for explaining another method of disconnection failure inspection of a transmission-dedicated wiring of a test jig.
FIG. 29 is a circuit diagram for explaining another method of disconnection failure inspection of a transmission-dedicated wiring of a test jig.
FIG. 30 is a circuit diagram for explaining an embodiment of the present invention.
FIG. 31 is a diagram showing a concept of a test jig for electrically connecting a tester and a device under test.
[Explanation of symbols]
24-1 to 24-n Test channels that can be sent and received
26-1 to 26-m Test channel dedicated for transmission
28-1 to 28-p Reception-only test channel
32 Test channels that can be sent and received

Claims (11)

A test for inspecting the wiring of a test jig that electrically connects a device under test having an electronic circuit and a test machine for testing the device under test by transmitting and receiving signals between the device under test. An inspection method for a jig,
Attaching the test jig to the test machine, and inspecting the wiring of the test jig using the test machine;
The step of inspecting the wiring of the test jig using the test machine,
During wiring of the test jig, a step of setting the potential of the wiring connected to the power source in the testing machine to a logical value capable of detecting a short-circuit failure;
A test jig inspection method comprising: determining a logical value of an output of a receivable test channel connected to a wiring of the test jig in a test channel in the test machine. When there is a transmission-only test channel connected to the wiring of the test jig in the test channel in the testing machine, the output state of the transmission-only test channel connected to the wiring of the testing jig Or setting the output of the transmission-dedicated test channel connected to the wiring of the test jig to a logic value opposite to the logic value capable of detecting the short-circuit fault. The test jig inspection method according to claim 1, wherein: When there is a test channel that can be sent and received that is connected to a wiring that is dedicated to transmission of the test jig in the test channel in the testing machine, the test channel that can be transmitted and received is used as a test channel dedicated to transmission. The test jig inspection method according to claim 1, wherein the test jig is handled. A test for inspecting the wiring of a test jig that electrically connects a device under test having an electronic circuit and a test machine for testing the device under test by transmitting and receiving signals between the device under test. An inspection method for a jig,
Attaching the test jig to the test machine, and inspecting the wiring of the test jig using the test machine;
The step of inspecting the wiring of the test jig using the test machine,
Of the connection pins of the test jig to the device under test, the connection pins connected to the receivable test channel in the testing machine are selected one by one, and a signal of a predetermined logic value is selected from the selected connection pin. Transmitting to the testing machine;
A test jig inspection method comprising: determining a logical value of an output of a receivable test channel connected to a wiring of the test jig in a test channel in the test machine. Of the connection pins of the test jig to the device under test, the connection pins connected to the receivable test channel in the testing machine are selected one by one, and a signal of a predetermined logic value is selected from the selected connection pin. The process of sending to the testing machine is
The test jig inspection method according to claim 4, wherein the test is performed from a probe-dedicated test channel in the testing machine via a probe. Of the connection pins of the test jig to the device under test, the connection pins connected to the receivable test channel in the testing machine are selected one by one, and a signal of a predetermined logic value is selected from the selected connection pin. The process of sending to the testing machine is
The test jig inspection method according to claim 4, wherein the inspection is performed from an empty test channel in the testing machine through a probe. A test for inspecting the wiring of a test jig that electrically connects a device under test having an electronic circuit and a test machine for testing the device under test by transmitting and receiving signals between the device under test. An inspection method for a jig,
Attaching the test jig to the test machine, and inspecting the wiring of the test jig using the test machine;
The step of inspecting the wiring of the test jig using the test machine,
From the test channels in the testing machine, one transmission-dedicated test channel connected to the test jig wiring is selected one by one, and a signal of a predetermined logic value is selected from the selected transmission-dedicated test channel to the test jig. A process of transmitting to the
A test jig inspection method comprising: determining a logical value of an output of a receivable test channel connected to a wiring of the test jig in a test channel in the test machine. A test for inspecting the wiring of a test jig that electrically connects a device under test having an electronic circuit and a test machine for testing the device under test by transmitting and receiving signals between the device under test. An inspection method for a jig,
Attaching the test jig to the test machine, and inspecting the wiring of the test jig using the test machine;
The step of inspecting the wiring of the test jig using the test machine,
A step of transmitting different parallel logic pattern signals from the plurality of test-dedicated test channels connected to the wiring of the test jig to the test jig in order one pattern at a time in the test channel in the test machine;
Determining a logical value of a signal output to a connection pin connected to a test channel dedicated to transmission in the test machine among connection pins of the test jig to the device under test. A method for inspecting test jigs. A test for inspecting the wiring of a test jig that electrically connects a device under test having an electronic circuit and a test machine for testing the device under test by transmitting and receiving signals between the device under test. An inspection method for a jig,
Attaching the test jig to the test machine, and inspecting the wiring of the test jig using the test machine;
The step of inspecting the wiring of the test jig using the test machine,
A step of transmitting a signal of a predetermined logical value to the test jig from a test-dedicated test channel connected to the wiring of the test jig among the test channels in the test machine;
Determining a logical value of a signal output to a connection pin connected to a test channel dedicated to transmission in the test machine among connection pins of the test jig to the device under test. A method for inspecting test jigs. A step of determining a logical value of a signal output to a connection pin connected to a test channel dedicated to transmission in the test machine among the connection pins of the test jig to the DUT,
Among the connection pins of the test jig to the device under test, a signal output to a connection pin connected to a test channel dedicated to transmission in the testing machine is sent via a probe to a probe dedicated test channel in the testing machine or The test jig inspection method according to claim 8, wherein the test jig is transmitted to an empty test channel. When there is a test channel that can be sent and received that is connected to a wiring that is dedicated to transmission of the test jig in the test channel in the testing machine, the test channel that can be transmitted and received is used as a test channel dedicated to transmission. The inspection method for a test jig according to claim 8, wherein the test jig is handled.

Images