JP3657702B2

JP3657702B2 - Liquid crystal display

Info

Publication number: JP3657702B2
Application number: JP20733696A
Authority: JP
Inventors: 良朗青木
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1996-08-06
Filing date: 1996-08-06
Publication date: 2005-06-08
Anticipated expiration: 2016-08-06
Also published as: JPH1048663A

Description

【０００１】
【発明の属する技術分野】
本発明は、アレイ基板上に駆動回路が組込まれたいわゆる駆動回路一体型の液晶表示装置に係り、特に、その駆動回路の構成に関する。
【０００２】
【従来の技術】
図１１に、いわゆる駆動回路一体型の液晶表示装置の一般的な構成図を示す。なお、図１１では、本願発明と従来技術との差異の理解を容易にするため、アレイ基板上における電源電圧配線１７、２０、グランド電圧配線１８、２１、及び補助容量線１９、１６の配置の状態に重点を置いて示してある。
【０００３】
信号線１４と走査線１５の各交差部には、各画素のスイッチング素子として用いられる薄膜トランジスタ（以下、ＴＦＴと記す）１１が形成され、ＴＦＴ（１１）のソース電極には画素電極１２が接続される。信号線１４からＴＦＴ（１１）を介して画素電極１２に供給された映像信号は、主として、画素電極１２と対向電極（図示せず）との間の容量、及び画素電極１２と補助容量線１６との間の補助容量１３に蓄積され、入力された映像信号に応じて、画素電極１２と対向電極の間に挟まれた液晶層が駆動される。その結果、入力された映像信号に対応して各画素により表示が行われる。
【０００４】
表示領域２２の周囲、即ちアレイ基板２７の周縁部には、各辺に沿って、信号線１４あるいは走査線１５に各種信号を供給するための信号線駆動回路２３、２４、及び走査線駆動回路２５、２６が形成される。各駆動回路は、更にアレイ基板２７の外部より、インターフェース部２８を経由してタイミング制御信号、映像信号、電源電圧、グランド電圧等の供給を受ける。なお、インターフェース部２８には、通常、ＯＬＢ（Outer Lead Bonding）が用いられる。
【０００５】
上記の様に、駆動回路一体型の液晶表示装置では、表示部２２の周囲のアレイ基板２７上に画素駆動用の回路を形成するため、駆動回路を構成する各素子の形成工程は、表示領域を構成するＴＦＴ、画素電極及び各種の配線等の形成と同時に行われるのが一般的である。
【０００６】
この様に、駆動回路と表示領域とがアレイ基板上に一体的に形成されるので、低コスト化及びコンパクト化には効果がある。その一方、全体の低コスト化を実現するためには、外部駆動方式の回路においては一般的な、多層配線あるいは鍍金による配線厚膜化などの様な配線の低抵抗化の手法は、製造工程の複雑化を避ける意味から採用することができない。このため、駆動回路一体型の液晶表示装置においては、低抵抗化された配線構造を駆動回路に採用することは、これまで十分には行われてはいなかった。特に、駆動回路を正常に動作させる上で重要な要因となる電源電圧配線及びグランド電圧配線を十分に低抵抗化することができないことは、駆動回路の高速化や、駆動回路の安定動作を妨げる一因となっていた。
【０００７】
以上の問題を解決する一般的方法として、配線幅の拡大による低抵抗化が挙げられる。この方法を用いることにより、配線幅の拡大に反比例して配線抵抗を減らすことが可能となり、製造工程の簡略化に伴う配線の高抵抗化をある程度補うことができる。しかしながら、この方法を用いた場合、駆動回路内における配線面積の占める割合が増大するので、駆動回路一体型液晶表示装置の特徴の一つであった表示装置のコンパクト化の効果が損なわれる。
【０００８】
また、上記の問題を解決する他の方法として、電源電圧配線１７、２０、及びグランド電圧配線１８、２１を、アレイ基板上の駆動回路領域内において部分的にオーバーラップさせることにより、駆動回路領域内の電源電圧配線とグランド電圧配線との間にバイパスコンデンサを形成する方法が挙げられる。この方法を用いることにより、配線幅を余り増大させずに、一体型駆動回路の安定動作を可能とすることができる。しかしながら、この方法を用いた場合、安定動作に十分なバイパスコンデンサの容量を確保するためには、電源電圧配線１７、２０とグランド電圧配線１８、２１のオーバーラップ面積を拡大するか、若しくはそれらの間隔を縮める方法が必要であり、その結果、駆動回路領域の面積の増大、あるいは電源電圧配線とグランド電圧配線との短絡不良の増加を招くなどの問題が生じていた。
【０００９】
また、上記の問題を解決する他の方法として、アレイ基板外部とのインターフェース２８に近いアレイ基板２７の外部で、電源電圧配線１７、２０とグランド電圧配線１８、２１の間にバイパスコンデンサを外部素子として付加する方法が挙げられる。この方法を用いることにより、バイパスコンデンサを駆動回路領域の内部に形成する場合に問題となっていた、駆動回路領域の面積の増大あるいは配線間の短絡不良の増加を防止することが可能となる。しかしながら、この方法を用いた場合でも、インターフェース部２８から遠くなるにつれて、配線における電圧降下がおこるため、駆動回路の安定動作を維持することが困難となっていた。
【００１０】
また、上記の問題を解決する他の方法として、アレイ基板外部とのインターフェース部をアレイ基板の周囲に多数形成する方法が挙げられる。この方法を用いることにより、電源電圧配線、グランド電圧配線の高抵抗化を防ぎ、駆動回路の安定動作が可能になる。しかしながら、この方法を用いた場合、インターフェース部の増加は、表示領域の周辺部の面積の拡大を招くため、表示装置のコンパクト化が困難になるなどの欠点を持っている。
【００１１】
また、これら全般に関わる問題として、画素の高精細化に伴う駆動回路の高速化や、表示装置のコンパクト化に伴う表示領域周辺部の更なる狭額縁化に、上記の方法のみでは対応することが困難になって来ていると言う問題がある。
【００１２】
例えば、狭額縁化を実現する手法の一つとして、アレイ基板外部とのインターフェース部を一箇所にまとめ、表示領域の周辺の駆動回路を片側のみに配置して、駆動回路部を含めた周辺領域の占有面積を従来のほぼ半分にする構成があるが（いわゆる片側駆動方式）、特に、この様な構成を採用した場合に、電源電圧及びグランド電圧を安定供給し、駆動回路の高速動作を維持することは容易ではない。
【００１３】
【発明が解決しようとする課題】
本発明は、以上の様な問題を解決するために成されたもので、本発明は、アレイ基板上に駆動回路が表示領域とともに一体的に形成された駆動回路一体型液晶表示装置において、製造工程の増加を伴うことなく、駆動回路に対して電源電圧及びグランド電圧を安定して供給する事が可能な駆動回路一体型液晶表示装置を提供することを目的とする
【００１４】
【課題を解決するための手段】
本発明の液晶表示装置は、
アレイ基板上に配列された複数の信号線と；信号線に直交して配列された複数の走査線と；信号線と走査線によりマトリクス状に区画される各領域に配置された画素電極と；信号線と走査線の各交点付近に形成され、ソースが画素電極に接続され、ドレインが信号線に接続され、ゲートが走査線に接続された薄膜トランジスタと；走査線と独立に配列され、画素電極に対して電気的に容量結合することにより補助容量を形成する補助容量線と；アレイ基板上に複数の辺に沿って配置され、走査線あるいは信号線を駆動する複数の駆動回路と；液晶層を介して画素電極に対向する対向電極が形成された対向基板と；を備えた液晶表示装置において、
前記アレイ基板上の一辺に沿って配置された第一の駆動回路の電源電圧配線と、前記アレイ基板上の他の一辺に沿って配置された第二の駆動回路の電源電圧配線とを、前記補助容量線を介して、互いに接続したことを特徴とする。
【００１５】
また、上記の構成に代って、上記の二つの駆動回路のグランド電圧配線を、前記補助容量線を介して互いに接続することもできる。
また、上記の構成に代って、上記の二つの駆動回路の電源電圧配線を補助容量線の一部（第一の補助容量線）を介して互いに接続するとともに、上記の二つのの駆動回路のグランド電圧配線を補助容量線の他の一部（第二の補助容量線）を介して互いに接続することもできる。
【００１６】
上記の様に、アレイ基板上の一辺に沿って配置された第一の駆動回路の電源電圧配線（あるいはグランド電圧配線）と、アレイ基板上の他の一辺に沿って配置された第二の駆動回路の電源電圧配線（あるいはグランド電圧配線）を、補助容量線を介して互いに接続することにより、駆動回路に電源電圧配線（あるいはグランド電圧）を安定供給する事が可能となり、アレイ基板上に表示領域ともに一体的に形成された駆動回路の安定動作が確保され、表示の高精細化、表示装置の狭額縁化などの要求に対応することが可能となる。
【００１７】
また、表示領域の周辺に、一対の信号線駆動回路及び一対の走査線駆動回路が、それぞれ配置される構成の場合、本発明の液晶表示装置は、
アレイ基板上に配列された複数の信号線と；信号線に直交して配列された複数の走査線と；信号線と走査線によりマトリクス状に区画される各領域に配置された画素電極と；信号線と走査線の各交点付近に形成され、ソースが画素電極に接続され、ドレインが信号線に接続され、ゲートが走査線に接続された薄膜トランジスタと；各走査線と平行に且つ各走査線と独立に配列され、画素電極に電気的に容量結合することにより補助容量を形成する補助容量線と；アレイ基板上の互いに対向する二つの辺に沿って配置された一対の信号線駆動回路と；アレイ基板上の互いに対向する他の二つの辺に沿って配置された一対の走査線駆動回路と；液晶層を介して画素電極に対向する対向電極が形成された対向基板と；を備えた液晶表示装置において、
前記一対の走査線駆動回路の電源電圧配線を、前記補助容量線を介して、互いに接続したことを特徴とする。
【００１８】
また、上記の構成に代って、前記一対の駆動回路のグランド電圧配線を、前記補助容量線を介して互いに接続することもできる。
また、上記の構成に代って、前記一対の駆動回路の電源電圧配線を前記補助容量線の一部（第一の補助容量線）を介して互いに接続するとともに、前記一対の駆動回路のグランド電圧配線を前記補助容量線の他の一部（第二の補助容量線）を介して互いに接続することもできる。なお、この様な構成の場合、第一の補助容量線と第二の補助容量線とを交互に配置することが望ましい。
【００１９】
上記の様に、アレイ基板上の互いに対向する二辺に沿って配置された一対の駆動回路の電源電圧配線（あるいはグランド電圧配線）を、補助容量線を用いて互いに接続することによって、駆動回路に電源電圧（あるいはグランド電圧）を安定供給する事が可能となり、アレイ基板上に表示領域ともに一体的に形成された駆動回路の安定動作が確保され、表示の高精細化、表示装置の狭額縁化などの要求に対応することが可能となる。
【００２０】
更に、電源電圧配線を互いに接続する補助容量線（第一の補助容量線）と、グランド電圧配線を互いに接続する補助容量線（第二の補助容量線）とを、表示領域内において交互に配列することによって、補助容量電位の異なる画素が混在することによって生じる光透過率変化の空間周波数が高くなるため、表示ムラが視認され難くなる。その結果、補助容量電位の相違に起因する表示ムラの発生を最小限に抑える事が可能となる。
【００２１】
また、いわゆる片側駆動方式の液晶表示装置の場合には、本発明の液晶表示装置は、
アレイ基板上に配列された複数の信号線と；信号線に直交して配列された複数の走査線と；信号線と走査線によりマトリクス状に区画される各領域に配置された画素電極と；信号線と走査線の各交点付近に形成され、ソースが画素電極に接続され、ドレインが信号線に接続され、ゲートが走査線に接続された薄膜トランジスタと；各走査線と平行に且つ各走査線と独立に配列され、画素電極に電気的に容量結合することにより補助容量を形成する補助容量線と；アレイ基板上の一辺に沿って配置された信号線駆動回路と；アレイ基板上の他の一辺に沿って配置された走査線駆動回路と；液晶層を介して画素電極に対向する対向電極が形成された対向基板と；を備えた液晶表示装置において、
前記信号線駆動回路の電源電圧配線と前記走査線駆動回路の電源電圧配線とを、前記補助容量線を介して、互いに接続したことを特徴とする。
【００２２】
この場合にも、先と同様に、上記の構成に代って、前記二つの駆動回路のグランド電圧配線を、前記補助容量線を介して互いに接続することもできる。また、前記二つの駆動回路の電源電圧配線を補助容量線の一部（第一の補助容量線）を介して互いに接続するとともに、前記二つの駆動回路のグランド電圧配線を補助容量線の他の一部（第二の補助容量線）を介して互いに接続することもできる。なお、この様な構成の場合にも、第一の補助容量線と第二の補助容量線とを交互に配置することが、望ましい。
【００２３】
即ち、信号線駆動回路の電源電圧配線（あるいはグランド電圧配線）と、走査線駆動回路の電源電圧配線（あるいはグランド電圧配線）とを、補助容量線を介して互いに接続することによって、それぞれの駆動回路に電源電圧（あるいはグランド電圧）を安定供給する事が可能となり、同様の効果を得ることができる。
【００２４】
更に、この様な片側駆動方式の液晶表示装置の場合には、
信号線駆動回路の電源電圧配線と走査線駆動回路の電源電圧配線とを、信号線駆動回路と走査線駆動回路が互いに隣接するアレイ基板上の角部付近で互いに接続するとともに、アレイ基板の縁に沿って、前記信号線駆動回路が配置された辺の対辺、及び前記走査線駆動回路が配置された辺の対辺を通る電源電圧配線を設けて、この電源電圧配線を介して互いに接続し、更に、信号線駆動回路のグランド電圧配線と走査線駆動回路のグランド電圧配線とを、アレイ基板上の前記角部付近で互いに接続するとともに、アレイ基板の縁に沿って、前記信号線駆動回路が配置された辺の対辺、及び前記走査線駆動回路が配置された辺の対辺を通るグランド電圧配線を設けて、このグランド電圧配線を介して互いに接続する。
【００２５】
上記の構成の場合、駆動回路が配置されていないアレイ基板の縁に沿って、電源電圧配線及びグランド電圧配線を設けることによって、それぞれの駆動回路に電源電圧及びグランド電圧を安定的に供給することができ、片側駆動方式の液晶表示装置において、表示品質を向上させる効果がある。
【００２６】
【発明の実施の形態】
本発明の実施の形態を図面に基いて詳細に説明する。
（例１）
図１は、本発明に基く駆動回路一体型の液晶表示装置の一例を示す回路構成図である。図中、２２は表示領域、２３、２４は信号線駆動回路、２５、２６は走査線駆動回路、２８はアレイ基板の外部とのインターフェース部、１７、２０ａは電源電圧配線、１８、２１ａはグランド電圧配線、１４は信号線、１５は走査線、１６は補助容量線、１１はＴＦＴ（画素ＴＦＴ）、１２は画素電極、１３は補助容量を表す。
【００２７】
図１に示す様に、アレイ基板２７の中央部には表示領域２２が形成され、表示領域２２の周囲に当るアレイ基板２７の周縁部には、上下一対の信号線駆動回路２３、２４、及び左右一対の走査線駆動回路２５、２６がそれぞれ形成される。信号線１４と走査線１５の各交差部にはＴＦＴ（１１）が形成され、ＴＦＴ（１１）のゲート電極には走査線１５が、ドレイン電極には信号線１４が、ソース電極には画素電極１２がそれぞれ接続される。また、画素電極１２と補助容量線１６との間で補助容量１３が形成されている。
【００２８】
更に、この例では、左右一対の走査線駆動回路２５、２６の電源電圧配線２０ａが、各走査線１５と平行に表示領域内に配列された補助容量線１６を介して、互いに接続されている。
【００２９】
この結果、走査線駆動回路２６は、アレイ基板２７の外部からインターフェース２８を経由して供給される経路に加えて、補助容量線１６を経由して表示領域を挟んでアレイ基板の反対側の位置する走査線駆動回路２４からも電源電圧を供給される形となる。
【００３０】
この様な構成をとることにより、駆動回路２６、２６内の電源電圧配線２０ａの幅を拡大すること無く、電源電圧をアレイ基板の外部から走査線駆動回路に安定的に供給することが可能になり、従来の構成（図１１）と比較して、走査線駆動回路の動作をより確実なものとすることができる。
【００３１】
次に、図１に示した駆動回路一体型の液晶表示装置の製造プロセスについて説明する。図２は、上記の駆動回路一体型の液晶表示装置の断面構造の概要を示す断面図である。
【００３２】
先ず、ガラス基板６１の上にプラズマＣＶＤ法、常圧ＣＶＤ法等を用いて、窒化シリコン、酸化シリコン等の絶縁性のアンダーコート膜６３を形成する。次に、プラズマＣＶＤ法により第一のアモルファスシリコン層（遮光層）６４を形成した後、加熱工程により膜中の水素を低減させる。
【００３３】
次に、窒化シリコンから成る絶縁層６５を形成し、その上に第二のアモルファスシリコン層６６をプラズマＣＶＤ法によって形成し、更に脱水素化の工程を経た後、エキシマレーザを用いてアニールして、第二のアモルファスシリコン層６６をポリシリコン化する。以上の工程で形成されたポリシリコン膜は、フォトエッチングプロセスを経ることによりパターニングされ、駆動回路領域の能動素子（回路ＴＦＴ）９２、９３のチャネル層７１ｂ、７４、表示領域内の画素のスイッチング素子９１（画素ＴＦＴ）のチャネル層７１、及び各画素の補助容量電極の下部電極７２などが形成される。
【００３４】
次に、常圧ＣＶＤ法により、ゲート絶縁膜６７、並びに補助容量の絶縁膜６７ｂとなる酸化シリコン層が形成される。この酸化シリコン層は高温加熱工程を経ることにより、欠陥の少ない緻密な膜となる。
【００３５】
次に、スパッタ法により、第一のＭｏＷ薄膜（モリブデン・タングステン薄膜）６８が形成される。このＭｏＷ薄膜６８は、フォトエッチングプロセスを経てパターニングされ、ｎ型ＴＦＴ（９１、９２）、及び補助容量の下部電極７２を形成するためのイオンドーピングによる不純物注入のマスクとなる。更に、同じくスパッタ法により、第二のＭｏＷ薄膜６９が形成され、パターニングされた後、駆動回路領域のｐ型ＴＦＴ（９３）を形成するための不純物注入のマスクとなる。上記の工程の後、第一のＭｏＷ薄膜６８及び第二のＭｏＷ薄膜６９は、再度パターニングされ、各ＴＦＴのゲート電極、駆動回路内の各種配線、補助容量電極の上部電極７０及び補助容量線（１６；図１）を形成する。その後、更にｎ型ＬＤＤ（Lightly Doped Drain)７３を形成するための不純物注入を行い、更に、基板を高温工程にてアニールすることにより注入不純物を活性化する。
【００３６】
次に、常圧ＣＶＤ法によって第一の層間絶縁膜となる酸化シリコン層７５を形成し、コンタクトホールを加工した後、スパッタ法によりアルミ薄膜を形成する。アルミ薄膜はフォトエッチングプロセスを経てパターニングされ、ＴＦＴのソース電極７７、ドレイン電極７６、信号線（１４；図１）、駆動回路領域の電源電圧配線４１及びグランド電圧配線４０などの各種の配線が形成される。更に、プラズマＣＶＤ法によって第二の層間絶縁膜８１となる窒化シリコン層を形成し、コンタクトホールを加工した後、スパッタ法により透明電極であるＩＴＯ膜を形成する。ＩＴＯ膜はパターニングされて画素電極３８になる。
【００３７】
一方、対向基板側のガラス基板６２には、ブラックマトリクス４５、カラーフィルタ４７、４８、及びそれらの上にＩＴＯからなる透明電極である対向電極４３が形成される。
【００３８】
以上の工程を経てアレイ基板及び対向基板を作成した後、それらの対向面に、液晶の配向制御を行うポリイミド配向膜（３９ａ、３９ｂ）を成膜して、両基板の表面の配向処理を行う。両基板をその周縁部近傍の貼り合わせシール領域４６において貼り合わせた後、両基板間に液晶４４を封入することにより、液晶セルが作成される。更に、液晶セルは、ＯＬＢ（Outer Lead Bonding）等を用いてインターフェースを介して外部と接続される。
【００３９】
以上の様にして、駆動回路一体型の液晶表示装置が形成される。以上の工程において、駆動回路部のＴＦＴ（９２、９３）及び配線４０、４１等は、表示領域部のＴＦＴ（９１）及び配線６９、７０、７６、７７等と同一の工程で形成される。なお、補助容量電極の上部電極７０及び補助容量線（１６；図１）はゲート電極を構成する金属薄膜層６８、６９の一部と同一のプロセスで形成され、第一の層間絶縁膜７５に形成されたスルーホールを介して、駆動回路部の電源電圧配線４１（２０ａ；図１）に接続される。
【００４０】
（例２）
図３は、本発明に基く駆動回路一体型の液晶表示装置の第二の例を示す回路構成図である。図中、２０ｂは走査線駆動回路の電源電圧配線、２１ｂは走査線駆動回路のグランド電圧配線、１６ｂは補助容量線を表す。その他の構成については、第一の例に示した駆動回路一体型の液晶表示装置（図１）と同一であるので、同一の部分には同一の符号を付して、その説明を省略する。
【００４１】
図に示す様に、この例では、左右一対の走査線駆動回路２５、２６のグランド電圧配線２１ｂが、各走査線１５と平行に表示領域内に配列された補助容量線１６ｂを介して、互いに接続される。この結果、走査線駆動回路２６は、アレイ基板２７の外部からインターフェース２８を経由して供給される経路に加えて、補助容量線１６ｂを経由して表示領域を挟んでアレイ基板２７の反対側の位置する走査線駆動回路２５からもグランド電圧を供給される形となる。
【００４２】
この様な構成をとることにより、走査線駆動回路２５、２６内のグランド電圧配線２１ｂの幅を拡大すること無く、グランド電圧をアレイ基板２７の外部から走査線駆動回路に安定的に供給することが可能になり、従来の構成（図１１）と比較して、走査線駆動回路の動作をより確実なものとすることができる。
【００４３】
（例３）
図４は、本発明に基く駆動回路一体型の液晶表示装置の第三の例を示す回路構成図である。図中、２０ｃは走査線駆動回路の電源電圧配線、２１ｃは走査線駆動回路のグランド電圧配線、１６ｃ及び１６ｄは補助容量線を表す。その他の構成については、第一あるいは第二の例に示した駆動回路一体型の液晶表示装置（図１、図２）と同一である。
【００４４】
図に示す様に、この例では、左右一対の走査線駆動回路２５、２６の電源電圧配線２０ｃが各走査線１５と平行に表示領域内に配列された一部の補助容量線１６ｃ（第一の補助容量線）を介して互いに接続されるとともに、グランド電圧配線２１ｃが他の一部の補助容量線１６ｄ（第二の補助容量線）を介して互いに接続される。この結果、走査線駆動回路２６は、アレイ基板２７の外部からインターフェース２８を経由して供給される経路に加えて、補助容量線１６ｃ、１６ｄを経由して表示領域２２を挟んでアレイ基板２７の反対側の位置する走査線駆動回路２５からも、電源電圧及びグランド電圧を供給される形となる。
【００４５】
この様な構成をとることにより、駆動回路２５、２６内の電源電圧配線２０ｃ及びグランド電圧配線２１ｃの幅を拡大すること無く、電源電圧及びグランド電圧をアレイ基板２７の外部から走査線駆動回路２５、２６に安定的に供給することが可能になり、従来の構成（図１１）と比較して、走査線駆動回路の動作をより確実なものとすることができる。
【００４６】
（例４）
図５は、本発明に基く駆動回路一体型の液晶表示装置の第四の例を示す回路構成図である。図中、２０ｄは走査線駆動回路の電源電圧配線、２１ｄは走査線駆動回路のグランド電圧配線、１６ｅ、１６ｆは補助容量線を表す。その他の構成については、第三の例に示した駆動回路一体型の液晶表示装置（図４）と同一である。
【００４７】
図に示す様に、第三の例と同様に、左右一対の走査線駆動回路２５、２６の電源電圧配線２０ｄ及びグランド電圧配線２１ｄが、補助容量線１６ｅ、１６ｆを介してそれぞれ互いに接続されている。これに加えて、この例においては、電源電圧配線２０ｄを互いに接続する補助容量線１６ｅ（第一の補助容量線）と、グランド電圧配線２１ｄを互いに接続する補助容量線１６ｆ（第二の補助容量線）とが、表示領域内において交互に各走査線１５と平行に配列されている。この様な構成をとることによって、第三の例と同様に、電源電圧及びグランド電圧をアレイ基板２７の外部から走査線駆動回路２５、２６に安定的に供給することが可能になることに加えて、補助容量電位の異なる画素が混在することによって生じる光透過率変化の空間周波数が高くなるため、表示ムラが視認され難くなる。その結果、補助容量電位の相違に起因する表示ムラの発生を最小限に抑える事が可能となる。
【００４８】
（例５）
図６は、本発明に基く駆動回路一体型液晶表示装置の第五の例を示す回路構成図である。図中、１７ｅは信号線駆動回路の電源電圧配線、１８ｅは信号線駆動回路のグランド電圧配線、２０ｅは走査線駆動回路の電源電圧配線、２１ｅは走査線駆動回路のグランド電圧配線を表す。その他の構成については、第四の例に示した駆動回路一体型の液晶表示装置（図５）と同一である。
【００４９】
図に示す様に、第四の例と同様に、電源電圧配線２０ｅを互いに接続する補助容量線１６ｅ（第一の補助容量線）と、グランド電圧配線２１ｅを互いに接続する補助容量線１６ｆ（第二の補助容量線）とが、表示領域内において各走査線１５と平行に交互に配置されている。これに加えて、この例においては、アレイ基板の角部付近の、走査線駆動回路と信号線駆動回路が互いに隣接する部分で、走査線駆動回路の電源電圧配線２０ｅが信号線駆動回路の電源電圧配線１７ｅに、走査線駆動回路のグランド電圧配線２１ｅが信号線駆動回路のグランド電圧配線１８ｅに、それぞれ接続されている。
【００５０】
この様な構成をとることによって、従来の構成と比較して走査線駆動回路の動作を確実なものとすることができるだけでなく、信号線駆動回路の動作についても、より確実なものとする事が可能となる。
【００５１】
（例６）
図７は、本発明に基く駆動回路一体型の液晶表示装置の第六の例を示す回路構成図である。図に示す様に、外部とのインターフェース部２８ｆが一箇所のみとなっている。その他の構成については、第五の例に示した駆動回路一体型の液晶表示装置（図６）と同一である。
【００５２】
この様な構成をとることによって、従来の構成に比較して、アレイ基板上に一体形成された駆動回路の動作を、より確実なものとする事ができるだけでなく、液晶表示装置の小型化が可能となる。
【００５３】
（例７）
図８は、本発明に基く駆動回路一体型の液晶表示装置の第七の例を示す回路構成図である。
【００５４】
図に示す様に、この例では、信号線１４及び走査線１５は共に片側駆動となっている。即ち、アレイ基板２７上の一辺（図では上辺側）に沿って信号線駆動回路２３ｇが形成され、これに隣接する他の一辺（図では左辺側）に沿って、走査線駆動回路２６ｇが形成される。一方、信号線駆動回路２３ｇが形成されている辺の対辺側（図では下辺側）には、信号線駆動回路に代って、電源電圧配線１７ｈ及びグランド電圧配線１８ｈのみが配置され、走査線駆動回路２６ｇが形成されている辺の対辺側（図では右辺側）には、走査線駆動回路に代って、電源電圧配線２０ｈ及びグランド電圧配線２１ｈのみが配置される。各電源電圧配線２０ｇ、１７ｈ、１７ｇ、２０ｈは順に接続され、同様に、各グランド電圧配線２１ｇ、１８ｈ、１８ｇ、２１ｈは順に接続され、アレイ基板２７の周縁部に沿ってそれぞれ閉回路を構成している。その他の構成については、第六の例に示した駆動回路一体型の液晶表示装置（図７）と同一である。なお、第六の例と同様に、外部とのインターフェース部２８ｆは一箇所のみとなっている。
【００５５】
この様な構成をとることによって、片側駆動方式の液晶表示装置においても、アレイ基板上に一体形成された駆動回路の動作をより確実なものとする事ができるので、液晶表示装置の一層の小型化が可能となる。
【００５６】
（例８）
図９は、本発明に基く駆動回路一体型の液晶表示装置の第九の例を示す断面構成図である。この例では、第一の例（図２）と異なり、画素電極３８と信号線７６との間の層間絶縁膜８２として、低誘電率の有機保護膜を用いると共に、図に示す様に、対向基板６２側にブラックマトリクス（４５（図２））が設けられていない。
【００５７】
この様に、層間絶縁膜８２として低誘電率の有機保護膜を用いることによって、画素電極３８と他の配線との間の電界のやりとりが低減されるため、従来の構成に比較して画素電極の周辺部でのエッジリバースの発生を低減することが可能となり、対向基板にブラックマトリクスを形成する必要がなくなる。従って、液晶表示装置の開口率を確保しつつ、補助容量の電位が表示に与える影響を最小限に抑えることが可能となる。
【００５８】
（例９）
図１０は、本発明に基く駆動回路一体型の液晶表示装置の第九の例を示す断面構成図である。この例では、図に示す様に、第一の例（図２）と異なり、対向基板６２側にはカラーフィルタ（４７、４８；図２）を配置せず、これに代って、画素電極３８とドレイン電極７６（信号線）との間の層間絶縁膜として、カラーレジスト４９、５０を使用している。
【００５９】
この様な構成をとることによって、対向基板にカラーフィルタを形成する必要が無くなるため、第一の例（図２）あるいは第八の例（図９）に示した構造と比較して、更に低コスト化が可能になる。
【００６０】
なお、本発明は上記の各例のみに限定されるものではない。例えば、アレイ基板上の駆動回路が、上記の例に示した製造工程とは異なる工程を経て形成されたものでも構わず、駆動回路内の能動素子がｎ型、もしくはｐ型のＴＦＴのみによって構成されていても構わない。また、アレイ基板の外部より電源電圧もしくはグランド電圧の供給を受ける方式を取る構成であるならば、駆動回路の一部がＴＡＢＩＣやＣＯＧ等を用いてアレイ基板外部の素子によって構成されていても、上記の例の場合と同様の効果を得ることができる。
【００６１】
【発明の効果】
以上、説明した様に、駆動回路一体型の液晶表示装置において、アレイ基板上の異なる二辺に沿って配置された複数の駆動回路の電源電圧配線あるいはグランド電圧配線を、補助容量線を用いて互いに接続することによって、駆動回路の安定動作が可能となり、回路の高速化、表示の高精細化、液晶表示装置のコンパクト化等の要求に対応することが可能となる。
【００６２】
また、上記の構成の場合、従来の駆動回路一体型の液晶表示装置の製造工程に新たな工程を付け加える必要が無いので、製造コストの増加の要因とはならない。
【図面の簡単な説明】
【図１】本発明に基く駆動回路一体型液晶表示装置の第一の例を示す回路構成図。
【図２】図１の駆動回路一体型液晶表示装置の断面構造の概要を示す断面図。
【図３】本発明に基く駆動回路一体型液晶表示装置の第二の例を示す回路構成図。
【図４】本発明に基く駆動回路一体型液晶表示装置の第三の例を示す回路構成図。
【図５】本発明に基く駆動回路一体型液晶表示装置の第四の例を示す回路構成図。
【図６】本発明に基く駆動回路一体型液晶表示装置の第五の例を示す回路構成図。
【図７】本発明に基く駆動回路一体型液晶表示装置の第六の例を示す回路構成図。
【図８】本発明に基く駆動回路一体型液晶表示装置の第七の例を示す回路構成図。
【図９】本発明に基く駆動回路一体型液晶表示装置の第八の例を示す断面構成図。
【図１０】本発明に基く駆動回路一体型液晶表示装置の第九の例を示す断面構成図。
【図１１】従来の駆動回路一体型液晶表示装置の一例を示す回路構成図。
【符号の説明】
１１・・・ＴＦＴ（画素ＴＦＴ）、
１２・・・画素電極、
１３・・・補助容量、
１４・・・信号線、
１５・・・走査線、
１６、１６ａ、１６ｂ・・・補助容量線、
１６ｃ、１６ｅ・・・第一の補助容量線
１６ｄ、１６ｆ・・・第二の補助容量線
１７・・・信号線駆動回路用の電源電圧配線、
１８・・・信号線駆動回路用のグランド電圧配線、
１９・・・補助容量線、
２０、２０ａ〜ｈ・・・走査線駆動回路用の電源電圧配線、
２１、２１ａ〜ｈ・・・走査線駆動回路用のグランド電圧配線、
２２・・・表示領域、
２３、２４・・・信号線駆動回路、
２５、２６・・・走査線駆動回路、
２７・・・アレイ基板、
２８、２８ｆ・・・インターフェース部、
３８・・・画素電極（ＩＴＯ薄膜）、
３９ａ、３９ｂ・・・ポリイミド配向膜、
４０・・・グランド電圧配線、
４１・・・電源電圧配線、
４３・・・対向電極（ＩＴＯ薄膜）、
４４・・・液晶層、
４５・・・ブラックマトリクス、
４６・・・貼り合わせシール領域、
４７、４８・・・カラーフィルタ、
４９、５０・・・カラーレジスト、
６１・・・ガラス基板（アレイ基板側）、
６２・・・ガラス基板（対向基板側）、
６３・・・アンダーコート膜、
６４・・・遮光層（第一のアモルファスシリコン層）、
６５・・・絶縁膜（窒化シリコン層）、
６６・・・ポリシリコン活性層、
６７・・・ゲート絶縁膜、
６８・・・ゲート電極（第一のＭｏＷ薄膜）、
６９・・・ゲート電極（第二のＭｏＷ薄膜）、
７０・・・補助容量電極の上部電極（第二のＭｏＷ薄膜）、
７１、７１ｂ・・・チャネル領域（ｎ型ポリシリコン領域）、
７２・・・補助容量電極の下部電極（ｎ型ポリシリコン領域）、
７３・・・ライトドープｎ型ポリシリコン領域、
７４・・・チャネル領域（ｐ型ポリシリコン領域）、
７５・・・第一の層間絶縁膜（酸化シリコン層）、
７６・・・ドレイン電極（アルミ薄膜）、
７７・・・ソース電極（アルミ薄膜）、
８１・・・第二の層間絶縁膜（窒化シリコン層）、
８２・・・第二の層間絶縁膜（低誘電率有機薄膜層）、
９１・・・画素ＴＦＴ、
９２・・・回路ＴＦＴ（ｎ型ＴＦＴ）、
９３・・・回路ＴＦＴ（ｐ型ＴＦＴ）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a so-called drive circuit integrated liquid crystal display device in which a drive circuit is incorporated on an array substrate, and more particularly to the configuration of the drive circuit.
[0002]
[Prior art]
FIG. 11 shows a general configuration diagram of a so-called drive circuit integrated liquid crystal display device. In FIG. 11, in order to facilitate understanding of the difference between the present invention and the prior art, the arrangement of the power supply voltage wirings 17 and 20, the ground voltage wirings 18 and 21 and the auxiliary capacitance lines 19 and 16 on the array substrate is shown. Shown with emphasis on condition.
[0003]
A thin film transistor (hereinafter referred to as TFT) 11 used as a switching element of each pixel is formed at each intersection of the signal line 14 and the scanning line 15, and a pixel electrode 12 is connected to a source electrode of the TFT (11). The The video signal supplied from the signal line 14 to the pixel electrode 12 via the TFT (11) mainly includes the capacitance between the pixel electrode 12 and the counter electrode (not shown), and the pixel electrode 12 and the auxiliary capacitance line 16. The liquid crystal layer sandwiched between the pixel electrode 12 and the counter electrode is driven according to the input video signal. As a result, display is performed by each pixel corresponding to the input video signal.
[0004]
Signal line drive circuits 23 and 24 for supplying various signals to the signal lines 14 or the scan lines 15 along the respective sides around the display area 22, that is, the peripheral edge of the array substrate 27, and the scan line drive circuits. 25 and 26 are formed. Each drive circuit further receives a timing control signal, a video signal, a power supply voltage, a ground voltage, and the like from the outside of the array substrate 27 via the interface unit 28. Note that OLB (Outer Lead Bonding) is usually used for the interface unit 28.
[0005]
As described above, in the driving circuit integrated liquid crystal display device, a pixel driving circuit is formed on the array substrate 27 around the display unit 22. It is generally performed at the same time as the formation of TFTs, pixel electrodes, various wirings, and the like constituting the.
[0006]
As described above, since the drive circuit and the display area are integrally formed on the array substrate, it is effective for cost reduction and compactness. On the other hand, in order to reduce the overall cost, a method for reducing the resistance of wiring, such as multilayer wiring or wiring thickening by plating, which is common in externally driven circuits, is used in the manufacturing process. It cannot be adopted in the sense of avoiding complications. For this reason, in a drive circuit integrated liquid crystal display device, the use of a wiring structure with reduced resistance in the drive circuit has not been sufficiently performed so far. In particular, the inability to sufficiently reduce the resistance of the power supply voltage wiring and the ground voltage wiring, which are important factors for the normal operation of the driving circuit, hinders the speeding up of the driving circuit and the stable operation of the driving circuit. It was a factor.
[0007]
As a general method for solving the above problems, there is a reduction in resistance by increasing the wiring width. By using this method, it becomes possible to reduce the wiring resistance in inverse proportion to the expansion of the wiring width, and it is possible to compensate to some extent the high resistance of the wiring accompanying the simplification of the manufacturing process. However, when this method is used, since the proportion of the wiring area in the drive circuit increases, the effect of downsizing the display device, which is one of the features of the drive circuit integrated liquid crystal display device, is impaired.
[0008]
Further, as another method for solving the above problem, the power supply voltage wirings 17 and 20 and the ground voltage wirings 18 and 21 are partially overlapped in the driving circuit region on the array substrate. For example, a bypass capacitor may be formed between the power supply voltage wiring and the ground voltage wiring. By using this method, it is possible to enable a stable operation of the integrated drive circuit without significantly increasing the wiring width. However, when this method is used, in order to ensure the capacity of the bypass capacitor sufficient for stable operation, the overlap area of the power supply voltage wirings 17 and 20 and the ground voltage wirings 18 and 21 is increased, or their A method for reducing the interval is necessary, and as a result, problems such as an increase in the area of the drive circuit region or an increase in short-circuit failure between the power supply voltage wiring and the ground voltage wiring have occurred.
[0009]
As another method for solving the above problem, a bypass capacitor is provided between the power supply voltage wirings 17 and 20 and the ground voltage wirings 18 and 21 outside the array substrate 27 close to the interface 28 with the outside of the array substrate. The method of adding is mentioned. By using this method, it is possible to prevent an increase in the area of the drive circuit region or an increase in short-circuit failure between wirings, which has been a problem when the bypass capacitor is formed inside the drive circuit region. However, even when this method is used, a voltage drop in the wiring occurs as the distance from the interface unit 28 increases, making it difficult to maintain a stable operation of the drive circuit.
[0010]
Another method for solving the above problem is a method of forming a large number of interface portions with the outside of the array substrate around the array substrate. By using this method, the resistance of the power supply voltage wiring and the ground voltage wiring can be prevented from being increased, and the driving circuit can be stably operated. However, when this method is used, an increase in the interface portion causes an increase in the area of the peripheral portion of the display region, and thus there is a drawback that it is difficult to make the display device compact.
[0011]
In addition, as a general problem, the above method alone can cope with the speeding up of the drive circuit accompanying the higher definition of pixels and the further narrowing of the peripheral area of the display area due to the compact display device. There is a problem that is becoming difficult.
[0012]
For example, as one of the methods for realizing a narrow frame, the interface part with the outside of the array substrate is gathered in one place, the drive circuit around the display area is arranged only on one side, and the peripheral area including the drive circuit part There is a configuration that occupies almost half of the area occupied by conventional devices (so-called one-side drive method). Especially when such a configuration is adopted, the power supply voltage and the ground voltage are stably supplied, and the high-speed operation of the drive circuit is maintained. It is not easy to do.
[0013]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems. The present invention provides a drive circuit integrated liquid crystal display device in which a drive circuit is integrally formed with a display area on an array substrate. An object is to provide a drive circuit integrated liquid crystal display device capable of stably supplying a power supply voltage and a ground voltage to a drive circuit without increasing the number of steps.
[0014]
[Means for Solving the Problems]
The liquid crystal display device of the present invention is
A plurality of signal lines arranged on the array substrate; a plurality of scanning lines arranged orthogonally to the signal lines; a pixel electrode arranged in each region partitioned in a matrix by the signal lines and the scanning lines; A thin film transistor formed near each intersection of a signal line and a scanning line, having a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line; and a pixel electrode arranged independently of the scanning line An auxiliary capacitance line that forms an auxiliary capacitance by being electrically capacitively coupled to the substrate; a plurality of drive circuits that are arranged on the array substrate along a plurality of sides and that drive scanning lines or signal lines; and a liquid crystal layer A liquid crystal display device comprising: a counter substrate on which a counter electrode facing the pixel electrode is formed via
The power supply voltage wiring of the first drive circuit arranged along one side on the array substrate, and the power supply voltage wiring of the second drive circuit arranged along the other side on the array substrate, It is characterized by being connected to each other via an auxiliary capacitance line.
[0015]
Further, instead of the above configuration, the ground voltage wirings of the two drive circuits can be connected to each other through the auxiliary capacitance line.
Further, instead of the above configuration, the power supply voltage wirings of the two drive circuits are connected to each other via a part of the auxiliary capacitance line (first auxiliary capacitance line), and the two drive circuits described above are connected. These ground voltage wirings can be connected to each other via another part of the auxiliary capacitance line (second auxiliary capacitance line).
[0016]
As described above, the power supply voltage wiring (or ground voltage wiring) of the first drive circuit arranged along one side on the array substrate and the second drive arranged along the other side on the array substrate. By connecting the power supply voltage wiring (or ground voltage wiring) of the circuit to each other via the auxiliary capacitance line, it is possible to stably supply the power supply voltage wiring (or ground voltage) to the drive circuit and display it on the array substrate. A stable operation of the drive circuit formed integrally in each region is ensured, and it becomes possible to meet demands such as higher definition of display and narrower frame of the display device.
[0017]
In the case where a pair of signal line driving circuits and a pair of scanning line driving circuits are arranged around the display area, the liquid crystal display device of the present invention
A plurality of signal lines arranged on the array substrate; a plurality of scanning lines arranged orthogonally to the signal lines; a pixel electrode arranged in each region partitioned in a matrix by the signal lines and the scanning lines; A thin film transistor formed near each intersection of a signal line and a scanning line, having a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line; parallel to each scanning line and each scanning line And an auxiliary capacitance line that forms an auxiliary capacitance by capacitively coupling to the pixel electrode, and a pair of signal line driving circuits arranged along two opposite sides on the array substrate; A pair of scanning line driving circuits arranged along two other sides facing each other on the array substrate; and a counter substrate on which a counter electrode facing the pixel electrode is formed via a liquid crystal layer. In liquid crystal display devices
The power supply voltage wirings of the pair of scanning line driving circuits are connected to each other through the auxiliary capacitance line.
[0018]
Further, instead of the above configuration, the ground voltage wirings of the pair of drive circuits can be connected to each other via the auxiliary capacitance line.
Further, instead of the above configuration, the power supply voltage wirings of the pair of drive circuits are connected to each other via a part of the auxiliary capacitance line (first auxiliary capacitance line), and the ground of the pair of drive circuits The voltage wirings can also be connected to each other via another part (second auxiliary capacity line) of the auxiliary capacity line. In the case of such a configuration, it is desirable to arrange the first auxiliary capacitance line and the second auxiliary capacitance line alternately.
[0019]
As described above, by connecting the power supply voltage wirings (or ground voltage wirings) of a pair of driving circuits arranged along two opposite sides on the array substrate to each other using the auxiliary capacitance lines, the driving circuit The power supply voltage (or ground voltage) can be stably supplied to the display circuit, and the stable operation of the drive circuit integrally formed with the display area on the array substrate is ensured. It is possible to meet demands such as
[0020]
Further, auxiliary capacitance lines (first auxiliary capacitance lines) for connecting power supply voltage lines to each other and auxiliary capacitance lines (second auxiliary capacitance lines) for connecting ground voltage lines to each other are alternately arranged in the display area. As a result, the spatial frequency of the change in light transmittance caused by the mixture of pixels with different storage capacitor potentials is increased, and thus display unevenness is difficult to be visually recognized. As a result, it is possible to minimize the occurrence of display unevenness due to the difference in storage capacitor potential.
[0021]
In the case of a so-called single-sided liquid crystal display device, the liquid crystal display device of the present invention is
A plurality of signal lines arranged on the array substrate; a plurality of scanning lines arranged orthogonally to the signal lines; a pixel electrode arranged in each region partitioned in a matrix by the signal lines and the scanning lines; A thin film transistor formed near each intersection of a signal line and a scanning line, having a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line; parallel to each scanning line and each scanning line An auxiliary capacitance line which is arranged independently of each other and electrically capacitively couples to the pixel electrode to form an auxiliary capacitance; a signal line driving circuit arranged along one side on the array substrate; and another on the array substrate A liquid crystal display device comprising: a scanning line driving circuit disposed along one side; and a counter substrate on which a counter electrode facing the pixel electrode is formed via a liquid crystal layer.
The power supply voltage wiring of the signal line driving circuit and the power supply voltage wiring of the scanning line driving circuit are connected to each other through the storage capacitor line.
[0022]
Also in this case, similarly to the above, instead of the above configuration, the ground voltage wirings of the two drive circuits can be connected to each other via the auxiliary capacitance line. The power supply voltage wirings of the two drive circuits are connected to each other via a part of the auxiliary capacitance line (first auxiliary capacitance line), and the ground voltage wiring of the two drive circuits is connected to the other of the auxiliary capacitance line. They can also be connected to each other via a part (second auxiliary capacitance line). Even in such a configuration, it is desirable to alternately arrange the first auxiliary capacitance line and the second auxiliary capacitance line.
[0023]
That is, the power supply voltage wiring (or ground voltage wiring) of the signal line driving circuit and the power supply voltage wiring (or ground voltage wiring) of the scanning line driving circuit are connected to each other via the auxiliary capacitance line, thereby driving each of them. A power supply voltage (or ground voltage) can be stably supplied to the circuit, and the same effect can be obtained.
[0024]
Furthermore, in the case of such a one-side drive type liquid crystal display device,
The power supply voltage wiring of the signal line driving circuit and the power supply voltage wiring of the scanning line driving circuit are connected to each other in the vicinity of the corners on the array substrate adjacent to each other and the edge of the array substrate. Along the opposite side of the side where the signal line drive circuit is disposed and the opposite side of the side where the scanning line drive circuit is disposed, and connected to each other via the power supply voltage line, Further, the ground voltage wiring of the signal line driving circuit and the ground voltage wiring of the scanning line driving circuit are connected to each other in the vicinity of the corner on the array substrate, and the signal line driving circuit is connected along the edge of the array substrate. A ground voltage wiring passing through the opposite side of the arranged side and the opposite side of the side where the scanning line driving circuit is arranged is provided and connected to each other through the ground voltage wiring.
[0025]
In the case of the above configuration, by providing the power supply voltage wiring and the ground voltage wiring along the edge of the array substrate on which the drive circuit is not arranged, the power supply voltage and the ground voltage can be stably supplied to each drive circuit. In the single-sided liquid crystal display device, the display quality can be improved.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings.
(Example 1)
FIG. 1 is a circuit configuration diagram showing an example of a liquid crystal display device integrated with a driving circuit according to the present invention. In the figure, 22 is a display area, 23 and 24 are signal line driving circuits, 25 and 26 are scanning line driving circuits, 28 is an interface portion with the outside of the array substrate, 17 and 20a are power supply voltage wirings, and 18 and 21a are grounds. Voltage wiring, 14 is a signal line, 15 is a scanning line, 16 is an auxiliary capacitance line, 11 is a TFT (pixel TFT), 12 is a pixel electrode, and 13 is an auxiliary capacitance.
[0027]
As shown in FIG. 1, a display region 22 is formed in the center of the array substrate 27, and a pair of upper and lower signal line drive circuits 23, 24, and A pair of left and right scanning line driving circuits 25 and 26 are formed. A TFT (11) is formed at each intersection of the signal line 14 and the scanning line 15, the scanning line 15 is formed on the gate electrode of the TFT (11), the signal line 14 is formed on the drain electrode, and the pixel electrode is formed on the source electrode. 12 are connected to each other. In addition, an auxiliary capacitor 13 is formed between the pixel electrode 12 and the auxiliary capacitor line 16.
[0028]
Further, in this example, the power supply voltage wirings 20a of the pair of left and right scanning line drive circuits 25 and 26 are connected to each other via the auxiliary capacitance lines 16 arranged in the display region in parallel with the respective scanning lines 15. .
[0029]
As a result, the scanning line driving circuit 26 has a position on the opposite side of the array substrate across the display area via the auxiliary capacitance line 16 in addition to the path supplied from the outside of the array substrate 27 via the interface 28. The power supply voltage is also supplied from the scanning line driving circuit 24.
[0030]
By adopting such a configuration, it is possible to stably supply the power supply voltage from the outside of the array substrate to the scanning line drive circuit without increasing the width of the power supply voltage wiring 20a in the drive circuits 26 and 26. Thus, the operation of the scanning line driving circuit can be made more reliable as compared with the conventional configuration (FIG. 11).
[0031]
Next, a manufacturing process of the drive circuit integrated liquid crystal display device shown in FIG. 1 will be described. FIG. 2 is a cross-sectional view showing an outline of a cross-sectional structure of the drive circuit integrated liquid crystal display device.
[0032]
First, an insulating undercoat film 63 such as silicon nitride or silicon oxide is formed on the glass substrate 61 using a plasma CVD method, an atmospheric pressure CVD method, or the like. Next, after forming a first amorphous silicon layer (light-shielding layer) 64 by plasma CVD, hydrogen in the film is reduced by a heating process.
[0033]
Next, an insulating layer 65 made of silicon nitride is formed, and a second amorphous silicon layer 66 is formed thereon by a plasma CVD method. Further, after a dehydrogenation step, annealing is performed using an excimer laser. Then, the second amorphous silicon layer 66 is polysiliconized. The polysilicon film formed by the above steps is patterned through a photo-etching process, and the channel layers 71b and 74 of the active elements (circuit TFTs) 92 and 93 in the drive circuit region, and the pixel switching elements in the display region. A channel layer 71 of 91 (pixel TFT), a lower electrode 72 of an auxiliary capacitance electrode of each pixel, and the like are formed.
[0034]
Next, a silicon oxide layer to be the gate insulating film 67 and the auxiliary capacitor insulating film 67b is formed by atmospheric pressure CVD. This silicon oxide layer becomes a dense film with few defects through a high-temperature heating process.
[0035]
Next, a first MoW thin film (molybdenum / tungsten thin film) 68 is formed by sputtering. The MoW thin film 68 is patterned through a photoetching process, and serves as a mask for impurity implantation by ion doping for forming the n-type TFTs (91, 92) and the lower electrode 72 of the auxiliary capacitor. Further, the second MoW thin film 69 is formed and patterned by the same sputtering method, and then becomes a mask for impurity implantation for forming the p-type TFT (93) in the drive circuit region. After the above process, the first MoW thin film 68 and the second MoW thin film 69 are patterned again, and the gate electrode of each TFT, various wirings in the drive circuit, the upper electrode 70 of the auxiliary capacitance electrode, and the auxiliary capacitance line ( 16; FIG. 1) is formed. Thereafter, impurity implantation for further forming an n-type LDD (Lightly Doped Drain) 73 is performed, and the implanted impurity is activated by annealing the substrate in a high temperature process.
[0036]
Next, a silicon oxide layer 75 to be a first interlayer insulating film is formed by an atmospheric pressure CVD method, a contact hole is processed, and then an aluminum thin film is formed by a sputtering method. The aluminum thin film is patterned through a photoetching process to form various wirings such as a TFT source electrode 77, drain electrode 76, signal line (14; FIG. 1), power supply voltage wiring 41 and ground voltage wiring 40 in the drive circuit region. Is done. Further, a silicon nitride layer to be the second interlayer insulating film 81 is formed by plasma CVD, and after processing the contact holes, an ITO film that is a transparent electrode is formed by sputtering. The ITO film is patterned to become the pixel electrode 38.
[0037]
On the other hand, on the glass substrate 62 on the counter substrate side, the black matrix 45, the color filters 47 and 48, and the counter electrode 43 which is a transparent electrode made of ITO are formed thereon.
[0038]
After forming the array substrate and the counter substrate through the above steps, polyimide alignment films (39a, 39b) for controlling the alignment of the liquid crystal are formed on the counter surfaces, and the alignment processing of the surfaces of both substrates is performed. . After the two substrates are bonded together in the bonding seal region 46 in the vicinity of the peripheral edge portion, the liquid crystal 44 is sealed between the substrates to form a liquid crystal cell. Further, the liquid crystal cell is connected to the outside through an interface using OLB (Outer Lead Bonding) or the like.
[0039]
As described above, a drive circuit integrated liquid crystal display device is formed. In the above process, the TFT (92, 93) and the wirings 40, 41 in the drive circuit portion are formed in the same process as the TFT (91) and the wirings 69, 70, 76, 77 in the display area portion. The upper electrode 70 and the auxiliary capacitance line (16; FIG. 1) of the auxiliary capacitance electrode are formed by the same process as part of the metal thin film layers 68 and 69 constituting the gate electrode, and are formed on the first interlayer insulating film 75. It is connected to the power supply voltage wiring 41 (20a; FIG. 1) of the drive circuit section through the formed through hole.
[0040]
(Example 2)
FIG. 3 is a circuit configuration diagram showing a second example of the drive circuit integrated liquid crystal display device according to the present invention. In the figure, 20b represents a power supply voltage wiring of the scanning line driving circuit, 21b represents a ground voltage wiring of the scanning line driving circuit, and 16b represents an auxiliary capacitance line. Other configurations are the same as those of the drive circuit integrated liquid crystal display device (FIG. 1) shown in the first example, and therefore, the same portions are denoted by the same reference numerals and description thereof is omitted.
[0041]
As shown in the figure, in this example, the ground voltage wirings 21b of the pair of left and right scanning line drive circuits 25, 26 are connected to each other via the auxiliary capacitance lines 16b arranged in the display region in parallel with the scanning lines 15. Connected. As a result, in addition to the path supplied from the outside of the array substrate 27 via the interface 28, the scanning line driving circuit 26 is on the opposite side of the array substrate 27 across the display area via the auxiliary capacitance line 16 b. The ground voltage is also supplied from the scanning line driving circuit 25 located.
[0042]
By adopting such a configuration, the ground voltage can be stably supplied from the outside of the array substrate 27 to the scanning line driving circuit without increasing the width of the ground voltage wiring 21b in the scanning line driving circuits 25 and 26. Therefore, the operation of the scanning line driving circuit can be made more reliable as compared with the conventional configuration (FIG. 11).
[0043]
(Example 3)
FIG. 4 is a circuit configuration diagram showing a third example of the drive circuit integrated liquid crystal display device according to the present invention. In the figure, 20c represents a power supply voltage wiring of the scanning line driving circuit, 21c represents a ground voltage wiring of the scanning line driving circuit, and 16c and 16d represent auxiliary capacitance lines. Other configurations are the same as those of the drive circuit integrated liquid crystal display device (FIGS. 1 and 2) shown in the first or second example.
[0044]
As shown in the figure, in this example, a part of the auxiliary voltage lines 16c (first capacitance lines 20c) in which the power supply voltage wirings 20c of the pair of left and right scanning line drive circuits 25 and 26 are arranged in the display region in parallel with the respective scanning lines 15 are shown. And the ground voltage wiring 21c are connected to each other via another part of the auxiliary capacitance line 16d (second auxiliary capacitance line). As a result, in addition to the path supplied from the outside of the array substrate 27 via the interface 28, the scanning line driving circuit 26 has the array region 27 sandwiched between the display area 22 via the auxiliary capacitance lines 16c and 16d. The power supply voltage and the ground voltage are also supplied from the scanning line driving circuit 25 located on the opposite side.
[0045]
By adopting such a configuration, the scanning line driving circuit 25 can supply the power supply voltage and the ground voltage from the outside of the array substrate 27 without increasing the width of the power supply voltage wiring 20c and the ground voltage wiring 21c in the driving circuits 25 and 26. , 26 can be stably supplied, and the operation of the scanning line driving circuit can be made more reliable as compared with the conventional configuration (FIG. 11).
[0046]
(Example 4)
FIG. 5 is a circuit diagram showing a fourth example of the drive circuit integrated liquid crystal display device according to the present invention. In the figure, 20d represents a power supply voltage wiring for the scanning line driving circuit, 21d represents a ground voltage wiring for the scanning line driving circuit, and 16e and 16f represent auxiliary capacitance lines. Other configurations are the same as those of the driving circuit integrated liquid crystal display device (FIG. 4) shown in the third example.
[0047]
As shown in the figure, similarly to the third example, the power supply voltage wiring 20d and the ground voltage wiring 21d of the pair of left and right scanning line driving circuits 25 and 26 are connected to each other via auxiliary capacitance lines 16e and 16f, respectively. Yes. In addition, in this example, the auxiliary capacity line 16e (first auxiliary capacity line) that connects the power supply voltage lines 20d to each other and the auxiliary capacity line 16f (second auxiliary capacity) that connects the ground voltage lines 21d to each other. Lines) are alternately arranged in parallel with the scanning lines 15 in the display area. By adopting such a configuration, it is possible to stably supply the power supply voltage and the ground voltage from the outside of the array substrate 27 to the scanning line driving circuits 25 and 26 as in the third example. As a result, the spatial frequency of the light transmittance change caused by the mixture of pixels having different storage capacitor potentials becomes high, and thus display unevenness is difficult to be visually recognized. As a result, it is possible to minimize the occurrence of display unevenness due to the difference in storage capacitor potential.
[0048]
(Example 5)
FIG. 6 is a circuit configuration diagram showing a fifth example of the drive circuit integrated liquid crystal display device according to the present invention. In the figure, 17e is a power supply voltage wiring of the signal line driving circuit, 18e is a ground voltage wiring of the signal line driving circuit, 20e is a power supply voltage wiring of the scanning line driving circuit, and 21e is a ground voltage wiring of the scanning line driving circuit. Other configurations are the same as those of the drive circuit integrated liquid crystal display device (FIG. 5) shown in the fourth example.
[0049]
As shown in the figure, as in the fourth example, the auxiliary capacitance line 16e (first auxiliary capacitance line) that connects the power supply voltage wirings 20e to each other and the auxiliary capacitance line 16f (first voltage) that connects the ground voltage wirings 21e to each other. Two auxiliary capacitance lines) are alternately arranged in parallel with the scanning lines 15 in the display area. In addition, in this example, the power supply voltage wiring 20e of the scanning line driving circuit is a power source of the signal line driving circuit near the corner portion of the array substrate where the scanning line driving circuit and the signal line driving circuit are adjacent to each other. The voltage wiring 17e is connected to the ground voltage wiring 21e of the scanning line driving circuit and the ground voltage wiring 18e of the signal line driving circuit.
[0050]
By adopting such a configuration, it is possible not only to ensure the operation of the scanning line driving circuit as compared with the conventional configuration, but also to ensure the operation of the signal line driving circuit. Is possible.
[0051]
(Example 6)
FIG. 7 is a circuit configuration diagram showing a sixth example of a liquid crystal display device integrated with a drive circuit according to the present invention. As shown in the figure, there is only one interface part 28f with the outside. Other configurations are the same as those of the drive circuit integrated liquid crystal display device (FIG. 6) shown in the fifth example.
[0052]
By adopting such a configuration, it is possible not only to make the operation of the drive circuit integrally formed on the array substrate more reliable than the conventional configuration, but also to reduce the size of the liquid crystal display device. It becomes possible.
[0053]
(Example 7)
FIG. 8 is a circuit configuration diagram showing a seventh example of the drive circuit integrated liquid crystal display device according to the present invention.
[0054]
As shown in the figure, in this example, both the signal line 14 and the scanning line 15 are driven on one side. That is, the signal line driving circuit 23g is formed along one side (upper side in the drawing) on the array substrate 27, and the scanning line driving circuit 26g is formed along another side (left side in the drawing) adjacent thereto. Is done. On the other hand, on the opposite side of the side where the signal line driving circuit 23g is formed (the lower side in the figure), only the power supply voltage wiring 17h and the ground voltage wiring 18h are arranged instead of the signal line driving circuit, and the scanning line Only the power supply voltage wiring 20h and the ground voltage wiring 21h are arranged on the opposite side of the side where the driving circuit 26g is formed (right side in the figure) instead of the scanning line driving circuit. The power supply voltage lines 20g, 17h, 17g, and 20h are connected in order, and similarly, the ground voltage lines 21g, 18h, 18g, and 21h are connected in order to form a closed circuit along the peripheral edge of the array substrate 27. ing. Other configurations are the same as those of the drive circuit integrated liquid crystal display device (FIG. 7) shown in the sixth example. As in the sixth example, there is only one interface portion 28f with the outside.
[0055]
By adopting such a configuration, even in a one-side drive type liquid crystal display device, the operation of the drive circuit integrally formed on the array substrate can be made more reliable, so that the liquid crystal display device can be further reduced in size. Can be realized.
[0056]
(Example 8)
FIG. 9 is a cross-sectional view showing a ninth example of the drive circuit integrated liquid crystal display device according to the present invention. In this example, unlike the first example (FIG. 2), an organic protective film having a low dielectric constant is used as the interlayer insulating film 82 between the pixel electrode 38 and the signal line 76, and as shown in FIG. The black matrix (45 (FIG. 2)) is not provided on the substrate 62 side.
[0057]
In this manner, by using an organic protective film having a low dielectric constant as the interlayer insulating film 82, the exchange of electric fields between the pixel electrode 38 and other wirings is reduced, so that the pixel electrode is compared with the conventional configuration. It is possible to reduce the occurrence of edge reverse at the periphery of the substrate, and it is not necessary to form a black matrix on the counter substrate. Therefore, it is possible to minimize the influence of the potential of the auxiliary capacitor on the display while ensuring the aperture ratio of the liquid crystal display device.
[0058]
(Example 9)
FIG. 10 is a cross-sectional view showing a ninth example of the drive circuit integrated liquid crystal display device according to the present invention. In this example, as shown in the figure, unlike the first example (FIG. 2), the color filter (47, 48; FIG. 2) is not arranged on the counter substrate 62 side, and instead, the pixel electrode Color resists 49 and 50 are used as an interlayer insulating film between the electrode 38 and the drain electrode 76 (signal line).
[0059]
By adopting such a configuration, it is not necessary to form a color filter on the counter substrate. Therefore, compared with the structure shown in the first example (FIG. 2) or the eighth example (FIG. 9), it is further lower. Cost can be reduced.
[0060]
In addition, this invention is not limited only to said each example. For example, the drive circuit on the array substrate may be formed through a process different from the manufacturing process shown in the above example, and the active element in the drive circuit is configured only by n-type or p-type TFTs. It does not matter. If the power supply voltage or the ground voltage is supplied from the outside of the array substrate, even if a part of the drive circuit is composed of elements outside the array substrate using TABIC or COG, The same effect as in the above example can be obtained.
[0061]
【The invention's effect】
As described above, in the drive circuit integrated liquid crystal display device, power supply voltage wirings or ground voltage wirings of a plurality of drive circuits arranged along two different sides on the array substrate are used by using auxiliary capacitance lines. By connecting each other, stable operation of the drive circuit is possible, and it is possible to meet the demands for speeding up the circuit, high-definition display, compact liquid crystal display device, and the like.
[0062]
In addition, in the case of the above configuration, it is not necessary to add a new process to the manufacturing process of the conventional drive circuit integrated liquid crystal display device, which does not cause an increase in manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a first example of a drive circuit integrated liquid crystal display device according to the present invention.
2 is a cross-sectional view showing an outline of a cross-sectional structure of the drive circuit integrated liquid crystal display device of FIG. 1;
FIG. 3 is a circuit configuration diagram showing a second example of a drive circuit integrated liquid crystal display device according to the present invention.
FIG. 4 is a circuit configuration diagram showing a third example of a drive circuit integrated liquid crystal display device according to the present invention.
FIG. 5 is a circuit configuration diagram showing a fourth example of a drive circuit integrated liquid crystal display device according to the present invention;
FIG. 6 is a circuit configuration diagram showing a fifth example of a drive circuit integrated liquid crystal display device according to the present invention;
FIG. 7 is a circuit configuration diagram showing a sixth example of a drive circuit integrated liquid crystal display device according to the present invention;
FIG. 8 is a circuit configuration diagram showing a seventh example of a drive circuit integrated liquid crystal display device according to the present invention;
FIG. 9 is a cross-sectional configuration diagram showing an eighth example of a drive circuit integrated liquid crystal display device according to the present invention;
FIG. 10 is a cross-sectional view showing a ninth example of a drive circuit integrated liquid crystal display device according to the present invention.
FIG. 11 is a circuit configuration diagram showing an example of a conventional drive circuit integrated liquid crystal display device.
[Explanation of symbols]
11 ... TFT (pixel TFT),
12 ... pixel electrode,
13 ... Auxiliary capacity,
14 ... Signal line,
15 ... scan line,
16, 16a, 16b ... auxiliary capacity line,
16c, 16e ... first auxiliary capacitance line
16d, 16f, second auxiliary capacitance line
17 ... Power supply voltage wiring for the signal line drive circuit,
18: Ground voltage wiring for signal line drive circuit,
19 ... Auxiliary capacitance line
20, 20a to h ... power supply voltage wiring for the scanning line driving circuit,
21, 21 a to h... Ground voltage wiring for the scanning line driving circuit,
22 ... display area,
23, 24... Signal line drive circuit,
25, 26... Scanning line driving circuit,
27 ... Array substrate,
28, 28f ... interface section,
38 ... Pixel electrode (ITO thin film),
39a, 39b ... polyimide alignment film,
40: Ground voltage wiring,
41 ... Power supply voltage wiring,
43 ... Counter electrode (ITO thin film),
44 ... Liquid crystal layer,
45 ... Black matrix,
46: Bonding seal area,
47, 48 ... color filters,
49, 50 ... Color resist,
61 ... Glass substrate (array substrate side),
62 ... Glass substrate (opposite substrate side),
63: Undercoat film,
64 ... light shielding layer (first amorphous silicon layer),
65 ... Insulating film (silicon nitride layer),
66... Polysilicon active layer,
67... Gate insulating film,
68: Gate electrode (first MoW thin film),
69 ... Gate electrode (second MoW thin film),
70 ... Upper electrode of the auxiliary capacitance electrode (second MoW thin film),
71, 71b ... channel region (n-type polysilicon region),
72 ... Lower electrode of the auxiliary capacitance electrode (n-type polysilicon region),
73: Lightly doped n-type polysilicon region,
74... Channel region (p-type polysilicon region)
75 ... first interlayer insulating film (silicon oxide layer),
76 ... Drain electrode (aluminum thin film),
77 ... Source electrode (aluminum thin film),
81 ... Second interlayer insulating film (silicon nitride layer),
82 ... second interlayer insulating film (low dielectric constant organic thin film layer),
91 ... Pixel TFT,
92 ... circuit TFT (n-type TFT),
93: Circuit TFT (p-type TFT).

Claims

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged independently of the scanning line and forms an auxiliary capacitance by capacitively coupling to the pixel electrode;
A plurality of drive circuits arranged on the array substrate along a plurality of sides and driving scanning lines or signal lines;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
The power supply voltage wiring of the first drive circuit arranged along one side on the array substrate, and the power supply voltage wiring of the second drive circuit arranged along the other side on the array substrate, A liquid crystal display device connected to each other through an auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged independently of the scanning line and forms an auxiliary capacitance by capacitively coupling to the pixel electrode;
A plurality of drive circuits arranged on the array substrate along a plurality of sides and driving scanning lines or signal lines;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
The ground voltage wiring of the first drive circuit arranged along one side on the array substrate, and the ground voltage wiring of the second drive circuit arranged along the other side on the array substrate, A liquid crystal display device connected to each other through an auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged independently of the scanning line and forms an auxiliary capacitance by capacitively coupling to the pixel electrode;
A plurality of drive circuits arranged on the array substrate along a plurality of sides and driving scanning lines or signal lines;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
The power supply voltage wiring of the first drive circuit arranged along one side on the array substrate, and the power supply voltage wiring of the second drive circuit arranged along the other side on the array substrate, While connecting to each other via part of the auxiliary capacitance line,
The ground voltage wiring of the first drive circuit arranged along one side on the array substrate, and the ground voltage wiring of the second drive circuit arranged along the other side on the array substrate, A liquid crystal display device connected to each other through another part of an auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A pair of signal line drive circuits arranged along two opposite sides on the array substrate;
A pair of scanning line drive circuits arranged along the other two opposite sides on the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
A liquid crystal display device, wherein power supply voltage wirings of the pair of scanning line driving circuits are connected to each other via the auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A pair of signal line drive circuits arranged along two opposite sides on the array substrate;
A pair of scanning line drive circuits arranged along the other two opposite sides on the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
A liquid crystal display device, wherein ground voltage wirings of the pair of scanning line driving circuits are connected to each other via the auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A pair of signal line drive circuits arranged along two opposite sides on the array substrate;
A pair of scanning line drive circuits arranged along the other two opposite sides on the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
The power supply voltage wirings of the pair of scanning line driving circuits are connected to each other via a part of the auxiliary capacitance line,
A liquid crystal display device, wherein ground voltage wirings of the pair of scanning line driving circuits are connected to each other via another part of the auxiliary capacitance line.

7. The liquid crystal according to claim 6, wherein the part of the auxiliary capacitance lines connecting the power supply voltage lines to each other and the other part of the auxiliary capacitance lines connecting the ground voltage lines to each other are alternately arranged. Display device.

The power supply voltage wiring of the scanning line driving circuit and the power supply voltage wiring of the signal line driving circuit are connected to each other in the vicinity of corners on the array substrate where the signal line driving circuit and the scanning line driving circuit are adjacent to each other,
The ground voltage wiring of the scanning line driving circuit and the ground voltage wiring of the signal line driving circuit are connected to each other in the vicinity of corners on the array substrate adjacent to each other. 8. The liquid crystal display device according to claim 6, wherein the liquid crystal display device is a liquid crystal display device.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A signal line drive circuit arranged along one side on the array substrate;
A scanning line driving circuit disposed along the other side of the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
A liquid crystal display device, wherein a power supply voltage wiring of the signal line driving circuit and a power supply voltage wiring of the scanning line driving circuit are connected to each other through the auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A signal line drive circuit arranged along one side on the array substrate;
A scanning line driving circuit disposed along the other side of the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
A liquid crystal display device, wherein a ground voltage wiring of the signal line driving circuit and a ground voltage wiring of the scanning line driving circuit are connected to each other through the auxiliary capacitance line.

A plurality of signal lines arranged on the array substrate; and
A plurality of scanning lines arranged orthogonal to the signal lines;
Pixel electrodes disposed in each region partitioned in a matrix by signal lines and scanning lines;
A thin film transistor formed near each intersection of a signal line and a scanning line, a source connected to the pixel electrode, a drain connected to the signal line, and a gate connected to the scanning line;
An auxiliary capacitance line which is arranged in parallel to each scanning line and independently of each scanning line, and forms an auxiliary capacitance by being electrically capacitively coupled to the pixel electrode;
A signal line drive circuit arranged along one side on the array substrate;
A scanning line driving circuit disposed along the other side of the array substrate;
A counter substrate on which a counter electrode facing the pixel electrode is formed through a liquid crystal layer;
In a liquid crystal display device comprising:
The power supply voltage wiring of the signal line drive circuit and the power supply voltage wiring of the scanning line drive circuit are connected to each other through a part of the auxiliary capacitance line,
A liquid crystal display device, wherein a ground voltage wiring of the signal line driving circuit and a ground voltage wiring of the scanning line driving circuit are connected to each other through another part of the auxiliary capacitance line.

12. The liquid crystal according to claim 11, wherein the part of the auxiliary capacitance lines connecting the power supply voltage lines to each other and the other part of the auxiliary capacitance lines connecting the ground voltage lines to each other are alternately arranged. Display device.

The power supply voltage wiring of the signal line driving circuit and the power supply voltage wiring of the scanning line driving circuit are connected to each other in the vicinity of corners on the array substrate where the signal line driving circuit and the scanning line driving circuit are adjacent to each other, Via the power supply voltage wiring provided along the edge on the array substrate so as to pass through the opposite side of the side where the signal line driving circuit is arranged and the opposite side of the side where the scanning line driving circuit is arranged. connection,
Further, the ground voltage wiring of the signal line driving circuit and the ground voltage wiring of the scanning line driving circuit are connected to each other in the vicinity of the corner on the array substrate, and the opposite side of the side where the signal line driving circuit is arranged And a ground voltage wiring provided along an edge on the array substrate so as to pass through the opposite side of the side on which the scanning line driving circuit is disposed. Item 13. A liquid crystal display device according to item 12.