JP3656744B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3656744B2
JP3656744B2 JP2001356462A JP2001356462A JP3656744B2 JP 3656744 B2 JP3656744 B2 JP 3656744B2 JP 2001356462 A JP2001356462 A JP 2001356462A JP 2001356462 A JP2001356462 A JP 2001356462A JP 3656744 B2 JP3656744 B2 JP 3656744B2
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Japan
Prior art keywords
electrode pad
bonding wire
semiconductor device
electrode
semiconductor chip
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Expired - Fee Related
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JP2001356462A
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Japanese (ja)
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JP2003158147A (en
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文成 鈴木
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Denso Corp
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Denso Corp
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Publication of JP3656744B2 publication Critical patent/JP3656744B2/en
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップの表面に形成された電極パッドと外部とがワイヤボンディングによって電気的に接続された構成を有する半導体装置に関する。
【０００２】
【従来技術】
半導体チップの表裏両面から放熱するとともに表裏両面に電流を流す構成の半導体装置として、図５に示す概略断面図のような構成が考えられる。
【０００３】
図５に示されるように、この半導体装置は、２つの半導体チップ１０１、１０２を並列接続しつつ、ヒートシンクブロック１０３及び第２の放熱部材１０５と第１の放熱部材１０４との間に、これら２つの半導体チップ１０１、１０２を狭持して、第１の放熱部材１０４と第２の放熱部材１０５との間を樹脂１０９でモールドしたものである。
【０００４】
そして、２つの半導体チップとしては、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ：Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）が形成された半導体チップ（以下、ＩＧＢＴチップと略す）１０１とフライホイールダイオード（ＦＷＤ：Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ）が形成された半導体チップ（以下、ＦＷＤチップと略す）１０２とを用いている。
【０００５】
また、上記ヒートシンクブロック１０３は、半導体チップ１０１、１０２の素子形成面（表面）１０１ａ、１０２ａにそれぞれ配置されている。
【０００６】
尚、このヒートシンクブロック１０３のうち、ＩＧＢＴチップ１０１の表面１０１ａに配置されたヒートシンクブロック１０３は、後述するボンディングワイヤ１０８が設けられる領域を確保するために設けられており、一方、ＦＷＤチップ１０２の表面１０２ａに配置されたヒートシンクブロック１０３は、後述する第２の放熱部材１０５が傾かないように高さを調整するために設けられている。
【０００７】
また、上記第１の放熱部材１０４は、ＩＧＢＴチップ１０１の裏面１０１ｂ（コレクタ）及びＦＷＤチップ１０２の裏面１０２ｂ（カソード）に接続されており、上記第２の放熱部材１０５は、ＩＧＢＴチップ１０１の表面１０１ａ（エミッタ）及びＦＷＤチップ１０２の表面１０２ａ（アノード）に接続されている。
【０００８】
これらの各部材１０３〜１０５は、半導体チップ１０１、１０２からの放熱を行うと同時に、半導体チップ１０１、１０２との電気的な経路となっている。
【０００９】
従って、放熱性を確保し電気抵抗を小さくするために、半導体チップ１０１、１０２と各部材１０３〜１０５とは、はんだなどの電気伝導性及び熱伝導性を有するはんだ１０６により接合されている。
【００１０】
また、図５におけるＣ−Ｃ面を矢印方向から見た図である図６に示されるように、ＩＧＢＴチップ１０１の表面１０１ａの所望の位置に複数形成されたゲート電極パッド１１０は、ボンディングワイヤ１０８により制御用端子１０７とそれぞれ電気的に接続されている。
【００１１】
そして、図５に示されるように、第１及び第２の放熱部材１０４、１０５のうちの半導体チップ１０１、１０２又はヒートシンクブロック１０３と接合されている面とは反対側の面１０４ｂ、１０５ａが露出するようにして、半導体チップ１０１、１０２、ヒートシンクブロック１０３、第１及び第２の放熱部材１０４、１０５、制御用端子１０７及びボンディングワイヤ１０８が封止部材１０９により封止されている。
【００１２】
さらに、第１及び第２の放熱部材１０４、１０５のうちの封止部材１０９から露出した部位、即ち、第１の放熱部材１０４の裏面１０４ｂ及び第２の放熱部材１０５の表面１０５ａを冷却部材（図示せず）などに当接させて、半導体チップ１０１、１０２からの放熱を促進している。
【００１３】
【発明が解決しようとする課題】
しかしながら、上記従来技術においては、図６及び図５におけるＤの部分の拡大図である図７に示されるように、ボンディングワイヤ１０８の先端部は、ＩＧＢＴチップ１０１の表面１０１ａに複数形成されたエミッタ電極１１１側に突出しているため、この先端部を考慮してヒートシンクブロック１０３を配置する必要がある。
【００１４】
具体的には、ボンディングワイヤ１０８とヒートシンクブロック１０３の短絡を防止するために、エミッタ電極１１１とゲート電極パッド１１０が離間するように両者を配置する必要がある。
【００１５】
しかしながら、それによって、半導体チップ１０１の面積が大きくなってしまい、コストの増加を誘引してしまっている。
【００１６】
そこで、本発明の目的は、上記問題点に鑑み、半導体チップの面積を小さくすることにより、コストを低減した半導体装置を提供することにある。
【００１７】
【課題を解決するための手段】
請求項１に記載の半導体装置は、半導体チップと、この半導体チップにおける一方の面の所定領域に設けられた素子領域と、この素子領域の周辺部に形成された電極パッドとを備え、電極パッドと外部とを複数のボンディングワイヤにより電気的に接続した半導体装置において、複数のボンディングワイヤは、電極パッドと接続された部位より外部側の部分である本体部とそれ以外の部分である先端部とで構成されており、前記本体部は前記素子領域における前記電極パッドと対向する一面に向って延在しているとともに、前記先端部は前記本体部に対して前記素子領域における前記電極パッドと対向する一面と略平行に折れ曲がっていることを特徴としている。
【００１８】
請求項１に記載の発明によれば、ボンディングワイヤの先端部が素子領域側に突出しなくなるので、それによって、半導体チップの面積を小さくすることができ、コストの低減を図ることができる。
【００１９】
請求項２に記載の半導体装置は、半導体チップと、この半導体チップにおける一方の面の所定領域に設けられた素子領域と、この素子領域の周辺部に形成された電極パッドとを備え、前記電極パッドと外部とを複数のボンディングワイヤにより電気的に接続した半導体装置において、前記複数のボンディングワイヤは、前記電極パッドと接続された部位より前記外部側の部分である本体部とそれ以外の部分である先端部とで構成されており、前記ボンディングワイヤは、その一端は前記電極パッドに接続されているとともに、その他端は制御用端子に接続されており、前記半導体チップにおける前記電極パッドが形成された面には、前記制御用端子との間に前記電極パッドが配置するような領域にブロックが接続されており、前記制御用端子と前記電極パッドを結ぶ直線上に前記ブロックが位置しているものであって、前記ボンディングワイヤの先端部の折れ曲がっている方向が、前記ブロックにおける前記制御用端子及び前記電極パッドと対向する側壁面と略平行であることを特徴としている。そして、前記制御用端子は、請求項３に記載のように、前記ボンディングワイヤの本体部の延在方向と略平行に延在していることを特徴としている。
【００２０】
従来、電極パッドにボンディングワイヤを接続する際に、ボンディングワイヤを押さえるための治具がブロックに接触してしまうのを防止するため、電極パッドとブロックとの間にはスペースが設けられていた。
【００２１】
しかしながら、請求項２または３に記載の発明によれば、治具の動きもボンディングワイヤに沿うものとなり、治具がブロックに接触することを防止できる。
【００２２】
それによって、電極パッドとブロックとの間に設けられていたスペースが不要になるため、半導体チップの面積を小さくすることができ、コストの低減を図ることができる。
【００２３】
請求項４または５に記載の半導体装置は、半導体チップには縦型の電力素子が形成されており、この縦型の電力素子における一方の主電極はブロックを介して放熱部材と電気的に接続され、縦型の電力素子における他方の主電極は基台と電気的に接続され、縦型の電力素子における制御電極は電極パッドと電気的に接続された半導体装置において、電極パッドは複数形成されており、縦型の電力素子が複数の領域に区分けされていることを特徴としている。
【００２４】
請求項４または５に記載のような構成の半導体装置において、上記請求項２又は３に記載のような構成を適用すると、上記請求項２又は３と同様の効果を得ることができる。
請求項６は、前記ボンディングワイヤの先端部の折れ曲がっている方向が、前記素子領域の周辺部に形成された複数の前記電極パッドの整列方向と略平行であることを特徴としている。請求項７は、前記ボンディングワイヤにおける先端部に形成された潰れ部は、その延在方向が前記ボンディングワイヤの折れ曲がっている方向とほぼ平行するように形成されていることを特徴としている。請求項８は、前記複数の電極パッドは、その長手方向が前記ボンディングワイヤの折れ曲がっている方向とほぼ平行するように設けられていることを特徴としている。このような特徴を有することにより、上記請求項１と同様に、ボンディングワイヤの先端部が素子領域側に突出しなくなるので、それによって、半導体チップの面積を小さくすることができ、コストの低減を図ることができる。
【００２５】
【発明の実施の形態】
以下、本発明を具体化した一実施形態を、図面に従って説明する。
【００２６】
図１には、本発明の一実施形態に係る半導体装置の概略断面図を示す。また、図２（ａ）には図１におけるＡ―Ａ面を矢印方向から見た図を示し、図２（ｂ）には図２（ａ）におけるＥの部分の拡大図を示し、図３には図１におけるＢの部分の拡大図を示す。
【００２７】
この図１に示されるように、本実施形態の半導体装置は、２つの半導体チップ１、２を並列接続しつつ、ヒートシンクブロック（ブロック）３及び第２の放熱部材５（放熱部材）と第１の放熱部材４（基台）との間に半導体チップ１、２を狭持して、第１の放熱部材４と第２の放熱部材５との間を樹脂９でモールドしたものである。
【００２８】
そして、本実施形態では、半導体チップとして、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ：Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）が形成された半導体チップ（以下、ＩＧＢＴチップと略す）１とフライホイールダイオード（ＦＷＤ：Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ）が形成された半導体チップ（以下、ＦＷＤチップと略す）２とを用いている。尚、これらの各半導体チップ１、２は、主としてシリコンからなり、厚みは０．５ｍｍ程度である。
【００２９】
以下、各半導体チップ１、２の外表面のうち、素子形成面側の面を表面１ａ、２ａといい、この表面１ａ、２ａとは反対側の面を裏面１ｂ、２ｂという。
【００３０】
尚、図１には示さないが、ＩＧＢＴチップ１の表面１ａにはエミッタ電極（一方の主電極）、ゲート電極（制御電極）が形成されており、裏面１ｂにはコレクタ電極（他方の主電極）が形成されている。
【００３１】
各半導体チップ１、２の表面１ａ、２ａには、電気伝導性を有する接合部材としてのはんだ６を介して、ヒートシンクブロック３の裏面３ｂが接合されている。
【００３２】
このヒートシンクブロック３のうち、ＩＧＢＴチップ１の表面１ａに配置されたヒートシンクブロック３は、後述するボンディングワイヤ８が設けられる領域を確保するために設けられており、一方、ＦＷＤチップ２の表面２ａに配置されたヒートシンクブロック３は、後述する第２の放熱部材５が傾かないように高さを調整するために設けられている。
【００３３】
また、各半導体チップ１、２の裏面１ｂ、２ｂには、電気伝導性を有する接合部材としてのはんだ６を介して、第１の放熱部材４の表面４ａが接合（電気的に接続）されており、ヒートシンクブロック３の裏面３ｂとは反対側の面である表面３ａには、電気伝導性を有する接合部材としてのはんだ６を介して、第２の放熱部材５の裏面５ｂが接合（電気的に接続）されている。
【００３４】
ヒートシンクブロック３としては、電気導電性を有する金属部材を用いることができ、本実施形態では、ヒートシンクブロック３としてＣｕを用いており、第１及び第２の放熱部材４、５としてＣｕ合金を用いている。
【００３５】
また、図２（ａ）に示されるように、ＩＧＢＴチップ１の表面１ａの所望の位置に複数形成されたゲート電極パッド１４は、ボンディングワイヤ８により制御用端子７とそれぞれ電気的に接続されている。
【００３６】
尚、ＩＧＢＴチップ１は複数のＩＧＢＴセルが並列的に集積された公知の構造を有しており、本実施形態では、この複数のＩＧＢＴセルが５つの領域に区分けされており、この５つの領域が同時に作動して１つのＩＧＢＴとして機能するように、共通に各部材１〜３の間に狭持されている。
【００３７】
また、図２（ａ）に示されるように、本実施形態では、全てのゲート電極パッド１４は各々ボンディングワイヤ８を介して制御用端子７に接続されているが、例えば、ゲート不良のある領域に相当するゲート電極パッド１４は、制御用端子７に接続されることなく、エミッタ電極１５と等電位になるように電気的に接続されていてもよい。
【００３８】
そして、図１に示されるように、各半導体チップ１、２、ヒートシンクブロック３、第１の放熱部材４の表面４ａ、第２の放熱部材５の裏面５ｂ、ボンディングワイヤ８、及び制御用端子７の一部が、一括して封止部材としての樹脂９により封止されている。
【００３９】
これにより、第１の放熱部材４の裏面４ｂと第２の放熱部材５の表面５ａ、及び制御用端子７の一部が露出した状態で各部材１〜８が封止された構成となっている。この樹脂９としては、例えば、エポキシ系モールド樹脂を用いることができる。尚、この場合、各部材１〜８を樹脂９でモールドするに当たっては、上下型からなる成形型（図示しない）を使用している。
【００４０】
また、図示しないが、樹脂９と第１及び第２の放熱部材４、５との密着力、樹脂９と各半導体チップ１、２との密着力、並びに、樹脂９とヒートシンクブロック３との密着力を強くするために、上記樹脂９をモールドする前に、各部材１〜５における樹脂９と接触する面にはコーティング樹脂が塗布されている。
【００４１】
このようにして、本実施形態の半導体装置が構成されており、この半導体装置では、各半導体チップ１、２からの発熱を、熱伝導性にも優れたはんだ６を介してヒートシンクブロック３と第１及び第２の放熱部材４、５に伝え、第１の放熱部材４の裏面４ｂ及び第２の放熱部材５の表面５ａから放熱を行うことができるようになっている。
【００４２】
さらに、第１及び第２の放熱部材４、５のうちの封止部材９から露出した部位、即ち、第１の放熱部材４の裏面４ｂ及び第２の放熱部材５の表面５ａを冷却部材（図示せず）などに当接させて、各半導体チップ１、２からの放熱を促進している。
【００４３】
ここで、図２（ａ）及び図３に示されるように、本実施形態のボンディングワイヤ８は、ゲート電極パッド１４と接続された部位より外部側の部分である本体部８ａとそれ以外の部分である先端部８ｂとで構成されており、この先端部８ｂは本体部８ａに対して折れ曲がっている。
【００４４】
具体的に説明すると、図２（ｂ）に示されるように、ボンディングワイヤ８の先端部８ｂ及びウェッジボンディング時のボンディングワイヤ８の潰れ部８ｃの延在方向が、半導体チップ１周辺とほぼ平行になっており、ボンディングワイヤ８の本体部８ａは、先端部８ｂ及び潰れ部８ｃに対して折れ曲がるように制御用端子７の方向へ伸びている。
【００４５】
従って、本実施形態のゲート電極パッド１４は、その長手方向がボンディングワイヤ８の先端部８ｂ及び潰れ部８ｃの延在方向、即ち、半導体チップ１周辺とほぼ平行するように設けられている。
【００４６】
このように、ボンディングワイヤ８の先端部８ｂが本体部８ａに対して折れ曲がっていることにより、ボンディングワイヤ８の先端部８ｂがエミッタ電極１５側に突出しなくなるので、従来技術において、ボンディングワイヤ８の先端部８ｂが突出していた領域は不要になる。
【００４７】
それによって、半導体チップ１の面積を小さくすることができ、コストの低減を図ることができる。
【００４８】
また、従来技術では、ゲート電極パッド１４にボンディングワイヤ８をウェッジボンディングする際に、ボンディングワイヤ８を押さえるための治具（図示せず）がヒートシンクブロック３に接触してしまうのを防止するため、ゲート電極パッド１４とヒートシンクブロック３との間にはスペースが設けられていた。
【００４９】
しかしながら、本実施形態のように、ボンディングワイヤ８の先端部８ｂが本体部８ａに対して折れ曲がるようにボンディングしたことにより、治具の動きもボンディングワイヤ８に沿うものとなり、治具がヒートシンクブロック３に接触することを防止できる。
【００５０】
それにより、治具がヒートシンクブロック３に接触してしまうのを防止するために設けられていたスペースが不要になるため、半導体チップ１の面積を小さくすることができ、コストの低減を一層図ることができる。
【００５１】
このように、本実施形態によれば、従来技術において、ボンディングワイヤ８の先端部８ｂが突出していた領域や治具がヒートシンクブロック３に接触してしまうのを防止するために設けられていたスペースが不要になることにより、半導体チップ１の面積を小さくすることができるが、これらの領域をエミッタ電極として確保して、これらの領域の分だけエミッタ電極１５を大きくすることもできるため、それにより、ＩＧＢＴチップ１の発熱を抑制することができる。
【００５２】
次に、上記構成の半導体装置の製造方法について、本製造方法を概略断面図にて示す工程図である図４を参照して説明する。
【００５３】
まず、第１及び第２の放熱部材４、５を板状のＣｕ合金部材などからパンチングなどにより形成する。また、ヒートシンクブロック３を形成するための板状のＣｕ部材を用意する。そして、パンチングなどによりＣｕ部材からヒートシンクブロック３の大きさのＣｕ部材を形成し、このＣｕ部材をプレスすることによりヒートシンクブロック３が完成する。
【００５４】
続いて、図４（ａ）に示されるように、第１の放熱部材４の表面４ａ上にはんだ６を介して各半導体チップ１、２を接合する。次に、各半導体チップ１、２の表面１ａ、２ａ上にはんだ６を介してヒートシンクブロック３を接合する。これにより、上記図４（ａ）に示す状態となり、このものをワーク１０とする。
【００５５】
その後、図示しないが、上述のように、ＩＧＢＴチップ１と制御用端子７とをボンディングワイヤ８により電気的に接続する。
【００５６】
次に、図４（ｂ）に示されるように、第２の放熱部材５の裏面５ｂを上にして治具１１上に搭載し、第２の放熱部材５の裏面５ｂの所望の位置にはんだ６を配設し、上記図４（ａ）に示すワーク１０を裏返しにして第２の放熱部材５上に搭載する。
【００５７】
さらに、第１の放熱部材４の裏面４ｂ上に板状の重り１２を載せる。また、治具１１には、第１及び第２の放熱部材４、５間の距離を規定するために一定の高さを持ったスペーサ１３が備えられる。この状態が図４（ｂ）に示す状態である。そして、この状態で加熱炉などに入れてはんだ６をリフローさせる。
【００５８】
その結果、重り１２によりワーク１０が加圧され、図４（ｃ）に示されるように、はんだ６が押しつぶされ、第２の放熱部材５の裏面５ｂと第１の放熱部材４の表面４ａとの距離がスペーサ１３の高さになる。これにより、第１の放熱部材４と第２の放熱部材５の平行度が調整される。
【００５９】
続いて、図示しないが、各半導体チップ１、２、第１及び第２の放熱部材４、５、ヒートシンクブロック３における樹脂９と接触する面に、コーティング樹脂を塗布する。この場合、例えばディッピング（浸漬）により塗布しても良いし、コーティング樹脂塗布用のディスペンサのノズルから滴下（または噴霧）することにより塗布しても良い。尚、制御用端子７やボンディングワイヤ８の表面にも、コーティング樹脂を塗布しておくことが好ましい。
【００６０】
その後、上記図１に示されるように、樹脂９によって各部材１〜８を封止することによって半導体装置が完成する。
【００６１】
尚、本発明は、上記実施形態に限られるものではなく、様々な態様に適用可能である。
【００６２】
例えば、上記実施形態では、接合部材としては、はんだ６を用いる例について示したが、これに限られるものではなく、その他にＡｇペーストなどを用いることができる。また、各接合部材として必ずしも同一のものを用いなくてもよい。
【００６３】
また、上記実施形態では、図２（ｂ）に示されるように、ボンディングワイヤ８の先端部８ｂ及び潰れ部８ｃは、エミッタ電極１５の長手方向に対して垂直になるように折れ曲がっているが、これに限られるものではなく、少なくともボンディングワイヤ８の先端部８ａ及び潰れ部８ｃがエミッタ電極１５の長手方向に対して平行になっていなければよい。
【００６４】
また、上記実施形態では、半導体チップとして、ＩＧＢＴチップ１を用いた構成について説明したが、これに限られるものではなく、半導体チップとしては、縦型のバイポーラトランジスタや縦型のＤＭＯＳＦＥＴを用いた構成にも適用することができる。尚、ＤＭＯＳＦＥＴを用いた場合、ＤＭＯＳＦＥＴはその内部にＦＷＤチップと同様の作用を有する寄生ダイオードを内蔵できるため、ＦＷＤチップは不要となる。
【００６５】
また、上記実施形態では、半導体チップ１、２の両面に放熱部材４、５を配設した両面放熱構造について説明したが、これに限られるものではなく、半導体チップ１、２の片面のみ、特に主面側に放熱部材を配設した片面放熱構造にも適用することができる。
【００６６】
また、半導体チップは、パワー素子としてのトランジスタ以外にも、その表面に電極パッドが形成されたものであれば何でも良い。また、樹脂でモールドされていない半導体装置にも適用することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る半導体装置の概略断面図である。
【図２】（ａ）は図１におけるＡ―Ａ面を矢印方向から見た図であり、（ｂ）は（ａ）におけるＥの部分の拡大図である。
【図３】図１におけるＢの部分の拡大図である。
【図４】図１に示す半導体装置の製造方法を示す工程図である。
【図５】従来技術の半導体装置の概略断面図である。
【図６】図４におけるＣ―Ｃ面を矢印方向から見た図である。
【図７】図４におけるＤの部分の拡大図である。
【符号の説明】
１…ＩＧＢＴチップ（半導体チップ）、
２…ＦＷＤチップ（半導体チップ）
３…ヒートシンクブロック（ブロック）、
４…第１の放熱部材（基台）、
５…第２の放熱部材（放熱部材）、
１ａ、２ａ、３ａ、４ａ、５ａ…各部材の表面、
１ｂ、２ｂ、３ｂ、４ｂ、５ｂ…各部材の裏面、
６…はんだ（接合部材）、
７…制御用端子、
８…ボンディングワイヤ、
８ａ…ボンディングワイヤの本体部、
８ｂ…ボンディングワイヤの先端部、
８ｃ…潰れ部、
９…樹脂、
１０…ワーク、
１２…重り、
１３…スペーサ、
１４…ゲート電極パッド、
１５…エミッタ電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a configuration in which an electrode pad formed on the surface of a semiconductor chip and the outside are electrically connected by wire bonding.
[0002]
[Prior art]
As a semiconductor device having a configuration in which heat is radiated from both the front and back surfaces of the semiconductor chip and a current is supplied to both the front and back surfaces, a configuration as shown in a schematic cross-sectional view of FIG.
[0003]
As shown in FIG. 5, this semiconductor device connects two semiconductor chips 101 and 102 in parallel, and between the heat sink block 103 and the second heat radiating member 105 and the first heat radiating member 104. The semiconductor chips 101 and 102 are sandwiched, and the space between the first heat radiating member 104 and the second heat radiating member 105 is molded with a resin 109.
[0004]
As the two semiconductor chips, a semiconductor chip (hereinafter abbreviated as IGBT chip) 101 on which an insulated gate bipolar transistor (IGBT) is formed and a flywheel diode (FWD: Free Wheeling Diode) are formed. The semiconductor chip (hereinafter abbreviated as FWD chip) 102 is used.
[0005]
The heat sink block 103 is disposed on the element formation surfaces (front surfaces) 101a and 102a of the semiconductor chips 101 and 102, respectively.
[0006]
Of the heat sink block 103, the heat sink block 103 disposed on the surface 101a of the IGBT chip 101 is provided to secure a region where a bonding wire 108 to be described later is provided, while the surface of the FWD chip 102 is provided. The heat sink block 103 arranged at 102a is provided to adjust the height so that a second heat radiating member 105 described later does not tilt.
[0007]
The first heat radiating member 104 is connected to the back surface 101 b (collector) of the IGBT chip 101 and the back surface 102 b (cathode) of the FWD chip 102, and the second heat radiating member 105 is connected to the surface of the IGBT chip 101. 101a (emitter) and the surface 102a (anode) of the FWD chip 102 are connected.
[0008]
Each of these members 103 to 105 radiates heat from the semiconductor chips 101 and 102 and at the same time serves as an electrical path to the semiconductor chips 101 and 102.
[0009]
Therefore, in order to ensure heat dissipation and reduce the electrical resistance, the semiconductor chips 101 and 102 and the members 103 to 105 are joined by a solder 106 having electrical and thermal conductivity such as solder.
[0010]
Further, as shown in FIG. 6 which is a view of the CC plane in FIG. 5 as viewed from the direction of the arrow, a plurality of gate electrode pads 110 formed at desired positions on the surface 101 a of the IGBT chip 101 are bonded wires 108. Are electrically connected to the control terminal 107 respectively.
[0011]
Then, as shown in FIG. 5, the surfaces 104 b and 105 a on the opposite side to the surface bonded to the semiconductor chips 101 and 102 or the heat sink block 103 of the first and second heat radiating members 104 and 105 are exposed. Thus, the semiconductor chips 101 and 102, the heat sink block 103, the first and second heat radiation members 104 and 105, the control terminal 107, and the bonding wire 108 are sealed with the sealing member 109.
[0012]
Furthermore, the part exposed from the sealing member 109 among the first and second heat radiating members 104, 105, that is, the back surface 104 b of the first heat radiating member 104 and the surface 105 a of the second heat radiating member 105 are cooled by a cooling member ( The heat dissipation from the semiconductor chips 101 and 102 is promoted by abutting against the semiconductor chip 101 and the like.
[0013]
[Problems to be solved by the invention]
However, in the above prior art, as shown in FIG. 7 which is an enlarged view of a portion D in FIGS. 6 and 5, a plurality of tip portions of the bonding wire 108 are formed on the surface 101 a of the IGBT chip 101. Since it protrudes to the electrode 111 side, it is necessary to arrange the heat sink block 103 in consideration of this tip.
[0014]
Specifically, in order to prevent the bonding wire 108 and the heat sink block 103 from being short-circuited, it is necessary to arrange the emitter electrode 111 and the gate electrode pad 110 so that they are separated from each other.
[0015]
However, this increases the area of the semiconductor chip 101 and induces an increase in cost.
[0016]
In view of the above problems, an object of the present invention is to provide a semiconductor device with reduced cost by reducing the area of a semiconductor chip.
[0017]
[Means for Solving the Problems]
The semiconductor device according to claim 1 includes a semiconductor chip, an element region provided in a predetermined region on one surface of the semiconductor chip, and an electrode pad formed in a peripheral portion of the element region. In a semiconductor device in which a plurality of bonding wires are electrically connected to each other by a plurality of bonding wires, the plurality of bonding wires includes a main body portion that is a portion on the outer side from a portion connected to the electrode pad and a tip portion that is the other portion. The main body portion extends toward a surface facing the electrode pad in the element region, and the tip portion faces the electrode pad in the element region with respect to the main body portion. It is characterized by being bent substantially parallel to one surface.
[0018]
According to the first aspect of the present invention, since the tip end portion of the bonding wire does not protrude toward the element region, the area of the semiconductor chip can be reduced, and the cost can be reduced.
[0019]
The semiconductor device according to claim 2 includes a semiconductor chip, an element region provided in a predetermined region on one surface of the semiconductor chip, and an electrode pad formed in a peripheral portion of the element region. In the semiconductor device in which the pad and the outside are electrically connected by a plurality of bonding wires, the plurality of bonding wires are connected to the body portion that is a portion on the outer side from the portion connected to the electrode pad and the other portions. is composed of a certain tip, the bonding wire has one end together with being connected to the electrode pad and the other end is connected to the control terminal, wherein the electrode pads of the semiconductor chip is formed On the other surface, a block is connected to a region where the electrode pad is disposed between the control terminal and the control terminal. The block is positioned on a straight line connecting the electrode pads, and the bending direction of the tip of the bonding wire is a side wall surface facing the control terminal and the electrode pad in the block. It is characterized by being substantially parallel. The control terminal is characterized in that, as described in claim 3, the control terminal extends substantially parallel to the extending direction of the main body of the bonding wire.
[0020]
Conventionally, when connecting a bonding wire to an electrode pad, a space has been provided between the electrode pad and the block in order to prevent a jig for holding the bonding wire from coming into contact with the block.
[0021]
However, according to the invention described in claim 2 or 3, the movement of the jig also follows the bonding wire, and the jig can be prevented from contacting the block.
[0022]
As a result, the space provided between the electrode pad and the block becomes unnecessary, so that the area of the semiconductor chip can be reduced and the cost can be reduced.
[0023]
In the semiconductor device according to claim 4 or 5, a vertical power element is formed on the semiconductor chip, and one main electrode of the vertical power element is electrically connected to the heat dissipation member through a block. In the semiconductor device in which the other main electrode in the vertical power element is electrically connected to the base and the control electrode in the vertical power element is electrically connected to the electrode pad, a plurality of electrode pads are formed. The vertical power element is divided into a plurality of regions.
[0024]
In the semiconductor device having the structure as described in claim 4 or 5, when applying the configuration as described in the preceding claims 2 or 3, it is possible to obtain the same effect as in the claim 2 or 3.
According to a sixth aspect of the present invention, the bending direction of the tip end portion of the bonding wire is substantially parallel to the alignment direction of the plurality of electrode pads formed in the peripheral portion of the element region. According to a seventh aspect of the present invention, the crushing portion formed at the tip of the bonding wire is formed such that the extending direction thereof is substantially parallel to the direction in which the bonding wire is bent. An eighth aspect of the present invention is characterized in that the plurality of electrode pads are provided so that the longitudinal direction thereof is substantially parallel to the direction in which the bonding wire is bent. By having such a feature, the tip end portion of the bonding wire does not protrude toward the element region as in the case of the first aspect, so that the area of the semiconductor chip can be reduced and the cost can be reduced. be able to.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment embodying the present invention will be described with reference to the drawings.
[0026]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A shows a view of the AA plane in FIG. 1 as viewed from the direction of the arrow, FIG. 2B shows an enlarged view of a portion E in FIG. 2A, and FIG. 1 shows an enlarged view of a portion B in FIG.
[0027]
As shown in FIG. 1, the semiconductor device of the present embodiment has a heat sink block (block) 3 and a second heat radiating member 5 (heat radiating member) and a first one while connecting two semiconductor chips 1 and 2 in parallel. The semiconductor chips 1 and 2 are sandwiched between the first heat radiating member 4 and the second heat radiating member 5 with a resin 9.
[0028]
In this embodiment, as a semiconductor chip, a semiconductor chip (hereinafter abbreviated as IGBT chip) 1 having an insulated gate bipolar transistor (IGBT) and a flywheel diode (FWD: Free Wheeling Diode) are formed. A semiconductor chip (hereinafter abbreviated as an FWD chip) 2 on which is formed is used. Each of these semiconductor chips 1 and 2 is mainly made of silicon and has a thickness of about 0.5 mm.
[0029]
Hereinafter, of the outer surfaces of the semiconductor chips 1 and 2, the surfaces on the element forming surface side are referred to as the front surfaces 1a and 2a, and the surfaces opposite to the surfaces 1a and 2a are referred to as the back surfaces 1b and 2b.
[0030]
Although not shown in FIG. 1, an emitter electrode (one main electrode) and a gate electrode (control electrode) are formed on the surface 1a of the IGBT chip 1, and a collector electrode (the other main electrode) is formed on the back surface 1b. ) Is formed.
[0031]
The back surface 3b of the heat sink block 3 is bonded to the front surfaces 1a and 2a of the semiconductor chips 1 and 2 via solder 6 as a bonding member having electrical conductivity.
[0032]
Of the heat sink block 3, the heat sink block 3 disposed on the surface 1a of the IGBT chip 1 is provided in order to secure a region where a bonding wire 8 to be described later is provided, and on the surface 2a of the FWD chip 2 is provided. The arranged heat sink block 3 is provided to adjust the height so that the second heat radiating member 5 described later does not tilt.
[0033]
Further, the front surface 4a of the first heat radiating member 4 is bonded (electrically connected) to the back surfaces 1b and 2b of the semiconductor chips 1 and 2 via solder 6 as a bonding member having electrical conductivity. The back surface 5b of the second heat radiating member 5 is joined to the surface 3a, which is the surface opposite to the back surface 3b of the heat sink block 3, via the solder 6 as a joining member having electrical conductivity (electrical). It is connected to the.
[0034]
As the heat sink block 3, a metal member having electrical conductivity can be used. In this embodiment, Cu is used as the heat sink block 3, and Cu alloys are used as the first and second heat radiating members 4, 5. ing.
[0035]
2A, the plurality of gate electrode pads 14 formed at desired positions on the surface 1a of the IGBT chip 1 are electrically connected to the control terminals 7 by bonding wires 8, respectively. Yes.
[0036]
The IGBT chip 1 has a known structure in which a plurality of IGBT cells are integrated in parallel. In this embodiment, the plurality of IGBT cells are divided into five regions. Are simultaneously sandwiched between the members 1 to 3 so that they can operate simultaneously and function as one IGBT.
[0037]
Further, as shown in FIG. 2A, in the present embodiment, all the gate electrode pads 14 are connected to the control terminals 7 through the bonding wires 8, respectively. The gate electrode pad 14 corresponding to may be electrically connected to the emitter electrode 15 so as to be equipotential without being connected to the control terminal 7.
[0038]
As shown in FIG. 1, the semiconductor chips 1, 2, the heat sink block 3, the front surface 4 a of the first heat radiating member 4, the back surface 5 b of the second heat radiating member 5, the bonding wire 8, and the control terminal 7. Are partially sealed with a resin 9 as a sealing member.
[0039]
Thereby, it becomes the structure by which each member 1-8 was sealed in the state in which the back surface 4b of the 1st heat radiating member 4, the surface 5a of the 2nd heat radiating member 5, and a part of control terminal 7 were exposed. Yes. As this resin 9, for example, an epoxy mold resin can be used. In this case, when the members 1 to 8 are molded with the resin 9, a molding die (not shown) composed of upper and lower molds is used.
[0040]
Although not shown, the adhesion between the resin 9 and the first and second heat radiation members 4 and 5, the adhesion between the resin 9 and each of the semiconductor chips 1 and 2, and the adhesion between the resin 9 and the heat sink block 3. In order to increase the force, a coating resin is applied to the surface of each member 1 to 5 that contacts the resin 9 before the resin 9 is molded.
[0041]
Thus, the semiconductor device of the present embodiment is configured. In this semiconductor device, the heat generated from each of the semiconductor chips 1 and 2 is transferred to the heat sink block 3 and the second through the solder 6 having excellent thermal conductivity. The heat is transmitted to the first and second heat radiating members 4 and 5, and heat can be radiated from the back surface 4 b of the first heat radiating member 4 and the surface 5 a of the second heat radiating member 5.
[0042]
Furthermore, the part exposed from the sealing member 9 among the first and second heat radiating members 4, 5, that is, the back surface 4 b of the first heat radiating member 4 and the surface 5 a of the second heat radiating member 5 are cooled by a cooling member ( The heat radiation from each of the semiconductor chips 1 and 2 is promoted by abutting against a semiconductor chip (not shown).
[0043]
Here, as shown in FIG. 2A and FIG. 3, the bonding wire 8 of the present embodiment includes a main body portion 8 a that is a portion on the outer side of the portion connected to the gate electrode pad 14 and other portions. The tip portion 8b is bent with respect to the main body portion 8a.
[0044]
Specifically, as shown in FIG. 2B, the extending direction of the tip 8b of the bonding wire 8 and the crushing portion 8c of the bonding wire 8 during wedge bonding is substantially parallel to the periphery of the semiconductor chip 1. Thus, the main body portion 8a of the bonding wire 8 extends in the direction of the control terminal 7 so as to be bent with respect to the distal end portion 8b and the crushed portion 8c.
[0045]
Therefore, the gate electrode pad 14 of this embodiment is provided so that the longitudinal direction thereof is substantially parallel to the extending direction of the tip end portion 8b and the crushed portion 8c of the bonding wire 8, that is, the periphery of the semiconductor chip 1.
[0046]
As described above, since the distal end portion 8b of the bonding wire 8 is bent with respect to the main body portion 8a, the distal end portion 8b of the bonding wire 8 does not protrude to the emitter electrode 15 side. The region where the portion 8b protrudes is unnecessary.
[0047]
Thereby, the area of the semiconductor chip 1 can be reduced, and the cost can be reduced.
[0048]
In the conventional technique, when the bonding wire 8 is wedge-bonded to the gate electrode pad 14, a jig (not shown) for holding the bonding wire 8 is prevented from coming into contact with the heat sink block 3. A space was provided between the gate electrode pad 14 and the heat sink block 3.
[0049]
However, since the tip 8b of the bonding wire 8 is bent so as to be bent with respect to the main body 8a as in the present embodiment, the movement of the jig also follows the bonding wire 8, and the jig becomes the heat sink block 3. Can be prevented from touching.
[0050]
Thereby, the space provided for preventing the jig from coming into contact with the heat sink block 3 becomes unnecessary, so that the area of the semiconductor chip 1 can be reduced and the cost can be further reduced. Can do.
[0051]
Thus, according to this embodiment, in the prior art, the space provided for preventing the region where the tip 8b of the bonding wire 8 protrudes and the jig from coming into contact with the heat sink block 3 are provided. Is unnecessary, the area of the semiconductor chip 1 can be reduced. However, these regions can be secured as emitter electrodes, and the emitter electrode 15 can be enlarged by the amount of these regions. The heat generation of the IGBT chip 1 can be suppressed.
[0052]
Next, a manufacturing method of the semiconductor device having the above configuration will be described with reference to FIG. 4 which is a process diagram showing the manufacturing method in a schematic sectional view.
[0053]
First, the first and second heat radiating members 4 and 5 are formed from a plate-like Cu alloy member or the like by punching or the like. A plate-like Cu member for forming the heat sink block 3 is prepared. Then, a Cu member having the size of the heat sink block 3 is formed from the Cu member by punching or the like, and the heat sink block 3 is completed by pressing the Cu member.
[0054]
Subsequently, as shown in FIG. 4A, the semiconductor chips 1 and 2 are bonded to the surface 4 a of the first heat radiating member 4 via the solder 6. Next, the heat sink block 3 is joined to the surfaces 1 a and 2 a of the semiconductor chips 1 and 2 via the solder 6. As a result, the state shown in FIG.
[0055]
Thereafter, although not shown, the IGBT chip 1 and the control terminal 7 are electrically connected by the bonding wire 8 as described above.
[0056]
Next, as shown in FIG. 4B, the back surface 5b of the second heat radiating member 5 is mounted on the jig 11 with the back surface 5b facing upward, and solder is placed on a desired position on the back surface 5b of the second heat radiating member 5. 6 is disposed, and the work 10 shown in FIG. 4A is turned over and mounted on the second heat radiating member 5.
[0057]
Further, a plate-like weight 12 is placed on the back surface 4 b of the first heat radiating member 4. In addition, the jig 11 is provided with a spacer 13 having a certain height in order to define the distance between the first and second heat radiating members 4 and 5. This state is the state shown in FIG. And in this state, it puts in a heating furnace etc. and reflows the solder 6. FIG.
[0058]
As a result, the workpiece 10 is pressed by the weight 12, and the solder 6 is crushed as shown in FIG. 4C, and the back surface 5b of the second heat radiating member 5 and the surface 4a of the first heat radiating member 4 Is the height of the spacer 13. Thereby, the parallelism of the 1st heat radiating member 4 and the 2nd heat radiating member 5 is adjusted.
[0059]
Subsequently, although not shown, a coating resin is applied to the surfaces of the semiconductor chips 1, 2, the first and second heat radiating members 4, 5, and the heat sink block 3 that are in contact with the resin 9. In this case, for example, it may be applied by dipping (immersion), or may be applied by dropping (or spraying) from a nozzle of a dispenser for applying a coating resin. It is preferable to apply a coating resin also to the surfaces of the control terminal 7 and the bonding wire 8.
[0060]
Thereafter, as shown in FIG. 1, the members 1 to 8 are sealed with the resin 9 to complete the semiconductor device.
[0061]
In addition, this invention is not restricted to the said embodiment, It can apply to various aspects.
[0062]
For example, in the above embodiment, the example in which the solder 6 is used as the joining member has been described. However, the present invention is not limited to this, and an Ag paste or the like can be used. Moreover, it is not always necessary to use the same member as each joining member.
[0063]
In the above embodiment, as shown in FIG. 2B, the tip 8b and the crushed portion 8c of the bonding wire 8 are bent so as to be perpendicular to the longitudinal direction of the emitter electrode 15. However, the present invention is not limited to this, and it is sufficient that at least the tip portion 8 a and the crushing portion 8 c of the bonding wire 8 are not parallel to the longitudinal direction of the emitter electrode 15.
[0064]
In the above-described embodiment, the configuration using the IGBT chip 1 as the semiconductor chip has been described. However, the present invention is not limited to this, and the configuration using a vertical bipolar transistor or a vertical DMOSFET as the semiconductor chip. It can also be applied to. When a DMOSFET is used, the DMOSFET can incorporate a parasitic diode having the same function as that of the FWD chip, so that the FWD chip is not necessary.
[0065]
Moreover, in the said embodiment, although the double-sided heat dissipation structure which has arrange | positioned the thermal radiation members 4 and 5 to both surfaces of the semiconductor chips 1 and 2 was demonstrated, it is not restricted to this, Only the single side | surface of the semiconductor chips 1 and 2 is especially The present invention can also be applied to a single-sided heat dissipation structure in which a heat dissipation member is disposed on the main surface side.
[0066]
The semiconductor chip may be anything other than a transistor as a power element as long as an electrode pad is formed on the surface thereof. Further, the present invention can be applied to a semiconductor device that is not molded with resin.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2A is a view of the AA plane in FIG. 1 as viewed from the direction of the arrow, and FIG. 2B is an enlarged view of a portion E in FIG.
FIG. 3 is an enlarged view of a portion B in FIG.
4 is a process diagram showing a manufacturing method of the semiconductor device shown in FIG. 1; FIG.
FIG. 5 is a schematic cross-sectional view of a conventional semiconductor device.
6 is a view of the CC plane in FIG. 4 as viewed from the direction of the arrow.
7 is an enlarged view of a portion D in FIG. 4;
[Explanation of symbols]
1 ... IGBT chip (semiconductor chip),
2 ... FWD chip (semiconductor chip)
3 ... heat sink block (block),
4 ... 1st heat radiating member (base),
5 ... 2nd heat radiating member (heat radiating member),
1a, 2a, 3a, 4a, 5a ... the surface of each member,
1b, 2b, 3b, 4b, 5b ... the back surface of each member,
6 ... solder (joining member),
7: Control terminal,
8: Bonding wire,
8a: the main body of the bonding wire,
8b: the tip of the bonding wire,
8c ... Collapsed part,
9 ... resin,
10 ... Work,
12 ... Weight,
13 ... Spacer,
14 ... Gate electrode pad,
15: Emitter electrode.

Claims (8)

半導体チップと、この半導体チップにおける一方の面の所定領域に設けられた素子領域と、この素子領域の周辺部に形成された電極パッドとを備え、前記電極パッドと外部とを複数のボンディングワイヤにより電気的に接続した半導体装置において、
前記複数のボンディングワイヤは、前記電極パッドと接続された部位より前記外部側の部分である本体部とそれ以外の部分である先端部とで構成されており、
前記本体部は前記素子領域における前記電極パッドと対向する一面に向って延在しているとともに、前記先端部は前記本体部に対して前記素子領域における前記電極パッドと対向する一面と略平行に折れ曲がっていることを特徴とする半導体装置。A semiconductor chip; an element region provided in a predetermined region on one surface of the semiconductor chip; and an electrode pad formed in a peripheral portion of the element region. The electrode pad and the outside are connected by a plurality of bonding wires. In electrically connected semiconductor devices,
The plurality of bonding wires are composed of a main body portion that is a portion on the outer side than a portion connected to the electrode pad and a tip portion that is the other portion,
The main body portion extends toward one surface facing the electrode pad in the element region, and the tip portion is substantially parallel to the one surface facing the electrode pad in the element region with respect to the main body portion. A semiconductor device which is bent. 半導体チップと、この半導体チップにおける一方の面の所定領域に設けられた素子領域と、この素子領域の周辺部に形成された電極パッドとを備え、前記電極パッドと外部とを複数のボンディングワイヤにより電気的に接続した半導体装置において、
前記複数のボンディングワイヤは、前記電極パッドと接続された部位より前記外部側の部分である本体部とそれ以外の部分である先端部とで構成されており、
前記ボンディングワイヤは、その一端は前記電極パッドに接続されているとともに、その他端は制御用端子に接続されており、前記半導体チップにおける前記電極パッドが形成された面には、前記制御用端子との間に前記電極パッドが配置するような領域にブロックが接続されており、前記制御用端子と前記電極パッドを結ぶ直線上に前記ブロックが位置しているものであって、
前記ボンディングワイヤの先端部の折れ曲がっている方向が、前記ブロックにおける前記制御用端子及び前記電極パッドと対向する側壁面と略平行であることを特徴とする半導体装置。 A semiconductor chip; an element region provided in a predetermined region on one surface of the semiconductor chip; and an electrode pad formed in a peripheral portion of the element region. The electrode pad and the outside are connected by a plurality of bonding wires. In electrically connected semiconductor devices,
The plurality of bonding wires are composed of a main body portion that is a portion on the outer side than a portion connected to the electrode pad and a tip portion that is the other portion,
The bonding wire has one end connected to the electrode pad and the other end connected to a control terminal. The surface of the semiconductor chip on which the electrode pad is formed is connected to the control terminal. A block is connected to a region where the electrode pad is disposed between, and the block is located on a straight line connecting the control terminal and the electrode pad,
Wherein a direction in which bent the leading end portion of the bonding wire, is substantially parallel to the said control terminal and the electrode pads facing the side wall surface of the block. 前記制御用端子は、前記ボンディングワイヤの本体部の延在方向と略平行に延在していることを特徴とする請求項２に記載の半導体装置。  The semiconductor device according to claim 2, wherein the control terminal extends substantially parallel to an extending direction of a main body portion of the bonding wire. 前記半導体チップには縦型の電力素子が形成されており、この縦型の電力素子における一方の主電極は前記ブロックを介して放熱部材と電気的に接続され、前記縦型の電力素子における他方の主電極は基台と電気的に接続され、前記縦型の電力素子における制御電極は前記電極パッドと電気的に接続されていることを特徴とする請求項２又は３に記載の半導体装置。  A vertical power element is formed on the semiconductor chip, and one main electrode of the vertical power element is electrically connected to a heat radiating member through the block, and the other of the vertical power element is 4. The semiconductor device according to claim 2, wherein the main electrode is electrically connected to a base, and a control electrode in the vertical power element is electrically connected to the electrode pad. 5. 前記半導体装置において、前記電極パッドは複数形成されるとともに、前記縦型の電力素子が複数の領域に区分けされていることを特徴とする請求項４に記載の半導体装置。  5. The semiconductor device according to claim 4, wherein a plurality of the electrode pads are formed and the vertical power element is divided into a plurality of regions. 前記ボンディングワイヤの先端部の折れ曲がっている方向が、前記素子領域の周辺部に形成された複数の前記電極パッドの整列方向と略平行であることを特徴とする請求項１乃至５の何れか１つに記載の半導体装置。  6. The bending direction of the tip end portion of the bonding wire is substantially parallel to the alignment direction of the plurality of electrode pads formed in the peripheral portion of the element region. The semiconductor device described in one. 前記ボンディングワイヤにおける先端部に形成された潰れ部は、その延在方向が前記ボンディングワイヤの折れ曲がっている方向とほぼ平行するように形成されていることを特徴とする請求項１乃至６の何れか１つに記載の半導体装置。  The crushing part formed at the tip of the bonding wire is formed so that its extending direction is substantially parallel to the direction in which the bonding wire is bent. The semiconductor device according to one. 前記複数の電極パッドは、その長手方向が前記ボンディングワイヤの折れ曲がっている方向とほぼ平行するように設けられていることを特徴とする請求項１乃至７の何れか１つに記載の半導体装置。  The semiconductor device according to claim 1, wherein the plurality of electrode pads are provided so that a longitudinal direction thereof is substantially parallel to a direction in which the bonding wire is bent.
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