JP3647753B2 - Frequency comparator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency comparator.
[0002]
[Prior art]
In the field of communications, the input of the receiver is only a random digital data signal, and no clock signal synchronized with the data bit rate is transmitted. However, since the data received on the receiving side has a waveform distorted in the transmission process as shown in FIG. 26, it is necessary to reproduce the signal using a clock synchronized with the bit rate of the data. In FIG. 26, the transmission data transmitted from the transmitter 1 reaches the receiver 2 while being distorted while passing through the transmission path. Therefore, the receiver 2 reproduces data using a clock synchronized with the bit rate.
[0003]
FIG. 27 shows the configuration of a general optical communication receiver. The optical communication receiver 10 includes an optical / electrical converter (PD) 3, an equalizing amplifier 4 that receives the output of the optical / electrical converter 3, and an identification circuit (DEC) that receives the output of the equalizing amplifier 4. 5 and a timing extraction circuit 6 for supplying a timing clock for reading to the identification circuit 5.
[0004]
The received signal photoelectrically converted by the optical / electrical converter 3 and amplified by the equalizing amplifier 4 is distributed to an identification circuit (decoder) 5 and a timing extraction circuit 6. The clock extracted by the timing extraction circuit 6 is input to the clock terminal of the identification circuit 5, and the distorted waveform is replayed to reproduce the data.
[0005]
The timing extraction circuit 6 is an essential circuit for signal reproduction, and in particular, a PLL circuit (Phase Lock Loop) is widely used because it is suitable for integration into an IC. A principle configuration diagram of the PLL circuit is shown in FIG. The PLL circuit requires a phase comparator 12 that compares the phases of the input signal and the internal clock, and a VCO (Voltage Control Oscillator) 11.
[0006]
In FIG. 28, the phase difference between the data / clock is detected by the phase comparator, the voltage applied to the oscillation frequency control terminal of the VCO 11 is changed according to the detected amount, and the oscillation frequency and phase of the VCO 11 are controlled. Frequency pull-in is realized.
[0007]
However, in a PLL circuit including only the phase comparator 12, when the frequency difference between the data bit rate and the oscillation frequency of the VCO 11 is large, such as when the power is turned on, the frequency cannot be pulled in and synchronized. Therefore, normally, as shown in FIG. 29, a frequency comparator for detecting a frequency difference is used together.
[0008]
FIG. 29 is a block diagram showing the configuration of the timing extraction circuit 6 having a frequency comparator. The same components as those in FIG. 28 are denoted by the same reference numerals. First, the switch SW is moved to the frequency comparator 13 side, the frequency of the input data is compared with the clock frequency of the VCO 11, and the operation is performed so that both frequencies coincide. When the frequency of the input data approaches the clock frequency of the VCO 11, the switch SW is moved to the phase comparator 12 side.
[0009]
Thus, in this circuit, a signal according to the frequency difference is obtained by the frequency comparator 13, and the oscillation frequency of the VCO 11 can be controlled by this signal to widen the frequency pull-in range. The frequency comparator 13 is essential for an actual PLL circuit. The present invention relates to this frequency comparator, and is characterized in that it operates even when the clock frequency is 1 / N (N is an arbitrary natural number) of the bit rate of data.
[0010]
[Problems to be solved by the invention]
The time division multiplexing system, which is one of the transmission systems, realizes a 1-bit signal with or without a short time pulse. Therefore, in order to increase the data capacity, it is necessary to transmit the data with a shorter time pulse train. Conventionally, electronic circuits and optical devices have been increased in speed and bandwidth. However, in recent years, this speed is about to reach 40 Gb / s or more, and the current situation is that the development of devices has not sufficiently caught up with the ultra-high speed operation required for electronic circuits. For this reason, it is difficult to apply the conventional PLL circuit including the frequency comparator as it is.
[0011]
There is data division widely used as a countermeasure. As shown in FIG. 30, a conventional technique can be applied to signal processing by dividing the data and reducing the bit rate. For example, if the signal is 40 Gb / s, it is divided into 2 to 20 Gb / s, 4 to 10 Gb / s, and 16 to 2.5 Gb / s. The part can be reduced.
[0012]
For this purpose, a PLL that operates even when the clock frequency is 1 / N of the data bit rate (N is an arbitrary natural number) as shown in FIG. 31 is required, and a frequency comparator for that purpose is also required. Become.
[0013]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a frequency comparator that compares a difference between a data bit rate and a 1 / N clock frequency.
[0014]
[Means for Solving the Problems]
(1) FIG. 1 is a principle block diagram of the present invention. In the figure, 13 is a frequency comparator. In FIG. 1, reference numeral 20 denotes an input change detection circuit for detecting a change in the state of a digital signal input from the outside, and 21 denotes an output from the input change detection circuit 20, and this change in state occurs during one cycle of the internal clock signal. A counter circuit that counts the number of times the signal is received, 23 is a reset signal generating circuit that receives a 1 / N (N is an arbitrary natural number) clock from the VCO and gives a reset signal to the counter circuit 21, and 22 is a count value of the counter circuit 21. A sampling circuit for sampling with a timing signal synchronized with an internal clock signal, 24 a timing signal generation circuit for receiving a 1 / N clock output and generating a timing signal for sampling the output of the sampling circuit 22, and 25 for the sampling A comparison circuit that compares the output of the circuit 22 with the predicted value, and the comparison circuit 25 Output enters the VCO as the frequency comparison signal (hereinafter, the same). Here, the predicted value refers to the number of change points that appear in one cycle of the VCO.
[0015]
With this configuration, the difference between the data bit rate and the 1 / N clock frequency can be compared.
(2) FIG. 2 is a block diagram showing a first configuration example of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the embodiment shown in FIG. 2, the input change detection circuit 20 shown in FIG. 1 is not used, and the rising or falling of the input signal is directly counted by the counter circuit 21.
[0016]
With this configuration, the difference between the data bit rate and the 1 / N clock frequency can be compared as in the case of (1).
(3) FIG. 3 is a block diagram showing a second configuration example of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The circuit shown in the figure is provided with an edge detection circuit 20 that detects a falling edge and a rising edge of a clock as an input change detection circuit.
[0017]
With this configuration, since the rising and falling edges of the clock are detected, the number of detections can be doubled, and the frequency comparison can be performed with only the most significant bit of the counter for an arbitrary number N. .
[0018]
FIG. 4 is a block diagram showing a third configuration example of the present invention. The same components as those in FIG. 1 are given the same reference numerals. This circuit uses a sampling unit 22a and a D / A conversion unit 22b that converts an output of the sampling unit 22a into an analog signal as a sampling circuit.
[0019]
With this configuration, the frequency difference of the internal clock signal with respect to the 1 / N frequency of the bit rate of the digital signal can be detected.
FIG. 5 is a block diagram showing a fourth configuration example of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. This circuit is obtained by adding a preset circuit 26 to the frequency comparison circuit of FIG. The preset circuit 26 receives the output of the reset signal generation circuit 23 and presets the counter circuit 21.
[0020]
With this configuration, it is possible to eliminate the need to set a predicted value by performing frequency comparison using only the most significant bit of the counter circuit 21.
FIG. 6 is a block diagram showing a fifth configuration example of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. This circuit is obtained by adding a preset value control circuit 27 for presetting a counter and controlling its value to the frequency comparison circuit of FIG. The preset value control circuit 27 receives the output of the reset signal generation circuit 23 and presets the counter circuit 21.
[0021]
With this configuration, it is possible to eliminate the need to set a predicted value by performing frequency comparison using only the most significant bit of the counter circuit 21.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
A normal external input signal has a random pattern, and the number of state changes in one cycle of the internal clock changes every moment. However, as shown in FIG. 32, when a normal random signal is viewed in a long cycle, the mark ratio of data “1” or “0” is ½, and the data is “1”. It is guaranteed that the density of change points changing from “0” or “0” to “1” is 0.5 (once every two bits). Therefore, the output level when averaged over a long period can be predicted as shown in FIG.
[0023]
FIG. 32 is an explanatory diagram of input change detection and predicted values. As shown in the figure, the input signal is a combination of “0” and “1”, the bit rate is f, the mark rate is 0.5, and the total is 24 bits. The rising point appears in 6 bits in 24 bits, the falling point appears in 6 bits in 24 bits, and the change point that is the sum of the rising point and the falling point appears in 12 bits in 24 bits.
[0024]
The expected count value when the clock to be used is 1 / N of f is as follows.
Rising point detection: N x 0.25
Change point detection: N x 0.5
FIG. 7 is a block diagram showing an embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. First, a change in state of an external input signal is detected by the input change detection circuit 20. Here, the change in the input state refers to a change in an edge such as rising or falling of data. Subsequently, the counter circuit 21 counts the number of input state changes of the external input signal for each cycle of the internal clock (1 / N clock).
[0025]
The value of the counter circuit 21 is sampled by a signal synchronized with the clock by the sampling circuit 22, and the value of the input state change number during one clock cycle is held for the time of one clock cycle. Next, the comparison circuit 25 compares the sampled value with the predicted value predicted from the input signal being a random pattern, and averages the difference to obtain a frequency comparison output, which is input to the VCO.
[0026]
FIG. 8 is a diagram showing the operation principle of the circuit shown in FIG. In (1), a change in the state of the input signal is detected. In (1), (a) shows the passage of time, (b) shows the external input signal, and (c) shows the output of the edge detection circuit. Since the input change detection circuit 20 detects the edges (rising and falling) of the input signal here, the input change detecting circuit 20 is as shown in (c).
[0027]
In (2), the number of input signals is counted for each cycle of the clock. In (2), (a) shows the passage of time, (b) shows the output of the edge detection circuit (input change detection circuit) 20, (c) shows the output of the counter circuit 21, and (d) shows the reset signal generation circuit. 23 shows reset signals output from 23 respectively. Here, the counter circuit 21 counts pulses that are the output of the edge detection circuit 20. The counter circuit 21 is reset to 0 each time a reset signal is input, and starts a new count. That is, the counter circuit 21 is reset at the clock cycle shown in (d).
[0028]
In (3), the counter value is sampled in one cycle of the clock. In (3), (a) shows the passage of time, (b) shows the output of the counter circuit 21, (c) shows the output of the sampling circuit 22, and (d) shows the timing signal which is the output of the timing signal generation circuit 24. Respectively.
[0029]
According to this embodiment, the difference between the data bit rate and the 1 / N clock frequency can be compared.
If the rising or falling edge of the data is detected, the input signal may be input directly to the counter circuit 21. An edge detection circuit is required to detect the change point density as an input change. Since the detection density is doubled by using the edge detection circuit, the predicted value is an integer or an integer +0.5 as shown in FIG. 32, and the frequency comparison is performed only for the most significant bit of the counter for an arbitrary N. Can
(Details will be described later).
[0030]
FIG. 9 is a diagram showing an embodiment of a frequency comparator configured on the basis of the above concept, and uses a D / A conversion circuit to convert a count signal into an analog signal. The same components as those in FIG. 7 are denoted by the same reference numerals. 10 is a time chart showing the operation of the A section (input change detection section), FIG. 11 is a time chart showing the operation of the B section (counter circuit), and FIG. 12 is a time chart showing the operation of the C section (sampling circuit). FIG. 13 is a time chart showing the operation of the D section (comparison circuit).
[0031]
The input change detection circuit 20 includes an exclusive OR (EXOR) gate 20a and a delay circuit 20b. Since the exclusive OR of the input signal and the delayed input signal is taken, the input change detection circuit 20 always detects the edge of the input signal.
[0032]
The counter circuit 21 is a 3-bit counter composed of three TF / Fs (flip-flops) 21a to 21c. These TF / Fs are configured such that the inverted signal of Q enters the clock input C of the next stage F / F. The parallel outputs of these TF / Fs are respectively input to the sampling circuit 22. The sampling circuit 22 includes a sampling unit 22a composed of three D type F / Fs and a D / A conversion unit 22b.
[0033]
Reference numeral 24 denotes a timing signal generation circuit for supplying a sampling signal to the sampling circuit 22, and is composed of an AND gate 24a and a delay circuit 24b. The 1 / N clock from the VCO enters the delay circuit 24b, and the AND of the output of the delay circuit 24b and the 1 / N clock is taken by the AND gate 24a. Will be. Here, N = 6. Then, the output of the AND gate 24a enters the sampling unit 22a as a latch pulse, and the output of the TF / F in the previous stage of each stage is latched in the D type F / F.
[0034]
On the other hand, since the output of the AND gate 24a enters the TF / F clear (CLR) input of each stage of the counter circuit 21 via the delay circuit 23 as a reset signal generation circuit, the output of the counter circuit 21 is sampled. After being latched by the circuit 22, the TF / Fs 21a to 21c are cleared.
[0035]
The D / A converter 22b is an adding circuit including a resistor that receives an output of the D type F / F and an operational amplifier U. The output of the first-stage D type F / F enters the operational amplifier U via a resistor having a resistance value of 4R, and the output of the second-stage D type F / F is supplied to the operational amplifier U via a resistor having a resistance value of 2R. The output of the third stage D type F / F enters the operational amplifier U via a resistor having a resistance value R. R is used as the resistance value of the feedback resistor of the adder circuit.
[0036]
The comparison circuit includes a comparator 25a and a low-pass filter (LPF) 25b that receives the output of the comparator 25a. The predicted value 3 is input to the other input of the comparator 25a. Therefore, the comparator 25a compares the output of the D / A converter 22b with the predicted value. The output of the comparator 25a is filtered by the low-pass filter 25b to become a frequency comparison signal, which is input to the VCO.
[0037]
In the figure, A is a time chart showing the operation of the input change detection circuit 20, B is a time chart showing the operation of the counter circuit 21, and C is a time chart showing the operation of the D / A converter 22b. D is a time chart showing the operation of the low-pass filter 25b.
[0038]
The circuit shown in FIG. 9 detects a change point as an input state change, and realizes frequency comparison with 1/6 clock. FIG. 14 shows a time chart when the clock frequency is equal to 1/6 of the bit rate of the input signal, and FIG. 15 shows a time chart when the clock frequency is higher than 1/6 of the bit rate of the input signal. In any case, the signals (a) to (q) shown in FIG. 9 correspond to the signals (a) to (q) shown in FIGS.
[0039]
The operation of this circuit will be described with reference to FIG. The input data (a) enters the edge detection circuit (input change circuit) 20 to obtain an output (b) in which the portion where the edge exists is converted into a pulse. The rising edge or falling edge of the pulse (b) is counted by the 3-bit counter circuit 21. Each bit output (c), (e), (g) of the counter is input to the corresponding D type F / F 22a to 22c, and by the input of the sampling timing signal (l), the bit of each bit at that moment is input. The output (0 or 1) is read.
[0040]
The outputs (h), (i), and (j) of the D type F / Fs 22a to 22c constituting the sampling circuit 22 are converted into analog signals (n) in the subsequent D / A converter 22b. This (n) and the predicted value (o) are compared, and the difference output (p) is smoothed by the low-pass filter 25b. The low-pass filter 25b may be disposed immediately after the D / A converter 22b. Since (q) that is finally output is an analog value, not only the three states of the clock frequency “high”, “equal”, and “low”, but also an advantage that information on how large the frequency difference is is obtained. There is.
[0041]
A circuit combining a delay circuit 24b and an AND gate 24a can be applied as the timing signal generation circuit, and the reset signal generation circuit 23 can be realized by a delay circuit that gives a slight delay time to the timing signal. Can do.
[0042]
In FIG. 14 where the clock frequency is equal to 1/6 of the data bit rate, the sampled output (n) is “33443233...”, The average output (q) is 0, and the frequency is equal.
[0043]
On the other hand, as shown in FIG. 15, when the clock frequency is higher, the output (n) is “2311321312141”, and the difference between the counter values and the predicted values is “3”. Thus, the output of the comparator 25a takes “0”, “−1”, and “−2”, and the average output (q) becomes “−1”, which indicates that the frequencies are not equal. In this example, the output of (q) can output a value of −3 to +4 according to the frequency difference.
[0044]
In the circuit of FIG. 9, a D / A conversion unit 22b that samples each bit of the counter circuit 21 and converts these sampling values into analog signals is required. However, there is a possibility that the scale of the circuit can be greatly simplified depending on the predicted value. As shown in FIG. 16, for example, when the predicted value is 5.5 (when the edge of the input signal is detected when N = 11), it is necessary to detect all bits of the counter in order to compare the clock frequencies. is there.
[0045]
However, assuming that the predicted value is 7.5, frequency comparison can be performed by detecting only the most significant bit, so that no other bit counter or D / A conversion circuit is required. In order to obtain the predicted value 7.5, the preset value “2” may be given at the time of reset. However, even if the change point is detected as shown in FIG. 17, the predicted value may be “integer + 0.5” or may be an integer. In the latter case, it is necessary to use a preset value control circuit as shown in FIG.
[0046]
FIG. 18 is a diagram showing an embodiment of a frequency comparator using a preset circuit. In this embodiment, N = 5 is used. The same components as those in FIG. 9 are denoted by the same reference numerals. In the figure, 20 is an input change detection circuit comprising a delay circuit 20b and an exclusive OR gate 20a, 21 is a counter circuit that counts the output of the input change detection circuit 20, and 22 is a latch of the output of the counter circuit 21. , A timing signal generating circuit for supplying a sampling signal to the sampling circuit 22, and a reset signal generating circuit for supplying a reset signal to the counter circuit 21.
[0047]
The circuit shown in FIG. 18 is applied when the predicted value is M + 0.5 (M is a natural number). When resetting, only a preset circuit that sets an appropriate preset value is required. First, a power of 2 greater than M + 0.5 is obtained. If this power number is P, the predicted value of the most significant bit is 0.5 by setting the preset value to P-M-1. 19 and 20 show time charts showing the operation of this circuit. FIG. 19 is a time chart when the clock frequency is equal to 1/5 of the bit rate of the input signal, and FIG. 20 is a time chart when the clock frequency is lower than 1/5 of the bit rate of the input signal. (A) to (j) of the circuit shown in FIG. 18 correspond to (a) to (j) of the circuits shown in FIGS.
[0048]
In FIG. 19, where the clock frequency is equal to 1/5 of the data bit rate, the predicted value M = 2.5. The power of 2 larger than this is 4 = 2 ^ (3-1), and a 3-bit counter configuration is adopted. Since the preset value is 001, the reset signal input of the least significant bit counter is used as a preset terminal. The most significant bit counter output (f) thus obtained is “0101010101...”, And the average output (j) is 0.5.
[0049]
On the other hand, when the clock frequency is lower as shown in FIG. 20, the output (f) is “01110111...” And the average output (j) is almost 1. Therefore, it can be detected that the clock frequency is low. it can.
[0050]
When the predicted value is M (M is a natural number), a preset value control circuit is required. As the preset value control circuit, for example, a circuit having a configuration shown in FIG. 21 is used. FIG. 21 is a diagram showing an embodiment of the preset value control circuit. In the figure, 28 is a reset signal generation circuit that receives a 1 / N clock and generates a reset signal, and 27 is a preset value control circuit that receives the output of the reset signal generation circuit 23. The preset value control circuit 27 includes a TF / F 27a and AND gates 27b and 27c. 27a is a TF / F that receives the clock input (g) at the input terminal C, and its Q output (j) is applied to the AND gate 27c. The output (i) of the reset signal generation circuit 28 is input to the AND gate 27b. An inverted signal (k) of Q of the TF / F 27a is input to the other input of the AND gate 27b, and an output (i) of the reset signal generation circuit 23 is input to the other input of the AND gate 27c. Yes.
[0051]
FIG. 22 is a time chart showing the operation of the preset value control circuit shown in FIG. In the figure, (g) is a 1 / N clock, (i) is a reset signal, (j) and (k) are output waveforms of the TF / F 27a, (l) is a clear signal (CLR), (m ) Indicates a preset signal. The 1 / N clock enters the TF / F 27a and is divided by ½, but the Q output of the TF / F 27a and its inverted output are alternately generated and enter the AND gates 27b and 27c. Then, a clear (CLR) signal and a preset (PR) signal are alternately generated and input to the counter circuit 21. Accordingly, the counter circuit 21 repeats the count operation and the clear operation at a cycle of 1 / N.
[0052]
When the clock signal is input to the TF / F 27a, a clock divided by ½ is obtained. When this clock and a normal reset signal are input to the AND gates 27b and 27c, the reset signal alternately appears in the outputs (l) and (m) every clock cycle. By connecting the outputs (l) and (m) to the clear terminal (CLR) and the preset terminal (PR) of the counter circuit 21, the preset values are set to 000 and 001 for each cycle of the clock. On the average, the most significant bits when they are equal alternate between 0 and 1. Therefore, the predicted value is 0.5.
[0053]
FIG. 23 is a diagram showing an embodiment of a frequency comparator using a preset value control circuit. The same components as those in FIGS. 18 and 21 are denoted by the same reference numerals. This embodiment shows a case where N = 6. In this embodiment, a preset value control circuit 27 shown in FIG. 21 is added to the circuit shown in FIG.
[0054]
The preset value control circuit 27 includes a T-FF 27a that receives the 1 / N clock, and AND gates 27b and 27c that receive the output of the T-FF 27a and the output of the reset signal generation circuit 26. The output of the AND gate 27b is connected to the preset input terminal PR of the first stage T-FF 21a of the counter circuit 21, and the output of the AND gate 27c is connected to the clear input terminal CLR of the first stage T-FF 21a.
[0055]
In the frequency comparison operation of this circuit, a time chart when the clock frequency is equal to 1/6 of the bit rate of the input signal is shown in FIG. 24 when the clock frequency is higher than 1/6 of the bit rate of the input signal. A time chart is shown in FIG. Signals (a) to (n) in FIG. 23 correspond to (a) to (n) in FIGS. 24 and 25, respectively.
[0056]
In FIG. 24 where the clock frequency is equal to 1/6 of the data bit rate, the predicted value M = 3. The power of 2 larger than this is 4 = 2 ^ (3-1), and a 3-bit counter configuration is adopted. The counter output (f) of the most significant bit obtained in this way is “001110110...”, And the average output (n) is 0.5 (an intermediate value between the “H” level and the “L” level).
[0057]
On the other hand, when the clock frequency is higher as shown in FIG. 25, the output (f) is “0000000001...” And the average output (n) is almost 0, so that it is detected that the clock frequency is high. Can do.
[0058]
(Supplementary note 1) An input change detection circuit for detecting a change in the state of a digital signal input from the outside, a counter circuit for counting the number of times this state change occurs in one cycle of the internal clock signal, and a count value of the counter circuit Sampling circuit that samples with a timing signal synchronized with the internal clock signal, and the sampled count value This is the number of change points that appear during one cycle of the VCO. 1 / N (N is an arbitrary natural number) frequency of the bit rate of the external input digital signal. The predicted count value A frequency comparator for detecting a frequency difference between internal clock signals as compared with the above.
[0059]
(Additional remark 2) The frequency comparator of Additional remark 1 characterized by counting the number of the rising or falling edge of a pulse instead of the said input change detection circuit.
(Supplementary note 3) The frequency comparator according to supplementary note 1, wherein an edge detection circuit is used as the input change detection circuit, and the number of both rising and falling edges of the pulse is counted as the state change of the input signal.
[0060]
(Supplementary note 4) The frequency comparator according to supplementary note 1, wherein the output of the sampling circuit is D / A converted and analog-output to a comparison circuit.
(Additional remark 5) The frequency comparator of Additional remark 1 characterized by adding the preset circuit which presets data to the said frequency comparator, and performing a frequency comparison only by the most significant bit of a counter.
[0061]
(Supplementary note 6) The preset value control circuit for presetting and controlling the value of the counter is added to the frequency comparator, and the frequency comparison is performed using only the most significant bit of the counter. Frequency comparator.
[0062]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to the first aspect of the present invention, the difference between the bit rate of data and the frequency of 1 / N clock can be compared.
[0063]
(2) According to the invention described in claim 2, as in the case of claim 1, the difference between the bit rate of data and the frequency of 1 / N clock can be compared.
(3) According to the invention described in claim 3, since the rising and falling edges of the clock are detected, the number of detections can be doubled, and more accurate operation is possible.
[0064]
In the present invention, the output of the sampling circuit is D / A converted and analog output to the comparison circuit, so that the frequency difference of the internal clock signal with respect to the 1 / N frequency of the bit rate of the digital signal can be detected.
[0065]
Further, in the present invention, a preset circuit for presetting data is added to the frequency comparator, and the frequency comparison is performed only with the most significant bit of the counter, so that the frequency comparison is performed with only the most significant bit of the counter circuit. Setting of a value can be made unnecessary.
[0066]
Further, in the present invention, by adding a preset control circuit for presetting the counter value to the frequency comparator and performing the frequency comparison only with the most significant bit of the counter, the frequency comparison is performed only with the most significant bit of the counter circuit. The setting of the predicted value can be made unnecessary.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a block diagram showing a first configuration example of the present invention.
FIG. 3 is a block diagram showing a second configuration example of the present invention.
FIG. 4 is a block diagram showing a third configuration example of the present invention.
FIG. 5 is a block diagram showing a fourth configuration example of the present invention.
FIG. 6 is a block diagram showing a fifth configuration example of the present invention.
FIG. 7 is a block diagram showing an exemplary embodiment of the present invention.
FIG. 8 is a diagram showing an operation principle of the present invention.
FIG. 9 is a diagram illustrating an embodiment of a frequency comparator using a D / A conversion circuit.
FIG. 10 is a time chart showing the operation of part A.
FIG. 11 is a time chart showing the operation of part B.
FIG. 12 is a time chart showing the operation of part C.
FIG. 13 is a time chart showing the operation of the D section.
FIG. 14 is a time chart when the data bit rate is equal to the 1 / N clock frequency.
FIG. 15 is a time chart when the data bit rate is smaller than the 1 / N clock frequency.
FIG. 16 is an explanatory diagram of frequency comparison using only the most significant bit.
FIG. 17 is an explanatory diagram of a difference in predicted values due to an input change.
FIG. 18 is a diagram illustrating an embodiment of a frequency comparator using a preset circuit.
FIG. 19 is a time chart when the data bit rate is equal to the 1 / N clock frequency.
FIG. 20 is a time chart when the data bit rate is higher than 1 / N clock frequency.
FIG. 21 is a diagram illustrating an embodiment of a preset value control circuit.
FIG. 22 is a time chart showing the operation of the preset value control circuit;
FIG. 23 is a diagram illustrating an embodiment of a frequency comparator using a preset value control circuit.
FIG. 24 is a time chart when the data bit rate is equal to the 1 / N clock frequency.
FIG. 25 is a time chart when the data bit rate is equal to the 1 / N clock frequency.
FIG. 26 is an explanatory diagram of data distortion due to communication;
FIG. 27 is an explanatory diagram of data reproduction by communication.
FIG. 28 is a diagram illustrating a configuration example of a timing extraction circuit.
FIG. 29 is a block diagram illustrating a configuration of a timing extraction circuit including a frequency comparator.
FIG. 30 is an explanatory diagram of frequency division of data.
FIG. 31 is a diagram illustrating a receiver configuration using a 1 / N divided clock of input data.
FIG. 32 is an explanatory diagram of input change detection and predicted values;
[Explanation of symbols]
13 Frequency comparator
20 Input change detection circuit
21 Counter circuit
22 Sampling circuit
23 Comparison circuit
24 Timing signal generation circuit
25 Comparison circuit

Claims (3)

An input change detection circuit for detecting a change in state of a digital signal input from the outside;
A counter circuit that counts the number of times this state change occurs in one cycle of the internal clock signal;
A sampling circuit that samples a count value of the counter circuit with a timing signal synchronized with an internal clock signal;
A comparison circuit that compares the sampled count value with an expected count value that is the number of change points that appear during one cycle of the VCO ;
A frequency comparator for detecting a frequency difference of an internal clock signal by comparing a 1 / N (N is an arbitrary natural number) frequency of a bit rate of an external input digital signal with the predicted count value . 2. The frequency comparator according to claim 1, wherein the number of rising or falling edges of the pulse is counted instead of the input change detection circuit. 2. The frequency comparator according to claim 1, wherein an edge detection circuit is used as the input change detection circuit, and the number of both rising and falling edges of the pulse is counted as a state change of the input signal.

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