JP3644413B2 - Element and wiring arrangement determination method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arrangement determination method for determining arrangement of elements and wirings in designing an electronic circuit. In particular, the present invention relates to an arrangement determining method for determining the arrangement of elements and wirings in the design of a semiconductor integrated circuit.
[0002]
[Prior art]
In an electronic circuit such as a semiconductor integrated circuit, crosstalk occurs between wirings due to capacitive coupling of wirings connecting elements such as cells. Such crosstalk will be described with reference to FIG. FIG. 7 is a diagram showing a part of a conventional semiconductor integrated circuit. In FIG. 7, the semiconductor integrated circuit 40 includes cells 41 to 44. The output of the cell 41 and the input of the cell 42 are connected by a wiring 45, and the output of the cell 43 and the input of the cell 44 are connected by a wiring 46. In this example, it is assumed that the wirings 45 and 46 are capacitively coupled.
In this semiconductor integrated circuit 40, when the signal output from the cell 41 to the wiring 45 is constant and the signal output from the cell 43 to the wiring 46 changes, the wiring changes at the timing of signal change on the wiring 46. Noise is generated on 45. Further, when the first signal output from the cell 41 to the wiring 45 and the second signal output from the cell 43 to the wiring 46 change at close timing, either the first signal or the second signal is output. Compared with the case where one signal does not change, the delay amount of the first or second signal varies, and the change of the first or second signal becomes faster or slower.
In a conventional semiconductor integrated circuit or the like, there has been a problem that noise and delay fluctuations due to crosstalk as described above cause malfunction of the semiconductor integrated circuit or the like.
[0003]
In order to prevent the above problems, a V _SS (ground potential) line has been arranged between the capacitively coupled wirings. However, since there are generally many capacitively coupled wirings in a semiconductor integrated circuit, the chip size becomes very large if _Vss lines are arranged between all capacitively coupled wirings.
[0004]
In addition, as a technique for preventing noise due to the above-described crosstalk, Japanese Patent Application Publication (JP-A) No. 10-308451 (hereinafter also referred to as “Document 1”) includes a plurality of logic functions. Layout of a semiconductor integrated circuit having a multilayer wiring structure in which standard cells, gate array cells, or functional block cells are automatically arranged, and a plurality of cells are connected to perform automatic wiring by inputting a net list satisfying a desired logical function. In the process, each wiring capacity is calculated after automatic wiring, a crosstalk reference value for adjacent wiring is set, and a part of wiring exceeding the reference value is converted to another layer and rewiring is performed. The wiring method is published. By performing automatic wiring using the automatic wiring method described in this document 1, it is possible to reduce crosstalk noise.
[0005]
On the other hand, in order to prevent the signal delay (crosstalk delay) due to the above-mentioned crosstalk, Japanese Patent Application Laid-Open No. 9-147909 (hereinafter also referred to as “Document 2”) discloses one source gate and one sink gate. The allowable value of the crosstalk delay value by the adjacent parallel wiring formed by the target path constituted by the adjacent path constituted by one source gate and one sink gate is obtained, and the upper limit value of the allowable value Specify the upper limit value of the length of adjacent parallel lines that can be placed by the source gate driver viability as the parameter between adjacent lengths, which is the length from the output point of the source gate of the target path to the start point of the adjacent parallel lines. A step of forming a function table for giving a function, a step of selecting a target path to be extracted from the upper limit value, Extracting the adjacent length of the selected path of interest and the driver viability of the source gate of the path of interest, selecting a function from the function table from the extracted driver viability, and adding the selected function to the above Calculating the upper limit of the parallel wiring length by substituting the extracted adjacent length, and determining the upper limit value of the adjacent parallel wiring satisfying the above-mentioned allowable value, etc. Is posted. The parallel wiring length limiting method described in this document 2 is to obtain the upper limit value of adjacent parallel wiring that satisfies the allowable value of the crosstalk delay value, so that the upper limit value of the adjacent path or adjacent path is not exceeded. By performing wiring, the allowable value of the crosstalk delay value can be satisfied.
[0006]
By the way, generally, in a semiconductor integrated circuit, the current drive capability of all cells is rarely the same. Further, there are cases where cells having the same function have about five types having different current driving capabilities. The crosstalk increases as the difference in current drive capability between cells that output signals to the respective capacitively coupled wires increases.
However, in the automatic wiring method described in Document 1 and the parallel wiring length limiting method described in Document 2, no consideration is given to the current drive capability of the cell.
Further, in the automatic wiring method described in Document 1, since a part of the wiring exceeding the crosstalk reference value is converted into another layer and rewiring is performed, the execution is not easy.
[0007]
[Problems to be solved by the invention]
Therefore, in view of the above points, the present invention provides an element and a wiring that can easily reduce crosstalk by determining the arrangement of the elements and the wiring that connects the elements according to the current driving capability of the elements. It is an object of the present invention to provide a method for determining the arrangement of
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the element and wiring arrangement determining method according to the first aspect of the present invention determines the arrangement of a plurality of elements and the arrangement of wirings connecting them according to a reference lattice. A method for determining the arrangement of elements and wirings, wherein a step (a) for extracting an element having the same current driving capability from a plurality of elements and a wiring for outputting a signal from the element extracted in step (a) are provided. (B) determining the arrangement of a plurality of elements and wirings so as to pass through adjacent reference grids.
[0009]
In addition, the element and wiring arrangement determining method according to the second aspect of the present invention determines the arrangement of a plurality of elements and the arrangement of wirings connecting between them according to the reference grid. A determination method comprising: (a) determining an initial arrangement of a plurality of elements and wirings; and extracting adjacent wirings that are a set of wirings that pass through an adjacent reference lattice from among the wirings determined to be arranged The step (b) of comparing the current driving capability of each element that outputs a signal to the adjacent wiring and the current driving capability of each element that outputs a signal to the adjacent wiring are different from each other. Each element other than the element having the maximum current drive capability among the elements that output a signal to each other has the same function as the element, and has the maximum current drive capability among the elements that output a signal to the adjacent wiring. The same current drive as the current drive capability of the device Comprising a step (d) replacing each element having a capability.
[0010]
In addition, the element and wiring arrangement determining method according to the third aspect of the present invention determines the arrangement of a plurality of elements and the arrangement of wirings connecting between them according to the reference lattice. A determination method comprising: (a) determining an initial arrangement of a plurality of elements and wirings; and extracting adjacent wirings that are a set of wirings that pass through an adjacent reference lattice from among the wirings determined to be arranged The step (b) of comparing the current driving capability of each element that outputs a signal to the adjacent wiring and the current driving capability of each element that outputs a signal to the adjacent wiring are different from each other. A step (d) of widening the interval between the adjacent wirings in accordance with the difference in the current driving ability of each element that outputs a signal.
[0011]
According to the element and wiring arrangement determination method configured as described above, the crosstalk can be easily reduced by determining the arrangement of the elements and the wirings connecting between the elements according to the current driving capability of the elements. Can do.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a flowchart showing a method for determining the arrangement of elements and wirings according to the first embodiment of the present invention. In the present embodiment, the arrangement of elements and wirings is determined according to a predetermined reference grid (grid).
[0013]
FIG. 2 is a diagram showing an apparatus for executing the element and wiring arrangement determining method according to the present embodiment. As shown in FIG. 2, the apparatus 10 includes an input unit 11, a netlist reception unit 12, an identical current driving capability cell extraction unit 13, an arrangement determination unit 14, a verification unit 15, and a display unit 16. Contains.
[0014]
Hereinafter, the element and wiring arrangement determining method according to the present embodiment will be described with reference to FIGS. 1 and 2.
First, when a designer of a semiconductor integrated circuit inputs a net list, which is data indicating cell functions and types, connection relationships between cells, and the like, to the input unit 11 of the apparatus 10, the net list receiving unit 12 of the apparatus 10 The received netlist is received (step S101). The device 10 may read a net list from a flexible disk, MO, or the like, or may receive a net list from another device via a network.
[0015]
When the netlist is input, the same current drivability cell extraction unit 13 extracts cells having the same current drivability from the cells described in the netlist (step S102).
Next, the arrangement determining unit 14 determines the arrangement of the cells and the wirings according to the grid so that the wiring for outputting a signal from the cell extracted in step S102 passes through the adjacent grid (step S103). Note that three or more wirings may be arranged adjacent to each other.
[0016]
After the arrangement of the cells and wirings is determined, the verification unit 15 performs verification such as crosstalk (step S104). Note that, when crosstalk or the like exceeding a predetermined standard is detected in the verification, steps S102 to S104 may be repeated.
After the verification is completed, the display unit 16 displays a layout based on the determined cell and wiring arrangement (step S105). Note that the apparatus 10 may print the layout, record it on a flexible disk, an MO, or the like, or send it to another apparatus via a network.
[0017]
As described above, in the element and wiring arrangement determination method according to the present embodiment, cells having the same current driving capability are extracted from the cells described in the netlist, and the extracted cells output signals. Since the arrangement of the cells and the wiring is determined so that the wiring to be passed passes through the adjacent grid, crosstalk can be reduced.
[0018]
Next, a second embodiment of the present invention will be described. FIG. 3 is a flowchart showing a method for determining the arrangement of elements and wirings according to the second embodiment of the present invention. In the present embodiment, the arrangement of elements and wirings is determined according to a predetermined grid.
[0019]
FIG. 4 is a diagram showing an apparatus for executing the element and wiring arrangement determining method according to the present embodiment. As shown in FIG. 4, the apparatus 20 includes an input unit 11, a netlist reception unit 12, an initial placement determination unit 21, an adjacent wiring extraction unit 22, a current drive capability comparison unit 23, and a cell replacement unit 24. And a verification unit 15 and a display unit 16.
[0020]
Hereinafter, the element and wiring arrangement determination method according to the present embodiment will be described with reference to FIGS. 3 and 4.
First, when the designer inputs a net list to the input unit 11 of the device 20, the net list receiving unit 12 of the device 20 receives the input net list (step S201).
When the netlist is input, the initial placement determining unit 21 determines the initial placement of cells and wirings according to the grid (step S202).
[0021]
Next, in step S203, the adjacent wiring extraction unit 22 checks whether there is an adjacent wiring that is a wiring passing through the adjacent grid. If there is an adjacent wiring, the process proceeds to step S204. If there is no adjacent wiring, the process proceeds to step S206.
If it is determined in step S203 that there is an adjacent wiring, in step S204, the current driving capability comparison unit 23 checks whether the current driving capability of the cells that output signals to the adjacent wiring is the same. . If the current driving capability of the cells that output signals to the adjacent wirings is the same, the crosstalk that occurs between the adjacent wirings is considered to be small, and the process moves to step S206. On the other hand, when the current driving capabilities of the cells that output signals to the adjacent wirings are not the same, it is considered that the crosstalk generated between the adjacent wirings is large, and thus the process proceeds to step S205.
[0022]
If it is determined in step S204 that the current driving capabilities of the cells that output signals to the adjacent wiring are not the same, in step S205, the cell replacement unit 24 performs current driving in the cells that output signals to the adjacent wiring. A cell having a small capacity is replaced with a cell having the same function as that of the cell and having the same current driving capacity as a cell having a large current driving capacity among cells that output signals to adjacent wirings. Even when three or more wirings are adjacent to each other, each cell other than the cell having the maximum current driving capability among the cells outputting signals to these wirings has the same function as each cell. Each cell that outputs a signal to the adjacent wiring can be replaced with a cell having the same current drive capability as that of the cell having the maximum current drive capability. Thereafter, the process returns to step S204.
[0023]
After the adjacent wiring check is completed in steps S203 to S205, the verification unit 15 verifies crosstalk or the like (step S206). If crosstalk exceeding a predetermined standard is detected in the verification, steps S202 to S205 may be repeated.
After the verification is completed, the display unit 16 displays a layout based on the determined cell and wiring arrangement (step S207).
[0024]
As described above, in the element and wiring arrangement determining method according to the present embodiment, after the cells and the wiring are initially arranged, the current driving ability of the cell that outputs a signal to the adjacent wiring is compared, and the signal is output to the adjacent wiring. Among the cells, a cell having a small current drive capability has the same function as the cell, and a cell having a current drive capability identical to that of a cell having a large current drive capability among cells that output signals to adjacent wirings Therefore, crosstalk can be reduced.
[0025]
Next, a third embodiment of the present invention will be described. FIG. 5 is a flowchart showing a method for determining the arrangement of elements and wirings according to the third embodiment of the present invention. In the present embodiment, the arrangement of elements and wirings is determined according to a predetermined grid.
[0026]
FIG. 6 is a diagram showing an apparatus for executing the element and wiring arrangement determining method according to the present embodiment. As shown in FIG. 6, the apparatus 30 includes an input unit 11, a netlist receiving unit 12, an initial arrangement determining unit 21, an adjacent wiring extracting unit 22, a current drive capability comparing unit 23, and a wiring arrangement correcting unit. 31, a verification unit 15, and a display unit 16.
[0027]
Hereinafter, the element and wiring arrangement determination method according to the present embodiment will be described with reference to FIGS. 5 and 6.
First, when the designer inputs a net list to the input unit 11 of the apparatus 30, the net list receiving unit 12 of the apparatus 30 receives the input net list (step S301).
When the netlist is input, the initial placement determining unit 21 determines the initial placement of cells and wirings according to the grid (step S302).
Next, in step S303, the adjacent wiring extraction unit 22 checks whether there is an adjacent wiring. If there is an adjacent wiring, the process proceeds to step S304. If there is no adjacent wiring, the process proceeds to step S306.
[0028]
If it is determined in step S303 that there is an adjacent wiring, in step S304, the current drive capability comparison unit 23 checks whether the current drive capability of the cells that output signals to the adjacent wires is the same. . If the current drive capability of the cells that output signals to the adjacent wirings is the same, the crosstalk that occurs between the adjacent wirings is considered to be small, and the process moves to step S306. On the other hand, if the current driving capabilities of the cells that output signals to the adjacent wirings are not the same, the crosstalk that occurs between the adjacent wirings is considered to be large, and the process moves to step S305.
[0029]
If it is determined in step S304 that the current driving capability of the cell that outputs a signal to the adjacent wiring is not the same, in step S305, the wiring placement correcting unit 31 outputs the current driving capability of the cell that outputs the signal to the adjacent wiring. The interval between adjacent wirings is widened in accordance with the difference. Even when three or more wirings are adjacent to each other, the interval between the wirings can be widened according to the difference in the current drive capability of each cell that outputs a signal to those wirings.
Thereafter, the process returns to step S303. Note that the adjacent wiring once checked in step S303 may not be checked again in step S303.
[0030]
After the adjacent wiring check is completed in steps S303 to S305, the verification unit 15 verifies crosstalk or the like (step S306). If crosstalk exceeding a predetermined standard is detected in the verification, steps S302 to S305 may be repeated.
Then, after the verification is completed, the display unit 16 displays a layout based on the determined cell and wiring arrangement (step S307).
[0031]
As described above, in the element and wiring arrangement determining method according to the present embodiment, after the cells and the wiring are initially arranged, the current driving ability of the cell that outputs a signal to the adjacent wiring is compared, and the signal is output to the adjacent wiring. Since the arrangement of the adjacent wiring is corrected according to the difference in the current driving ability of the cell, the crosstalk can be reduced.
[0032]
【The invention's effect】
As described above, according to the present invention, the crosstalk can be easily reduced by determining the arrangement of the elements and the wiring connecting the elements in accordance with the current driving capability of the elements.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an element and wiring arrangement determination method according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an apparatus for executing the element and wiring arrangement determining method according to the first embodiment of the present invention.
FIG. 3 is a flowchart showing a method for determining arrangement of elements and wirings according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating an apparatus for executing an element and wiring arrangement determination method according to a second embodiment of the present invention.
FIG. 5 is a flowchart showing a method for determining the arrangement of elements and wirings according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an apparatus for executing an element and wiring arrangement determination method according to a third embodiment of the present invention.
FIG. 7 is a diagram showing a part of a conventional semiconductor integrated circuit.
[Explanation of symbols]
10, 20, 30 Device 11 for executing element and wiring arrangement determination method 11 Input unit 12 Netlist reception unit 13 Same current drivability cell extraction unit 14 Arrangement determination unit 15 Verification unit 16 Display unit 21 Initial arrangement determination unit 22 Adjacent wiring extraction unit 23 Current drive capability comparison unit 24 Cell replacement unit 31 Wiring arrangement correction unit 40 Semiconductor integrated circuits 41 to 44 Cells 45 and 46 Wiring

Claims (3)

An element and wiring arrangement determining method for determining the arrangement of a plurality of elements and determining the arrangement of wirings connecting between them according to a reference grid,
Extracting an element having the same current driving capability from the plurality of elements (a);
A step (b) of determining the arrangement of the plurality of elements and the wiring so that the wiring from which the element extracted in step (a) outputs a signal passes through an adjacent reference lattice;
And a method for determining the arrangement of wirings. An element and wiring arrangement determining method for determining the arrangement of a plurality of elements and determining the arrangement of wirings connecting between them according to a reference grid,
Determining an initial placement of the plurality of elements and the wiring;
A step (b) of extracting adjacent wires, which are a set of wires passing through adjacent reference grids, among the wires determined to be arranged;
A step (c) of comparing the current drive capability of each element that outputs a signal to the adjacent wiring;
When the current drive capability of each element that outputs a signal to the adjacent wiring is different, each element other than the element having the maximum current drive capability among the elements that output a signal to the adjacent wiring has the same function as the element. And replacing each of the elements that output signals to the adjacent wiring with elements having the same current drive capability as the current drive capability of the element having the maximum current drive capability;
And a method for determining the arrangement of wirings. An element and wiring arrangement determining method for determining the arrangement of a plurality of elements and determining the arrangement of wirings connecting between them according to a reference grid,
Determining an initial placement of the plurality of elements and the wiring;
A step (b) of extracting adjacent wires, which are a set of wires passing through adjacent reference grids, among the wires determined to be arranged;
A step (c) of comparing the current drive capability of each element that outputs a signal to the adjacent wiring;
A step (d) of widening the interval between adjacent wirings according to the difference in current driving capability of each element outputting a signal to the adjacent wiring when the current driving capacity of each element outputting a signal to the adjacent wiring is different; ,
And a method for determining the arrangement of wirings.

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