JP3641063B2 - Macro library generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for generating a macro library used for layout design and design rule check of a semiconductor device.
[0002]
In recent years, semiconductor devices have been highly integrated, and the development period has been shortened. Accordingly, development of a large-scale macro circuit created using cells prepared in advance corresponding to logic elements having a predetermined function is required. Therefore, in order to use a macro in the layout design of a semiconductor device, it is necessary to be able to quickly cope with the generation of a macro library.
[0003]
[Prior art and problems to be solved by the invention]
  In order to create a macro, a logical description language defined by cell type information, macro pin information, net information in the macro, etc.Description data described by (hereinafter also referred to as “logical description language”)Is created. Based on this logic description language, the layout of the cells in the macro is performed, the wiring connecting the macro terminals and the cell terminals and the wiring connecting the cell terminals are performed, and the macro is created. The macro created in this way is registered in the file as a library and used for the layout design of the semiconductor device. The macro library is defined by a macro name, frame information indicating the area occupied by the macro, and macro terminal information. The macro terminal information includes a terminal attribute indicating what function the macro terminal has, an input load capacity and an output drive capability necessary for performing a logic simulation.
[0004]
Conventionally, the generation of a macro library is performed manually by a macro designer. For this reason, in particular, setting the terminal attribute is time-consuming and error-prone when a plurality of cell terminals are connected to the macro terminal. In addition, the macro input load capacity and output drive capability were roughly estimated values by the macro designer, so the accuracy of these values was inferior.
[0005]
The present invention has been made to solve the above-described problems, and an object of the present invention is to easily generate a macro library and to generate a highly reliable macro library without human error. .
[0006]
[Means for Solving the Problems]
  In order to achieve the above object, the invention of claim 1MaCell used in blackWhenNet in macroWhenDefined inAnd macroLogical description languageMore descriptive dataFor macros designed using cell library cells defined in cell terminal characteristics and attributes, the macro terminal characteristics and attributesIncludingA macro library generation device that generates a defined library,In the description dataCell basedofThe layoutBy runningThe wiring that connects the macro terminals and cell terminals is laid outA layout device for generating graphic data;About the macro terminal and the wiring connected to the macro terminalAs information composed of dataPhysical libraryGenerated based on the graphic dataPhysical libraryGenerationDevice and the wiring connected to the macro terminal based on the graphic data.wiringA wiring capacity extraction device for extracting the capacity;The physical library; andWiring capacityas well asBased on the characteristics of all cell terminals connected to the macro terminalSetMacro terminal characteristicsWhen,Based on the attributes of all cell terminals connected to the macro terminalSetMacro terminal attributesWhenTheGenerate a library by synthesisA library synthesizing apparatus.
[0007]
  The physical library creation device of the invention of claim 2 is the physical library.GenerationThe deviceFurther, the physical library is configuredPosition of macro terminal and wiring layer of wiring connected to macro terminalInformation aboutTheBased on the graphic dataExtract
  The library synthesizing device of the invention of claim 3Designed using cells in the cell library defined by the characteristics and attributes of the cell terminals based on the description data described in the macro's logical description language, defined by the cells used in the macro and the nets in the macro. A macro library generation device that generates a library defined for a macro that includes characteristics and attributes of a macro terminal, and executes a layout of the cell based on the description data, whereby a macro terminal and a cell terminal A layout device for generating graphic data in which wirings for connecting terminals are laid out, and a physical library as information configured to include data on macro terminals and wirings connected to the macro terminals based on the graphic data Generation capacity and wiring capacity of wiring connected to the macro terminal based on the graphic data A wiring capacitance extracting device for extracting, with the physical library, the characteristic of the first macro terminal that is set based on the characteristics of all the cell terminal connected to the wiring capacitance and the macro terminal,SaidDescriptive dataOn the basis of theRead from the cell library,Characteristics of all cell terminals connected to each macro terminalAnd a library synthesizing device that generates a library by synthesizing the characteristics of the second macro terminal reflecting the above and the attributes of the macro terminals set based on the attributes of all the cell terminals connected to the macro terminal.
[0008]
  The library synthesizing device of the invention of claim 4Designed using cells in the cell library defined by the characteristics and attributes of the cell terminals based on the description data described in the macro's logical description language, defined by the cells used in the macro and the nets in the macro. A macro library generation device that generates a library defined for a macro that includes characteristics and attributes of a macro terminal, and executes a layout of the cell based on the description data, whereby a macro terminal and a cell terminal A layout device for generating graphic data in which wirings for connecting terminals are laid out, and a physical library as information configured to include data on macro terminals and wirings connected to the macro terminals based on the graphic data Generation capacity and wiring capacity of wiring connected to the macro terminal based on the graphic data A wiring capacitance extracting device for extracting, with the physical library, the characteristics of the macro terminal is set based on the characteristics of all the cell terminal connected to the wiring capacitance and the macro terminal,SaidDescriptive dataOn the basis of theRead from the cell library,Attributes of all cell terminals connected to each macro terminalWas reflectedMacro terminalAnd a library synthesizing device for generating a library by synthesizing these attributes.
[0009]
(Function)
In the present invention, the characteristics of the macro terminal are calculated in detail and in a short time by calculating the characteristics of all the cells connected to the macro terminal and the wiring capacity of the wiring connecting the macro terminal and the cell terminal created in the macro layout. Can be calculated. Further, the attributes of the macro terminal can be easily extracted from the terminal attributes of all the cell terminals connected to the macro terminal.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a design system 10 for a semiconductor device (LSI). The system 10 includes a logical data file 1, a cell library file 2, a macro layout device 11, a graphic data file 3, a macro library generation device 12, a chip layout device 16 and a design rule check device 17 in this embodiment.
[0011]
The cell library file 2 stores cell data corresponding to various logic elements having a predetermined function. Examples of the logic element include an AND circuit, an OR circuit, a NOR circuit, an XOR (exclusive OR) circuit and the like in addition to the inverters 22 and 23 and the NAND circuit 24 shown in FIG. As shown in FIG. 3, the cell library file 2 stores data of cells 32 and 33 corresponding to the inverters 22 and 23 and data of a cell 34 corresponding to the NAND circuit 24. The data of each cell includes cell name data, cell terminal information, transistor pattern data constituting the cell, wiring pattern data constituting a net in the cell, and the like. Cell terminal information includes position information (numerical coordinate data or grid coordinate data) of each cell terminal, terminal type information (normal terminal, clock terminal, etc.), input load capacity information, and output drive capacity information. Including.
[0012]
The logic description file 1 stores a macro logic description language created by a macro designer. The logical description language is defined by macro name information, cell type information used in the macro, macro terminal information, and net information for connecting the macro terminal and the cell terminal. The macro terminal information includes information on the name of each macro terminal (character text information) and information on the terminal type of the macro terminal (input terminal, output terminal, or input / output terminal).
[0013]
FIG. 2 shows a macro 21 expressed in an example logical description language stored in the logical description file 1. In the macro 21, inverters 22 and 23 and a NAND circuit 24 as logic elements are used, and an input terminal A1 and an output terminal X1 as macro terminals are provided. The macro 21 includes a net N1 that connects the input terminal A1 and the input terminals of the inverters 22 and 23, a net N2 that connects the output terminal of the inverter 22 and one input terminal of the NAND circuit 24, and an output terminal of the inverter 23. And a net N3 for connecting the other input terminal of the NAND circuit 24 and a net N4 for connecting the output terminal of the NAND circuit 24 and the output terminal X1. Hereinafter, for convenience of explanation, it is assumed that the logical description file 1 stores the logical description language of the macro 21 shown in FIG.
[0014]
The macro layout device 11 includes a microprocessor and operates based on predetermined program data.
The macro layout device 11 reads the logic description language of the macro 21 from the logic description file 1, reads cell pattern data corresponding to various logic elements used in the logic description language from the cell library file 2, and reads the read data. Based on the obtained data, various cell pattern layouts are performed. Therefore, the data of the cells 32 and 33 corresponding to the inverters 22 and 23 are read from the cell library file 2, and the pattern of the cells 32 and 33 is laid out as shown in FIG. Similarly, the data of the cell 34 corresponding to the NAND circuit 24 is read from the cell library file 2, and the pattern of the cell 34 is laid out as shown in FIG.
[0015]
The macro layout apparatus 11 determines the position of each macro terminal based on the macro terminal information in the logic description language of the macro 21 and adds terminal name text pattern (character text) information to the determined position. Accordingly, as shown in FIG. 3, the positions of the input terminal A1 and the output terminal X1 are determined to be positions indicated by “·” based on the terminal information of the input terminal A1 and the output terminal X1, and the determined positions of the respective terminals. Are added with text pattern information “A1” and “X1”.
[0016]
Further, the macro layout apparatus 11 has a net wiring pattern for connecting terminals of various cells laid out based on net information in the logic description language of the macro 21, and a net wiring pattern for connecting the macro terminal and the cell terminal. Layout. A via pattern for connecting the wiring patterns is also laid out. Therefore, as shown in FIG. 3, wiring patterns L1, L2, and L3 that connect the input terminal A1, the input terminal 32A of the cell 32, and the input terminal 33A of the cell 33 are laid out based on the information of the net N1. Based on the information of the net N2, wiring patterns L4, L5, L6, L7, and L8 that connect the output terminal 32B of the cell 32 and the input terminal 34A of the cell 34 are laid out. Further, wiring patterns L9, L10, L11, L12, and L13 that connect the output terminal 33B of the cell 33 and the input terminal 34B of the cell 34 are laid out based on the information of the net N3. Further, the wiring pattern L14 that connects the output terminal X1 and the output terminal 34C of the cell 34 is laid out based on the information of the net N4. A via pattern for connecting the wiring patterns is also laid out, but not shown.
[0017]
Also, as shown in FIG. 3, the wiring layer pattern information “5” is added to the wiring pattern L1, and the wiring layer pattern information “10” is added to the wiring pattern L14. The wiring layer pattern information “5” and “10” indicate the first and second layers of the metal wiring layer, respectively.
[0018]
When the cell arrangement and the wiring are completed, the macro layout device 11 includes all the laid out cells and all the wiring patterns, and creates pattern information of a polygonal frame passing on the macro terminal. The frame pattern information includes position information (numerical coordinate data or grid coordinate data) of a plurality of vertices of the frame. The position of each vertex is represented by coordinates when an arbitrary vertex is used as the origin among a plurality of vertices. Accordingly, in FIG. 3, a rectangular frame 31 including the cells 32 to 34 and the wiring patterns L1 to L14 and passing on the input terminal A1 and the output terminal X1 is generated, and four apexes 31a, 31b, 31c, Pattern information is created based on the position information 31d.
[0019]
Then, the macro layout apparatus 11 stores the graphic data of the pattern layout result shown in FIG.
The macro library generation device 12 includes a physical library generation device 13, a physical library file 4, a wiring capacity extraction device 14, a net capacity list 5, a macro library synthesis device 15, and a macro library file 6.
[0020]
FIG. 4 shows the structure of the macro library file 6 in this embodiment, and storage areas 41 and 42 are provided for one macro. In addition, storage areas 43, 431, 432, 433, 434, 435, and 436 are provided for each macro terminal in the macro. That is, the storage area 41 stores macro name information, and the storage area 42 stores macro frame pattern information. The storage area 43 stores macro terminal name information (text pattern information), the storage area 431 stores macro terminal coordinate data, and the storage area 432 stores wiring layer pattern information. The storage area 433 stores the input load capacity data of the macro terminal, and the storage area 434 stores the output drive capacity data of the macro terminal. Further, the storage area 435 stores data of terminal type 1 indicating that the macro terminal is either an input terminal, an output terminal, or an input / output terminal, and the storage area 436 has what function the macro terminal has. Data of terminal type 2 indicating the terminal is stored.
[0021]
The physical library file 4 in this embodiment has a structure in which the storage areas 433 to 436 in the macro library file 6 are omitted.
The physical library generation device 13 includes a microprocessor, operates based on predetermined program data, and performs a physical library generation process shown in FIG. That is, the physical library generation device 13 extracts macro frame patterns, macro terminal coordinates, and wiring layers from the macro graphic data stored in the graphic data file 3, and stores the extracted data in the physical library file 4. To do.
[0022]
First, in step 51, the macro name information is stored in the storage area 41 shown in FIG. 4, the pattern information of the macro frame 31 is read from the graphic data, and the coordinates of each vertex are stored in the storage area 42.
[0023]
In step 52, the macro terminal text pattern information, the macro terminal coordinate data describing the terminal text pattern information, and the wiring layer pattern information are read from the graphic data, and the macro terminal text pattern information is stored in the storage area. 43, the macro terminal coordinate data is stored in the storage area 431, and the wiring layer pattern information is stored in the storage area 432.
[0024]
In step 53, it is determined whether there is an unprocessed macro terminal. If there is an unprocessed macro terminal, the process returns to step 52 and the process of step 52 is repeatedly executed. Step 52 is performed for all macro terminal texts.
[0025]
The wiring capacity extraction device 14 is also composed of a microprocessor, operates based on predetermined program data, and performs the wiring capacity extraction processing shown in FIG. That is, the wiring capacity extracting device 14 extracts the wiring capacity from the macro graphic data stored in the graphic data file 3 to the terminals of all the cells connected to the macro terminal, and uses the extracted wiring capacity. Store in the net capacity list 5.
[0026]
First, in step 61, all macro terminal text pattern information, all wiring pattern data, and all via pattern data are read from the graphic data and stored in a first table (not shown) prepared on the memory. Therefore, in FIG. 3, the information of the terminal text patterns A1 and X1, the information of the wiring patterns L1 to L14, and the via pattern are read out.
[0027]
In step 62, a second table (not shown) is prepared on the memory, and one terminal text pattern information among the macro terminal text pattern information of the first table is registered in the second table.
[0028]
In step 63, it is determined whether or not there is an unprocessed macro terminal. If there is an unprocessed macro terminal, the process proceeds to step 64. In step 64, a wiring pattern or a via pattern connected to the terminal text pattern A1 registered in the second table is searched from the first table, and the searched pattern is registered in the second table. In FIG. 3, the wiring pattern L1 connected to the terminal text pattern A1 is searched, and information on the wiring pattern L1 is registered in the second table.
[0029]
In step 65, a wiring pattern or a via pattern connected to the wiring pattern newly registered in the second table is searched from the first table, and the searched pattern is registered in the second table.
[0030]
In step 66, it is determined whether there is a newly registered wiring pattern or via pattern. If there is a newly registered wiring pattern or via pattern, the process returns to step 65 and the process of step 65 is repeatedly executed. In FIG. 3, the wiring patterns L2 and L3 connected to the wiring pattern L1 are searched.
[0031]
In step 67, the wiring capacity of one net is calculated by multiplying the area of the wiring pattern or via pattern registered in the second table by the unit wiring capacity. The calculated capacity value is output to the net capacity list 5 shown in FIG. 5 together with the macro terminal name registered in the second table.
[0032]
Thereafter, the processing of steps 62 to 67 is performed until the text pattern information of the macro terminal stored in the first table is exhausted.
The macro library synthesizing device 15 is composed of a microprocessor, operates based on predetermined program data, and performs the process of calculating the characteristics of the macro terminal shown in FIG. That is, the macro library synthesizing device 15 obtains information on input load capacities of all cell terminals (see FIG. 3) connected to the macro terminal from the cell library 2 based on the macro logic description language stored in the logic description file 1. The input load capacity of the macro terminal is calculated by reading and summing them. Further, the macro library synthesis device 15 reads the information of the output drive capability of all the cell terminals connected to the macro terminal from the cell library 2, and determines the smallest one of the output drive capabilities of these cell terminals as the output drive capability of the macro terminal. To do.
[0033]
The macro library synthesizing device 15 operates based on predetermined program data, and performs the macro terminal attribute recognition process shown in FIG. That is, the macro library synthesis apparatus 15 reads the terminal type described in the macro logic description language stored in the logic description file 1 and determines the terminal type 1 of the macro terminal. Further, the macro library synthesis device 15 reads from the cell library 2 the terminal type information of all the cell terminals (see FIG. 3) connected to the macro terminal based on the macro logic description language stored in the logic description file 1. The terminal type 2 of the macro terminal is determined. At this time, if the terminal types of the plurality of cell terminals are different, the terminal type 2 of the macro terminal is selected from the nature of the terminal type.
[0034]
Further, the macro library synthesizing device 15 operates based on predetermined program data, and performs the library synthesizing process shown in FIG. That is, the macro library synthesizing apparatus 15 inputs the macro terminal into the physical library file 4 by synthesizing the input load capacity information of all the cells connected to the macro terminal and the wiring capacity information stored in the net capacity list 5. The macro library file 6 is generated by combining the load capacity information, the macro terminal output drive capability information, and the terminal type 1 and 2 information.
[0035]
Next, the process of calculating the characteristics of the macro terminal performed by the macro library synthesis apparatus 15 will be described with reference to FIG.
First, in step 71, an unprocessed macro terminal is searched from the macro logic description language stored in the logic description file 1, and the searched macro terminal is stored in a table (not shown) prepared on the memory. To do. This table is provided with a storage area in which information on the input load capacity and information on the output drive capability can be set for the macro terminal. Therefore, in FIG. 3, the information of the macro terminal A1 (input terminal) is stored in the table.
[0036]
In step 72, it is determined whether or not there is an unprocessed macro terminal. If there is an unprocessed macro terminal, the process proceeds to step 73. In step 73, the wiring capacity information for the macro terminal A1 registered in the table is searched from the net capacity list 5, and the wiring capacity information “100” for the macro terminal A1 is set in the input load capacity storage area of the table.
[0037]
Next, in step 74, all cell terminals connected to the macro terminal A1 are searched based on the net described in the logic description language of the logic description file 1, and information on the input load capacity of each searched cell terminal is obtained as a cell. It is read from the library file 2 and its input load capacity is set by adding to the value already set in the storage area of the input load capacity of the table. In FIG. 3, a value obtained by adding the sum of the input load capacity of the cell terminal 32A and the input load capacity of the cell terminal 33A and the wiring capacity “100” is set in the storage area of the input load capacity.
[0038]
In step 75, the cell terminal connected to the macro terminal A1 is searched based on the net described in the logic description language of the logic description file 1, and the information of the output drive capability of each searched cell terminal is read from the cell library file 2. The information of the output drive capability is set in the output drive capability storage area of the table. At this time, the smaller value is set between the value already set in the storage area of the output drive capability of the table and the newly read output drive capability. The output drive capability value may be an average value of the output drive capability of all the cell terminals depending on the LSI technology. In FIG. 3, since the macro terminal A1 is an input terminal and the cell terminals 32A and 33A connected to the macro terminal A1 are input terminals, the output drive capability is “0”.
[0039]
Thereafter, the processes in steps 71 to 75 are performed for all the macro terminals described in the macro logic description language.
Next, macro terminal attribute recognition processing performed by the macro library synthesis apparatus 15 will be described with reference to FIG.
[0040]
First, in step 81, an unprocessed macro terminal is searched from the macro logic description language stored in the logic description file 1, and the searched macro terminal is stored in a table (not shown) prepared on the memory. To do. This table is provided with a storage area in which information of terminal types 1 and 2 can be set for the macro terminal. Therefore, in FIG. 3, the information of the macro terminal A1 (input terminal) is stored in the table.
[0041]
In step 82, it is determined whether or not there is an unprocessed macro terminal. If there is an unprocessed macro terminal, the process proceeds to step 83. In step 83, information on the terminal type (input terminal, output terminal, or input / output terminal) of the macro terminal described in the logic description language for the macro terminal A1 registered in the table is read and set in the storage area of terminal type 1 in the table. To do. Therefore, information of the input terminal is set in the storage area of the terminal type 1 of the macro terminal A1.
[0042]
Next, in step 84, all cell terminals connected to the macro terminal A1 are searched based on the net described in the logic description language of the logic description file 1, and the terminal types (normal terminals, (Clock terminal etc.) information is stored in a table.
[0043]
In step 85, it is determined whether or not all cell terminals stored in the table have the same terminal type. In step 86, the terminal type information stored in step 84 is set in the storage area of terminal type 2 for the macro terminal A1 stored in step 81.
[0044]
If it is determined in step 85 that the terminal types of all the cell terminals are not the same, that is, there are a plurality of terminal types, the process proceeds to step 87. In step 87, when there are a normal terminal and a clock terminal as the terminal type of the cell terminal, the macro terminal stored in step 81 is selected by selecting a terminal type with severe conditions so that the clock terminal is selected as the terminal type. The terminal type information is set in the storage area of terminal type 2 for A1.
[0045]
Thereafter, the processing in steps 81 to 87 is performed for all macro terminals described in the macro logic description language.
Next, library synthesis processing performed by the macro library synthesis apparatus 15 will be described with reference to FIG.
[0046]
First, in step 91, macro name information and frame pattern information are read from the physical library file 4 and stored in a table (not shown) prepared on the memory. Also, macro terminal information items relating to one macro terminal are sequentially read from the physical library file 4 and stored in the table. This table is provided with a storage area in which information on input load capacity, information on output drive capability, and information on terminal types 1 and 2 can be set for the macro terminal.
[0047]
Next, in step 92, it is determined whether there is an unprocessed macro terminal. If there is an unprocessed macro terminal, the process proceeds to step 93. In step 93, information on the input load capacity obtained by the characteristic calculation process shown in FIG. 8 is set in the table.
[0048]
In step 94, the information of the output drive capability obtained by the characteristic calculation process shown in FIG. 8 is set in the table.
In step 95, information of terminal types 1 and 2 obtained by the macro terminal attribute recognition processing shown in FIG. 9 is set in a table. The processes in steps 91 to 95 are performed for all the macro terminals stored in the physical library file 4, and all information set in the table is output to the macro library file 6 to generate a macro library.
[0049]
The chip layout device 16 performs chip layout based on the data of the macro library file 6, the data of the cell library file 2, and the logic description data of the semiconductor circuit.
[0050]
The design rule check device 17 verifies the layout result by the chip layout device 16 based on the data of the macro library file 6.
Now, this embodiment has the following effects.
[0051]
(1) By calculating the characteristics of the macro terminal, the characteristics of all cells connected to the macro terminal, and the wiring capacity of the wiring connecting the macro terminal and the cell terminal created in the macro layout, the input load capacity of the macro terminal The output drive capability can be calculated in detail and in a short time.
[0052]
(2) Since the attributes of the macro terminal are extracted from the terminal attributes of all the cell terminals connected to the macro terminal, the terminal type of the macro terminal can be easily selected. As a result, a macro library can be easily generated, and a highly reliable macro library can be generated without human error.
[0053]
【The invention's effect】
As described above in detail, the present invention can easily generate a macro library, and can generate a highly reliable macro library without human error.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an LSI design system.
FIG. 2 is an explanatory diagram showing a logical structure of an example macro
FIG. 3 is an explanatory diagram showing an example macro pattern structure;
FIG. 4 is an explanatory diagram showing an example macro library file.
FIG. 5 is an explanatory diagram showing an example of a net capacity list;
FIG. 6 is a flowchart showing physical library generation processing;
FIG. 7 is a flowchart showing a wiring capacity extraction process;
FIG. 8 is a flowchart showing processing for calculating characteristics of a macro terminal.
FIG. 9 is a flowchart showing macro terminal attribute recognition processing;
FIG. 10 is a flowchart showing library synthesis processing.
[Explanation of symbols]
2 cell library
13 Physical library generator
14 Wiring capacity extraction device
15 Library synthesizer
21 Macro
32, 33, 34 cells
A1 Macro terminal (input terminal)
X1 Macro terminal (output terminal)

Claims (4)

Macro is defined by the nets within cells and macros for use in, based on the more the described description data in logical description language macros, using a cell of defined cell library in characteristics and attributes of a cell terminal for macro designed Te, a macro library generation device for generating libraries defined include properties and attributes of the macro terminal,
By executing the layout of cells based on the description data, and the layout unit for generating graphic data lines are laid for connecting the macro terminals and cell terminals,
A physical library generating device for generating a physical library as information configured to include data on a macro terminal and wiring connected to the macro terminal based on the graphic data ;
A wiring capacity extraction device that extracts the wiring capacity of the wiring connected to the macro terminal based on the graphic data;
Macro terminal characteristics set based on the physical library, the characteristics of all the cell terminals connected to the wiring capacity and the macro terminal, and the macro terminals set based on the attributes of all the cell terminals connected to the macro terminal macro library generation apparatus and a library synthesizer for generating a library by synthesizing the attributes. The macro library generation device according to claim 1, wherein the physical library generation device further extracts information on a position of a macro terminal constituting the physical library and a wiring layer of a wiring connected to the macro terminal based on the graphic data . Designed using cells in the cell library defined by the characteristics and attributes of the cell terminals based on the description data described in the macro's logical description language, defined by the cells used in the macro and the nets in the macro. A macro library generating device for generating a library defined including the characteristics and attributes of the macro terminal for the generated macro,
A layout device for generating graphic data in which wiring for connecting a macro terminal and a cell terminal is laid out by executing a cell layout based on the description data;
A physical library generating device for generating a physical library as information configured to include data on a macro terminal and wiring connected to the macro terminal based on the graphic data;
A wiring capacity extraction device that extracts the wiring capacity of the wiring connected to the macro terminal based on the graphic data;
Each macro terminal read from the cell library based on the physical library, the characteristics of the first macro terminal set based on the characteristics of all the cell terminals connected to the wiring capacity and the macro terminal, and the description data A library is created by combining the characteristics of the second macro terminal, which reflects the characteristics of all the cell terminals connected to, and the attributes of the macro terminals set based on the attributes of all the cell terminals connected to the macro terminal A library synthesizer
A macro library generation device comprising: Designed using cells in the cell library defined by the characteristics and attributes of the cell terminals based on the description data described in the macro's logical description language, defined by the cells used in the macro and the nets in the macro. A macro library generating device for generating a library defined including the characteristics and attributes of the macro terminal for the generated macro,
A layout device for generating graphic data in which wiring for connecting a macro terminal and a cell terminal is laid out by executing a cell layout based on the description data;
A physical library generating device for generating a physical library as information configured to include data on a macro terminal and wiring connected to the macro terminal based on the graphic data;
A wiring capacity extraction device that extracts the wiring capacity of the wiring connected to the macro terminal based on the graphic data;
Read from the cell library based on the physical library, the characteristics of the macro terminals set based on the characteristics of all the cell terminals connected to the wiring capacity and the macro terminal, and the description data , and connect to each macro terminal A library synthesizer that generates a library by synthesizing the attributes of the macro terminals that reflect the attributes of all the cell terminals ;
A macro library generation device comprising:

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