JP3614619B2 - Pattern design method and pattern design apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit in which a wiring area ratio is made uniform for each wiring layer by using a dummy pattern, a pattern design method and a design apparatus therefor.
[0002]
[Prior art]
The wiring area ratio formed by the ratio of the wiring area to the chip area in each wiring layer of the integrated circuit generally differs depending on the model of the integrated circuit or each wiring layer. Due to the difference in wiring area ratio, the etching rate varies for each model or wiring layer in the semiconductor manufacturing process.
[0003]
[Problems to be solved by the invention]
According to the above-described conventional configuration, there are problems in that the etching rate varies, thereby causing variations in the finished dimensions of the wiring, disconnection due to overetching, bridging between wirings due to etching residue, and the like, thereby reducing the yield. In order to prevent the yield from being lowered, the manufacturing parameters must be adjusted for each type of integrated circuit or for each wiring layer, which is complicated.
[0004]
In view of the above-described conventional problems, an object of the present invention is to provide an integrated circuit having a wiring set to a uniform optimal wiring area ratio.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the solution provided by the present invention is that an integrated circuit includes a first wiring layer and a second wiring formed above or below the first wiring layer via an interlayer insulating film. Each of the first wiring layer and the second wiring layer has a power supply wiring, a signal wiring, and a first dummy pattern, and the first dummy pattern of the first wiring layer is a second wiring pattern. so as to overlap with the region of the power source system wiring of the wiring layer, and it is an configuration formed with a predetermined interval between the signal system wiring so as not to overlap with the signal system line of the first wiring layer .
Another solution provided by the present invention is that, in addition to the first dummy pattern, the integrated circuit is connected to the first wiring layer and the power supply system wiring and signal of the first wiring layer and the second wiring layer. The system wiring is configured to include a second dummy pattern formed in a non-wiring region composed of a region where none exists.
[0007]
With the above configuration, a dummy pattern can be formed by effectively using a region where no wiring exists in each wiring layer of the integrated circuit.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
An integrated circuit according to the present invention will be described with reference to FIGS. FIG. 3 is a pattern diagram showing an original pattern PI composed of a pattern having no dummy pattern for obtaining an integrated circuit according to the present invention. In FIG. 3, a first layer signal wiring 10 formed on the integrated circuit 1 is a pattern representing a signal wiring to be formed on the first wiring layer. The second layer signal wiring 20 is a pattern representing the signal wiring in the second wiring layer to be formed on the first wiring layer via the interlayer insulating film. The second layer power supply system wiring 21 is a pattern representing a power supply system wiring for supplying a power supply voltage or a ground voltage in the second wiring layer. The first layer signal system wiring 10, the second layer signal system wiring 20, and the second layer power system wiring 21 together constitute an original pattern PI.
[0009]
FIG. 1 is a pattern diagram of an integrated circuit according to the present invention. Components identical to those already shown in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 1, the first dummy pattern DP1 overlaps the region of the second layer power system wiring 21 and does not overlap the region of the first layer signal system wiring 10, and the first dummy pattern DP1 and the first layer signal system wiring 10 This is a dummy pattern formed on the first wiring layer at a predetermined distance from the outer edge of the two-layer power supply wiring 21. The second dummy pattern DP2 is formed on the outer edge of each wiring in an unwired region formed by a region where none of the first layer signal wiring 10, the second layer signal wiring 20, and the second layer power supply wiring 21 exists. And a dummy pattern formed on the first wiring layer at predetermined intervals from the outer edge of the integrated circuit 1.
[0010]
According to the integrated circuit of the present invention, in the integrated circuit 1, the first dummy pattern DP1 using the lower layer of the power supply system wiring having a large area of the wiring, and the second dummy pattern DP2 using the unwired region. Are formed on the first wiring layer. As a result, even in different integrated circuit models or different wiring layers, a dummy pattern is formed by effectively using the lower layer region or the unwired region of the power supply system wiring, so that the wiring having a uniform wiring area ratio Can be formed. In addition, since the dummy pattern in the unwired area is formed at a predetermined interval from the signal wiring of another wiring layer, no coupling capacitance is generated between the signal wiring and the dummy pattern, and the integrated circuit Can be prevented from malfunctioning. Further, a dummy pattern can be formed through the interlayer insulating film between the overlapping power supply lines for supplying the power supply voltage and the ground voltage, respectively. In this case, since a coupling capacitance is generated between the power supply voltage and the ground voltage, noise radiated from the integrated circuit can be reduced, and noise entering from the outside can be removed to reduce malfunction of the integrated circuit.
[0011]
In the above description, the dummy pattern formed on the first wiring layer has been described. However, the present invention is not limited to this, and a dummy pattern may be formed in an unwired region in the second wiring layer, and a dummy pattern is formed in the third wiring layer formed on the second wiring layer via an interlayer insulating film. May be formed.
[0012]
A pattern design apparatus according to the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the pattern design apparatus according to the present invention. The first dummy pattern generation unit 30 is a pattern generation unit for generating the first dummy pattern DP1 based on the received original pattern PI, the first resize value RS1, and the first design rule DR1. . The first dummy pattern generation unit 30 includes a logical operation unit 31, a logical operation unit 32, a first resize unit 33, and a first design rule check unit 34.
[0013]
The second dummy pattern generation unit 40 is a pattern generation unit for generating the second dummy pattern DP2 based on the received original pattern PI, the second resize value RS2, and the second design rule DR2. . The second dummy pattern generation unit 40 includes a logical operation unit 41, a second resizing unit 42, a logical operation unit 43, and a second design rule check unit 44.
[0014]
The dummy pattern determining means 50 determines the received first dummy pattern DP1 and second dummy pattern DP2 based on the received original pattern PI, the third resize value RS3, and the third design rule DR3, respectively. This is a pattern determining means for determining an optimal dummy pattern in combination. The dummy pattern determining unit 50 includes a wiring area ratio determining unit 51, a third resizing unit 52, and a third design rule checking unit 53.
[0015]
The logical operation means 60 is a pattern generation means for generating an optimization pattern based on the original pattern PI and the optimum dummy pattern received from the dummy pattern determination means 50, respectively.
[0016]
The operation of the pattern design apparatus in FIG. 2 will be described with reference to FIG. 1 and FIGS. Components identical to those already shown in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. In the following description, all of the generated dummy patterns are generated in the first wiring layer.
[0017]
FIG. 4 is a pattern diagram showing the first pattern P1 supplied by the logical operation means 31. As shown in FIG. The logical operation means 31 extracts only the second layer power system wiring 21 from the received original pattern PI to generate and supply the first pattern P1. FIG. 5 is a pattern diagram showing the second pattern P2 supplied by the logical operation means 32. As shown in FIG. The logical operation means 32 generates and supplies the second pattern P2 by excluding the area overlapping the first layer signal wiring 10 from the first pattern P1 received from the logical operation means 31. FIG. 6 is a pattern diagram showing the third pattern P3 supplied by the first resizing means 33. As shown in FIG. The first resizing means 33 generates the third pattern P3 by reducing the second pattern P2 received from the logical operation means 32 by the first resizing value RS1, based on the received first resizing value RS1, and Supply. The first design rule checking means 34 checks the third pattern P3 received from the first resizing means 33 based on the received first design rule DR1. As a result of the check, if there is a part that violates the first design rule DR1, the third pattern P3 received in that part is corrected, and if there is no part that violates, the received third pattern P3 is supplied as it is. FIG. 6 shows a case where the third pattern P3 does not violate the first design rule DR1. Therefore, in this case, the first design rule check means 34 supplies the first dummy pattern DP1 composed of the third pattern P3.
[0018]
FIG. 7 is a pattern diagram showing the fourth pattern P4 supplied by the logical operation means 41. As shown in FIG. Based on the received original pattern PI, the logical operation means 41 generates and supplies the fourth pattern P4 by taking the logical sum of all the wirings included in the original pattern PI. FIG. 8 is an explanatory diagram for explaining the operation of the second resizing means 42. FIG. 9 is a pattern diagram showing a fifth pattern P5 composed of an enlarged wiring pattern supplied by the second resizing means 42. FIG. The second resizing means 42 generates a fifth pattern P5 by expanding the fourth pattern P4 received from the logical operation means 41 by the second resizing value RS2 based on the received second resizing value RS2, and Supply. FIG. 10 is a pattern diagram showing the sixth pattern P6 supplied by the logical operation means 43. As shown in FIG. Based on the fifth pattern P5 received from the second resizing means 42, the logical operation means 43 inverts the fifth pattern P5 to generate and supply a sixth pattern P6. FIG. 11 is a pattern diagram showing the second dummy pattern DP2 supplied by the second design rule check means 44. As shown in FIG. The second design rule check means 44 checks the sixth pattern P6 received from the logic operation means 43 based on the received second design rule DR2. As a result of the check, if there is a portion that violates the second design rule DR2, the sixth pattern P6 received at that portion is corrected, and if there is no portion that violates, the sixth pattern P6 is supplied as it is. FIG. 10 shows a case where the sixth pattern P6 violates the second design rule DR2. Therefore, in this case, the second design rule check means 44 corrects the sixth pattern P6 in a portion where the sixth pattern P6 is contrary to the second design rule DR2. That is, the pattern is removed so as to keep a predetermined distance from the outer edge in the portion where the pattern exists up to the outer edge of the integrated circuit 1, and further, the pattern is removed in a portion where the pattern becomes smaller than the predetermined width as a result of the removal. The second dummy pattern DP2 shown in FIG. 11 is generated.
[0019]
The wiring area ratio determining means 51 first receives the original pattern PI, the first dummy pattern DP1, and the second dummy pattern DP2, respectively. Next, on the basis of each received pattern, the first wiring area, which is the wiring area of the actual wiring composed of the power supply wiring and the signal wiring in the first wiring layer, the first dummy pattern DP1 and the actual wiring The second wiring area, which is the sum of the wiring areas, the third wiring area, which is the sum of the wiring areas of the second dummy pattern DP2 and the actual wiring, and the first dummy pattern DP1 and the second dummy pattern. A fourth wiring area that is the sum of the wiring areas of DP2 and the actual wiring is calculated. Next, first to fourth wiring area ratios are calculated, which are ratios of the calculated first to fourth wiring areas with respect to the chip area of the integrated circuit. Next, a wiring area ratio closest to a predetermined optimum wiring ratio is selected from the calculated first to fourth wiring area ratios, and a combination of wirings corresponding to the selected wiring area ratio is selected. Supply data to represent.
[0020]
When the wiring area ratio corresponding to the data received from the wiring area ratio determining means 51 exceeds the optimum wiring ratio, the third resizing means 52 is based on the received third resizing value RS3. The second dummy pattern DP1 or DP2 is reduced, the received data is corrected so that the wiring area ratio is equal to or less than the optimal wiring ratio, and the corrected dummy pattern is supplied.
[0021]
The third design rule check means 53, when a portion that does not satisfy the third design rule DR3 occurs in the modified dummy pattern received from the third resizing means 52 based on the received third design rule DR3 In this case, the unsatisfied part is corrected based on the third design rule DR3.
[0022]
The logical operation means 60 calculates the logical sum of the modified dummy pattern and the original pattern PI to generate and supply the optimized pattern of the integrated circuit 1 shown in FIG.
[0023]
As described above, according to the pattern design apparatus of the present invention, in the integrated circuit 1, the dummy pattern is generated in the lower layer region and the unwired region of the power supply wiring having a large area in the wiring. The first dummy pattern DP1 and the second dummy pattern DP2 are designed respectively. Further, the first or second dummy pattern DP1 or DP2 is corrected so that the closest wiring area ratio is equal to or less than a predetermined optimum wiring ratio. Therefore, even between different models of integrated circuits or between different wiring layers, dummy patterns are generated and corrected by effectively using unwired areas or lower layer areas of power supply system wiring. Wiring having a wiring area ratio can be designed.
[0024]
In addition, the dummy pattern is designed so that the dummy pattern in the unwired area keeps a predetermined distance from the signal wiring in the other wiring layer. As a result, since no coupling capacitance is generated between the signal system wiring and the dummy pattern, an integrated circuit that is unlikely to malfunction can be realized.
[0025]
Further, it may be designed such that a dummy pattern is formed through an interlayer insulating film between overlapping power supply lines for supplying a power supply voltage and a ground voltage. In this case, since a coupling capacitance is generated between the power supply voltage and the ground voltage, it is possible to realize an integrated circuit in which noise entering from the outside is reduced, malfunction is difficult, and radiation noise is reduced.
[0026]
In the above description, the case where the dummy pattern is generated in the first wiring layer has been described. However, the present invention is not limited to this, and a dummy pattern may be generated in an unwired area in the second wiring layer, and a dummy pattern is generated in the third wiring layer generated on the second wiring layer via an interlayer insulating film. May be generated. Further, only one of the first dummy pattern generation unit 30 and the second dummy pattern generation unit 40 may be used according to the optimum wiring rate.
[0027]
【The invention's effect】
According to the present invention, the first dummy pattern formed in the wiring layer composed of the upper layer or the lower layer of the power supply system wiring and the second dummy pattern formed in the non-wiring region in the wiring layer are combined, and The first or second dummy pattern is corrected as necessary so as to obtain an optimum wiring area ratio. Therefore, even with different integrated circuit models or different wiring layers, wiring having a uniform optimal wiring area ratio is formed. As a result, variations in the etching rate in the semiconductor manufacturing process are suppressed, so that an integrated circuit with high yield and dimensional accuracy of wiring can be realized.
[0028]
In addition, since the dummy pattern in the non-wiring area is formed at a predetermined interval from the signal wiring of the other wiring layer, no coupling capacitance is generated between the dummy pattern and the signal wiring. It is possible to realize an integrated circuit that is difficult to perform.
[0029]
In addition, coupling between the power supply voltage and the ground voltage is achieved by forming a dummy pattern through the interlayer insulating film between the power supply wirings formed so as to overlap each other to supply the power supply voltage and the ground voltage. Since the capacitance is generated, it is possible to realize an integrated circuit in which noise entering from the outside is reduced, malfunction is difficult, and noise radiated is reduced.
[Brief description of the drawings]
FIG. 1 is a pattern diagram of an integrated circuit according to the present invention.
FIG. 2 is a block diagram showing a configuration of a pattern design apparatus according to the present invention.
FIG. 3 is a pattern diagram showing an original pattern of an integrated circuit according to the present invention.
4 is a pattern diagram showing a first pattern of FIG. 2; FIG.
FIG. 5 is a pattern diagram showing a second pattern of FIG. 2;
6 is a pattern diagram showing a third pattern and a first dummy pattern in FIG. 2; FIG.
7 is a pattern diagram showing a fourth pattern in FIG. 2; FIG.
FIG. 8 is a diagram for explaining the operation of the second resizing means in FIG. 2;
FIG. 9 is a pattern diagram showing a fifth pattern of FIG. 2;
10 is a pattern diagram showing a sixth pattern of FIG. 2. FIG.
FIG. 11 is a pattern diagram showing a second dummy pattern of FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Integrated circuit 10 1st layer signal system wiring 20 2nd layer signal system wiring 21 2nd layer power system wiring 30 1st dummy pattern production | generation means 40 2nd dummy pattern production | generation means 50 Dummy pattern determination means DP1 1st dummy pattern DP2 Second dummy pattern PI Original pattern

Claims (6)

A pattern design method for designing a pattern of an integrated circuit having a first wiring layer formed on a semiconductor substrate and a second wiring layer formed above or below the first wiring layer via an interlayer insulating film. ,
Data representing a region including the power supply system wiring of the second wiring layer and excluding the signal system wiring of the second wiring layer is extracted from data representing the original pattern, and the extracted data and the first wiring layer A first logical operation step for calculating a logical product of inverted data of data representing the signal system wiring of
In the first wiring layer, generating a first dummy pattern to the second overlaps with the wiring layer of the power supply system line, and the outer edge or et region of the inner by a first resize value of the dummy pattern region made of logical product A first dummy pattern generating step to perform,
A pattern design method comprising: a first dummy pattern correction step of correcting a portion of the first dummy pattern that violates a first design rule. The pattern design method according to claim 1,
A second logical operation step of calculating data representing a region including the power supply system wiring and the signal system wiring of the first wiring layer and the second wiring layer;
In the first wiring layer, the data calculated by the second logical operation process generates an enlarged wiring pattern enlarged regions outward by a second resizing value, data representing the enlarged wiring pattern which is the product A second dummy pattern generating step of generating a second dummy pattern by inverting
A second dummy pattern correction step of correcting a portion of the second dummy pattern that violates a second design rule;
The first wiring area ratio, which is the ratio of the area of the actual wiring composed of the power supply wiring and the signal wiring of the first wiring layer to the chip area, and the total area of the first dummy pattern and the actual wiring A second wiring area ratio composed of a ratio of the chip area with respect to the chip area, a third wiring area ratio composed of a ratio of the total area of the second dummy pattern and the substantial wiring with respect to the chip area, And a fourth wiring area ratio comprising a ratio of a total area of the first dummy pattern, the second dummy pattern, and the actual wiring to the chip area, and A pattern design method, further comprising: a wiring area ratio determining step of selecting one wiring area ratio closest to a predetermined optimum area ratio among the first to fourth wiring area ratios. The pattern design method according to claim 2,
When said one of the said first selected in the wiring area ratio determining step the fourth wiring area ratio exceeds the optimum area ratio, said first selected in the wiring area ratio determining step The first or second dummy pattern is reduced based on the third resize value so that one of the fourth to fourth wiring area ratios is equal to or less than the optimum area ratio, and the reduced A pattern design method, further comprising a resizing and design rule check step for correcting a portion of the dummy pattern that violates a third design rule. A pattern design apparatus for designing a pattern of an integrated circuit having a first wiring layer formed on a semiconductor substrate and a second wiring layer formed above or below the first wiring layer via an interlayer insulating film. There,
Data representing a region including the power supply system wiring of the second wiring layer and excluding the signal system wiring of the second wiring layer is extracted from data representing the original pattern, and the extracted data and the first wiring layer First logical operation means for calculating a logical product of inverted data of data representing signal system wiring;
In the first wiring layer, generating a first dummy pattern to the second overlaps with the wiring layer of the power supply system line, and the outer edge or et region of the inner by a first resize value of the dummy pattern region made of logical product And a first dummy pattern generation and correction means for correcting a portion of the first dummy pattern that violates the first design rule. The pattern design device according to claim 4,
Second logic operation means for calculating data representing a region including power supply system wiring and signal system wiring of the first wiring layer and the second wiring layer;
In the first wiring layer, the data calculated by the second logical operation process generates an enlarged wiring pattern enlarged regions outward by a second resizing value, data representing the enlarged wiring pattern which is the product A second dummy pattern generating and correcting means for generating a second dummy pattern and correcting a part of the second dummy pattern that violates the second design rule;
The first wiring area ratio, which is the ratio of the area of the actual wiring composed of the power supply wiring and the signal wiring of the first wiring layer to the chip area, and the total area of the first dummy pattern and the actual wiring A second wiring area ratio composed of a ratio of the chip area with respect to the chip area, a third wiring area ratio composed of a ratio of the total area of the second dummy pattern and the substantial wiring with respect to the chip area, And a fourth wiring area ratio comprising a ratio of a total area of the first dummy pattern, the second dummy pattern, and the actual wiring to the chip area, and A pattern design apparatus, further comprising: a wiring area ratio determining means for selecting one wiring area ratio closest to a predetermined optimum area ratio among the first to fourth wiring area ratios. The pattern design apparatus according to claim 5,
When said one of the said first selected in the wiring area ratio determining means fourth wiring area ratio exceeds the optimum area ratio, said first selected in the wiring area ratio determining means The first or second dummy pattern is reduced based on a third resize value so that one of the fourth to fourth wiring area ratios is equal to or less than the optimum area ratio, and the reduced A pattern design apparatus, further comprising resizing and design rule checking means for correcting a portion of the dummy pattern that violates a third design rule.

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