JP3611518B2 - LCD panel scanning line driver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display panel scanning line driver for driving a liquid crystal, and more particularly to measures for reducing fluctuations in display electrode potential of a liquid crystal display panel.
[0002]
[Prior art]
Conventionally, a liquid crystal display panel scanning line driver usually receives data of a shift register including a plurality of flip-flops provided corresponding to a plurality of scanning electrode lines, an output circuit, and data of the last stage shift register in the next stage. It is composed of an input / output control circuit for transmitting to the LSI. Then, during the operation of the liquid crystal display panel scanning line driver, a plurality of scanning electrode lines are sequentially activated by the output shift operation of the shift register, and the display screen of the liquid crystal display panel is scanned in the vertical direction. The shift data of the shift register is input to the drive signal input terminal of the next-stage LSI, and the next-stage LSI is operated.
[0003]
FIG. 7 is a circuit diagram schematically showing a configuration of one unit in an output circuit of a conventional liquid crystal display panel scanning line driver. As shown in the figure, the output circuit of the conventional liquid crystal display panel scanning line driver includes a control circuit 100, an output buffer (inverter) composed of a P-channel transistor M101 and an N-channel transistor M102, and an output terminal 105. I have. With this configuration, when the input signal S1 is “H”, the signal “H” is supplied from the control circuit 100 to the output buffer, and the output signal Yg from the output buffer (inverter) becomes “L”. Then, a thin film transistor (not shown) of the liquid crystal display panel performs a switching operation by the output signal Yg.
[0004]
Here, in the liquid crystal display panel scanning line driver, in order to maximize the drive capability for switching a thin film transistor (not shown) of the liquid crystal display panel, in general, the P-channel transistor M101 and the N-channel transistor M102 of the output buffer are used. The capacities are almost the same, and the current driving capability is higher.
[0005]
FIG. 2 is an electric circuit diagram (equivalent circuit diagram) showing a part of the liquid crystal element portion in the liquid crystal display panel. As shown in the figure, the liquid crystal element is represented as a capacitive element having a liquid crystal capacitance CL. A thin film transistor TFT for applying a display electrode voltage to one liquid crystal element is arranged, and each liquid crystal element and the thin film transistor TFT are arranged in a matrix. The gate electrode G of each thin film transistor TFT is connected to a gate wiring that supplies a gate voltage Vg, and the source electrode S of the thin film transistor TFT is connected to a source wiring that supplies a source voltage VS. The drain electrode D of the thin film transistor TFT is connected to the display electrode A of the liquid crystal element, and the common electrode B of the liquid crystal element is connected to a common electrode wiring for supplying a common voltage Vco. At this time, a parasitic capacitance Cds exists between the drain electrode D and the source electrode S of the thin film transistor TFT, and a parasitic capacitance Cgd exists between the gate electrode G and the drain electrode D of the thin film transistor TFT.
[0006]
The output signal Yg of the liquid crystal display panel scanning line driver is supplied as the gate voltage Vg from the gate wiring of the thin film transistor TFT, and the output of the liquid crystal data driver is input to the source electrode S of the thin film transistor TFT. When the gate voltage Vg of the thin film transistor TFT is at the H level, the thin film transistor TFT is turned on, the voltage of the source electrode S is transmitted to the display electrode A of the liquid crystal element, and according to the potential difference with the common voltage Vco of the common electrode B. The state of the liquid crystal in the liquid crystal element is controlled
[0007]
[Problems to be solved by the invention]
Here, the conventional liquid crystal display panel scanning line driver has the following problems.
[0008]
FIG. 8 is a timing chart showing a time change of a signal related to a conventional thin film transistor TFT. As shown in the figure, when the first frame is entered at time t101 and the level “H” (ON voltage VDD2) is input to the gate electrode G, the thin film transistor TFT1 is turned on, and the liquid crystal capacitance CL and parasitic capacitance Cds, Charges corresponding to the potential difference between the source voltage VS and the supply voltage Vco are accumulated in Cgd, and the potential of the display electrode A (display electrode voltage) approaches the source voltage VS. Subsequently, when the voltage of the gate electrode G falls to the level “L” (off voltage VSS2) at time t102, the thin film transistor TFT1 is turned off, and the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd hold the accumulated charges. The potential of the display electrode A (display electrode voltage) is held substantially equal to the source voltage VS.
[0009]
Subsequently, at the time t103, the second frame is entered, and when the level “H” is input to the gate electrode G again, the thin film transistor TFT1 is turned on, and according to the potential difference between the inverted source voltage VS and the common voltage Vco. Charges are accumulated in the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd, and the potential of the display electrode A (display electrode voltage) approaches the inverted source voltage VS. Subsequently, when the voltage of the gate electrode G falls to the level “L” (off voltage VSS2) at time t104, the thin film transistor TFT1 is turned off, and the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd hold the accumulated charges. The potential of the display electrode A (display electrode voltage) is held substantially equal to the source voltage VS.
[0010]
At this time, when the output signal Yg (= gate voltage Vg) of the liquid crystal display panel scanning line driver changes from “H” to “L” at time t102 and time t104, the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd When the accumulated charge is pulled to the potential of the liquid crystal data driver (source voltage VS), there is a possibility that the variation ΔV of the potential of the display electrode A (display electrode voltage) occurs. Since the variation ΔV of the potential of the display electrode (display electrode voltage) becomes a different value for each frame (there is variation), the variation of the variation ΔV in the liquid crystal electrode voltage causes flickering on the screen of the liquid crystal display device ( There was a problem of appearing as flicker.
[0011]
An object of the present invention is to suppress flickering of a screen of a liquid crystal display device by taking a measure capable of reducing the fluctuation ΔV of the display electrode voltage.
[0012]
[Means for Solving the Problems]
The first liquid crystal display panel scanning line driver of the present invention is a liquid crystal display panel scanning line driver provided with a unit output circuit for supplying a voltage to the scanning lines of the liquid crystal display panel. A node supplying the drain, an output node connected to the source, a p-channel transistor connected to the gate of the first input signal and a node supplying the low potential side voltage to the source, the output node to the drain, A second input signal is provided between the n-channel transistor connected to the gate, the output node and the node supplying the low potential side voltage, and the voltage applied to the external signalCan be switched on / offSwitching elements andAnother switching element interposed between the switching element and the output node for adjusting the falling timing of the output node of the unit output circuit;It has.
[0013]
As a result, when the output signal output from the output node is used as the scanning line driving voltage, the output signal does not rapidly fall, and shows a gradual falling waveform corresponding to the current drive capability of the switching element. Become. Therefore, in the liquid crystal element driven by the output signal via the scanning line, fluctuations in the display electrode voltage of the liquid crystal element due to a rapid drop in the voltage on the scanning line are suppressed, and variations in the display electrode voltage are also reduced. Therefore, the flicker of the screen of the liquid crystal display device can be effectively suppressed.
Further, by further comprising another switching element interposed between the switching element and the output node for adjusting the falling timing of the output node of the unit output circuit, the falling state can be moderated. However, after a certain period of time, the output signal can be quickly reduced to the off voltage. For example, in general, a liquid crystal display panel is provided with a thin film transistor that controls supply of a voltage to a display electrode of a liquid crystal element. Therefore, an output signal can be lowered to an on voltage after the thin film transistor is turned off.
[0014]
In that case, since the switching element is constituted by a transistor, the current driving capability is determined by the value of the external signal applied to the gate of the switching element. That is, the falling waveform of the output signal can be adjusted by the voltage value of the external signal. Therefore, it is possible to obtain an appropriate output signal falling waveform according to the specifications of the liquid crystal display panel.
[0016]
The other switching element isNThe current driving capability is preferably smaller than that of the channel transistor.
[0017]
Further, since the switching element is set to be always on, control can be simplified.
[0018]
BookA second liquid crystal display panel scanning line driver of the invention is a liquid crystal display panel scanning line driver having a unit output circuit for supplying a voltage to the scanning lines of the liquid crystal display panel, and is provided for each of the unit output circuits. A control circuit for controlling the falling waveform of the output signal of the unit output circuit is provided.
[0019]
As a result, the output signal can be adjusted to show a gradual falling waveform without suddenly falling. Therefore, in the liquid crystal element driven by the output signal via the scanning line, fluctuations in the display electrode voltage of the liquid crystal element due to a rapid drop in the voltage on the scanning line are suppressed, and variations in the display electrode voltage are also reduced. Therefore, the flicker of the screen of the liquid crystal display device can be effectively suppressed..
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The liquid crystal display panel scanning line driver according to the present invention smoothly falls the falling waveforms of all of the plurality of liquid crystal display panel scanning line drivers, and responds to the characteristics of a thin film transistor or a liquid crystal element mounted with the falling waveforms. It can be made variable.
[0021]
Hereinafter, specific embodiments of the output circuit of the liquid crystal display panel scanning line driver according to the present invention will be described with reference to the drawings.
[0022]
FIG. 1 is a diagram showing a circuit configuration of a liquid crystal display panel scanning line driver in the present embodiment. As shown in the figure, the liquid crystal display panel scanning line driver 1 of the present embodiment includes a shift register 10 composed of a large number of D flip-flops FF0-FFn and an output composed of a large number of unit output circuits BF0-BFn. Circuit 30. Outside the shift register 10, a drive signal input terminal 11 for supplying data to the data terminal D of each flip-flop FF0-FFn and a clock for supplying a clock to the clock terminal CK of each flip-flop FF0-FFn. A signal input terminal 12 is provided. Outside the output circuit 30, a control signal terminal 21 for supplying a control signal V4 to each unit output circuit BF0-BFn and an input signal terminal 22 for supplying an input signal S32 to each unit output circuit BF0-BFn. And an input signal terminal 23 for supplying the input signal S33 to each unit output circuit BF0-BFn, and output terminals Ot1-Otn for outputting the output signals Yg0-Ygn supplied to the gate electrodes of the thin film transistors. It has been. Further, the unit output circuits BF0 to BFn of the output circuit 30 are supplied with the thin film transistor on voltage VDD2 and the thin film transistor off voltage VSS2.
[0023]
Here, as an example of voltage values used in the liquid crystal display panel scanning line driver 1 of this embodiment, the logic power supply voltage VDD1 is 2.7 V to 5.5 V, the logic ground voltage VSS is 0 V (ground GND). The on-voltage VDD2 of the thin film transistor TFT is 8V to 10V, and the off-voltage VSS2 of the thin film transistor is -5V to -3V.
[0024]
In the shift register 10, the data input terminal D of the first stage D flip-flop FF0 is connected to the drive signal input terminal 11, and for each stage, the output terminal Q of the Q output of the previous stage D flip-flop FFj is the next stage D flip-flop. Is connected to the data input terminal D of the FFj + 1. The outputs from the output terminals Y of the D flip-flops FF0 to FFn are respectively input to the corresponding unit output circuits BF0 to BFn. The active-low clock input terminals CK of all D flip-flops FF0 to FFn are commonly connected to one clock signal input terminal 12, and the same clock signal is supplied to each D flip-flop FF0 to FFn.
[0025]
The output circuit 30 supplies output signals Yg0 to Ygn to scanning electrode lines of a liquid crystal display panel (not shown). That is, as shown in FIG. 3 to be described later, in the output circuit 30, an on-voltage VDD2 that is a liquid crystal driving power supply voltage on the high potential side according to the output signal from each flip-flop FF0-FFn of the shift register 10, The level is shifted to the amplitude of the off voltage VSS2, which is the power supply voltage for driving the liquid crystal on the low potential side, and output.
[0026]
FIG. 3 is a circuit diagram showing a configuration of one unit output circuit BF in the output circuit 30 of the liquid crystal display panel scanning line driver in the present embodiment. The unit output circuit BF includes a control circuit 35 that receives the output of the shift register 10, first, second, and third level shifters 31-33 that receive the output of the control circuit 35, and first and second units arranged in series. , Fourth switching elements M31, M32, and M34, and a third switching element M33 that receives the output of the level shifter 33.
[0027]
The first switching element M31 is composed of an enhancement type P-channel MOSFET. The second switching element M32 is made of an enhancement type N-channel MOSFET and has a low current capability. The third switching element M33 is composed of an enhancement type N-channel MOSFET, and has a current capability higher than that of the second switching element M32. Fourth switching element M34 isIt consists of an enhancement type N-channel MOSFET. The drain of the first switching element M31 is connected to a node for supplying the liquid crystal driving power supply voltage (ON voltage) VDD2 on the high potential side, and the drain of the second switching element M32 is the source of the first switching element M31. The source of the second switching element M32 is connected to the drain of the fourth switching element M34, and the source of the fourth switching element M34 supplies the low-potential-side liquid crystal driving power supply voltage (off voltage) VSS2. It is connected to a node that
[0028]
The gate of the first switching element M31 is connected to the output of the first level shifter circuit 31, the gate of the second switching element M32 is connected to the output of the second level shifter circuit 32, and the first switching element M31. The output node Nn connected to the source of the second switching element M32 and the drain of the second switching element M32 are connected to the drain of the third switching element M33, and the sources of the third and fourth switching elements M33 and M34 are driven on the low potential side liquid crystal, respectively. The power supply VSS2 is connected, the gate of the third switching element M33 is connected to the output of the third level shifter circuit 33, and the output terminal Ot is connected to the output node Nn.
[0029]
In other words, the drain of the second switching element M32 is connected to the output node Nn of the inverter composed of the first switching element M31 and the third switching element M33 (the same structure as the conventional unit output circuit shown in FIG. 7). Further, this corresponds to the fourth switching element M34 interposed between the second switching element 32 and the ground.
[0030]
The input sides of the first level shifter circuit 31, the second level shifter circuit 32, and the third level shifter circuit 33 are connected to the output signal terminals O31, O32, and O33 of the control circuit 35, respectively. An output signal Yo from the output terminal Y of the shift register 10 is input to the terminal I31, input signals S32 and S33 from the outside are input to the input signal terminals I32 and I33, and the fourth switching element M34 is externally input. The input voltage V4 is input. The input signal S32 does not directly control the on / off of the second switching element M32, and the input signal S33 does not directly control the on / off of the third switching element M33. .
[0031]
Also in this embodiment, the configuration of the liquid crystal element section in the liquid crystal display panel is as shown in FIG. That is, as shown in the figure, the liquid crystal element is represented as a capacitive element having a liquid crystal capacitance CL. A thin film transistor TFT for applying a display electrode voltage to one liquid crystal element is arranged, and each liquid crystal element and the thin film transistor TFT are arranged in a matrix. The gate electrode G of each thin film transistor TFT is connected to a gate wiring that supplies a gate voltage Vg, and the source electrode S of the thin film transistor TFT is connected to a source wiring that supplies a source voltage VS. The drain electrode D of the thin film transistor TFT is connected to the display electrode A of the liquid crystal element, and the common electrode B of the liquid crystal element is connected to a common electrode wiring for supplying a common voltage Vco. At this time, a parasitic capacitance Cds exists between the drain electrode D and the source electrode S of the thin film transistor TFT, and a parasitic capacitance Cgd exists between the gate electrode G and the drain electrode D of the thin film transistor TFT.
[0032]
FIG. 4 is a timing chart showing temporal changes of respective signals in the unit output circuit BF and the liquid crystal element section.
[0033]
Hereinafter, operations of the output circuit 30 and the liquid crystal element section of the liquid crystal display panel scanning line driver configured as described above will be described with reference to FIGS.
[0034]
Here, the external input voltage V4 is set so that the fourth switching element M34 is always kept on.
[0035]
At time t1, the first frame is entered, and the output signal Yo from the shift register 10 is output at the level “H”. In the initial state, the level of the external input signal S32 is “H”, and the level of the input signal S33 is “L”. In this state, the output level of the output signal terminal O31 of the control circuit 35 is “H”, the output level of the output signal terminal O32 is “L”, and the output level of the output signal terminal O33 is “L”. . Then, the first level shifter circuit 31, the second level shifter circuit 32, and the third level shifter circuit 33 shift the signal amplitude to VDD2-VSS2, the first switching element M31 is turned on, and the second switching is performed. The element M32 and the third switching element M33 are turned off, and the on voltage VDD2 is output from the output terminal Ot. Since the output terminal Ot is connected to the gate electrode G of the thin film transistor TFT1 in the equivalent circuit of the liquid crystal element portion of FIG. 2, the thin film transistor TFT1 is turned on, and the source voltage VS− is applied to the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd. Charges corresponding to the potential difference of the supply voltage Vco are accumulated, and the potential of the display electrode A (display electrode voltage) approaches the source voltage VS.
[0036]
Next, at time t2, when the external input signal S32 becomes level "L" and the input signal S33 becomes level "L", the first switching element M31 is turned off and the second switching element M32 is turned on. Thus, the third switching element M33 is turned off, and the output terminal Ot gradually changes from the on voltage VDD2 to the off voltage VSS2. At this time, in particular, the second switching element M32 is provided with a lower current capability than the third switching element M33.tAs shown from 2 to t3, the falling waveform of the output terminal Ot becomes smooth. As the output terminal Ot falls smoothly, the thin film transistor TFT1 slowly changes from the on state to the off state. Thus, by slowly switching the thin film transistor TFT1 to the OFF state, the liquid crystal capacitor CL and the parasitic capacitors Cds and Cgd can continue to be charged with the source potential VS, so that the potential of the display electrode A (display electrode voltage) is the source. It is held approximately equal to the potential VS. That is, the display electrode voltage fluctuation ΔV can be reduced as compared with the conventional liquid crystal display panel scanning line driver.
[0037]
Subsequently, at time t3, the external input signal S32 is at level “L"In the input signal S33Since the output signal Yo from the shift register 10 is output at the level “L” in synchronization with the clock, the first switching element M31 is turned off and the second switching element M32 is turned on. The third switching element M33 is turned on and the off voltage VSS2 is output from the output terminal Ot. Since the third switching element M33 has a sufficiently large current capability as compared with the second switching element M32, the falling waveform of the output from the output terminal Ot becomes very sharp. At this time, the timing at time t3, that is, the timing at which the input signal S33 changes from the level “L” to the level “H” is set when it is later than the timing at which the thin film transistor TFT1 is turned off. After the thin film transistor TFT1 is turned off, even if the gate voltage Vg of the thin film transistor TFT1 is quickly lowered, the source potential VS corresponding to the charge charged in the liquid crystal capacitance CL and the parasitic capacitances Cds and Cgd varies as long as there is no leakage current. Therefore, the display electrode A is held at the source potential VS.
[0038]
Then, the input signal S32 is raised at time t4, and then the input signal S33 is lowered at time t5 to return to the initial state.
[0039]
Although the description is omitted, also in the second frame, by inputting the input signals S31 and S32 in the same sequence as in the first frame, at time t6 to t11, each of the first frame at time t1 to t5 is basically the same. Therefore, the display electrode voltage variation ΔV can be reduced.
[0040]
According to the liquid crystal display panel scanning line driver of the present embodiment, the fourth switching element M34 that is always turned on according to the external signal V4 is connected between the output node Nn of the inverter and the off-potential VSS2 that is the low-potential side potential. By interposing it in between, the fall of the voltage supplied to the gate electrode G of the thin film transistor TFT can be moderated. That is, since the change in the output Yg (= gate voltage Vg) of the liquid crystal display panel scanning line driver from “H” to “L” becomes gentle (between times t2 and t3 shown in FIG. 4), the liquid crystal capacitance CL and The action of the electric charges accumulated in the parasitic capacitances Cds and Cgd being pulled to the potential of the liquid crystal data driver (source voltage VS) is suppressed, and the fluctuation ΔV of the potential of the display electrode A (display electrode voltage) is reduced. As a result, variation in the variation ΔV in the potential of the display electrode (display electrode voltage) in each frame is reduced, and thus flickering of the screen of the liquid crystal display device can be effectively suppressed. In particular, since the fourth switching element M34 composed of a MOSFET is disposed, an appropriate falling waveform of the gate voltage Vg according to the structure of the output circuit 30 or the liquid crystal element unit can be obtained.
[0041]
Specifically, in the sequence at time t2, the gate voltage of the fourth switching element M34 is adjusted by the voltage value of the input voltage V4 from the outside, so that the output of the output terminal Ot from time t2 to time t3 is adjusted. The falling waveform can be freely adjusted according to the specifications of the liquid crystal display panel.
[0042]
FIG. 5 is a diagram illustrating IV characteristics of the fourth switching element M34. As shown in FIG. 5, the fourth switching element M34 formed of a MOSFET exhibits a saturation characteristic of the current value Ids when the source / drain voltage Vds becomes a certain value or more, and the saturation value is the gate-source voltage Vgs. The bigger is the bigger. Therefore, when the external voltage V4 is increased by utilizing the saturation characteristics of the MOSFET, the output signal Yg shown in FIG. 4 falls steeply, whereas when the external voltage V4 is reduced, the output signal Yg shown in FIG. Falling is gradual. That is, the falling waveform can be adjusted using the saturation region of the IV characteristic. The timing at which the output signal Yg becomes the off voltage VSS2 can be adjusted by setting the timing at which the second switching element M32 is turned on.
[0043]
In the unit output circuit BF shown in FIG. 3, the basic effect of the present invention can be obtained without the second switching element M32.
[0044]
FIG. 6 is a circuit diagram of the unit output circuit BF ′ according to a modification of the present embodiment in which the second switching element M <b> 32 is not disposed. That is, the drain of the fourth switching element M34 is connected to the output node Nn of the inverter (the same structure as the conventional unit output circuit shown in FIG. 7) composed of the first switching element M31 and the third switching element M33. It corresponds to.
[0045]
When the structure shown in the figure is adopted, in the timing chart shown in FIG. 4, the timing at which the output signal Yg becomes the off voltage VSS2 is adjusted by the current driving capability of the fourth switching element M34. That is, if the current driving capability of the fourth switching element M34 is set sufficiently large, the timing at which the output signal Yg becomes the off-voltage VSS2 is advanced, and if the current driving capability of the fourth switching element M34 is set small, The timing when the output signal Yg becomes the off voltage VSS2 can be delayed. In this modification, it is only necessary to add one line for supplying an input signal from the outside as compared with the conventional structure, so that the occurrence of flicker can be suppressed while suppressing an increase in cost.
[0046]
When the structure shown in FIG. 6 is adopted, the fourth switching element M34 may be switched on / off by the external voltage V4 input to the gate of the fourth switching element M34.
[0047]
【The invention's effect】
According to the liquid crystal display panel scanning line driver of the present invention, in the output circuit for generating a voltage to be supplied to the scanning line of the liquid crystal display panel, a transistor for moderating the falling waveform of the output signal is connected to the output node of the inverter. And the low potential supply node, the conditions for reducing flicker due to fluctuations in the liquid crystal display voltage can be freely adjusted according to the specifications of the liquid crystal display panel.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a liquid crystal display panel scanning line driver in an embodiment of the present invention.
FIG. 2 is an electric circuit diagram (equivalent circuit diagram) showing a part of a liquid crystal element portion in a general liquid crystal display panel.
FIG. 3 is a circuit diagram showing a configuration of one unit output circuit in the output circuit of the liquid crystal display panel scanning line driver in the embodiment of the present invention.
FIG. 4 is a timing chart showing a time change of a signal in a unit output circuit and a liquid crystal element unit according to the embodiment of the present invention.
FIG. 5 is a diagram illustrating IV characteristics of a fourth switching element according to the embodiment of the present invention.
FIG. 6 is a circuit diagram of a unit output circuit in a modification of the embodiment of the present invention.
FIG. 7 is a circuit diagram schematically showing a configuration of one unit in an output circuit of a conventional liquid crystal display panel scanning line driver.
FIG. 8 is a timing chart showing a time change of a conventional control voltage.
[Explanation of symbols]
10 Shift register
11 Drive signal input terminal
12 Clock signal input terminal
BF unit output circuit
FF flip-flop
S31 Input signal
S32 input signal
21 First level shifter circuit
22 Second level shifter circuit
23 Third level shifter circuit
24 output terminals
30 Output circuit
35 Control circuit
100 LCD panel scanning line driver
TFT Thin film transistor
M31 first switching element
M32 second switching element
M32 third switching element
M34 Fourth switching element
FF0 D flip-flop
Yg0, Yg1, ... Ygn output signal
VDD1 Logic power supply
VSS1 Ground for logic
VDD2 ON voltage
VSS2 OFF voltage
V4 External voltage

Claims (7)

In a liquid crystal display panel scanning line driver having a unit output circuit for supplying a voltage to a scanning line of a liquid crystal display panel,
The unit output circuit is
A p-channel transistor in which a node for supplying a high potential side voltage is connected to the drain, an output node is connected to the source, and a first input signal is connected to the gate;
An n-channel transistor in which a node for supplying a low potential side voltage is connected to a source, the output node is connected to a drain, and a second input signal is connected to a gate;
A switching element that is provided between the output node and a node that supplies the low-potential-side voltage and that is switched on and off by a voltage applied to an external signal;
A liquid crystal display panel comprising: another switching element interposed between the switching element and the output node for adjusting the falling timing of the output node of the unit output circuit. Scan line driver. The liquid crystal display panel scanning line driver according to claim 1 ,
The liquid crystal display panel scanning line driver, wherein the another switching element has a smaller current driving capability than the n-channel transistor. The liquid crystal display panel scanning line driver according to claim 2 ,
The liquid crystal display panel scanning line driver, wherein the switching element is set to be always on. In the liquid crystal display panel scanning line driver according to claim 3 ,
The switching element and the another switching element are both switching n-channel transistors, and the another switching element and the switching element are provided between the output node and a node supplying the low potential side voltage. A scanning line driver for a liquid crystal display panel, wherein the external signal is connected to the gate of the switching element, and the third input signal is connected to the gate of the other switching element. In the liquid crystal display panel scanning line driver according to claim 4 ,
A liquid crystal display panel scanning line driver comprising a control circuit for controlling a falling waveform of an output signal of the output node corresponding to the unit output circuit. In the liquid crystal display panel scanning line driver according to claim 5 ,
The control circuit controls the first input signal, the second input signal, and the third input signal,
A first state in which the p-channel transistor is turned on, the n-channel transistor and the other switching element are turned off, and a first state in which the p-channel transistor is turned off and the n-channel transistor is turned on. 2. A liquid crystal display panel scanning line driver comprising a third state in which the p-channel transistor and the n-channel transistor are turned off and the other switching element is turned on between the two states . In the liquid crystal display panel scanning line driver according to claim 6 ,
The timing of changing from the third state to the second state is the timing at which the voltage at the output node reaches a predetermined voltage by adjusting the current driving capability of the switching element by the voltage applied to the external signal. A liquid crystal display panel scanning line driver characterized by being set later.

Images