JP3606145B2 - Data transfer control device and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer control device and an electronic device, and more particularly to a data transfer control device and an electronic device for performing data transfer according to a standard such as IEEE 1394 between a plurality of nodes connected to a bus.
[0002]
[Background Art and Problems to be Solved by the Invention]
In recent years, an interface standard called IEEE 1394 has been in the spotlight. This IEEE 1394 standardizes a high-speed serial bus interface that can be used for next-generation multimedia. According to the IEEE 1394, it is possible to handle data such as a moving image that requires real-time performance. In addition to computer peripheral devices such as printers, scanners, CD-RW drives, and hard disk drives, home appliances such as video cameras, VTRs, and TVs can be connected to the IEEE 1394 bus. For this reason, it is expected that digitalization of electronic devices can be dramatically accelerated.
[0003]
In SBP-2 (Serial Bus Protocol-2), which is standardized as a higher-level protocol of IEEE 1394, resets such as agent reset, target reset, and reset start are defined. That is, when an error occurs in the target (printer, scanner, CD-RW, etc.) and it is determined that the data transfer process cannot be continued, the initiator (personal computer, etc.) requests the reset. When such a reset is requested, a received packet that becomes unnecessary due to the reset needs to be discarded.
[0004]
In IEEE 1394, when an electronic device is newly connected to the bus or an electronic device is removed from the bus and the number of nodes connected to the bus increases or decreases, a so-called bus reset occurs. When a bus reset occurs, the topology information of the node is cleared, and all incomplete transactions are canceled. Therefore, all packets received before the bus reset occurs are invalidated.
[0005]
However, in general, firmware for processing packets generally operates on a CPU with a low processing speed. Accordingly, the processing for the received packet is performed after a given time has elapsed after the reception of the packet. For this reason, a large number of unprocessed packets are always present on the target data buffer. Therefore, it takes a lot of time to search for unnecessary received packets by reset (agent reset, bus reset, etc.) from a large number of received packets existing on the data buffer. For this reason, the reset process takes a long time, causing problems such as stalling of the entire system process and excessive firmware processing load.
[0006]
The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a data transfer control device and an electronic apparatus capable of reducing the time required for reset processing and reducing the processing load. Is to provide.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is a data transfer control device for data transfer between a plurality of nodes connected to a bus, and analyzes a received packet written in a data buffer of its own node, Packet analysis means for storing the analyzed received packet in the queue, repeating the analysis of the received packet and storing in the queue until there are no more received packets on the data buffer, and when the received packet on the data buffer is exhausted, it is stored in the queue Packet processing means for processing received packets, and if the processed received packets are packets for instructing resetting, packet discarding for discarding received packets that are not required by the reset among the received packets stored in the queue Means.
[0008]
According to the present invention, the analyzed received packet is not processed immediately but is stored in the queue. Then, when there are no received packets on the data buffer, processing of the received packets stored in the queue is started. If the received packet is a packet for instructing resetting, the received packet that becomes unnecessary by the reset is discarded. In this way, it is possible to prevent unnecessary packet processing from being performed on received packets that are not required by reset (received packets that are affected by reset), and the time required for reset processing can be greatly shortened.
[0009]
Although it is desirable to provide a plurality of queues, one queue may be used. As processing of the received packet performed by the packet processing means, for example, processing such as passing the received packet to a subsequent processing means (request execution means or the like) can be considered. Further, as a process of discarding unnecessary received packets, a process of clearing a queue or the like can be considered, but received packets may be discarded individually.
[0010]
In the present invention, a plurality of queues are prepared as the queue, the packet analyzing unit stores the analyzed received packet in any one of the plurality of queues, and the packet discarding unit processes the received packet. When the packet is a packet for instructing resetting, the queue storing received packets that become unnecessary by resetting is cleared.
[0011]
In this way, received packets that become unnecessary due to reset can be discarded together, so that the process of discarding received packets can be made more efficient.
[0012]
It should be noted that it is desirable that each of the plurality of queues is provided with a queue corresponding to a subsequent processing means (request execution means or the like) that passes the received packet.
[0013]
The present invention also provides a first request execution means for receiving a received packet from the packet processing means and executing a request from another node; and receiving a received packet from the packet processing means and executing a request from another node And a second request execution unit that is also reset when the first request execution unit is reset, and the packet analysis unit is to receive the first request execution unit. The packet is stored in the first queue, the received packet to be passed to the second request execution unit is stored in the second queue, and the packet processing unit receives the reception stored in the first queue. The packet is processed with priority over the received packet stored in the second queue.
[0014]
In this way, the received packet to be passed to the first request execution means is processed preferentially. Accordingly, it is possible to prevent the received packet of the second request execution unit that is reset when the first request execution unit is reset, and to reduce the time required for the reset process. .
[0015]
As the first and second request execution means, for example, a management agent or a fetch agent in SBP-2 can be considered, but the present invention is not limited to this.
[0016]
According to the present invention, the packet discarding means clears both the first and second queues when the processed received packet is a packet for instructing resetting of the first request execution means. It is characterized by.
[0017]
In this way, the received packets of the second request execution means that do not need to be processed are discarded together, so that the processing efficiency can be improved.
[0018]
In the present invention, the second request execution unit includes a third request execution unit that executes a command control request for an upper layer device, and a fourth request execution unit that executes a data transfer request. The analysis means stores the received packet to be passed to the third request execution means in a third queue, stores the received packet to be passed to the fourth request execution means in a fourth queue, and The processing means processes the received packet stored in the third queue with priority over the received packet stored in the fourth queue.
[0019]
In this way, it is possible to preferentially process the received packet to be passed to the third request execution means, and it is possible to interrupt the device command control request during the data transfer process.
[0020]
The present invention also relates to a data transfer control device for data transfer between a plurality of nodes connected to a bus, which analyzes received packets written in the data buffer of the own node and queues the analyzed received packets. And packet analysis means for repeatedly analyzing received packets and storing them in the queue until there are no more received packets on the data buffer, and a packet for processing the received packets stored in the queue when there are no more received packets on the data buffer And a processing unit and a packet discarding unit for discarding a received packet before the occurrence of the reset when a reset for clearing the topology information of the node occurs.
[0021]
According to the present invention, the analyzed received packet is not processed immediately but is stored in the queue. Then, when there are no received packets on the data buffer, processing of the received packets stored in the queue is started. When a reset that clears the topology information of the node occurs, the received packet before the reset occurs is discarded. Therefore, useless packet processing can be prevented from being performed on packets received before the occurrence of reset, and the time required for reset processing can be greatly shortened.
[0022]
Further, the present invention is characterized in that the packet discarding means clears a queue storing received packets when a reset for clearing the topology information of the node occurs.
[0023]
In this way, the received packets before the occurrence of reset can be discarded together, so that the processing efficiency can be improved.
[0024]
Whether or not to clear the queue may be determined every time the received packet is stored in the queue, or may be determined after all the received packets are stored in the queue.
[0025]
The reset for clearing the topology information of the node is preferably a bus reset defined in the IEEE 1394 standard.
[0026]
In the present invention, it is desirable to perform data transfer conforming to the IEEE 1394 standard.
[0027]
An electronic device according to the present invention includes any one of the data transfer control devices described above, a device that performs a given process on the data transfer control device and data received from a partner node via a bus, and a process. And a device for outputting or storing the received data. An electronic apparatus according to the present invention includes any one of the data transfer control devices described above, a device that performs a given process on the data transfer control device and data transmitted to a partner node via a bus, and a process. And a device for capturing data.
[0028]
According to the present invention, it is possible to reduce the processing load of firmware or the like that controls data transfer, and thus it is possible to reduce the cost of electronic devices and increase the processing speed. In addition, since it is possible to prevent a situation in which processing of the entire system is stalled due to occurrence of a reset, the reliability of the electronic device can be improved.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0030]
1. IEEE 1394
First, IEEE 1394 will be briefly described.
[0031]
1.1 Overview
IEEE 1394 (IEEE 1394-1995, P1394.a) enables high-speed data transfer of 100 to 400 Mbps (800 to 3200 Mbps in P1394.b). It is also permitted to connect nodes with different transfer rates to the bus.
[0032]
Each node is connected in a tree shape, and a maximum of 63 nodes can be connected to one bus. If a bus bridge is used, it is possible to connect approximately 64,000 nodes.
[0033]
In IEEE 1394, asynchronous transfer and isochronous transfer are prepared as packet transfer methods. Asynchronous transfer is a transfer method suitable for data transfer that requires reliability, and isochronous transfer is a transfer method suitable for data transfer such as moving images and audio that requires real-time property.
[0034]
1.2 Layer structure
The layer structure (protocol structure) of IEEE1394 is shown in FIG.
[0035]
The IEEE 1394 protocol includes a transaction layer, a link layer, and a physical layer. Serial bus management monitors and controls the transaction layer, link layer, and physical layer, and provides various functions for node control and bus resource management.
[0036]
The transaction layer provides a transaction unit interface (service) to the upper layer, and performs transactions such as a read transaction, a write transaction, and a lock transaction through the interface provided by the lower link layer.
[0037]
Here, in the read transaction, data is transferred from the response node to the request node. On the other hand, in a write transaction, data is transferred from the request node to the response node. In the lock transaction, data is transferred from the request node to the response node, and the response node processes the data and returns it to the request node.
[0038]
The link layer provides addressing, data check, data framing for packet transmission / reception, cycle control for isochronous transfer, and the like.
[0039]
The physical layer provides conversion of logical symbols used by the link layer into electrical signals, bus arbitration, and a physical interface of the bus.
[0040]
1.3 SBP-2
As shown in FIG. 2, a protocol called SBP-2 (Serial Bus Protocol-2) has been proposed as an upper protocol including a part of the functions of the transaction layer of IEEE1394.
[0041]
Here, SBP-2 is proposed in order to make a SCSI command set available on the IEEE 1394 protocol. By using this SBP-2, the SCSI command set used in the existing SCSI standard electronic device can be minimally changed and used in the IEEE 1394 standard electronic device. Therefore, the design and development of electronic equipment can be facilitated. In addition, not only SCSI commands but also device-specific commands can be encapsulated and used, so the versatility is very high.
[0042]
As shown in FIG. 3, in SBP-2, a login process is first performed using a login ORB (Operation Request Block) created by an initiator (for example, a personal computer) (step T1). Next, initialization of the fetch agent is performed using the dummy ORB (step T2). Then, command processing is performed using the command block ORB (normal command ORB) (step T3), and finally logout processing is performed using the logout ORB (step T4).
[0043]
Here, in the command processing in step T3, as shown at A1 in FIG. 4, the initiator transfers the write request packet (issues a write request transaction) and rings the target doorbell register. Then, as shown in A2, the target transfers a read request packet, and the initiator returns a corresponding read response packet. As a result, the ORB (command block ORB) created by the initiator is fetched into the target data buffer. Then, the target analyzes the command included in the fetched ORB.
[0044]
If the command included in the ORB is a SCSI write command, the target transfers a read request packet to the initiator and the initiator returns a corresponding read response packet, as shown at A3. As a result, data stored in the data buffer of the initiator is transferred to the target. For example, when the target is a printer, the transferred data is printed by the printer engine.
[0045]
On the other hand, if the command included in the ORB is a SCSI read command, the target transfers a series of write request packets to the initiator, as indicated by B1 in FIG. Thereby, for example, when the target is a scanner, the scan data acquired by the scanner engine is transferred to the data buffer of the initiator.
[0046]
According to SBP-2, the target can transmit and receive data by transferring a request packet (issuing a transaction) when it is convenient for itself. Therefore, it is not necessary for the initiator and the target to move in synchronization, so that the data transfer efficiency can be improved.
[0047]
In addition to SBP-2, a protocol called FCP (Function Control Protocol) has been proposed as a higher-level protocol of IEEE 1394.
[0048]
1.4 Bus reset
In IEEE1394, a bus reset occurs when power is turned on or when a device is inserted or removed in the middle. That is, each node monitors port voltage changes. When a change occurs in the port voltage, for example, when a new node is connected to the bus, the node that has detected this change informs other nodes on the bus that a bus reset has occurred. The physical layer of each node notifies the link layer that a bus reset has occurred.
[0049]
When a bus reset occurs in this way, the topology information such as the node ID is cleared. Thereafter, the topology information is automatically reset. That is, tree identification and self-identification are performed after the bus reset. Thereafter, management nodes such as an isochronous resource manager, a cycle master, and a bus manager are determined. Then, normal packet transfer is resumed.
[0050]
As described above, in IEEE 1394, topology information is automatically reset after a bus reset, so that a cable of an electronic device can be freely inserted and removed, and a so-called hot plug can be realized.
[0051]
If a bus reset occurs in the middle of a transaction, the transaction is cancelled. Then, the request node that has issued the canceled transaction transfers the request packet again after the topology information is reset. In addition, the response node must not return a response packet of the transaction canceled by the bus reset to the request node.
[0052]
2. overall structure
Next, an example of the overall configuration of the data transfer control device of this embodiment will be described with reference to FIG. In the following, a case where the target (own node) that performs data transfer with the initiator (partner node) is a printer will be described as an example, but the present invention is not limited to this.
[0053]
The data transfer control device 10 of the present embodiment includes a PHY device 12 (physical layer device), a link device 14 (link layer device), a CPU 16 (processor), a data buffer 18 (storage means), and firmware 20 (processing means). including. Note that the PHY device 12, the link device 14, the CPU 16, and the data buffer 18 are arbitrary components, and the data transfer control device 10 of the present embodiment does not need to include all these components.
[0054]
The PHY device 12 is a circuit for realizing the physical layer protocol of FIG. 1 by hardware, and has a function of converting a logical symbol used by the link device 14 into an electrical signal.
[0055]
The link device 14 is a circuit for realizing a part of the link layer protocol and the transaction layer protocol in FIG. 1 by hardware, and provides various services for packet transfer between nodes.
[0056]
The CPU 16 controls the entire apparatus and data transfer.
[0057]
The data buffer 18 is a buffer that temporarily stores transfer data (packets), and is configured by hardware such as SRAM, SDRAM, or DRAM. In the present embodiment, the data buffer 18 functions as a random-accessible packet storage unit, although not particularly limited thereto.
[0058]
The firmware 20 is a program including various processing routines (processing modules) that operate on the CPU 16, and a transaction layer protocol is realized by the firmware 20, the CPU 16 that is hardware, and the like.
[0059]
The device driver 102 included in the personal computer 100 as an initiator is a program including various processing routines for managing and controlling peripheral devices. This program is installed in the personal computer 100 using the information storage medium 110 (FD, CD-ROM, DVD, ROM).
[0060]
Here, the program of the device driver 102 may be downloaded from an information storage medium (hard disk, magnetic tape, etc.) of the host system via a network such as the Internet and installed in the personal computer 100.
[0061]
The firmware 20 (F / W) includes a communication unit 30 (COM), a management agent 40 (MNG), a fetch agent 50 (FCH1), a fetch agent 60 (FCH2), and a print task unit 70 (PRT).
[0062]
Here, the communication unit 30 is a processing module that functions as an interface with hardware such as the link device 14.
[0063]
The management agent 40 (first request execution means) is a processing module that manages login, reconnect, logout, reset, and the like. For example, when the initiator requests the target to log in, the management agent 40 first accepts the login request.
[0064]
The fetch agents 50 and 60 (command block agents, second request execution means) are processing modules for executing a request from the initiator, and more specifically, execute commands included in the command block ORB. Unlike the management agent 40 that can handle only a single request, the fetch agents 50 and 60 can also handle a linked list of ORBs fetched by a request from an initiator.
[0065]
The printer disk unit 70 is a processing module for performing DMA transfer with a printer engine or a scanner engine (upper layer device).
[0066]
The fetch agent 50 (third (second) request execution means) is a processing module for command control of the printer engine and scanner engine (upper layer device) in the subsequent stage, and the fetch agent 60 (fourth (second) The request execution means 2) is a processing module for data transfer with a subsequent printer engine or scanner engine.
[0067]
For example, when it is desired to check the remaining ink amount during data transfer with the printer engine, if there is only one fetch agent, the remaining ink amount cannot be checked until all the data transfer by the ORB linked list is completed.
[0068]
In this embodiment, two fetch agents independent of each other are provided (three or more may be used). Then, the priority of processing of the fetch agent 50 for command control is set higher than the priority of processing of the fetch agent 60 for data transfer. More specifically, as will be described later, the received packet passed to the command control fetch agent 50 is processed with priority over the received packet passed to the data transfer fetch agent 60.
[0069]
By doing so, it is possible to interrupt a printer command control process such as an ink remaining amount check during the data transfer process based on the ORB link list. Therefore, it is possible to check the remaining ink amount without waiting for a long time until the data transfer process is completed, and it is possible to control the command of the device without affecting the data transfer.
[0070]
The communication unit 30 includes a packet analysis unit 32, a packet processing unit 34, and a packet discard unit 36.
[0071]
Here, the packet analysis unit 32 analyzes the received packet written in the data buffer 18 from the personal computer 100 via the IEEE 1394 bus, the PHY device 12, and the link device 14. The analyzed received packet is stored in the queue.
[0072]
This queue can be secured on the local memory of the CPU 16, for example. As will be described later, when there are a plurality of queues, the packet analysis unit 32 stores the received packet in a queue corresponding to the analysis result.
[0073]
Then, when the received packet is stored in the queue, the packet analyzing unit 32 analyzes the next received packet. The received packets are repeatedly analyzed and stored in the queue until there are no more received packets on the data buffer 18.
[0074]
The packet processing unit 34 processes the received packet stored in the queue when there is no received packet on the data buffer 18. More specifically, the received packet stored in the queue is transferred to the management agent 40 (MNG), the fetch agent 50 (FCH1), or the fetch agent 60 (FCH2). For example, when there are a plurality of queues such as a queue for MNG, a queue for FCH1, and a queue for FCH2, the received packets stored in the queue for MNG are passed to the management agent 40. The received packets stored in the FCH1 and FCH2 queues are transferred to the fetch agents 50 and 60, respectively.
[0075]
When the received packet processed by the packet processing unit 34 is a packet instructing reset such as agent reset, target reset, reset start, etc., the packet discard unit 36 resets the received packets stored in the queue. The process of discarding the received packet (received packet affected by the reset) that becomes unnecessary due to the above is performed. For example, when there are a plurality of queues, the received packets are discarded together by clearing the queue of the agent to be reset.
[0076]
Further, when a bus reset (a reset that clears node topology information in a broad sense) occurs, the packet discard unit 36 performs a process of discarding a packet received before the bus reset occurs.
[0077]
3. Features of this embodiment
3.1 Discarding unnecessary packets at reset
In SBP-2, when an error occurs in the target, the initiator can transfer a packet for instructing the target to reset (hereinafter referred to as a reset packet). In this case, various resets with different levels are prepared in SBP-2. For example, reset start is the strongest level of reset and all node states are reset. Further, in the abort task or abort task set, the task or task set is reset, and in the target reset, the target is reset. In the agent reset, only the fetch agent is reset.
[0078]
The reset start and agent reset are transmitted to the target by the initiator writing predetermined information to the predetermined register, and the abort task, abort task set, and target reset are performed using the management ORB transferred from the initiator. To be told.
[0079]
As described above, when the reset packet is transferred from the initiator, it is necessary to discard the packet which becomes unnecessary by the reset. In this case, in the comparative example of FIG. 7, the packet processing (processing for passing the received packet to the agent, etc.) is performed immediately after analyzing the received packet (steps T1, T2). Next, it is determined whether or not the received packet is a reset packet. If the received packet is a reset packet, processing for discarding the received packet is performed (steps T3 and T4). The above processing is repeated until there are no received packets (step T5).
[0080]
However, in this comparative example, packet processing is performed even for a received packet that is destined to be discarded by resetting. Therefore, the reset process becomes very inefficient.
[0081]
In particular, when the data transfer control device of this embodiment is incorporated in a peripheral device such as a printer, a scanner, or a CD-RW, an inexpensive CPU with low processing capability is often used due to product cost constraints. The firmware operating on the CPU is also affected by the restrictions, and the processing speed is slowed down. For this reason, the processing of the received packet is not in time, and a large number of unprocessed received packets exist on the data buffer of the own node (target). Therefore, the problem of increasing the reset processing time becomes more serious.
[0082]
Therefore, in this embodiment, as shown by C1 and C2 in FIG. 8, after analyzing the received packet written in the target data buffer, the analyzed received packet is not immediately processed but stored in the queue. Then, as shown in C3, when there are no received packets on the data buffer, the received packets stored in the queue are processed. Then, as shown in C4, when the processed received packet is a reset packet such as an agent reset, the received packet that is unnecessary by the reset (received packet affected by the reset) is discarded.
[0083]
In this way, it is not necessary to perform packet processing on a received packet that becomes unnecessary without performing packet processing by resetting. Therefore, compared with the comparative example of FIG. 7 in which packet processing is performed on all received packets, the time required for reset processing can be greatly shortened. As a result, it is possible to prevent a situation where the processing of the entire system is stalled due to the reset processing, and to reduce the processing load of the firmware.
[0084]
Furthermore, in this embodiment, a plurality of queues for storing received packets are prepared, and the analyzed received packets are sorted and stored in any of the plurality of queues. When a reset occurs, the queue storing received packets that become unnecessary due to the reset is cleared.
[0085]
More specifically, as shown in FIG. 9A, an MNG queue for storing received packets to be passed to the management agent and an FCH queue for storing received packets to be passed to the fetch agent are prepared. Then, as shown in FIGS. 9A and 9B, the received packet is stored in a queue according to the analysis result of the received packet. That is, a packet to be passed to the management agent is stored in the MNG queue, and a packet to be passed to the fetch agent is stored in the FCH queue.
[0086]
Then, as shown in FIG. 9C, for example, when the received packet is found to be an agent reset (when it is found to be a write packet to the agent reset register), the FCH queue is cleared. That is, the received packet stored in the FCH queue is a packet that is passed to the fetch agent, and is a packet that becomes unnecessary when the agent is reset. Therefore, by clearing the agent queue itself, these unnecessary packets can be discarded together.
[0087]
In this way, if received packets are discarded by clearing the queue, unnecessary received packets can be discarded all at once, and the process of discarding received packets can be made more efficient. Thereby, the reset process can be further speeded up.
[0088]
Further, in the present embodiment, when there is a relationship that the second agent is reset when the first agent is reset, the received packet stored in the queue for the first agent is Processing is prioritized over received packets stored in the agent queue.
[0089]
More specifically, as shown in FIG. 10A, when there is an MNG queue for the management agent (first request execution means) and an FCH queue for the fetch agent (second request execution means). Preferentially processes received packets stored in the MNG queue (the fetch agent is in a reset relationship when the management agent is reset). That is, after the packet processing (processing such as passing a packet to the management agent) for all received packets stored in the MNG queue is completed, the packets are stored in the FCH queue as shown in FIG. Start packet processing for received packets.
[0090]
In this way, as shown in FIG. 10C, for example, when there is a packet instructing a reset start in the received packets stored in the MNG queue, both the MNG queue and the FCH queue can be cleared. . As a result, the received packets stored in the FCH queue are discarded, and unnecessary packet processing is not required for these received packets. As a result, the efficiency of the reset process can be further improved, and the reset process can be completed at high speed.
[0091]
In this embodiment, as shown in FIG. 11A, as a fetch agent (second request execution means), a command control fetch agent FCH1 (third request execution means) and a data transfer fetch agent are used. FCH2 (fourth request execution means) is prepared. The received packet to be passed to the command control fetch agent FCH1 is stored in the FHC1 queue, and the received packet to be passed to the data transfer fetch agent FCH2 is stored in the FHC2 queue. Then, as shown in FIG. 11A, the command control received packets stored in the FCH1 queue are preferentially processed, and after the packet processing for all received packets in the FCH1 queue is completed, FIG. As shown in (B), packet processing of the received packet stored in the FCH2 queue is started.
[0092]
In this way, processing by the fetch agent FCH1 is prioritized, and command control processing by the fetch agent FCH1 can be easily interrupted during data transfer processing by the fetch agent FCH2. Accordingly, it is possible to check the remaining ink amount without waiting for the printing to be completed.
[0093]
3.2 Unnecessary packet processing at bus reset
In IEEE 1394, a bus reset occurs when an electronic device is newly connected to the bus or an electronic device is removed from the bus. When a bus reset occurs, the node topology information is cleared, and all transactions that have not been completed when the bus reset occurs are cancelled. For this reason, all the packets received before the bus reset occurs are invalidated.
[0094]
However, as described above, the CPU that operates in the peripheral device in which the data transfer control device is incorporated has low processing capability. For this reason, the firmware operating on the CPU cannot process received packets at high speed, and a large number of unprocessed received packets exist on the data buffer. Therefore, when a bus reset occurs, it is necessary to distinguish and discard a packet before the bus reset from among these many unprocessed received packets. Therefore, the processing load on the firmware becomes excessive.
[0095]
Therefore, in this embodiment, as shown in FIG. 12A, after analyzing the received packet written in the target data buffer, the analyzed received packet is stored in the queue without being immediately processed. Then, when there are no received packets on the data buffer, the received packets stored in the queue are processed. When a bus reset occurs, the packet received before the bus reset occurs is discarded.
[0096]
More specifically, as shown in FIG. 12B, when a bus reset occurs on the IEEE 1394 bus while the received packet is stored in the queue, the received packet queue is cleared and the bus reset is performed. The received packet before the occurrence is discarded (in this case, it is desirable to discard the received packet on the data buffer). Also, as shown in FIG. 12C, after all received packets are stored in the queue, even when a bus reset occurs during the processing of the received packets, the received packet queue is cleared and the received packets are cleared. Is discarded.
[0097]
By doing so, it is not necessary to perform packet processing on received packets that become unnecessary without performing packet processing due to the bus reset. Therefore, the time required for the bus reset process can be greatly shortened compared to the comparative example of FIG. 7 in which packet processing is performed on all received packets. As a result, it is possible to prevent a situation where the processing of the entire system is stalled due to the bus reset processing, and to reduce the processing load of the firmware.
[0098]
Also, if the received packets are discarded by clearing the queue, a large number of received packets before the occurrence of the bus reset can be discarded together, so that the process of discarding the received packets can be made more efficient. In particular, when a large number of unprocessed received packets exist in the data buffer due to the low processing capability of the CPU, the method of this embodiment for discarding the received packets by clearing the queue is It is very effective for improving the efficiency of the system.
[0099]
4). Processing of this embodiment
Next, a detailed processing example of this embodiment will be described using the flowcharts of FIGS.
[0100]
When an interrupt from the CPU (or link device) occurs, the interrupt factor is analyzed, and the analyzed interrupt factor is cleared (step S1). The interrupt factors include a packet reception interrupt, a bus reset generation interrupt, a DMA transfer end interrupt to the printer, and a CPU timer interrupt.
[0101]
Next, it is determined whether or not the analyzed interrupt factor is a packet reception interrupt (step S2). If it is not a packet reception interrupt, it is determined whether or not a bus reset interrupt occurs (step S3). . If it is a bus reset interrupt, all of the agent queue and the transmission queue are cleared (step S4, see FIGS. 12B and 12C), and the received packet before the bus reset occurs is discarded. .
[0102]
Next, it is determined whether or not there is an interrupt factor from the CPU (step S5). If there is an interrupt factor, the interrupt factor is analyzed, and the analyzed interrupt factor is cleared (step S6). Next, it is determined whether or not there is an unprocessed interrupt factor that has not been analyzed (step S7). If it exists, the process returns to step S2, and if not, the interrupt process is terminated.
[0103]
If it is determined in step S2 that a packet reception interrupt has occurred, it is determined whether or not the received packet is an initiator response packet to the request packet transferred by itself (step S8 in FIG. 14). If the packet is a response packet, processing related to the response packet (pointer control of the storage location of the response packet in the data buffer, etc.) is performed (step S9).
[0104]
Next, based on the packet analysis result, it is determined whether the received packet is a packet to be passed to the agent (step S10). If the packet is to be passed to the agent, the received packet is stored in the queue of the corresponding agent as described in FIGS. 9A and 9B (step S11). For example, a received packet to be passed to the management agent is stored in the MNG queue, and a received packet to be passed to the fetch agent is stored in the FCH queue.
[0105]
Next, it is determined whether a bus reset has occurred (step S12). If a bus reset has occurred, all the agent queues and the transmission queue are cleared as described with reference to FIG. 12B (step S22). On the other hand, if it does not occur, it is determined whether or not the received packet to be stored in the queue still exists on the data buffer (step S13), and if it exists, the process returns to step S11. Then, the processes in steps S11, S12, and S13 are repeated until there are no received packets on the data buffer.
[0106]
Next, after storing the received packet in the queue, it is determined whether or not a bus reset has occurred (step S14). If it has occurred, as described in FIG. 12C, all of the agent queue and the transmission queue are cleared (step S22). On the other hand, if it does not occur, as shown in C3 of FIG. 8, it is determined whether or not there is a process for the received packet stored in the queue (such as a process to be passed to the agent) (step S15). If there is a process, as described with reference to FIG. 10A, the process is performed from an agent queue (for example, MNG queue) having a high priority (step S16).
[0107]
Next, it is determined whether the received packet is a reset packet (a packet for instructing reset) (step S17). For example, in the case of target reset, the agent can determine whether it is a reset packet by analyzing the contents of the ORB. In the case of agent reset or reset start, the agent can determine whether or not the packet is a reset packet by analyzing the write address of the packet.
[0108]
If the received packet is a reset packet, the agent queue affected by the reset is cleared as described with reference to FIGS. 9C and 10C (step S18). For example, when the management agent is reset, both the MNG queue and the FCH queue are cleared. On the other hand, when the fetch agent is reset, only the FCH queue is cleared.
[0109]
Next, it is determined whether there is a vacancy in the transmission buffer on the data buffer and there is a transmission request (step S19). If it exists, packet transmission is performed (step S20). Next, it is determined whether or not a bus reset has occurred (step S21). If so, all of the agent queue and the transmission queue are cleared (step S22). On the other hand, if not, the process returns to step S3 in FIG.
[0110]
Then, the processes of steps S3 to S7, S2, and S8 to S21 are repeated to sequentially process the received packets stored in the queue one by one. That is, first, received packets stored in the highest priority queue (for example, MNG queue) are sequentially processed one by one, and when processing for all received packets is completed, the second priority Process the received packets stored in the queue with higher (for example, FCH1 queue). When processing of all received packets in the queue is completed, the received packets stored in the third highest priority queue (for example, FCH2 queue) are processed. As described above, processing is performed on all received packets stored in the queue.
[0111]
5. Electronics
Next, an example of an electronic device including the data transfer control device of this embodiment will be described.
[0112]
For example, FIG. 15A shows an internal block diagram of a printer which is one of electronic devices, and FIG. 16A shows an external view thereof. A CPU (microcomputer) 510 controls the entire system. An operation unit 511 is used by a user to operate the printer. The ROM 516 stores control programs, fonts, and the like, and the RAM 518 functions as a work area for the CPU 510. A display panel 519 is for informing the user of the operation state of the printer.
[0113]
Print data sent from a partner node such as a personal computer via the PHY device 502 and the data transfer control device 500 is sent directly to the print processing unit (printer engine) 512 via the bus 504. The print data is subjected to given processing by the print processing unit 512, and is printed on paper by a print unit (device for outputting data) 514 including a print header and the like.
[0114]
FIG. 15B shows an internal block diagram of a scanner which is one of electronic devices, and FIG. 16B shows an external view thereof. The CPU 520 controls the entire system. The operation unit 521 is for the user to operate the scanner. The ROM 526 stores control programs and the like, and the RAM 528 functions as a work area for the CPU 520.
[0115]
An image of a document is read by an image reading unit (device for capturing data) 522 including a light source, a photoelectric converter, and the like, and the read image data is processed by an image processing unit (scanner engine) 524. Then, the processed image data is sent directly to the data transfer control device 500 via the bus 505. The data transfer control device 500 generates a packet by adding a header or the like to the image data, and transmits the packet to a counterpart node such as a personal computer via the PHY device 502.
[0116]
FIG. 15C shows an internal block diagram of a CD-RW drive which is one of electronic devices, and FIG. 16C shows an external view thereof. The CPU 530 controls the entire system. The operation unit 531 is for the user to operate the CD-RW. The ROM 536 stores control programs and the like, and the RAM 538 functions as a work area for the CPU 530.
[0117]
Data read from the CD-RW 532 by the reading & writing unit (device for capturing data or device for storing data) 533 including a laser, a motor, an optical system, etc. is input to the signal processing unit 534 and an error occurs. A given signal process such as a correction process is performed. Then, the data subjected to signal processing is directly sent to the data transfer control device 500 via the bus 506. The data transfer control device 500 generates a packet by adding a header or the like to this data, and transmits the packet to a counterpart node such as a personal computer via the PHY device 502.
[0118]
On the other hand, the data sent from the counterpart node via the PHY device 502 and the data transfer control device 500 is sent directly to the signal processing unit 534 via the bus 506. Then, given signal processing is performed on this data by the signal processing unit 534, and the data is stored in the CD-RW 532 by the reading & writing unit 533.
[0119]
15A, 15B, and 15C, in addition to the CPUs 510, 520, and 530, a CPU for data transfer control in the data transfer control device 500 may be provided separately.
[0120]
15A, 15B, and 15C, the RAM 501 (corresponding to the data buffer) is provided outside the data transfer control device 500, but the RAM 501 may be built in the data transfer control device 500. Good.
[0121]
If the data transfer control device of this embodiment is used in an electronic device, even if an error occurs in the data transfer control device or the electronic device and the data transfer control device is reset, the normal state can be restored in a short time. It becomes like this. In addition, even when a new electronic device is connected to the bus and a bus reset occurs, it is possible to recover from the bus reset state in a short time and to prevent a situation where the entire system is stalled.
[0122]
Further, if the data transfer control device of this embodiment is used in an electronic device, high-speed data transfer can be performed. Therefore, when the user gives a printout instruction using a personal computer or the like, printing can be completed with a small time lag. In addition, the user can view the read image with a small time lag after the image capture instruction to the scanner. In addition, data can be read from the CD-RW and data can be written to the CD-RW at high speed.
[0123]
Further, by using the data transfer control device of this embodiment in an electronic device, the processing load of firmware operating on the CPU can be reduced, and an inexpensive CPU or a low-speed bus can be used. Furthermore, since the cost and scale of the data transfer control device can be reduced, the cost and scale of the electronic device can be reduced.
[0124]
In addition to the above, the electronic apparatus to which the data transfer control device of this embodiment can be applied includes, for example, various optical disk drives (CD-ROM, DVD), magneto-optical disk drives (MO), hard disk drives, TVs, VTRs, Various things, such as a video camera, an audio equipment, a telephone, a projector, a personal computer, an electronic notebook, a word processor, can be considered.
[0125]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0126]
For example, the configuration of the data transfer control device of the present invention is particularly preferably the configuration shown in FIG. 6, but is not limited thereto.
[0127]
Further, the method described in the present embodiment is also preferable as a method for discarding received packets, but is not limited to this.
[0128]
In the present embodiment, the case where two or three queues are provided has been described. However, four or more queues may be provided.
[0129]
The present invention is particularly preferably applied to data transfer according to the IEEE 1394 standard, but is not limited to this. For example, the present invention can also be applied to data transfer in a standard based on the same idea as IEEE 1394 or a standard developed from IEEE 1394.
[Brief description of the drawings]
FIG. 1 is a diagram showing a layer structure of IEEE1394.
FIG. 2 is a diagram for explaining SBP-2.
FIG. 3 is a diagram for explaining an outline of SBP-2 data transfer processing;
FIG. 4 is a diagram for explaining command processing when data is transferred from an initiator to a target.
FIG. 5 is a diagram for explaining command processing when data is transferred from a target to an initiator;
FIG. 6 is a diagram illustrating a configuration example of a data transfer control device according to the present embodiment.
FIG. 7 is a flowchart for explaining processing of a comparative example.
FIG. 8 is a diagram for explaining a technique of the present embodiment at the time of resetting.
FIGS. 9A, 9B, and 9C are diagrams for explaining a method of discarding unnecessary packets by preparing a plurality of queues and clearing the queues.
FIGS. 10A, 10B, and 10C are diagrams for explaining a method for preferentially processing a queue having a high priority. FIG.
FIGS. 11A and 11B are diagrams for explaining a technique for preferentially processing a queue of a fetch agent for command control.
FIGS. 12A, 12B, and 12C are diagrams for explaining the method of the present embodiment at the time of bus reset.
FIG. 13 is a flowchart illustrating a detailed processing example of the present embodiment.
FIG. 14 is a flowchart illustrating a detailed processing example of the present embodiment.
FIGS. 15A, 15B, and 15C are examples of internal block diagrams of various electronic devices.
16A, 16B, and 16C are examples of external views of various electronic devices.
[Explanation of symbols]
10 Data transfer control device
12 PHY devices
14 Link device
16 CPU
18 Data buffer
20 Firmware (F / W)
30 Communication Department (COM)
32 Packet analyzer
34 Packet processor
36 Packet discard unit
40 Management Agent (MNG, first request execution means)
50 fetch agent (FCH1, third (second) request execution means)
60 Fetch agent (FCH2. Fourth (second) request execution means)
70 Print Task (PRT)
100 Personal computer
102 Device driver
104 Data buffer
110 Information storage medium

Claims (11)

A data transfer control device for transferring data between a plurality of nodes connected to a bus,
A packet analysis means for analyzing the received packet written in the data buffer of its own node, storing the analyzed received packet in a queue, repeating the analysis of the received packet and storing in the queue until there is no received packet on the data buffer;
A packet processing means for processing the received packet stored in the queue when there is no received packet on the data buffer;
When the processed received packet is a packet instructing resetting, packet discarding means for discarding a received packet that is unnecessary due to the reset among the received packets stored in the queue ,
A plurality of queues are prepared as the queue,
The packet analysis means
The analyzed received packet is stored in one of the plurality of queues,
The packet discarding means,
A data transfer control device , wherein when a processed received packet is a packet instructing resetting, a queue storing received packets that become unnecessary by resetting is cleared . In claim 1,
First request execution means for receiving a received packet from the packet processing means and executing a request from another node;
Receiving a received packet from the packet processing means, executing a request from another node, and a second request executing means having a relationship of resetting itself when the first request executing means is reset ,
The packet analysis means is
The received packet to be passed to the first request execution means is stored in the first queue, the received packet to be passed to the second request execution means is stored in the second queue,
The packet processing means is
A data transfer control device that processes a received packet stored in the first queue in preference to a received packet stored in the second queue. A data transfer control device for transferring data between a plurality of nodes connected to a bus,
A packet analysis means for analyzing the received packet written in the data buffer of its own node, storing the analyzed received packet in a queue, repeating the analysis of the received packet and storing in the queue until there is no received packet on the data buffer;
A packet processing means for processing the received packet stored in the queue when the received packet on the data buffer is exhausted;
When the processed received packet is a packet for instructing resetting, a packet discarding unit for discarding a received packet that is unnecessary due to the reset among the received packets stored in the queue ;
First request execution means for receiving a received packet from the packet processing means and executing a request from another node;
Receiving a received packet from the packet processing means, executing a request from another node, and a second request executing means having a relationship of resetting itself when the first request executing means is reset ,
The packet analysis means comprises:
The received packet to be passed to the first request execution means is stored in the first queue, the received packet to be passed to the second request execution means is stored in the second queue,
The packet processing means is
Wherein the received packet stored in the first queue, the data transfer control device which comprises treating in preference to the received packet that is stored in the second queue. In claim 2 or 3,
The packet discarding means,
A data transfer control device characterized by clearing both the first and second queues when the processed received packet is a packet for instructing reset of the first request execution means. In any of claims 2 to 4 ,
The second request execution means is
A third request execution means for executing a command control request for an upper layer device; and a fourth request execution means for executing a data transfer request;
The packet analysis means comprises:
The received packet to be passed to the third request execution means is stored in a third queue, the received packet to be passed to the fourth request execution means is stored in a fourth queue,
The packet processing means is
The data transfer control device, wherein the received packet stored in the third queue is processed in preference to the received packet stored in the fourth queue. A data transfer control device for transferring data between a plurality of nodes connected to a bus,
A packet analysis means for analyzing the received packet written in the data buffer of its own node, storing the analyzed received packet in a queue, repeating the analysis of the received packet and storing in the queue until there is no received packet on the data buffer;
A packet processing means for processing the received packet stored in the queue when the received packet on the data buffer runs out;
When the reset that clears node topology information has occurred, see contains a discarding packet discarding means for receiving packets before the occurrence of the reset,
The packet discarding means,
Each time a received packet is stored in the queue, it is determined whether the reset has occurred. If it is determined that the reset has occurred, the queue storing the received packet before the reset is cleared. Thus , the data transfer control device , wherein the received packet before the occurrence of the reset is discarded . In claim 6,
The packet discarding means,
A data transfer control device characterized by clearing a queue storing received packets when a reset for clearing topology information of a node occurs. In claim 6 or 7,
A data transfer control device, wherein the reset for clearing the topology information of a node is a bus reset defined in the IEEE 1394 standard. In any one of Claims 1 thru | or 8.
A data transfer control device that performs data transfer conforming to the IEEE 1394 standard. A data transfer control device according to any one of claims 1 to 9,
A device that performs a given process on data received from a partner node via the data transfer control device and the bus; and
And an apparatus for outputting or storing processed data. A data transfer control device according to any one of claims 1 to 9,
A device that performs a given process on the data transfer control device and data transferred to the counterpart node via the bus;
And an apparatus for capturing data to be processed.

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