JP3600830B2 - Processor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing system, and more particularly to a microprocessor LSI and a part of a peripheral circuit for controlling a memory.
[0002]
[Prior art]
The dynamic memory is generally called a DRAM (Dynamic Random Access Memory). A typical dynamic memory LSI specification is described in “Hitachi IC Memory Data Book 3 (DRAM, DRAM module, pages 445 to 464).” The dynamic memory of this document has ten addresses A0 to A9. Although an input terminal is provided, an address given via the input terminal is multiplexed with a row / column (see page 448), and in the read / write access of this document, an address is assigned to a dynamic memory LSI in the order of row and column. (Page 454), and the read access time from the determination of the external address at that time is 70 nanoseconds (1 nanosecond = 10 to the power of (-9) seconds). Page 461), after the first row and column address transfer, the second and subsequent access Scan as long as performed in the same row access can omit the transmission of the row address, the read access time from the external address determination of said second and subsequent is even suppressed as small as 20 nanoseconds.
[0003]
An example of a DRAM control function of a conventional microprocessor (hereinafter simply referred to as a processor) is described in Non-Patent Document 1. On page 4.2.3 of the collection of lecture materials, there is described a diagram in which a processor LSI and two banks of DRAM chips are directly connected. In addition, the timing diagram on page 4.2.8 of Non-Patent Document 1 describes “Check fast page cache-hit” (cache hit of high-speed page). You can guess using mode. This operation can be performed by, for example, storing the row address when the previous dynamic memory was accessed. However, there is no mention of how to use a two-bank DRAM, or the relationship between a high-speed page cache hit and a two-bank DRAM.
[Non-patent document 1]
"4th Hot Chips Lecture Materials, pages 4.2.1 to 4.2.12, August 1992" (Hot Chips IV, pp. 4.2.1-4.2.12). Aug. 1992, held in Stanford Univ.)
[0004]
It is assumed that a conventional processor LSI includes a row / column for a dynamic memory and a multiplexed address among terminals of the processor. FIG. 2 shows an example of access performed by the processor LSI. In FIG. 2, it is assumed that the horizontal direction is the time axis, 201 is a processor access request, 202 is a processor dynamic address terminal A0-9, and 203 is a dynamic memory row address strobe (RAS-n) signal. , 204 indicate a column address strobe (CAS-n) signal of the dynamic memory. "-N" added to the end of the signal line indicates a negative polarity signal. This access occurs, for example, when a block copy is performed, that is, when the contents of the memory in one area are copied to the memory in another area. In FIG. 2, the area starting from address A000 is copied to the area starting from address 7040. However, in the present application, addresses are represented by hexadecimal numbers. Reference numeral 205 is an explanatory diagram showing how a 32-bit physical address is used. Bits (30 to 31) of the physical address are assigned to an address in a word, bits (21 to 29) are assigned to a column address of a dynamic memory, and bits (11 to 20) are assigned to a row address of a dynamic memory. Bit (i) indicates the ith bit when the left end is bit 0. At that time, if you follow the operation in time order, it will be as follows.
Operation 1: Read to address A000. Transfer the row address / column address to the dynamic memory. The row address is 14 because of the address bits (11 to 20). Since the column address is the address bits (21 to 29), it is 0.
Operation 2: Read to address A004. Since the row address is equal to the previous row address, the transfer to the dynamic memory is omitted. Transfer column addresses to dynamic memory.
Operation 3: Write at address 7040. Transfer the row address / column address to the dynamic memory.
Step 4: Read to address 7044. Since the row address is equal to the previous row address, the transfer to the dynamic memory is omitted. Transfer column addresses to dynamic memory.
The subsequent four accesses perform the same operation, and thus will not be described.
[Problems to be solved by the invention]
As shown in this example, in the prior art example, when the row address on the read (source) side and the row address on the write (destination) side are different in block copy processing, each time the access source and destination are switched, the dynamic memory There is a problem that the high-speed mode in which row addresses are omitted cannot be used.
[0005]
An object of the present invention is to solve the problem that the high-speed mode in which the row address of the dynamic memory is omitted cannot be used.
[0006]
Another object of the present invention is to enable the use of a high-speed mode in which a row address of a dynamic memory is omitted in a processor without a multiplexed address terminal for a dynamic memory, and at the same time, minimize the amount of logic outside the processor LSI To provide a signal line interface of a processor LSI for performing the operation.
[0007]
It is another object of the present invention to provide a signal line interface of a processor LSI for setting information on an operation mode of a synchronous dynamic memory from a processor LSI and minimizing an external logic amount of the processor LSI.
[0008]
[Means for Solving the Problems]
A processor for outputting an access address to access a memory, wherein the access address has a row address, a column address, and a bank address, and the processor specifies a position of the bank address among the access addresses. Therefore, it is configured to have a control circuit.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 3 shows an access pattern of an information processing apparatus using the present invention. Reference numerals 301, 114, 117, 116, and 305 correspond to 201 to 205 in FIG.
Omitted. As shown in 205, in the present example, bits (30 to 31) of the 32-bit physical address are the least significant two bits in the word address, bits (21 to 29) are the column address of the dynamic memory, and bit (20). Are allocated to the bank address of the dynamic memory, and the bits (9 to 19) are allocated to the row address of the dynamic memory. Reference numeral 115 denotes a processor LSI terminal indicating a bank bit. In one access, only the dynamic memory LSI specified by the bank bit is accessed.
In the dynamic memory, only one portion divided by the bank bit is accessed in one access. Specific examples of the configuration of the memory will be described in detail in other embodiments. During the access period of addresses A000 and A004, the dynamic memory LSI corresponding to bank 0 is accessed. During the access period of addresses 7040 and 7044, the dynamic memory LSI corresponding to bank 1 is accessed, but the dynamic memory LSI corresponding to bank 0 is not accessed. Thereafter, when reading to address A008, the row address of the dynamic memory LSI corresponding to bank 0 is equal to that of the previous time, so that
Row address transfer can be omitted. During that period, the dynamic memory LSI corresponding to bank 1 is not accessed. Thereafter, when reading to the address 7048, the row address of the dynamic memory LSI corresponding to the bank 1 is the same as the previous row address, so that the row address transfer can be omitted.
Comparing FIG. 3 with FIG. 2, row address transfer at the time of accessing addresses A008 and 7048 can be omitted. In such a case, the access time can be short as described above, and as a result, the processing speed can be improved.
When this block copy process continues, the high-speed page mode can be used and the transfer of the row address can be omitted as long as access to the same row continues at both the source and the destination.
The effects of the present invention on other objects will be described through the following examples.
[0010]
FIG. 1 shows an example of a processor of an information processing apparatus according to an embodiment of the present invention. 100 is a processor. 101 and 102 are row address registers (register = storage unit). 103 and 104 are bits indicating the validity of 101 and 102, respectively, and are called valid bits. 105 and 106 are selection circuits. 105 selects one of the outputs of 103 and 104 and transmits the selection result to the control circuit 108. 106 selects one of the outputs of 101 and 102 and outputs it to the signal line 112. A coincidence comparator 107 compares a row address of the access request address 110 with one of the row address registers 101 and 102 selected by the selection circuit 106. 108 is a control circuit. 109 is a selection circuit.
When an access is made to the external dynamic memory, the processor 100 selects either the row address or the column address portion of the access request address 110 by using the selection circuit 109, and selects the dynamic memory address terminal A (0:10) (114). Output to The control circuit 108 receives the output of the valid bit of the selection circuit 105 and the output signal 113 of the row address comparison of the coincidence comparator 107. The control circuit 108 receives the bank bit portion of the address bus 110. Further, the control circuit 108 outputs signal values of three external terminals BANK (115), RAS-n (117) (-n indicates a signal of negative polarity), and CAS-n (116).
As shown in FIG. 3, a row address, a column address, and a bank address are assigned to the 32-bit physical address.
The flow of processing when the processor 100 issues an access request is as follows.
First, an access request signal from a data processing unit (not shown because the relationship is thin) consisting of an instruction processing unit and an operand processing unit inside the processor is transmitted to the control circuit 108 via the signal line 111. At the same time, the requested access address is transmitted via the address bus PA (0 to 31) (110). The control circuit 108 selects one of the outputs of the row address registers 101 and 102 by the selection circuit 106 using the bank address (bit 20) among the requested addresses. One of the valid bits 103 and 104 is also selected by the selection circuit 105 using the bank address. When the row address selected by the selection circuit 106 is equal to the row portion of the request address and the valid bit is 1, it is called a hit.
If a hit occurs, the bank is accessed at the same row address as the previous access. At that time, the dynamic memory is accessed in an operation mode in which the transmission of the row address of the dynamic memory is omitted.
If it is not a hit, the dynamic memory is first accessed in an operating mode that transfers both row and column addresses of the dynamic memory. Second, the row portion of the request address is registered in the side selected by the bank address out of 101 and 102, and the valid bit (103 or 104) on the same side is rewritten to 1.
The valid bits 103 and 104 have a value of 0 in an initial state after the power is turned on, and have a function of preventing a hit from being erroneously made when the row address coincides by the first access after the power is turned on.
[0011]
FIG. 4 shows a system diagram including the processor 100. Reference numerals 401 and 402 denote synchronous dynamic memory LSIs. The control signals A (0:10) (114), BANK (115), RAS-n (117), and CAS-n (116) of the processor LSI 100 are connected to 401 and 402. However, the internal memory of the synchronous dynamic memory LSI 401 is divided into two banks 403 and 404, and the memory 404 is accessed when BANK (115) = 0 and the memory 403 is accessed when BANK (115) = 1. . Note that 0 of the signal line indicates low potential and 1 of the signal line indicates high potential.
When the BANK (115) signal is 0, a logical 1 is generated at the output of the inverter (logical inverter) 407 and transmitted to the bank 0 memory control circuit 406. This translates into an indication to access bank 0 memory. When the BANK (115) signal is 1, the logical value 1 is transmitted to the bank 0 memory control circuit 405. This translates into an indication to access the bank 1 memory.
In addition, the dynamic memory has the following terminals. i / O0-7 (409, 410) is an 8-bit data input / output signal. WE-n (411, 412) is a write instruction signal of negative polarity, and becomes a logical value 0 at the time of writing. CLK (413, 414) is a clock input terminal. CKE (415, 416) is a clock enable signal, and controls whether or not to transmit a clock to the inside. DQM (407) is an access mask signal, which is used as an output enable of the data input / output signal i / O0-7 at the time of read access and at the time of write access.
Functions as a write enable signal in clock units.
Further, the dynamic memories 401 and 402 have several operation modes when performing a synchronous operation. These are the RAS delay (the number of clock cycles from RAS to data access), the CAS delay (the number of clock cycles from CAS to data access), and the burst length (the cycle until the address counts up and returns to its original state). is there. These mode information are written via address terminals A0-10 when RAS-n (117), CAS-n (116) and WE-n (411) are all at the potential L.
[0012]
FIG. 5 shows a dynamic memory in another system diagram including the processor 100 and its control circuit. Each of 501 and 503 is an inverter (logic inverter). Each of the circuits in 502 is a 2-input AND circuit, and the output value becomes 1 only when both of the input values are 1. Reference numeral 504 denotes a dynamic memory of bank 0, and reference numeral 505 denotes a dynamic memory of bank 1. Reference numerals 506 and 507 denote a row address strobe signal and a column address strobe signal of the negative polarity of the dynamic memory 504 of the bank 0, respectively. 508 and 509 are negative row address strobe and column address strobe signals of the dynamic memory 505 of the bank 1, respectively.
When the signal BANK (115) is 0, the negative pulses (see 303 and 304 in FIG. 3) appearing on RAS-n (117) and CAS-n (116) are transmitted to 506 and 507, respectively. , 508, 509 are not communicated. As a result, the dynamic memory 504 of the bank 0 is accessed. When BANK (115) is 1, pulses of negative polarity appearing on RAS-n (117) and CAS-n (116) are transmitted to 508 and 509, respectively, and are not transmitted to 506 and 507, respectively. As a result, the dynamic memory 505 of the bank 1 is accessed.
[0013]
An example of another processor using the present invention is shown in FIG. 600 is a processor. 601 to 608, 610, and 611 to 613 are the same as 101 to 108, 110, and 111 to 113 in FIG. Processor 600 has a low /
The column does not have a multiplexed address terminal, but has a 32-bit address terminal A (0:31) (614) containing a row address and a column address.
A two-input selector 615 selects either the access request address 610 or the register 617 and outputs it to the address terminal A (0:31) (614). Reference numeral 616 denotes an output buffer of the LSI, whose input and output have the same logical value.
The case where the two-input selector 615 selects the access request address 610 is similar to the operation described with reference to FIG. Hereinafter, a case where the access request address 610 is selected will be described.
The flow of processing when the processor 600 issues an access request is as follows. First, an access request signal is transmitted to the control circuit 608 via a signal line 611 from a processing unit including an instruction processing unit and an operand processing unit inside the processor. At the same time, the access address is transmitted via the address bus PA (0:31) (610). The control logic 608 selects one of the outputs of the row address registers 601 and 602 by using the bank address among the request addresses. Further, one of the valid bits 603 and 604 is selected by the selection circuit 605 using the bank address.
If a hit occurs, the control circuit 608 sets the output terminal SAR (609) to 1. SAR is an output signal indicating access to the same row area. The definition of the hit is the same as the definition in the description of FIG.
If it is not a hit, the control circuit 608 sets SAR (609) to 0. In addition, registration of information in 601, 602, 603, and 604 is performed in the same manner as the example of the processor 100.
The external circuit of the processor LSI 600 can detect that SAR (609) is 1 and use a high-speed operation mode in which the sending of the row address of the dynamic memory is omitted.
[0014]
Unlike the processor LSI 100, the position of the bank bit is not fixed in the processor LSI 600. FIG. 7 shows a configuration diagram of a portion related to a bank bit selection method. 7, 601, 602, 606, 608, and 612 have already been described, so a new description will be omitted. The two-input selector 606 in FIG. 7 is controlled by the bank bit control signal 703. Reference numeral 702 denotes a 21-input selector, which outputs one of the input signals 704, 705,..., 706, 707 to the bank bit control signal 703 according to the control signal 701 from the control logic 608. 704, 705, 706, and 707 are individual address signals of the request address PA (0:31) of the address bus 610 in FIG. The processor 600 can arbitrarily set the control signal 701 by using a specific instruction. In summary, it is possible to use an arbitrary bit between bit positions 0 and 20 in the request address as the bank address.
Next, a case where the two-input selector 615 of FIG. 6 selects the register 617 will be described. Information on the operation mode (RAS delay, CAS delay, burst length) of the synchronous dynamic memory is set in the register 617. By executing a specific instruction in the processor 600, the two-input selector 615 selects the register 617 and outputs it to the address terminal A (0:31) (614). The operation mode setting operation of the synchronous dynamic memory connected to the outside of the processor 600 is achieved by combining with an appropriate external circuit.
[0015]
FIG. 8 shows a configuration diagram of an information processing apparatus using the processor LSI600. FIG. 8 is roughly divided into a processor LSI 600, an external circuit control LSI 801 and a main storage LSI 402 using a synchronous dynamic memory.
First, the transmission path of the address signal 614 of the processor LSI 600 will be described. The address signal 614 is input to the external circuit control LSI 801 and stored in the address register 802 first. Reference numeral 805 denotes a row address of the main storage LSI 402, and reference numeral 806 denotes a column address of the main storage LSI 402. Either 805 or 806 is selected by the two-input selector 803 and sent to the system address bus 811. The address of the system address bus 811 is further transferred to an address terminal of the main storage LSI 402.
The upper address 807 of the address of the address register 802 is decoded by the address decoder 814, and the result of the decoding is transmitted to the chip select terminal 813 of the main storage LSI 402.
Reference numeral 812 denotes a 32-bit system data bus, and data transfer between the processor LSI 600 and the main memory LSI 402 is performed via 812. Since the data terminal of the LSI 402 has an 8-bit width, this apparatus includes a minimum of four LSIs 402 for transmitting and receiving 32-bit data. The external circuit control LSI 801 includes an access request management logic 804. Reference numeral 804 manages a state related to access. An access request signal 808, an identical address instruction signal 609, and a dynamic memory operation mode setting request signal 815 are transmitted from the processor LSI 600 to the access request management logic 804.
The operation of the access request management logic 804 when the signal 815 has the logical value 0 is as follows. First, when the access request is in the signal 808 and the same address instruction signal 609 has a logical value of 0, RAS-n (809) is issued to the main memory LSI 402, and at the same time, the row address 805 is given to the system address bus 811. . Subsequently, CAS-n (809) is issued to the main storage LSI 402, and at the same time, a column address 805 is given to the system address bus 811.
Second, when the access request is in the signal 808 and the same address instruction signal has the logical value 1, the issuance of the RAS-n (809) and the row address 805 is omitted as compared with the first case. When the processor 600 executes the specific instruction described above (the instruction described in the description of the register 617), the operation mode setting request signal 815 becomes a logical value 1. When the signal 815 has the logical value 0, the access request management logic 804 sets RAS-n (809), CAS-n (810), and WE-n (816) to the potential L. At the same time, the value of the operation mode register 617 is transmitted to the main storage LSI 402 via the system address bus 811. Thus, the operation mode setting process of the main storage LSI 402 is achieved. This process is performed at the time of initial power-on processing and at the time of reset. Since the processor 600 includes the operation mode setting request signal 815, a logic conventionally required for generating a signal for generating an operation mode setting processing start signal of the main memory LSI 402, for example, an address decoding logic becomes unnecessary.
[0016]
The present invention is not limited to the specific embodiments described above, and various modifications are possible within the scope of the technical idea.
For example, the number of row address registers and the number of banks of dynamic memory are two, but the number of registers and the number of banks are 4, 8,. . . Can also be increased. Further, the row address register and the match comparator do not necessarily need to be present in the processor LSI, and the same processing as that of the present embodiment can be performed outside the processor LSI, for example, by the external circuit control LSI 801.
[0017]
According to the embodiment of the present invention, in the case of a block copy process, the high-speed operation mode of the dynamic memory can be used in which the transfer of the row address is omitted by holding the source / destination in the row address register. .
Further, in the embodiment of the present invention, by providing the row address hit information 609 as an output signal of the processor LSI 600, a processor having an address terminal that is not multiplexed for a dynamic memory and having an external logic amount of the processor LSI 600 is provided. Is minimized, and the use of a high-speed operation mode of a dynamic memory that omits row address transfer is enabled.
In the embodiment of the present invention, since the processor 600 includes the operation mode setting request signal 815, logic conventionally required to generate a signal for generating an operation mode setting process start signal of the main memory LSI 402, for example, Address decoding logic may not be required.
[0018]
【The invention's effect】
Information on the operation mode of the synchronous dynamic memory can be set from the processor LSI.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a processor LSI of an information processing apparatus using the present invention.
FIG. 2 shows an access pattern (time change) in a conventional information processing apparatus.
FIG. 3 is an access pattern (time change) in an information processing apparatus using the present invention.
FIG. 4 is a system diagram including a synchronous dynamic memory having a two-bank configuration.
FIG. 5 shows a dynamic memory and a control circuit thereof in an information processing apparatus using the present invention.
FIG. 6 is a configuration diagram of a processor LSI of another information processing apparatus using the present invention.
FIG. 7 shows a bank selection circuit and a bank bit selection circuit of the processor shown in FIG. 6;
8 is a configuration diagram of an information processing apparatus using the processor shown in FIG.
[Explanation of symbols]
100: Processor LSI, 101, 102: Row address register (storage unit), 103, 104: Valid bit, 105, 106: Select circuit, 107: Match comparator, 108: Control circuit, 109: Select circuit, 110: Address bus, 111 access request signal, 112 selected row address, 113 comparison result, 114 dynamic memory address terminal, 115 bank control signal, 116 row address strobe signal, 117 column address・ Strobe signal,
201: Processor access request, 202: Dynamic memory address signal,
203: row address strobe signal, 204: column address strobe signal, 205: address assignment diagram of physical addresses,
301: Processor access request, 302: Dynamic memory address signal, 303: Row address strobe signal, 304: Column address strobe signal, 305: Address assignment diagram of physical addresses, 306: Bank control signal,
Reference numerals 401, 402: two banks of synchronous dynamic memories, 403, 404: memories, 405, 406: memory access control circuits, 407: inverters (logical inverters), 408: input / output data mask control signals, 409, 410 ... data terminals, 411, 412 ... write (write) enable signals, 413, 414 ... clock signals, 415, 416 ... clock enable signals,
501, 503: inverter (logic inverter), 502: 2-input AND gate, 504, 505: dynamic memory, 506, 508: row address strobe signal, 507, 509: column address strobe signal,
600: Processor LSI, 601, 602: Row address register, 603, 604: Valid bit, 605, 606, 615: Selection circuit, 607: Match comparator, 608: Control circuit, 609: Same row area instruction signal, 610 .., An address bus, 611, an access request signal, 612, a selected row address, 613, a comparison result, 614, an address terminal, 616, an output buffer, 617, an operation mode register of a dynamic memory,
701: bit position selection signal of bank bit, 702: selection circuit, 703: bank bit signal, 704, 705, 706, 707: individual bit signal line of request address,
801, an external circuit control LSI, 802, an address register, 803, a selection circuit, 804, an access request management logic, 805, a row address, 806, a column address, 807, an upper address, 808, an access request signal, 809, a row address strobe Signal, 810: column address strobe signal, 811: system address bus, 812: system data bus, 813: chip select signal, 814: address decoder, 815: operation mode setting request signal of synchronous dynamic memory, 816: write (Write) enable signal.

Claims (7)

A processor that outputs an access address to access a memory,
The processor has a physical address including the access address,
The access address has a row address, a column address and a bank address,
A control circuit for allocating the column address to some bits of the physical address and specifying a position of the bank address among all bits of the physical address higher than a bit corresponding to the column address; A processor comprising: In claim 1,
The processor further includes a first selector to which the access address is input,
The processor according to claim 1, wherein the first selector receives a control signal output from the control circuit and outputs a bank bit control signal corresponding to the bank address among the access addresses. In claim 2,
The memory has a plurality of banks,
The processor further includes a plurality of address registers provided corresponding to the plurality of banks, and a second selector connected to the plurality of address registers,
The processor according to claim 2, wherein the second selector selects one of the plurality of address registers according to the bank bit control signal. In claim 3,
The plurality of address registers hold a row address of an access address issued to the corresponding plurality of banks,
The first selector outputs a bank bit control signal corresponding to a bank address of a current access address issued to the memory,
The processor further includes a comparator for comparing a row address held in an address register selected by the second selector based on the bank bit control signal with a row address of a current access address. A processor characterized by the above-mentioned. In claim 3 or 4,
The processor has an operation mode in which the row address of the current access address is not output when the row address held in the address register selected by the second selector matches the row address of the current access address. A processor, characterized in that: In any one of claims 1 to 5,
The processor, wherein the position of the bank address can be set by a specific instruction. In any one of claims 1 to 6,
The processor outputs the row address and the column address of the access address in parallel.

Images