JP3589931B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit in which an input buffer and an output buffer (hereinafter, referred to as an input / output buffer) can be freely arranged in a chip internal area.
[0002]
[Prior art]
Recently, the miniaturization of the wafer process has rapidly progressed, and the number of pins of a semiconductor package on which a semiconductor chip has been mounted has been increasing at the same time. For this reason, the area of the internal region of the semiconductor chip becomes relatively small, while the area of the I / O region constituting the outer peripheral portion of the semiconductor chip where the input / output buffer is arranged becomes relatively large, and the entire semiconductor chip becomes large. Many cases where the area is determined by the number of pins have come to occur.
[0003]
A first conventional technique for solving this problem will be described with reference to FIG. 17. A large number of solder balls 172 are mounted on a semiconductor chip 171 and arranged in a semiconductor chip internal region 173 via the solder balls 172. The internal circuit and the electrodes respectively corresponding to the solder balls on the substrate (not shown) are connected.
[0004]
The input / output buffer 174 disposed on the outer peripheral portion of the semiconductor chip internal region 173 includes cells 175A to 175C such as NAND circuits, NOR circuits, and flip-flop circuits disposed in the semiconductor chip internal region 173, RAM blocks, ROM blocks, An output signal from the macro cells 175D to 175F such as a CPU is amplified and output to the solder ball 172, and a signal input from the solder ball 172 is amplified and input to the cells 175A to 175C or the macro cells 175D to 175F.
[0005]
In the semiconductor chip having this structure, the solder balls 172 can be arranged over the entire surface of the semiconductor chip 171, so that the number of pins and the number of pins are larger than those of the semiconductor device in which the input / output buffer 174 and the external leads are connected by bonding wires. When the area of the chip internal region 173 is relatively small, the chip area can be reduced.
[0006]
However, if the number of pins further increases and the number of input / output buffers 174 further increases as compared with the example shown in FIG. 17, the I / O area in which the input / output buffers 174 are arranged further increases. Therefore, the chip area is determined from the number of pins regardless of the circuit size arranged in the chip internal region 173, and the degree of integration of the chip internal region 173, that is, the number of circuit elements / chip area is reduced. There is.
[0007]
A second conventional example that solves the above problem is described in Japanese Patent Application Laid-Open No. 9-69568 as a layout and wiring method for a flip-chip type semiconductor device.
[0008]
Next, a second prior art described in the above publication will be described with reference to the drawings.
[0009]
FIG. 14 is a flowchart showing a method of arranging and wiring the flip-chip type semiconductor device according to the second conventional technique, which will be described below with reference to this drawing.
[0010]
First, the function description data 111 is embodied as circuit diagram data 114 having circuit blocks as constituent elements by logic synthesis (processing step 113) after confirming the operation of the function level by function level simulation (processing step 112). After calculating the chip size based on the circuit diagram data (processing step 115), an arrangement position defining process (processing step 116) that does not distinguish both the input / output buffer and the cells constituting the internal circuit is performed on the chip surface. .
[0011]
Here, the internal circuit means a circuit composed of a large number of cells having basic logic functions such as NAND, NOR, EX-OR and flip-flop, or a macro cell such as RAM, ROM, and CPU. Denotes a circuit having a function of supplying power and inputting / outputting a signal.
[0012]
The size of each of the cells and input / output buffers constituting these internal circuits is determined by an integer value in each of the x direction and the y direction with reference to the unit of the minimum partition in the arrangement called the basic cell.
[0013]
Therefore, the chip size calculation is performed by adding the basic cell number of each circuit block constituting the entire circuit, and further adding an empirically required area amount such as a wiring area and a power wiring area necessary for connection between these circuit blocks ( The processing step 115) is performed.
[0014]
Here, referring also to FIG. 15 showing a plan view when a partition is defined with the basic cell as the minimum unit, when the chip size is determined, the basic cell described above is defined as the minimum unit on the entire chip based on the chip size. Is performed (processing step 116). The mesh-shaped section 155 forms rectangular coordinates in units of basic cells, and various internal blocks 153a to 153d and the input / output buffer 152 are arranged with the same section 155 as a minimum unit. This partition definition is a block arrangement position definition.
[0015]
That is, it is characterized in that there is no distinction between the arrangement position of the input / output buffer and the arrangement position of the circuit blocks forming the internal circuit, and both circuit blocks can be freely arranged.
[0016]
In addition to the processing flows of the above steps 115 and 116, grouping of input / output buffers, that is, buffer division processing is performed as processing of the floor plan (processing step 117) (processing step 118).
[0017]
This grouping considers the consistency of the operation timing, the mutual interference of signals, the positional relationship of the terminals on the substrate on which the semiconductor chip is mounted, the manufacturing process, the test environment, and the like. Vdd) and a group of input / output buffers that may be connected to ground (GND), and a group of input / output buffers that should be connected to another Vdd and GND pair that is electrically separated and independent from each other. Even if it can be connected to a pair of Vdd and GND, it may be in another group depending on the positional relationship of terminals on mounting.
[0018]
Next, the floor plan of the circuit blocks constituting the input / output buffer and the internal circuit is performed. In this processing step, where the input / output buffer is to be placed on the semiconductor chip is determined according to the processing result of the input / output buffer grouping step (processing step 118).
[0019]
At the same time, restrictions on the signal propagation time in the entire LSI including the input / output buffer and the internal circuit, that is, the relative positional relationship of circuit blocks related to the critical path, mutual signal interference, noise interference, other manufacturing processes and tests In addition to taking into account the above restrictions, circuit blocks with a large layout area such as memory blocks should be balanced so that they are suitable for input / output buffers. The positions of the circuit blocks are determined in consideration of the respective cases (processing steps 119 and 120).
[0020]
In particular, the input / output buffers are roughly arranged in accordance with the above-described grouping so that the input / output buffers are arranged in a line in each group (processing step 119).
[0021]
More strictly, the input / output buffers are arranged in a line in either the main axis direction or the sub-axis direction orthogonal to the wiring laying in the automatic wiring processing. Normally, the main axis direction and the sub-axis direction correspond to two orthogonal directions along each side of the semiconductor chip.
[0022]
Here, the long side of a row of rectangles in which the input / output buffers are arranged corresponds to the length of one side of the chip on which the input / output buffers can be arranged (the total length in the vertical or horizontal direction of the block arrangement position definition area 154 in FIG. 15). It can exceed that. In that case, the one input / output buffer group is further subdivided, and the subdivided groups are rearranged so as to maintain a single line.
[0023]
The circuit blocks that determine the arrangement position in the floor plan (processing step 117) are the input / output buffers and the circuit blocks that constitute the internal circuits that are subject to the above-described various considerations. Delegated to processing. Note that, similarly to the above-described arrangement position definition (processing step 116), there is no distinction in the arrangement area between the input / output buffer and the circuit block constituting the internal circuit in the floor plan.
[0024]
With the processing described above, the floor plan of FIG. 14 (processing step 117) ends.
[0025]
In the next processing step, a macro data generation processing for generating various data necessary for treating input / output buffer blocks arranged in a line including the Vdd and GND terminals as one macro is performed (processing step 122). .
[0026]
Next, a signal wiring length between blocks is predicted based on the floor plan data, and a tentative wiring length simulation is performed using the electric load amount (processing step 123). Here, it is checked whether or not the LSI circuit operates as expected. If there is a defect, the operation is returned to the appropriate previous process which is not shown in FIG. Do.
[0027]
If the operation is confirmed, the process enters the automatic placement and routing processing step 124. In this step, in addition to the circuit blocks (specifically, two types of absolute position specification and relative position specification called grouping) that have been specified in the floor plan described above, the specification has not been received. The arrangement positions of all blocks including the remaining circuit blocks are determined, and in that state, automatic wiring is performed for signal lines between block terminals.
[0028]
Here, since all the actual wiring lengths in the chip are determined, the operation is confirmed by an actual wiring length timing simulation in consideration of the electric load of the wiring (processing step 125). If there is a defect, the process returns to the appropriate previous process, and the necessary processes are repeated until the operation is finally confirmed.
[0029]
Thereafter, the symbolic data used in the processing up to now is converted into mask data 126 for manufacturing a mask, and the process proceeds to a mask manufacturing process.
[0030]
The above is the design flow of the placement and routing method for the flip-chip type semiconductor device according to the second conventional technique.
[0031]
Next, a semiconductor chip 160 designed by using the flip-chip type semiconductor device arrangement and wiring method according to the second conventional technique will be described with reference to FIG.
[0032]
The input / output buffer 161A has the smallest area among the input / output buffers, and has the lowest current driving capability. Reference numeral 161B denotes an input / output buffer configured by connecting three input / output buffers 161A in parallel, and has a medium current driving capability. Reference numeral 161C denotes an input / output buffer configured by connecting six input / output buffers 161A in parallel. In this example, the current driving capability is the largest.
[0033]
The power (Vdd) wiring 162 and the GND wiring 163 pass through the inside of each input / output buffer in parallel, and supply current to the input / output buffers constituting each group by these wirings 162 and 163.
[0034]
In the internal circuit arrangement areas 164A to 164D, circuit blocks forming internal circuits are arranged. As can be seen from FIG. 16, in the placement and routing method of the flip-chip type semiconductor device according to the second prior art, the input / output buffers are provided for a plurality of groups not only in the outer peripheral portion of the semiconductor chip 160 but also in the internal region. Are also arranged in a line.
[0035]
It should be noted that the arrangement direction of the input / output buffer is the same as that of the power supply (Vdd) wiring 162 and the GND wiring 163.
[0036]
[Problems to be solved by the invention]
The layout method of the semiconductor integrated circuit according to the first prior art described above requires a very large number of pins, and if the number of input / output buffers arranged on the outer peripheral portion of the semiconductor chip increases with this, The area of the I / O area where the buffer is arranged is relatively larger than the area of the chip internal area where the internal circuit is arranged, and the chip area is independent of the circuit size arranged in the chip internal area. Therefore, the degree of integration of the chip internal area, that is, the number of circuit elements / chip area is reduced.
[0037]
A feature of the arrangement and wiring method of the flip-chip type semiconductor device described in Japanese Patent Application Laid-Open No. 9-69568 is that an input / output buffer is also arranged in an internal region of a chip so that an area of an I / O region is relatively small. The feature is that the degree of integration is uniformed over the entire semiconductor chip by balancing the area of the I / O region and the area of the chip internal region.
[0038]
On the other hand, in a semiconductor integrated circuit whose speed has been rapidly increasing recently, a timing margin is extremely small, and a delay due to a wiring capacitance hinders an increase in speed.
[0039]
In other words, if the wiring length between the input / output buffer and the internal circuit connected to it becomes longer, the wiring delay increases, and the constraints on the wiring delay are not satisfied.Therefore, the layout design must be repeated many times to reduce the wiring delay. Must.
[0040]
In the placement and wiring method of the flip-chip type semiconductor device described in the above-mentioned publication, there is a strong restriction that the grouped input / output buffers must be basically arranged in a line. The buffer and the internal circuit cannot be freely arranged. In particular, when the number of input / output buffers constituting one group is large, the length of the arrangement area in which the input / output buffers are arranged in a line becomes long, and the minimum amount of wiring for connecting the input / output buffers and the internal circuit is minimized. However, there is a problem in that it is difficult to implement such a configuration, and there is a high possibility that a timing error due to a wiring delay occurs.
[0041]
The above contents will be described in more detail with reference to FIG. 12 (a). FIG. 12 (a) shows the connection between an input / output buffer and a cell or a macro cell in a layout and wiring method of a flip-chip type semiconductor device according to a second conventional example. The relative positional relationship is shown.
[0042]
In FIG. 12A, reference numerals 121A to 121E denote input / output buffers, 122 denotes a cell or a macro cell, and 123A to 124E denote wirings for connecting the input / output buffers 121A to 121E and the cell or the macro cell 122, respectively.
[0043]
In the conventional layout method of the flip-chip type semiconductor device, the input / output buffers can be arranged only in one line. Therefore, if the wiring 123C is made the minimum length, the wirings 123A and 123E become long. For this reason, a wiring delay caused by the wirings 123A and 123E increases, and a timing error is likely to occur.
[0044]
Further, in order to eliminate the above-described timing error, the arrangement and wiring of the cells or macrocells constituting the input / output buffer and the internal circuit must be redone many times, which causes a problem that the design period is lengthened. .
[0045]
Therefore, an object of the present invention is not only to arrange an input / output buffer group arrangement area for grouping and arranging a plurality of input / output buffers in an internal area of a chip, but also to arrange an input / output buffer group It is an object of the present invention to provide a layout method of a semiconductor integrated circuit which can be arranged in a shape in which each wiring length with each input / output buffer constituting a buffer group arrangement area is as short as possible.
[0046]
It is another object of the present invention to provide a layout method of a semiconductor integrated circuit which does not cause a timing error due to a wiring delay caused by a wiring connecting an input / output buffer and an internal circuit.
[0047]
Still another object of the present invention is to provide a semiconductor integrated circuit capable of eliminating a timing error with a small number of layout corrections even if a timing error occurs due to a wiring delay caused by a wiring connecting an input / output buffer and an internal circuit. An object of the present invention is to provide a circuit layout method.
[0048]
[Means for Solving the Problems]
Therefore, a layout method of a semiconductor integrated circuit according to the present invention provides a plurality of internal circuit blocks and an interface between the plurality of internal circuit blocks and the outside, and is arranged adjacent to each other in the X direction or the Y direction. In any direction A first step of generating circuit connection information of a semiconductor integrated circuit including a plurality of input / output buffers to which a power supply wiring and a GND wiring are commonly connected;
A second step of grouping the plurality of input / output buffers into a plurality of input / output buffer groups corresponding to a plurality of electrically independent power supplies based on the circuit connection information;
A third step of defining a partition for setting an arrangement grid for common arrangement on a semiconductor chip over the entire surface of the semiconductor chip without distinguishing both the input / output buffer and the internal circuit block;
A fourth step of arranging the plurality of input / output buffers constituting the input / output buffer group on the arrangement grid so as to be adjacent to each other and arranging the plurality of internal circuit blocks on the arrangement grid;
The power supply wiring and the GND wiring which are independent for each of the input / output buffers for the plurality of input / output buffers constituting each of the input / output buffer groups; the power supply wiring and the GND wiring for the internal circuit block; A fifth step of interconnecting the internal circuit blocks and interconnecting the plurality of input / output buffers.
[0049]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a first embodiment of a semiconductor integrated circuit layout method according to the present invention will be described with reference to the drawings.
[0050]
First, the input / output buffer used in the layout method of the semiconductor integrated circuit of the present invention will be described with reference to FIG. FIG. 5 is a layout diagram of an input / output buffer according to the present invention. Reference numeral 501 denotes a cell frame of the input / output buffer. The input / output buffer is arranged using a reference point 507 provided on the cell frame 501 as a reference point.
[0051]
Reference numeral 502 denotes a VDD wiring made of an upper layer, for example, a sixth-layer aluminum wiring for supplying a current to a transistor (not shown) constituting an input / output buffer, and is arranged in the X direction. Similarly, reference numeral 504 denotes a VDD wiring made of a lower layer, for example, a fifth layer of aluminum wiring, and is arranged in the Y direction.
[0052]
Reference numeral 503 denotes an upper layer connected to each transistor constituting the input / output buffer, for example, a GND wiring made of a sixth-layer aluminum wiring, which is arranged in the X direction. Similarly, 505 denotes a lower layer, for example, a fifth-layer aluminum wiring. This is a GND wiring made of wiring, and is arranged in the Y direction. Reference numeral 506A denotes a through hole connecting the upper VDD wiring 502 and the lower VDD wiring 504, and reference numeral 506B denotes a through hole connecting the upper GND wiring 503 and the lower GND wiring 505.
[0053]
With such a configuration, when the input / output buffers are arranged adjacent to each other in the X direction or the Y direction, the VDD wirings and the GND wirings of the input / output buffers adjacent to each other are connected to each other on the cell frame 501. . For example, when the input / output buffers are arranged adjacent to each other in the X direction, the VDD wirings 502 constituting the adjacent input / output buffers are connected to each other on the cell frame 501, and similarly, the GND wirings constituting the adjacent input / output buffers The wirings 503 are connected to each other on the cell frame 501. Similarly, in the Y direction, the VDD wiring and the GND wiring forming the adjacent input / output buffers are connected to each other on the cell frame 501.
[0054]
Therefore, by arranging a plurality of input / output buffers belonging to the same group adjacent to each other in the X direction or the Y direction, the VDD wiring and the GND wiring of the input / output buffers constituting the same group are automatically connected.
[0055]
Next, a semiconductor chip 601 laid out using the input / output buffer according to the present invention will be described with reference to FIG. As shown in FIG. 6, the input / output buffer arrangement areas 602A, 602B, and 602C can have various shapes. That is, the input / output buffer arrangement area 602A is constituted by a unit input / output buffer having a minimum area, and the input / output buffer arrangement area 602B is constituted by four unit input / output buffers and has a convex shape.
[0056]
In addition, the input / output buffer arrangement area 602C is composed of six unit input / output buffers and has an L-shape. As described above, according to the semiconductor integrated circuit layout method of the present invention, an input / output buffer arrangement region having various shapes such as a convex shape, an L-shape, a convex shape, a crank shape, and a step shape is constituted by a unit input / output buffer; It is characterized in that the VDD wiring and the GND wiring of each unit input / output buffer constituting the same input / output buffer arrangement area are automatically and commonly connected.
[0057]
Next, a layout method for a conductor integrated circuit according to the present invention will be described with reference to the flowchart shown in FIG. Processing steps surrounded by a bold frame and a dotted line in the figure are processing different from the arrangement and wiring method of the flip-chip type semiconductor device according to the second conventional example described with reference to FIG.
[0058]
First, in step S11, the function of the LSI is described using VHDL or the like so as to satisfy the specifications required for the semiconductor integrated circuit (LSI), and the function description data 11 is output.
[0059]
Next, in step S12, a simulation at the function level is performed on the function description data 11 generated in step S11, and operation verification at the function level is performed. Then, the function description data 11 is corrected until the result of the operation verification satisfies the required specifications.
[0060]
Subsequently, in step S13, logic synthesis is performed using the function description data 11 that satisfies the verification of the function level simulation, and circuit connection information 12 including circuit blocks as components is generated.
[0061]
Next, with reference to the circuit diagram connection information 12, in step S15, an initial chip area representing a rough chip area in an initial stage where the chip area is not determined is calculated. FIG. 2 is a flowchart showing a detailed flow of step S15, and the process of step S15 will be described in detail with reference to FIG.
[0062]
First, referring to the pin information 22 included in the circuit connection information 12, in step S21, the number of pads formed on the semiconductor chip corresponding to the input signal pins or output signal pins which are external terminals, ie, signal pads The number (N1) is calculated. In step S22, the number of pads formed on the semiconductor chip corresponding to the external power supply, that is, the number of external power supply pads (N2) is calculated. In step S23, the number of internal power supplies connected to the internal power supply is calculated. The number of pads, that is, the number of internal power supply pads (N3) is calculated, and in step S24, the number of signal pads (N1), the number of external power supply pads (N2), and the number of internal power supply pads (N3) are added to obtain the total number of pads. Calculate the number (N).
[0063]
Here, the internal power supply pad is a pad used for checking a voltage or the like of an internal power supply generated by increasing or decreasing an external power supply at a wafer stage.
[0064]
Next, referring to the solder ball pitch d stored in the solder ball pitch information 21 and the total number of pads calculated in step S24, all the pads of the signal pad, the external power supply pad, and the internal power supply pad are determined. An area S1 when the semiconductor chips are spread on the semiconductor chip is calculated by the following equation (1).
[0065]
S1 = d ² × (square root N-1) ² + Α (1)
Here, the first term (square root N-1) indicates the number of sides divided by the pitch d when all the pads are laid out in a square. Also, d is the solder ball pitch, which substantially matches the pitch of the pads.
[0066]
Next, referring to the cell information 23 for storing the type of cell and the number of cells mounted on the semiconductor chip and the cell utilization information 24 for storing the cell utilization, the area S2 is changed to the next (step S26). It is calculated by the equation 2).
[0067]
S2 = total cell area / cell usage rate + β (2)
Here, the total cell area is the total area of the cells arranged on the semiconductor chip, and the cell usage rate is generally a value obtained by dividing the area of the semiconductor chip by the total cell area. It is calculated from an empirical formula that takes into account various factors such as the degree and the design period.
[0068]
In Equations (1) and (2), α and β are correction terms for the area, and are corrected so that the length of the side of the semiconductor chip is an integral multiple of the section definition. Referring to FIG. 7, solder balls 73 are arranged in a matrix on a semiconductor chip 71, and the semiconductor chip 71 is configured with a partition definition 72 as a unit. At this time, the correction areas 74 corresponding to the correction terms α and β are provided such that the length of the side of the semiconductor chip 71 is an integral multiple of the section definition 72.
[0069]
Next, in step S27, the area S1 is compared with the area S2. If the area S1 is larger than or equal to the area S2, the initial chip area S is set as the area S1 in step S28, and if the area S1 is smaller than the area S2. In step S29, the initial chip area S is set to an area S2. That is, the larger one of the areas S1 and S2 is set as the initial chip area.
[0070]
For example, when the total number of pads N is 120 and the pitch d of the solder balls is 1 mm, S1 = 10.99.1 + α is obtained from the equation (1), and S1 = 100 mm by setting the correction term α to 0.9. ² (10 mm □).
[0071]
From the initial chip area S obtained as described above, the length of the side of the initial chip where S = a × b is calculated.
[0072]
Next, the process proceeds to step S16 in FIG. 1, and as shown in FIG. 7, a partition definition 72 that does not distinguish between the layout area and the layout grid of both the input / output buffer and the circuit block constituting the internal circuit is formed on the entire surface of the initial chip 71. Set over.
[0073]
In step S17, the input / output buffers are grouped in step S171 with reference to the layout restriction data 13 storing various layout conditions for the input / output buffers and the circuit blocks constituting the internal circuit. In step S <b> 172, the general layout of each input / output buffer and the specific internal circuit block specified by the layout restriction data 13 are performed, and in step S <b> 173, the specific internal circuit block specified by the input / output buffer and the layout restriction data 13. Fine-tune the placement position of.
[0074]
The internal circuit blocks other than the specified specific internal circuit block are automatically arranged in step 30 described later.
[0075]
First, the grouping of the input / output buffers in step S171 will be described more specifically. All the input / output buffers included in the circuit connection information 12 are grouped into a plurality of groups with reference to the circuit connection information 12.
[0076]
This grouping is performed in consideration of the operation timing consistency, the mutual interference of signals, the positional relationship of the terminals on the board on which the chip is mounted, the manufacturing process, and the layout restriction data 13 such as the test environment.
[0077]
In this case, each group is provided with a required number of power supply cells for supplying power to the input / output buffers constituting each group and GND cells connected to the GND wiring of each input / output buffer. That is, the power supply wiring and the GND wiring of each group are basically independent of each other.
[0078]
Next, in steps S172 and S173, a specific circuit block specified by the input / output buffer and the layout restriction data 13 is roughly arranged on the semiconductor chip. At this time, layout restrictions related to critical paths, crosstalk between signals, malfunctions caused by noise jumping into the signal lines, various restrictions in testing, and the balance of the layout positions of macrocells with large areas and input / output buffers In consideration of the data 13, the arrangement of each input / output buffer, the arrangement of specific circuit blocks constituting an internal circuit, and the relative arrangement of each input / output buffer and a specific circuit block so as to satisfy these conditions. Do.
[0079]
For example, recently, ASICs are often equipped with high-speed A / D converters, D / A converters, PLL circuits, and the like, but these analog circuits are extremely sensitive to noise.
[0080]
However, as the speed of the digital circuit increases, the noise power of the noise increases, and the noise in the analog circuit is easily mixed. Therefore, it is extremely important how to arrange a circuit block that generates noise and an analog circuit so that the characteristics of the analog circuit do not deteriorate.
[0081]
In steps S172 and S173, unlike the layout and wiring method of the flip-chip type semiconductor device according to the second conventional example, the input / output buffer layout areas 602A, 602B and 602C are formed in various shapes as shown in FIG. Can be. That is, in the second conventional example, the input / output buffer arrangement areas can be basically arranged only in one row, which is a large restriction on the arrangement. However, by using the input / output buffer according to the present invention, the rectangular area having the minimum area can be obtained. An input / output buffer having various shapes such as a unit input / output buffer having a shape, an input / output buffer having a convex shape, an input / output buffer having an L-shape, and the same input / output buffer can be formed. The VDD wiring and the GND wiring of each unit input / output buffer constituting the arrangement area are automatically and commonly connected.
[0082]
As a result, the above-mentioned critical path, crosstalk between signals, malfunction caused by noise jumping into the signal line, various restrictions in testing, balance of arrangement of macro cell with large area and input / output buffer, etc. It is possible to arrange each input / output buffer, the arrangement of specific circuit blocks that constitute the internal circuit, and the relative arrangement of each input / output buffer and specific circuit block in consideration of various related conditions. is there.
[0083]
The above contents will be described in more detail with reference to FIG. 12 (b). FIG. 12 (b) shows the relative positional relationship between the input / output buffer and the cell or macro cell when the input / output buffer according to the present invention is used. ing.
[0084]
In FIG. 12B, reference numerals 121A 'to 121E' denote input / output buffers according to the present invention, and reference numerals 123A 'to 124E' denote wirings for connecting the input / output buffers 121A 'to 121E' and the cell or macrocell 122, respectively. .
[0085]
Since the input / output buffers 121A 'to 121E' according to the present invention can be arranged in a U-shape as shown in FIG. 12B, the input / output buffers 121A 'to 121E' should be arranged so as to surround the cell or the macro cell 122. Can be done.
[0086]
Therefore, the lengths of the wirings 123A 'to 124E' can be equalized as compared with the case of the layout and wiring method of the flip-chip type semiconductor device according to the second conventional example shown in FIG. Therefore, when a semiconductor integrated circuit is laid out using the input / output buffers 121A 'to 121E' according to the present invention, a timing error is less likely to occur.
[0087]
In order to facilitate the explanation, the steps inside the floor plan are described in order. However, in actuality, various setups are conceivable depending on the design target at each time, and the order of the steps is not necessarily described above. You do not need to follow the instructions.
[0088]
Next, in step S18, steps from automatic placement of internal blocks other than a specific internal block to timing verification by actual wiring are performed. This processing step will be described in detail with reference to FIG.
[0089]
First, in step 30, automatic placement of internal circuit blocks other than the specific internal circuit block designated by the placement restriction data 13 is performed, and the placement data, the input / output buffer generated in step S173, and the specific internal circuit block From the placement data, the placement data 31 of all the circuit blocks including the input / output buffer is generated.
[0090]
Next, in step S31, the wiring length between the circuit blocks is predicted with reference to the placement data 31, the wiring capacity of the wiring is calculated using the predicted wiring length, and the timing verification using the temporary wiring is performed. That is, a timing simulation is performed using temporary wiring, and the result is output as error information.
[0091]
If the above timing conditions are satisfied, in step S32, the detailed arrangement of all the circuit blocks including the input / output buffer and the internal circuit block and the detailed wiring based on the detailed arrangement are automatically performed using a computer. The placement / wiring data 32 is generated.
[0092]
If it is determined in step S31 that the timing condition is not satisfied, the input / output buffer and the specific internal circuit block arranged in step S173 or the circuit blocks other than the specific internal circuit arranged in step S30 are determined. Then, in step S33, by changing the arrangement so that part or all of these arrangements satisfy the timing condition, it is determined whether or not the result satisfies the timing condition, and it is determined that the timing change is satisfied by the change in the arrangement. If so, the arrangement is corrected in step S34, and the arrangement data 31 is updated to the corrected new arrangement data.
[0093]
Next, in step S35, the actual wiring length between the circuit blocks is extracted with reference to the placement / wiring data 32, the wiring capacitance of the wiring is calculated using the extracted actual wiring length, and the timing verification using the actual wiring is performed. Do. That is, a timing simulation is performed using actual wiring, and the result is output as error information. If it is determined that the timing is satisfied, the symbolic layout data used in the above processing is all converted into artwork data for mask production, and becomes data for mask production.
[0094]
If it is determined in the processing step S35 that the timing is not satisfied, the wiring constituting the placement / wiring data 32 is changed in step S36 so as to satisfy the timing condition. As a result, the timing is satisfied. If it is determined that it is possible to change the wiring so as to satisfy the timing by changing a part or all of the wiring between the circuit blocks, the wiring is changed in step S37 and the placement / wiring data 32 is changed. Is updated to the corrected new wiring data.
[0095]
When it is determined that the timing condition is not satisfied even if the arrangement of the input / output buffer and the internal circuit block is changed in step S33, an enlarged chip area obtained by increasing the chip area is calculated in step S19 in FIG.
[0096]
Next, the processing flow for expanding the chip area in step S19 will be described in detail with reference to FIG.
[0097]
First, in step S41, the number of errors K that have caused a timing error is calculated from error information in the timing simulation using the temporary wiring or the timing simulation using the actual wiring.
[0098]
Next, in step S42, an increase rate g of the wiring grid is determined. Here, the increase rate g of the wiring grid is a ratio of the number of wiring grids increasing to the original number of wiring grids. For example, when three wiring grids are increased for 100 wiring grids, Is 3%.
[0099]
Next, in step S43, the wiring grid enlargement ratio γ is calculated from the following equation (3) from the wiring grid increase rate g calculated in step S42 and the wiring grid interval D.
[0100]
γ = gD (μm) (3)
Next, in step S44, one side of the semiconductor chip in the X-axis direction and the Y-axis direction is calculated from the following equation (4) based on the number of errors K calculated in step S41 and the wiring grid enlargement ratio γ calculated in equation (1). Are enlarged by ΔX and ΔY calculated from.
[0101]
ΔX = ΔY = (K ÷ 2) × γ (μm) (4)
That is, the lengths of the sides in the X-axis direction and the Y-axis direction are made equally long according to the number of errors K.
[0102]
In the above description, the length of the side of the semiconductor chip is uniformly increased in the X-axis direction and the Y-axis direction according to the number of errors K. However, the present invention is not limited to this. May be changed.
[0103]
Next, in step S45, the solder ball interval information 401 in which the solder ball interval H (μm) is stored, and the enlarged lengths ΔX and ΔY of the sides of the semiconductor chip in the X-axis direction and the Y-axis direction calculated in step S44. It is determined whether or not the solder ball spacing H has been exceeded. If the enlarged lengths ΔX and ΔY have exceeded the solder ball spacing H, the solder balls have a value obtained by rounding ΔX (= ΔY) / H to an integer in step S46. Are increased in the X-axis direction and the Y-axis direction, respectively, and the solder balls are not added unless the enlarged lengths ΔX and ΔY exceed the solder ball interval H.
[0104]
Next, after performing the processing of steps S45 and S46, the processing step S16 shown in FIG. 1 is executed. That is, the partition definition that does not distinguish both the input / output buffer and the circuit block constituting the internal circuit is updated on the enlarged chip obtained from the enlarged chip area in response to the results of step S45 and step S46, and the updated partition is On the basis of the definition, in step S172, a specific circuit block constituting an input / output buffer and an internal circuit is roughly arranged.
[0105]
In this way, the processing flow described above is repeatedly executed until all timing errors are eliminated, and when all timing errors are eliminated, the chip area at that time is determined as the final chip area of the semiconductor integrated circuit.
[0106]
That is, when the initial chip area is calculated in step S15 according to the layout method of the semiconductor integrated circuit according to the present invention, the chip area is set to be as small as possible. By appropriately increasing the chip area, it is possible to design a semiconductor integrated circuit that satisfies the timing conditions without unnecessarily increasing the chip area.
[0107]
Next, how the chip area is specifically reduced when designing using the layout method of the semiconductor integrated circuit according to the present invention described above will be specifically described.
[0108]
As an example, as shown in FIGS. 11A and 11B, when the total number of external pins is 400 pins, the cell usage rate is 20%, and the area of the input / output buffer is 50 μm × 500 μm, FIG. In the conventional layout method of a semiconductor integrated circuit shown in FIG. 1, the length of the side of the semiconductor chip is 50 μm × 100 pins + 500 μm × 2 = 6 mm. However, it is assumed that 100 pins are distributed to each of the upper side, the lower side, the left side, and the right side. Therefore, the chip area according to the conventional semiconductor integrated circuit layout method is 6 mm × 6 mm = 36 mm. ² It becomes.
[0109]
On the other hand, in the layout method of the semiconductor integrated circuit according to the present invention, the area of the chip internal region is 5 mm × 5 mm = 25 mm. ² Is the area for arranging all the circuit blocks constituting the internal circuit. ² × 0.2 = 5mm ² And the area of 400 input / output buffers, ie, 50 μm × 500 μm × 400 = 10 mm ² 5mm ² + 10mm ² = 15mm ² Is the chip area.
[0110]
Therefore, 15mm ² ÷ 36mm ² = 0.42, and when the layout method of the semiconductor integrated circuit according to the present invention is used, the chip area can be significantly reduced.
[0111]
In addition, by using the input / output buffer according to the present invention shown in FIG. 5, the shape of the input / output buffer area can be made various shapes as shown in FIG. As a result, the shape of the input / output buffer arrangement area and the arrangement of the input / output buffers can be determined so as to satisfy the timing condition. The number of times of repeating the wiring process is reduced, and the entire design period can be shortened.
[0112]
Next, a semiconductor chip 801 designed by using the semiconductor integrated circuit layout method according to the present invention will be described with reference to FIGS.
[0113]
FIG. 8 is a diagram for conceptually explaining the planar structure of the semiconductor chip 801. Solder balls 803 are arranged at the same solder ball pitch over the entire surface of the semiconductor chip 801. 804A, 804B, and 804C. In addition, cells 805A and 805B and macro cells 805C and 805D constituting an internal circuit are arranged. FIG. 9 is an enlarged view of the area indicated by the dotted line A in FIG. 8, and will be described with reference to FIG.
[0114]
Reference numerals 901A and 901B denote internal power (Vi) pads, 902A and 902B denote internal GND (Gi) pads, 903A to 903D denote signal pads, and 904A and 904B denote external power (V). ), And 905A and 905B are pads for external GND (G).
[0115]
Reference numerals 910A to 910F denote input / output buffers according to the present invention. Reference numerals 911A to 911F denote input / output buffers 910A to 910F, signal pads 903A to 903D, external power (V) pads 904A, and external GND (G) pads. 905A.
[0116]
Similarly, 920A to 920D are input / output buffers according to the present invention, and 921A to 921D are input / output buffers 920A to 920D, signal pads (not shown), external power (V) pads 904B, and external GND ( G) for connecting the respective pads 905B.
[0117]
930A to 930D represent cells or macro cells.
[0118]
Next, the layout will be described in more detail mainly on the input / output buffers 910A to 910F and 920A to 920D.
[0119]
910C constitutes a power supply cell, is connected to an external power supply (V) pad 904A via a wiring 911C, and is adjacent to and in contact with the input / output buffers 910A and 910E. , 910E are automatically connected to the power supply wiring. Therefore, current flows from the external power supply (V) pad 904A to the input / output buffers 910A and 910E and the input / output buffers 910B and 910F adjacent to the input / output buffers 910A and 910E via the power supply cell 910C. Supplied.
[0120]
Similarly, 910D constitutes a GND cell, is connected to an external GND (G) pad 905A via a wiring 911D, and is adjacent to and in contact with the input / output buffers 910B and 910F. The GND lines of the output buffers 910B and 910F are automatically connected to the GND lines. Therefore, current flows from the input / output buffers 910B and 910F and the input / output buffers 910A and 910E adjacent to the input / output buffers 910B and 910F to the external GND (G) pad 905A via the GND cell 910D. Flows.
[0121]
The input / output buffer 910A is connected to the signal pad 903A via the wiring 911A, amplifies a signal applied to the signal pad 903A, and inputs the amplified signal to the cell 930C.
[0122]
The input / output buffer 910E is connected to the signal pad 903B via the wiring 911E, amplifies the signal output from the macro cell 930D, and outputs the amplified signal to the signal pad 903B.
[0123]
As described above, the input / output buffers 910A to 910F constitute one group, which includes the power supply cell 910C and the GND cell 910D, and supplies power to each of the input / output buffers 910A to 910F constituting the group. I do.
[0124]
The group composed of the input / output buffers 920A to 920D is basically the same as the above-described layout structure, but the shape of the input / output buffer arrangement area is L-shaped. This is because the signal pad connected to the input / output buffer 920D is located on the right side of the input / output buffer 920D, and the signal pad connected to the input / output buffer 920B is located below the input / output buffer 920B. , 921B and 921D.
[0125]
Next, with reference to FIG. 10, a description will be given of a layout of a semiconductor chip in an intermediate step of a layout method of a semiconductor integrated circuit according to the present invention.
[0126]
FIG. 10A shows a layout in which solder balls 102 are arranged over the entire surface of the initial chip 101 on the initial chip 101 based on the initial chip area calculated in step S15 of FIG.
[0127]
Next, FIG. 10B shows a layout when the input / output buffers 110A to 110D and specific circuit blocks 120A to 120C constituting the internal circuit are arranged in step S172 of FIG.
[0128]
Next, FIG. 10C shows that a timing error occurs as a result of the timing verification using the temporary wiring or the timing verification using the actual wiring in step S18 in FIG. 1, and the chip area is increased in step S19 according to the number of timing errors. This is shown. Here, reference numeral 103 denotes an enlarged semiconductor chip.
[0129]
Although the solder balls 105 are arranged on the entire surface in the enlarged area, the solder balls 105 need not always be arranged. However, the use of the solder balls 105 further improves the degree of freedom in the arrangement of the input / output buffers.
[0130]
Next, a second embodiment of a layout method for a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.
[0131]
In the first embodiment of the layout method of the semiconductor integrated circuit according to the present invention, the number of timing errors is calculated without regard to the position on the semiconductor chip where the timing errors occurred in step S41 of FIG. In step S44, the semiconductor chip is extended by ΔX in the X-axis direction and ΔY in the Y-axis direction by a distance proportional to the number of timing errors. However, in the second embodiment, in step S41 ′ instead of step S41, From the simulation result, the position where the timing error has occurred is calculated from the node where the error has occurred and the layout data corresponding to this node, and in step S44 'instead of step S44, the position where the timing error has occurred is directed outward from the semiconductor chip. To enlarge the semiconductor chip.
[0132]
Next, the contents described above will be described more specifically with reference to FIG.
[0133]
FIG. 13A shows that timing errors have been detected at two locations on the initial chip 131, that is, at the locations of 133A and 133B in step S41 '. 132 is the center position of the initial chip 131, and 134A to 134E indicate cells or macro cells.
[0134]
Subsequently, in step S44 ', the initial chip 131 is enlarged outward from the position 133A. Next, in step S16, the partition definition that does not distinguish between the input / output buffer and the circuit block constituting the internal circuit is also performed on the enlarged region.
[0135]
In FIG. 13 (b), 135A and 136A are straight lines in the Y-axis direction and the X-axis direction passing through the position 133A, respectively, and only d2 in the X-axis direction and d1 in the y-axis direction. On the left side of the straight line 135A and above the straight line 136A. Here, d1 is a wiring grid in the Y-axis direction, d2 is a wiring grid in the X-axis direction, and 135 'and 136A' represent straight lines after the straight lines 135 and 136A have moved by the wiring grid.
[0136]
As a result, the cell 134A moves leftward by the distance d2 and upwards by the distance d1. The cell 134B moves upward by the distance d1.
[0137]
Similarly, in step S44 ', the initial chip 131 is enlarged outward from the position 133B. Subsequently, in step S16, a partition definition that does not distinguish between the input / output buffer and the circuit block forming the internal circuit is also performed on the enlarged region.
[0138]
135B and 136B are straight lines in the Y-axis direction and the X-axis direction passing through the position 133B, respectively, and are enlarged by the wiring grid, that is, d2 in the X-axis direction and d1 in the y-axis direction. As a result, the cell 134D moves rightward by the distance d2. The cell 134E moves downward by the distance d1.
[0139]
Also, even if the initial chip is enlarged, the macro cell 134C does not move because it is located inside the positions 133A and 133B where the timing error has occurred.
[0140]
Next, in steps S172 and 173 in FIG. 1, after the input / output buffers and specific internal circuit blocks are roughly arranged, in step S18, timing verification using temporary wiring or timing verification using actual wiring is performed. As a result, when the timing error corresponding to the position 133A is eliminated and the timing error corresponding to the position 133B is not eliminated, as shown in FIG. 13C, the wiring grid is further enlarged with respect to the position 133B. That is, the right side from the straight line 135B is moved by two wiring grids in the right direction, and the lower side from the straight line 136B is moved by two wiring grids in the downward direction.
[0141]
As described above, until all the timing errors are resolved, the semiconductor chip, that is, the partition definition is sequentially enlarged by the minimum unit distance from the position where the timing error occurred to the outside, and the input / output buffer and the internal circuit block are rearranged. And rewiring. Then, when all the timing errors have been resolved, the chip area at that time is determined as the final chip area of the semiconductor integrated circuit.
[0142]
In the layout method of the semiconductor integrated circuit according to the second embodiment described above, the position where the timing error has occurred is detected, and the area of the partition definition is expanded toward the outside of the detected position. As compared with the layout method of the semiconductor integrated circuit according to the embodiment, the input / output buffer and the internal circuit block can be efficiently rearranged and re-routed by using the enlarged area of the section definition. As compared with the case of using the semiconductor integrated circuit layout method, the number of layout repetitions is further reduced, so that not only the design period is shortened, but also the area of the semiconductor chip can be reduced.
[0143]
In the above description, the semiconductor chip having the flip-chip configuration is mainly described. However, the present invention is not limited to the flip-chip, and may be applied to a semiconductor integrated circuit of a type in which external pins and pads formed on the semiconductor chip are connected by bonding wires. Applicable.
[0144]
Further, in FIG. 5, the case where the VDD wiring or the GND wiring is linearly arranged from the left end to the right end or from the upper end to the lower end of the cell frame in the X direction or the Y direction has been described, but is not necessarily limited to this wiring method. However, it is important that the positions of the VDD wiring and the GND wiring on the cell frame and the wiring layer are common to the input / output buffers. If this condition is satisfied, the VDD wiring and the GND wiring of each input / output buffer constituting the group can be commonly connected by adjoining the input / output buffers constituting the group in the X direction or the Y direction. .
[0145]
Although FIG. 9 illustrates the case where one group includes one power supply cell and one GND cell, the case where two or more power supply cells and GND cells are provided in one group can be easily expanded. . In this case, the current supply capability can be enhanced.
[0146]
【The invention's effect】
As described above, in the layout method of the semiconductor integrated circuit according to the first embodiment of the present invention, when calculating the initial chip area, the chip area is set to be as small as possible, and thereafter, a timing error occurs. By enlarging the chip area according to the number of errors, it is possible to design a semiconductor integrated circuit that satisfies the timing conditions without unnecessarily increasing the chip area.
[0147]
Further, the layout method of the semiconductor integrated circuit according to the second embodiment of the present invention detects a position where a timing error has occurred, and enlarges the area of the partition definition outward of the detected position. The input / output buffer and the internal circuit block can be efficiently rearranged and re-routed by using the area of the enlarged section definition as compared with the layout method of the semiconductor integrated circuit according to the embodiment. As compared with the case of using the semiconductor integrated circuit layout method according to the embodiment, the number of layout repetitions is further reduced, so that not only the design period is shortened, but also the area of the semiconductor chip can be reduced.
[0148]
Further, by using the input / output buffer according to the present invention, the shape of the input / output buffer area can be made various. Thus, the shape of the input / output buffer arrangement area and the arrangement of the input / output buffer can be determined so as to satisfy the timing condition. The number of times of repeating the process of rewiring between circuit blocks is reduced, and the entire design period can be shortened.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an embodiment of a semiconductor integrated circuit layout method according to the present invention.
FIG. 2 is a flowchart for explaining details of step S15 in FIG. 1 for calculating an initial chip area;
FIG. 3 is a flowchart for explaining details from automatic wiring to timing verification by actual wiring in step S18 in FIG. 1;
FIG. 4 is a flowchart for explaining in detail a processing content of step S19 in FIG. 1 for expanding a chip area;
FIG. 5 is a layout diagram of an input / output buffer according to the present invention.
FIG. 6 is a layout diagram showing an embodiment in which input / output buffers according to the present invention are grouped and input / output buffers belonging to each group are arranged on a semiconductor chip.
FIG. 7 is a chip layout diagram for explaining a solder ball 73 arranged on a semiconductor chip 71, a section definition 72, and a correction area 74 corresponding to correction terms α and β.
FIG. 8 is a layout diagram of a semiconductor chip designed using the semiconductor integrated circuit layout method according to the present invention.
FIG. 9 is an enlarged layout diagram showing a part A of FIG. 8;
FIG. 10 is a diagram illustrating each layout of a semiconductor chip in an intermediate step of a layout method of a semiconductor integrated circuit according to the present invention.
11A and 11B are a chip layout diagram for calculating each chip area and a layout diagram of an input / output buffer in a conventional semiconductor integrated circuit layout method and a semiconductor integrated circuit layout method according to the present invention.
FIG. 12 illustrates a difference in wiring length between an input / output buffer and a cell or a macrocell due to a difference in arrangement of each input / output buffer in a conventional semiconductor integrated circuit layout method and a semiconductor integrated circuit layout method according to the present invention. It is a conceptual layout diagram for explaining.
FIG. 13 is a chip layout diagram for explaining each processing step of step S41 ′ and step S44 ′ in the semiconductor integrated circuit layout method according to the second embodiment of the present invention.
FIG. 14 is a flowchart showing a method of placing and wiring a flip-chip type semiconductor device according to a second conventional technique.
FIG. 15 is a plan view when a partition is defined using a basic cell as a minimum unit in the placement and routing method for a flip-chip type semiconductor device according to the second conventional technique.
FIG. 16 shows an input / output buffer for each group arranged by using the arrangement and wiring method of the flip-chip type semiconductor device according to the second prior art, power supply wiring and GND wiring connected to the input / output buffer, and an internal circuit arrangement area 164A. 164D is a chip layout diagram. FIG.
FIG. 17 is a chip layout diagram showing a first conventional example of a layout method of a semiconductor integrated circuit.
[Explanation of symbols]
11,111 Function description data
12 Circuit connection information
13,121 Placement restriction data
14,126 Mask data
21 Solder ball pitch information
22 pin information
23 cell information
24 Cell usage information
31 Placement data
32 Placement / wiring data
71, 101, 131 Initial chip
72 Section definition
73, 102, 105, 172, 803 solder ball
74 Correction area
103, 111, 131 ", 151, 181, 601, 801 Semiconductor chip
110A to 110C, 134A, 134B, 134D, 134E, 175A to 175C, 805A, 805B cells
112A to 112D, 121A to 121E, 152, 161A to 161C, 174 I / O buffer
114 Circuit diagram data
120A to 120C, 134C, 175D to 175F, 805C, 805D Macrocell
121A 'to 121E', 910A to 910F, 920A to 920D Input / output buffer according to the present invention
122,930A-930D cell or macro cell
123A to 123E, 123A 'to 123E', 911A to 911F, 921A to 921D Wiring
132 Center of Semiconductor Chip
133A, 133B Position on semiconductor chip where timing error was detected
135A Straight line in Y-axis direction passing through position 133A
135B Straight line in Y-axis direction passing through position 133B
136A Straight line in X-axis direction passing through position 133A
136B Straight line in X-axis direction passing through position 133B
135A 'Straight line obtained by moving straight line 135A outward
135B 'A straight line obtained by moving the straight line 135B outward.
136A 'Straight line obtained by moving straight line 136A outward
136B 'Straight line obtained by moving straight line 136B outward
153a to 153d Internal circuit block
154 Block placement position definition area
155 Section definition
162, 502, 504 VDD wiring
163, 503, 505 GND wiring
164A to 164D Internal circuit layout area
173 Internal area of semiconductor chip
401 Solder ball spacing information
402 Wiring grid interval information
501 I / O buffer cell frame
506A, 506B Through hole
507 Reference point provided on cell frame 501
602A to 602C, 804A, 804B, 804C Input / output buffer arrangement area
603 Internal circuit layout area
901A, 901B Internal power supply (Vi) pad
902A, 902B Pad for internal GND (Gi)
903A to 903D Signal pad
904A, 904B External power supply (V) pad
905A, 905B Pad for external GND (G)

Claims (8)

A plurality of internal circuit blocks and an interface between the plurality of internal circuit blocks and the outside, and when arranged adjacent to each other in the X direction or the Y direction, the power supply wiring and the GND wiring are commonly connected in any direction. A first step of generating circuit connection information of a semiconductor integrated circuit including a plurality of input / output buffers;
A second step of grouping the plurality of input / output buffers into a plurality of input / output buffer groups corresponding to a plurality of electrically independent power supplies based on the circuit connection information;
A third step of defining a partition for setting an arrangement grid for common arrangement on a semiconductor chip over the entire surface of the semiconductor chip without distinguishing both the input / output buffer and the internal circuit block;
A fourth step of arranging the plurality of input / output buffers constituting the input / output buffer group on the arrangement grid so as to be adjacent to each other and arranging the plurality of internal circuit blocks on the arrangement grid;
The power supply wiring and the GND wiring which are independent for each of the input / output buffers for the plurality of input / output buffers constituting each of the input / output buffer groups; the power supply wiring and the GND wiring for the internal circuit block; And a fifth step of interconnecting the internal circuit block and the plurality of input / output buffers with each other. The input / output buffer group is connected to a power supply pad formed on the semiconductor chip and configured to supply power to the plurality of input / output buffers and the plurality of internal circuit blocks, thereby forming the input / output buffer group. By arranging adjacently to the output buffer, a power supply cell to which the input / output buffer and the power supply wiring are connected in common,
The input / output buffer and the GND line are connected in common by being connected to a GND pad formed on the semiconductor chip and connected to an external GND line and adjacent to the input / output buffer constituting the input / output buffer group. A GND cell to be
2. The layout method for a semiconductor integrated circuit according to claim 1, wherein at least one of each is provided. The input / output buffer is wired such that a first power supply wiring and a first GND wiring formed of a first wiring layer connect both ends of a cell frame indicating an outer shape of the input / output buffer in a first direction. A second power supply wiring and a second GND wiring made of two wiring layers are connected to connect both ends of the cell frame in a second direction orthogonal to the first direction, and the first power supply wiring is provided. A through hole is provided at a location where the first power line and the second power line intersect with each other, and the first power line and the second power line are electrically connected to each other, and the first GND line and the second GND are connected. 2. The layout method for a semiconductor integrated circuit according to claim 1, wherein the through hole is provided at a location where the wiring intersects, and the first GND wiring and the second GND wiring are electrically connected. The input / output buffer constituting the input / output buffer group is arranged in any one of an L-shape, a concave shape, a convex shape, a crank shape, and a step shape. A layout method for a semiconductor integrated circuit. A plurality of internal circuit blocks and an interface between the plurality of internal circuit blocks and the outside, and when arranged adjacent to each other in the X direction or the Y direction, the power supply wiring and the GND wiring are commonly connected in any direction. A first step of generating circuit connection information of a semiconductor integrated circuit including a plurality of input / output buffers; and a step of corresponding the plurality of input / output buffers to a plurality of electrically independent power supplies based on the circuit connection information. A second step of grouping into a plurality of input / output buffer groups, a third step of calculating an initial chip area that is a schematic chip area of the semiconductor integrated circuit, and a semiconductor chip calculated from the initial chip area. On an initial chip, an arrangement grid for arranging the input / output buffer and the internal circuit block in common without distinguishing both, A fourth step of defining a partition set over the entire surface of the initial chip, and arranging the plurality of input / output buffers constituting the input / output buffer group on the arrangement grid so as to be adjacent to each other; A fifth step of arranging an internal circuit block on the arrangement grid, and the power supply wiring and the GND wiring which are independent for each of the input / output buffers for the plurality of input / output buffers constituting each of the input / output buffer groups; A sixth step of performing wiring between the power supply wiring and the GND wiring for the internal circuit block, and wiring between the plurality of internal circuit blocks and the plurality of input / output buffers, the fifth step, and the sixth step. A timing simulation of the semiconductor integrated circuit is performed based on each processing result of the step. A seventh step of determining whether or not the timing simulation result satisfies a predetermined timing condition; and expanding the initial chip area if the timing simulation result does not satisfy a predetermined timing condition in the seventh step. Eighth step of calculating an enlarged chip area, and, based on the processing result of the eighth step, both the input / output buffer and the internal circuit block are placed on an enlarged chip which is a semiconductor chip calculated from the enlarged chip area. A ninth step of defining a section for setting an arrangement grid for common arrangement without distinction over the entire surface of the enlarged chip, and an arrangement grid in the fifth step are obtained in the ninth step. A tenth step of performing the processing of the fifth step by changing the arrangement grid to An eleventh step of performing the sixth processing based on the arrangement result of the input / output buffer and the internal circuit block, which is the processing result of the tenth step, and a eleventh step. The third step is a twelfth step of calculating the number of signal pads formed on the semiconductor chip for inputting and outputting signals to and from the outside, and an external power supply pad formed on the semiconductor chip and applied with an external power supply A thirteenth step of calculating the number of internal power supply pads formed on the semiconductor chip and to which an internal power supply generated within the semiconductor integrated circuit is applied; and a thirteenth step of calculating the number of signal pads. A fifteenth step of calculating the total number of pads by adding the number of external power supply pads and the number of internal power supply pads, and a first area which is an area when the total number of pads is spread over the semiconductor chip And calculating the second area of the semiconductor chip from the type of the internal circuit block and the number of the circuit blocks mounted on the semiconductor chip for each type. Comparing the first area with the second area, and if the first area is greater than or equal to the second area, the first area is The semiconductor integrated circuit according to claim 5, further comprising an eighteenth step in which, when the first area is smaller than the second area, the second area is the initial chip area. Layout method. The first area S1 is represented by the following equation , where d is a solder ball pitch, N is the total number of pads, and α is a correction term of the area.
S1 = d ² × (square root N−1) ² + α
Layout method of a semiconductor integrated circuit according to claim 6, wherein the in is calculated. The eighth step is a nineteenth step of calculating the number of timing errors based on error information output when the timing simulation result does not satisfy the predetermined timing condition in the seventh step. ,
A twentieth step of calculating an increase rate of a wiring grid set on the semiconductor chip when the number of the timing errors is one;
6. The semiconductor integrated circuit according to claim 5, comprising: a twentieth step of calculating a length of extending each side of the semiconductor chip in the X direction and the Y direction from the number of the timing errors and the increasing rate of the wiring grid. Circuit layout method.

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