JP3589580B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device having a trench element isolation region, including a mask alignment step and a planarization step by a chemical mechanical polishing method.
[0002]
Problems to be solved by the prior art and the invention
Usually, a LOCOS (Local Oxidation of Silicon) method is used to form an element isolation region in a MOS semiconductor device. In recent years, with the miniaturization of semiconductor devices, miniaturization of the dimensions of element isolation regions has been desired. However, if the element isolation regions formed by the LOCOS method are excessively miniaturized, it is possible to ensure a sufficient electric element isolation withstand voltage. However, there is a problem that it is difficult to control a dimensional shift of the element isolation region due to a so-called bird's beak.
[0003]
As an element isolation method for solving these problems, a trench element isolation method is known. In the trench element isolation method, a trench (a groove for forming an element isolation region) is formed in a substrate, an insulating film is deposited on the entire surface of the substrate, and the insulating film is removed leaving only the trench of the silicon substrate to remove the trench element. Forming an area. As a method of removing the insulating film, a method of polishing and removing the insulating film by a CMP (Chemical Mechanical Polishing) method has been proposed.
Here, in an actual semiconductor device, the width of the element isolation region may be 100 μm or more. In this region, after the insulating film is removed by the CMP method, the thickness of the insulating film in the trench may be several tens to several hundreds nm thinner than other element isolation regions. This phenomenon is called dishing.
3A to 3D and FIG. 4 show a technique for preventing dishing. FIG. 3B is a schematic sectional view taken along line BB of FIG.
[0004]
A silicon oxide film 21 (about 0.005 to 0.04 μm) is formed on a silicon substrate 11, and a silicon nitride film 31 (about 0.05 to 0.3 μm) is deposited. The silicon nitride film 31 has a role of preventing an unwanted region from being polished by the CMP method. Thereafter, by photolithography and anisotropic etching, the trench 41 is formed in the circuit region X, and the accuracy measurement groove used for measuring the alignment accuracy of the mask in the alignment accuracy measurement mark region Y (error recognition is prohibited). Groove 71 is formed. Next, the trench 41 and the groove 71 are buried with the insulating film 51 by stacking the insulating film 51 on the entire surface of the substrate 11 by the CVD method. Through these steps, as shown in FIG. 3A, a convex insulating film having the same thickness as the deposited insulating film is formed in a wide region between the trenches 71, between the trenches 71 and the trenches 41, and between the trenches 41. In a narrow region between the trenches 41, a convex insulating film having a height lower than that of the deposited insulating film is formed.
[0005]
Next, after a photoresist is applied to the entire surface of the insulating film 51, the photoresist other than over the trench 41 and the region having the predetermined width F from the end of the trench 41 is removed by photolithography on a wide area of the circuit area X. Thus, a mask 61 having an opening is formed. Next, the insulating film 41 below the opening is removed by an anisotropic etching method. Here, if the predetermined width F is set to a certain value or less, the polishing rate of the insulating film 41 by the CMP method is increased, and the polishing amount in the wide area and the narrow area is almost uniform. Therefore, the amount of over-etching of the insulating film on the trench is reduced. Therefore, dishing of the element isolation region can be prevented (see FIG. 3C).
On the other hand, in the alignment accuracy measurement mark area Y, after applying a photoresist on the insulating film 51, a mask 61 having an opening having a predetermined width C is formed. Here, the alignment is performed by comparing the center coordinates of the predetermined width C of the opening with the center coordinates between the grooves 71 (C + 2D). If there is a deviation between the two coordinates, the photoresist is removed, and the photolithography step is performed again. If this comparison is not performed, the desired position cannot be etched, and this comparison is performed until there is no deviation.
[0006]
Here, as C, C + 2D, and D are larger, the measurement accuracy of the alignment can be increased. Therefore, the maximum is set within the range that can be observed by the lenses of the C and D alignment accuracy measuring devices. Specifically, C and D are generally several tens of μm.
After the insulating film between the grooves 71 is removed by using the mask 61 having the opening having the width C as described above (see FIGS. 3B and 4), the alignment is measured by the CMP method. Since the insulating film on the substrate in the mark region Y is wider than the insulating film on the substrate in the circuit region X, the polishing rate is reduced, and the remaining insulating film 81 is generated (see FIG. 3C). Further, when the silicon nitride film 31 is removed, a silicon nitride film residue 91 is generated at a position where the residue 81 is generated (see FIG. 3D). The remaining portion 91 becomes dust in a later process and causes a reduction in yield.
Further, a groove 71 is provided in order to prevent the positioning accuracy measuring device from erroneously recognizing the mark region Y for measuring the positioning accuracy, but the width of the groove 71 is usually required to be several tens of μm. In such a wide groove 71, a level difference occurs due to dishing when planarizing by the CMP method. For this reason, in a photolithography process for patterning the wiring to be performed later, there is a problem that a wiring shape defect occurs due to a focus shift due to a step.
[0007]
As a method for solving this problem, there is a technique disclosed in Japanese Patent Application Laid-Open No. 7-78866. This technique will be described with reference to FIGS.
First, similarly to FIG. 3A, a trench 41 and a groove 71 are formed in the substrate 11, and the entire surface is covered with an insulating film 51 (see FIG. 5A). Thereafter, the insulating film in the alignment accuracy measurement mark area Y is completely removed by photolithography and anisotropic etching using the mask 62 covering the circuit area X (see FIG. 5B).
After removing the mask 62, the photolithography step, the anisotropic etching step, and the silicon nitride film 31 are removed in the same manner as in FIGS. 3B to 3D (see FIGS. 5C to 5E). . Here, in this method, since the insulating film 51 does not exist in the alignment accuracy measurement mark area Y, the remaining insulating film 81 as shown in FIG. 3C does not occur. Since the insulating film 51 does not exist in the groove 71, dishing does not occur.
Next, the silicon oxide film 21 is removed (see FIG. 5F).
However, in this method, it is necessary to add a photolithography step and an anisotropic etching step in order to remove the insulating film 51 in the alignment accuracy measurement mark area Y in advance, and there is a problem that the manufacturing cost increases.
[0008]
[Means for Solving the Problems]
According to the present invention, a step of forming a pair of trenches for measuring the alignment accuracy of a mask in a circuit region of a substrate and a region other than the above-described region, and laminating an insulating film over the entire surface of the substrate to form a pair of trenches Filling the trench with an insulating film, forming a mask on the insulating film by photolithography, aligning the mask, removing an insulating film other than under the mask by anisotropic etching, and removing the mask After that, a step of removing the insulating film on the substrate other than in the pair of trenches and trenches by chemical mechanical polishing method and flattening,
A pair of patterns each having a predetermined width formed on the insulating film in a region where the mask is separated from the groove by a distance that allows measurement of alignment accuracy of the mask from the groove, and a predetermined width from the end of the trench and the trench. And a pattern that can cover the area of
The alignment of the mask is performed by comparing the center coordinates between the pair of grooves and the center coordinates between the pair of patterns, and if there is no displacement, anisotropic etching is performed continuously. A method for manufacturing a semiconductor device is provided.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention will be described with reference to FIGS. 1 (a) to 1 (e) and FIG. Incidentally, FIG. 1 (b) is a schematic cross-sectional view of line A-A of FIG.
First, the substrate 1 that can be used in the present invention is not limited. In particular, it is preferable to use a silicon substrate. Further, a film (CMP stopper) having a role of preventing the substrate from being polished in a later CMP step may be formed on the substrate 1. This CMP stopper may be composed of a silicon oxide film, a silicon nitride film, and a laminated film thereof. For example, in FIG. 1A, the CMP stopper includes two layers of a silicon oxide film 2 and a silicon nitride film 3 from the substrate 1 side. In this case, the silicon oxide film usually has a thickness in the range of 0.005 to 0.02 μm, and the silicon nitride film has a thickness in the range of 0.1 to 0.3 μm. Note that the silicon oxide film can be formed by a thermal oxidation method, a CVD method, a sputtering method, or the like, and the silicon nitride film can be formed by a CVD method, a sputtering method, or the like.
[0010]
Next, a trench 4 is formed in the circuit area X on the substrate 1 and a pair of grooves 7 for measuring the alignment accuracy of the mask are formed in the alignment accuracy measurement mark area Y other than the circuit area X. Here, one or more trenches 4 may be formed in the substrate 1. Further, the trench 4 usually has a width in the range of 0.1 to several tens μm and a depth in the range of 0.1 to 1 μm. On the other hand, the groove 7 for measuring the alignment accuracy of the mask preferably has a width a that does not cause dishing in the subsequent CMP process, and specifically, preferably has a range of 0.2 to 1 μm. The depth of the groove 7 is the same as that of the trench 4, and is preferably in the range of 0.1 to 1 μm. The groove 7 is preferably separated from the circuit region X by a predetermined width e (for example, 5 μm or more). The trench 4 and the groove 7 can be formed by combining known photolithography and anisotropic etching.
[0011]
Next, an insulating film 5 is laminated on the entire surface of the substrate 1 (see FIG. 1A). By stacking the insulating film 5, the trench 4 and the groove 7 are filled with the insulating film. The thickness of the insulating film 5 is a thickness that can at least fill the trench 4 and the groove 7, and is preferably in the range of 0.1 to 1.5 μm. Examples of a method for laminating the insulating film 5 include a CVD method and a sputtering method.
Next, after applying a photoresist on the insulating film 5, a mask having the following pattern is formed by photolithography.
That is, the mask 6
A pair of patterns 101 having a predetermined width b formed on the insulating film 5 at a distance d between the pair of grooves 7 and at a distance d from which the alignment accuracy of the mask can be measured;
A pattern 102 that can cover the trench 4 and a region having a predetermined width f from the end of the trench 4
have.
[0012]
Here, the distance d at which the alignment accuracy of the mask can be measured is preferably several tens μm, and particularly preferably 5 to 10 μm.
Further, the predetermined width b of the pattern 101 is preferably a width that does not remain in a subsequent CMP step, and specifically, is preferably 0.2 to 1 μm. With this width, the polishing time for polishing the insulating film 5 until the CMP stopper is exposed can be reduced. At the same time, since the variation in the polishing amount can be suppressed, the overetch amount of the insulating film 5 decreases, the polishing amount of the insulating film in the trench decreases, and dishing can be suppressed.
Further, the interval between the pair of patterns 101 (FIG. 1B and FIG. 2C) is preferably the largest size in a range that can be observed by the lens of the alignment measuring device, and specifically, 10 to 20 μm. It is preferable that
[0013]
On the other hand, the predetermined width f of the pattern 102 is preferably a width equal to or more than the amount of displacement during exposure, and particularly preferably 0.1 to 0.3 μm. Note that it is particularly useful to provide the resist opening 103 formed above the trench and in a region other than the region having the predetermined width f from the trench end when the width between the trenches is large (for example, 0.5 μm or more). That is, when the insulating film in the wide region and the insulating film in the narrow region between the trenches are removed by the CMP method, the removal rates of the two insulating films can be made substantially the same, and the removal of the insulating film is prevented from remaining. This is because you can do it.
[0014]
Next, using the pattern 101 and the groove 7, the alignment accuracy of the mask is measured. As a measuring method, there is a method of comparing the center coordinates of 2a + 2b + c + 2d or 2b + c + 2d and the center coordinates of 2b + c or c, and calculating a shift amount between both center coordinates. Here, if there is a deviation between the two center coordinates, the mask is peeled off, and a mask having the mask 6 and the pattern 101 is formed again.
Next, the insulating film 5 on the substrate 1 other than under the mask 6 is removed by anisotropic etching (see FIGS. 1B and 2). In addition. In FIG. 2, the planar shape of the groove 7 and the pattern 101 is square, but is not limited to this shape, and may be rectangular, circular, elliptical, or the like.
[0015]
Next, after the mask 6 is removed, the insulating film 5 on the substrate 1 other than the trenches 4 and the trenches 7 is removed by CMP to planarize (see FIG. 1C). Here, the width of the insulating film 5 located below the pattern 102 is adjusted so that the polishing rate is substantially the same as that of the other polished portions.
Thereafter, when a CMP stopper is formed, a semiconductor device having a trench element isolation region can be manufactured by removing the CMP stopper (see FIGS. 1D and 1E).
[0016]
【The invention's effect】
According to the method of manufacturing a semiconductor device of the present invention, an extra insulating film after the element isolation region formed on the substrate and the pair of trenches for precision measurement are buried with the insulating film is removed and planarized by the CMP method. In this case, dishing of the insulating film buried in the element isolation region and the pair of grooves can be prevented. Further, a decrease in yield due to an insulating film remaining on the substrate after planarization by the CMP method can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic process sectional view of a manufacturing method of the present invention.
FIG. 2 is a schematic process plan view of the manufacturing method of the present invention.
FIG. 3 is a schematic cross-sectional process view of a conventional manufacturing method.
FIG. 4 is a schematic process plan view of a conventional manufacturing method.
FIG. 5 is a schematic process sectional view of a conventional manufacturing method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 11 Substrate 2, 21 Silicon oxide film 3, 31 Silicon nitride film 4, 41 Trench 5, 51 Insulating film 6, 61, 62 Mask 7, 71 Groove 81 for measuring alignment accuracy of mask 81 Silicon oxide film remaining 91 Silicon Remaining nitride film 101, 102 Pattern X Circuit area Y Alignment accuracy measurement mark area

Claims (3)

Forming a pair of grooves for measuring the alignment accuracy of the mask in a region other than the trench and the region in the circuit region of the substrate, and laminating an insulating film over the entire surface of the substrate, thereby forming the pair of grooves and the trench with the insulating film. A step of embedding, a step of forming a mask on the insulating film by a photolithography method, aligning the mask, and removing an insulating film other than under the mask by anisotropic etching; Removing the insulating film on the substrate other than the pair of trenches and trenches by a polishing method and flattening,
A pair of patterns each having a predetermined width formed on the insulating film in a region where the mask is separated from the groove by a distance that allows measurement of alignment accuracy of the mask from the groove, and a predetermined width from the end of the trench and the trench. And a pattern that can cover the area of
The alignment of the mask is performed by comparing the center coordinates between the pair of grooves and the center coordinates between the pair of patterns, and if there is no displacement, anisotropic etching is performed continuously. A method for manufacturing a semiconductor device. 2. The manufacturing method according to claim 1, further comprising forming a mask again when there is a positional shift during mask alignment. The distance at which the alignment accuracy of the mask can be measured is 5 to 10 μm, the width of the pair of patterns is 0.2 to 1 μm, and the width of the pair of grooves is 0.2 to 1 μm. The method according to 1.

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