JP3567318B2 - Semiconductor memory device and design method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique effective when applied to a design method of a semiconductor memory device and a common design of two types of semiconductor memory devices, for example, to a technology effective when applied to a clock synchronous semiconductor memory device.
[0002]
[Prior art]
A synchronous static RAM (hereinafter, abbreviated as a synchronous SRAM) is used as a normal write SRAM used as a main memory of a large computer and a cache memory of an EWS (Engineering Work Station). There is an SRAM of late write specification.
[0003]
In an SRAM of the normal write specification, a write address and write data are simultaneously taken into a memory and immediately written into a memory array. On the other hand, in the SRAM of the late write specification, write data is taken in at a timing one cycle later than the write address, and writing to the memory array is actually performed in the cycle at which the next write address is input.
[0004]
[Problems to be solved by the invention]
The conventional normal write SRAM and the late write SRAM have been designed separately even though the timing difference seen from the outside is slight. However, since the product life of a semiconductor integrated circuit including an SRAM has been increasingly shortened in recent years, if the synchronous SRAM of the normal write specification and the synchronous SRAM of the late write specification were separately designed, There has been a problem that the development period of a new product becomes longer and the cost becomes higher.
[0005]
An object of the present invention is to provide a synchronous SRAM design method capable of efficiently designing a product having a short development period and a price competitiveness. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be described as follows.
[0007]
That is, the internal circuit of the synchronous SRAM of the normal write specification has the same configuration as the internal circuit of the synchronous SRAM of the late write specification, and the input register (or buffer) of the write data has a two-stage configuration. The write data input register is configured to be switchable between a state in which input data is passed as it is and a state in which input data is temporarily latched, for example, according to the potential state of the external control terminal.
[0008]
Specifically, a memory array, an address input circuit for receiving an externally input address signal for selecting a desired memory cell in the memory array, and a corresponding memory cell which decodes the input address signal and A semiconductor comprising: a decoder circuit for forming a signal for selection; an output circuit for outputting a signal read from a selected memory cell to the outside; and a data input circuit for receiving write data input from the outside In the storage device, the data input circuit includes a first input register and a second input register cascaded to the first input register, and the first input register inputs input data in accordance with a potential state of an external control terminal. The configuration is such that it can be switched to either a state in which the data is passed as it is or a state in which input data is temporarily latched.
[0009]
According to the above-described means, since the synchronous SRAM of the normal write specification and the late write specification can be integrated into the same chip, it is necessary to design only the internal circuit of the SRAM of the late write specification in the development of a new product. Because it is good, the development period can be shortened, and a single production line can be used, so that a product that is price competitive can be provided.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a synchronous SRAM to which the present invention is applied.
[0011]
In FIG. 1, reference numeral 10 denotes a memory array in which a plurality of memory cells are arranged in a matrix, 11A denotes a first address register that receives and holds externally input address signals SA0 to SA16, and 11B denotes an address register 11A. The second address register 11A and 11B latch and hold the address signal in synchronization with the clock signal. An address multiplexer 12 selects one of the address signals held in the address registers 11A and 11B. A decoder 13 decodes the address signal selected by the address multiplexer 12 and decodes the address signal in the memory array 10. A decoder circuit for selecting a corresponding word line and data line.
[0012]
Although not shown, the decoder circuit 13 includes an X decoder for selecting a word line corresponding to an input address and a Y decoder for selecting a data line corresponding to an input address, as in a general-purpose memory. From the memory array 10, 4-byte (36-bit) data having a parity of 1 bit per byte is read out by the input address signals SA 0 to SA 16, amplified by the sense amplifier circuit 14, and passed through the data multiplexer 15. And held in the output data register 16. 17A is a first input data register for receiving and holding externally input 4-byte write data signals DQa0 to DQa8, DQb0 to DQb8, DQc0 to DQc8, DQd0 to DQd8, and 17B is an input data register 17A. A second input data register for further latching and holding the fetched write data signal; The write data fetched by the second input data register 17B is supplied to the memory array 10 via the write driver 18, and the data is written to the memory cell selected at that time.
[0013]
The point that two stages of input data registers are provided does not exist in the conventional synchronous SRAM of the normal write specification nor in the synchronous SRAM of the late write specification. Moreover, in the synchronous SRAM of this embodiment, the first input data register 17A stores the write data input from the outside as it is in accordance with the potential of the mode control terminal CTRL provided as an external terminal. (Hereinafter referred to as a late write mode) or an operation of temporarily latching externally input write data and then supplying the same to the second input data register 17B. (Hereinafter, referred to as a normal write mode).
[0014]
In addition, the synchronous SRAM of the present embodiment supplies all the 4-byte write data held in the second input data register 17B to the memory array 10 or reads the 4-byte write data read from the memory array 10. A global write signal latch circuit 19 for receiving a global write signal / SWE for externally instructing to output all read data, and supplies any one byte of the four bytes of write data to the memory array 10. Select signal / SWEa, b, c, d byte select signal latch circuit 20A for instructing to perform operation, and the second byte for further latching and holding the byte select signal fetched by latch circuit 20A A selection signal latch circuit 20B is provided. The preceding latch circuit 20A has a function of decoding the 2-bit byte selection signal / SWEa, b, c, d to form and hold a 4-bit internal byte selection signal. Reference numeral 21 denotes a chip selection signal latch circuit which receives a chip selection signal / SS for selecting the SRAM supplied from the outside.
[0015]
In the synchronous SRAM of this embodiment, the address transfer timing from the first address register 11A to the second address register 11B and the first input data are stored on the basis of clocks K and / K supplied from the outside. A clock control circuit 22 for forming a clock for giving a data transfer timing or the like from the register 17A to the second input data register 17B; an address taken into the first address register 11A and held in the second address register 11B And a comparator 23 for comparing the address with the address. The data multiplexer 15 reads the read data or the second input data read from the memory array 10 based on the coincidence detection signal of the comparator 23 and the byte selection signal from the second byte selection signal latch circuit 20B. One of the data held in the register 17B is selected and supplied to the output data register 16. The data captured by the output data register 16 is output to the outside via the output buffer 24. Further, there is provided an output control register 25 which can control the output timing from the output buffer 24 and all or four bytes of data to be output.
[0016]
As described above, the comparator 23 for comparing the address and the output data register by selecting either the read data read from the memory array 10 or the data held in the second input data register 17B. The data multiplexer 15 that supplies the data to the memory array 10 is provided in the late write mode, as described above. Since the next write data is not input but at the time of the cycle in which the next write data is input, if data of the same address is read before that, there is no newest data in the memory array 10. So that the write data still held in the input data register 17B can be output to the outside. It is an order.
[0017]
In the synchronous SRAM of the above-described embodiment, among the control signals input from the outside, the control signal whose symbol is prefixed with "/" indicates that the low level is the effective level. In the synchronous SRAM of this embodiment, the mode control terminal CTRL is connected to a power supply voltage terminal or a ground terminal via a bonding wire, for example, via a bonding wire outside the chip, so that the potential is fixed in a DC manner. Can be set.
[0018]
The function of the synchronous SRAM of this embodiment will be described below with reference to the block diagram and timing chart of the conventional normal write synchronous SRAM shown in FIGS. 2 and 3, and FIGS. 4 and 5. This will be described with reference to a block configuration diagram and a timing chart of a synchronous SRAM of late write specification.
[0019]
As described above, the synchronous SRAM of the present embodiment has a configuration similar to that of the synchronous SRAM of the late write specification shown in FIG. 4, and the input data register has a two-stage configuration. Only the differences. In the synchronous SRAM according to the present embodiment, the first input data register 17A uses the write data input from the outside as the second data in accordance with the potential of the mode control terminal CTRL provided as an external terminal. An operation of supplying to the input data register 17B (late write mode) or an operation of temporarily latching externally input write data and then supplying the same to the second input data register 17B (normal write mode) Are selectively performed.
[0020]
Here, as apparent from the block diagram of the synchronous SRAM of the late write specification shown in FIG. 4, in the synchronous SRAM of the embodiment of FIG. 1, the first input data register 17A is externally input. If the operation is performed so as to supply the written write data as it is to the second input data register 17B, it is exactly the same as without the first input data register 17A. Therefore, in this case, the timing chart of the synchronous SRAM according to the embodiment is exactly the same as the timing chart of the synchronous SRAM of the late write specification shown in FIG. 5, and it can be seen that it has the same operation and the same function.
[0021]
On the other hand, in the synchronous SRAM of the embodiment shown in FIG. 1, the first input data register 17A is provided so that write data input from the outside is temporarily latched and then supplied to the second input data register 17B. When operated, the write data input in synchronization with the write control signal (global write signal / SWE) is taken into the first input data register 17A at the rise or fall of the clocks K and / K. The data is transferred to the second input data register 17B at the next rising or falling of the clocks K and / K. That is, when viewed from the outside, the synchronous SRAM of the embodiment takes in the write data input in synchronization with the write control signal (global write signal / SWE), so that it is the same as the synchronous SRAM of the normal write specification. It is operating.
[0022]
Regarding the timing at the time of data reading, it is apparent from FIG. 3 showing a timing chart of a conventional normal write synchronous SRAM and FIG. 5 showing a timing chart of a late write synchronous SRAM. Thus, the timing is the same. Therefore, the operation of the synchronous SRAM of this embodiment in the normal write mode is exactly the same as that of the conventional normal write synchronous SRAM when viewed from the outside.
[0023]
On the other hand, comparing FIG. 1 showing the configuration of the synchronous SRAM of the present embodiment with FIG. 2 showing the block configuration of the conventional synchronous SRAM of the normal write specification, it is clear that both have different internal circuits. Thus, the synchronous SRAM of this embodiment has a configuration similar to that of the conventional synchronous SRAM of the late write specification. In the synchronous SRAM of this embodiment, the first input data register 17A functions effectively in the normal write mode, so that the write address and the write data are externally input at the timing of the normal write specification of FIG. Even if the write address and write data are input to the internal circuits (circuits other than the first input data register 17A) at the timing of the late write specification shown in FIG. Will be visible.
[0024]
As for the timing at the time of data reading, as described above, the conventional SRAM of the normal write specification and the synchronous SRAM of the late write specification have the same timing. Therefore, in the synchronous SRAM of the present embodiment, even if the internal circuit operates differently from the conventional synchronous SRAM of the normal write specification, the input / output timing viewed from the outside will be the same as that of the normal write specification including the data read. Is exactly the same as the synchronous SRAM. As a result, according to the present embodiment, both the synchronous SRAM of the normal write specification and the synchronous SRAM of the normal write specification can be provided as the same semiconductor chip. Since only the internal circuit of the SRAM needs to be designed, the development period can be shortened, and a single production line can be used, so that a product that is price competitive can be provided.
[0025]
FIGS. 6 and 7 show specific circuit examples of the first input data register 17A in the synchronous SRAM of the above embodiment.
[0026]
The embodiment of FIG. 6 includes a latch circuit LT including inverters INV1 and INV2 and an output inverter INV3 whose input / output terminals are coupled to each other, and clock signals provided on the input side and output side of the latch circuit LT, respectively. Transmission gates TG1 and TG2, which are MOSFETs controlled by the control circuit, and provided on bypass paths bypassing the latch circuit LT between the output-side transmission gate TG2 and the output terminal OUT and between the input terminal IN and the output terminal OUT, respectively. And transmission gates TG3 and TG4 formed of MOSFETs controlled by a potential applied to the control terminal CTRL.
[0027]
In the circuit of this embodiment, when the control terminal CTRL is set to a high level (power supply voltage Vcc), the transmission gate TG3 is cut off, TG4 is turned on, and the signal supplied to the input terminal IN (input write in this embodiment) (Data) is transmitted from the output terminal OUT to the next-stage circuit without passing through the latch circuit LT. On the other hand, when the control terminal CTRL is set to the low level (ground potential 0 V), the transmission gate TG3 is turned on and the TG4 is turned off, and the signal supplied to the input terminal IN is synchronized with the clock signal (K, / K). Then, the latch circuit LT operates so as to transmit the latched signal from the output terminal OUT to the next-stage circuit.
[0028]
The input data register of the embodiment shown in FIG. 7 is controlled by a signal obtained by logically synthesizing the clock signal and the signal of the control terminal CTRL instead of directly controlling the transmission gates TG1 and TG2 in the embodiment of FIG. An AND gate G1 which receives an inverted signal of a clock signal and a signal of a control terminal for forming a signal for controlling the transmission gate TG1, and an inverted signal of an output of the AND gate G1 And a NAND gate G2 that receives a signal obtained by inverting the signal of the terminal.
[0029]
In the circuit of this embodiment, when the control terminal CTRL is set to a high level (power supply voltage Vcc), the transmission gates TG1 and TG2 are turned on regardless of whether the clock signal (K, / K) is high or low, and the input is controlled. The signal (input write data in the embodiment) supplied to the terminal IN is immediately transmitted from the output terminal OUT to the next circuit via only the inverter INV3 of the latch circuit LT. On the other hand, when the control terminal CTRL is set to a low level (ground potential 0 V), the transmission gates TG1 and TG2 are turned on / off complementarily in response to the high / low of the clock signal (K, / K), and the input terminal IN To the latch circuit LT during the low-level period of the clock signal (K, / K) and holds the latched signal. The latched signal is output from the output terminal OUT via the transmission gate TG2 during the high-level period of the clock signal. It operates to transmit to the next stage circuit.
[0030]
FIG. 8 shows another embodiment of a method for switching the synchronous SRAM of the above embodiment between a normal write mode and a late write mode. In this embodiment, the write data input terminal Din is selectively connected to the first input data register 17A or the second input data register 17B by changing a wiring pattern forming mask. FIG. 8 conceptually shows this.
[0031]
As described above, in the above embodiment, the internal circuit of the SRAM of the normal write specification has the same configuration as the internal circuit of the SRAM of the late write specification, and the write data input register has a two-stage configuration. The write data input register has a configuration capable of switching to a state in which input data is passed as it is or a state in which input data is temporarily latched in accordance with an external control signal or a potential state of a predetermined terminal. Therefore, the synchronous SRAM of the normal write specification and the late write specification can be integrated into the same chip. In the development of a new product, only the internal circuit of the SRAM of the late write specification has to be designed. To provide products that are price competitive because only one production line is required. There is an effect that it is.
[0032]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, in the above embodiment, the input address signal is 17 bits, and the data is configured to be readable / writable up to 4 bytes in byte units. Is not limited to the embodiment.
[0033]
In the above description, the case where the invention made by the inventor is mainly applied to a synchronous SRAM as a background of application has been described. However, the present invention is not limited to this, and semiconductors other than the synchronous SRAM are used. It can be widely used for designing techniques for memories and semiconductor integrated circuits.
[0034]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0035]
That is, new products of the synchronous SRAM of the normal write specification and the synchronous SRAM of the late write specification can be developed in a short time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a synchronous SRAM as an example of a semiconductor memory device suitable for applying the present invention.
FIG. 2 is a block diagram showing an example of a conventional normal-write synchronous SRAM.
FIG. 3 is a timing chart showing the operation timing of a conventional normal write synchronous SRAM.
FIG. 4 is a block diagram showing an example of a conventional synchronous SRAM of late write specification.
FIG. 5 is a timing chart showing operation timing of a conventional synchronous SRAM of late write specification.
FIG. 6 is a circuit diagram showing a first embodiment of a first input data register in a synchronous SRAM to which the present invention is applied;
FIG. 7 is a circuit diagram showing a second embodiment of the first input data register in the synchronous SRAM to which the present invention is applied;
FIG. 8 is a conceptual diagram showing another embodiment of a method for switching a synchronous SRAM to which the present invention is applied between a normal write mode and a late write mode.
[Explanation of symbols]
Reference Signs List 10 Memory array 11A, 11B Address register 12 Address multiplexer 13 Decoder 14 Sense amplifier circuit 15 Data multiplexer 16 Output data register 17A, 17B Input data register 18 Write driver 19 Global write signal latch circuit 20A, 20B Byte select signal Latch circuit 21 Chip select signal latch circuit 22 Clock control circuit 23 Address comparator 24 Output buffer 25 Output control register CTRL Mode control terminal

Claims (3)

A memory array, an address input circuit for receiving an externally input address signal for selecting a desired memory cell in the memory array, and a signal for decoding the input address signal and selecting a corresponding memory cell , An output circuit for outputting a signal read from a selected memory cell to the outside, a data input circuit for receiving write data input from the outside, and a byte selection signal input from the outside And a register for capturing the
The data input circuit includes a first input register and a second input register connected in cascade to the first input register. The first input register is configured to pass input data as it is in accordance with a potential state of an external control terminal. Alternatively, it is configured to be able to switch to one of a state in which input data is temporarily latched, and to be able to write at least write data to the memory array in byte units according to the byte selection signal. Semiconductor storage device. The address input circuit comprises a cascade-connected two-stage register, a comparator for comparing the addresses of a preceding-stage address register and a subsequent-stage address register, and a comparator for detecting an address match when the comparator detects an address match. 2. The semiconductor memory device according to claim 1, further comprising a data multiplexer for supplying data held in said data input circuit to an output circuit instead of data read from a memory array. The internal circuit has the same configuration as the clock synchronous static RAM of the late write specification, and the input circuit for the write data has a two-stage configuration of cascade-connected registers. Designed to have a configuration that can switch to any of the states in which input data is temporarily latched, so that a clock synchronous static RAM of normal write specification and a clock synchronous static RAM of late write specification are the same semiconductor chip. A method of designing a semiconductor memory device, characterized in that the method is provided as:

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