JP3564309B2 - Data processing device and control method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing device that processes data input in a packet format and a control method thereof, and further relates to a digital broadcast receiver including the data processing device.
[0002]
[Prior art]
In general, data such as images and sounds in digital broadcasting is sent in a fixed-length data sequence called a transport stream packet (hereinafter abbreviated as a TS packet). For example, the widely used standard of Moving Picture Experts Group 2 (hereinafter abbreviated as “MPEG2”) is a TS packet having a length of 188 bytes. Hereinafter, the TS packet will be described using MPEG2 as an example, but the principle is the same in other standards as long as the packet format is used.
[0003]
FIG. 6 is a schematic diagram showing a general format of a TS packet.
The TS packet is a fixed-length packet of 188 bytes, and the first four bytes are particularly called a packet header. The first byte is a synchronization byte for synchronizing with the processing device that processes the TS packet, and the data value is always '47h (h represents a hexadecimal number)'. Thereafter, when a data error is detected by the demodulation circuit, a transport error indicator (transport_error_indicator) bit that is set to “1” and a payload unit start indicator indicating that there is a head of a PES (packetized_elementary_stream) packet. (Payload_unit_start_indicator) bit, a PID (Packet ID) bit for specifying the type of packet, an adaptation field control (adaption_field_control) bit indicating the presence or absence of an adaptation field, and a CC (control_control) indicating packet continuity. Bits are assigned I have.
[0004]
The fifth and subsequent bytes are called a payload, which is an area where actual data is stored. In the area of the payload, a PES packet including an image and a voice, section data including additional information such as information for specifying a receiver and various service information, an adaptation field having time information, and the like are stored. Which data is stored in the packet can be determined by checking the PID and the adaptation_field_control bit.
[0005]
The TS packet received by the digital broadcast receiver is subjected to filtering for extracting only necessary data, descrambling of scrambled data so that only a specific subscriber can view the data, and then storing the data in a memory. In general, a mechanism is used in which an AV decoder for extracting audio and / or video uses packets stored in a memory. Means having a function of filtering and descrambling a TS packet and storing it in a memory is called a TDDS (transport decoder / descrambler).
[0006]
FIG. 7 is a block diagram schematically illustrating a TDDS 310 in the digital broadcast receiver and a configuration connected to the periphery thereof (here, the demodulation circuit 300, the memory manager 330, the memory 331, and the CPU 332). Arrows 350 to 364 indicate signal lines for transmitting information.
[0007]
The demodulation circuit 300 demodulates the received broadcast data to generate a TS packet. The output from the demodulation circuit 300 to the TDDS 310 indicated by the signal line 350 conforms to the MPEG2 standard. The TDDS 310 performs filtering, descrambling, error detection, formatting, and the like on the TS packet input from the signal line 350. The TDDS 310 will be described later in detail. The memory manager 330 stores TS packet data output from the signal line 360 in the memory 331 via the signal line 361 while arbitrating access to the memory 331 from the CPU 332 via the signal lines 362 and 361. The memory 331 can store a TS packet and can be used as a main memory of the CPU 332 and can be directly accessed from the CPU 332.
[0008]
Next, each configuration in the TDDS 310 will be described. The TDDS 310 includes a synchronization circuit 311, a PID filter 312, a descrambler 313, a formatter 314, a section filter 315, a transfer circuit 316, and a status processing circuit 317. The status processing circuit 317 further includes a status register 318.
[0009]
The synchronization circuit 311 detects head data from a fixed-length TS packet input via the signal line 350. The data of the first byte of the TS packet in MPEG2 is determined to be '47h (h represents a hexadecimal number)'. Upon detecting “47h”, the synchronization circuit 311 checks whether “47h” is detected for each fixed-length byte (188 bytes) of the TS packet from the position where “47h” is detected. The detected '47h' is recognized as the head of the packet, and synchronization is established. It is possible to arbitrarily set how far ahead the data '47h' is confirmed. When synchronization is established, the synchronization circuit 311 outputs a TS packet to the signal line 351.
[0010]
The PID filter 312 outputs only necessary packets to the signal line 352 based on the PID of the TS packet input via the signal line 351 and discards unnecessary packets.
[0011]
The descrambler 313 descrambles (descrambles) the data of the TS packet input via the signal line 352 and outputs the descrambled signal to the signal line 353.
[0012]
The formatter 314 extracts data (for example, an adaptation field, a section, a PES packet, and the like) necessary for subsequent processing from the TS packet input via the signal line 353. By extracting necessary data instead of transmitting all the input TS packets, it is possible to save the memory for storing the packets and reduce the load on the CPU 332 that uses the packets. The extracted data is output to a signal line 354.
[0013]
The section filter 315 filters the header of the section of the data input via the signal line 354, acquires a necessary section, and outputs the required section to the signal line 355. Data other than the section is output to the signal line 355 as it is.
[0014]
The transfer circuit 316 transfers data (or a packet) extracted from the TS packet subjected to the above processing and output to the signal line 355 to the memory 331 via the memory manager 330. Since the memory 331 is also accessed from the CPU 332, the memory manager 330 manages the right to access the memory 331. The transfer circuit 316 temporarily stores the data from the section filter 315 in a data buffer in the circuit, and transfers the data to the memory 331 when the memory manager 330 receives permission to access the memory 331.
[0015]
Some TDDSs 310 can detect a status including an error in a TS packet, a status of processing by the TDDS 310, and an abnormality in processing (to be collectively referred to as status information). An example will be described with reference to FIG.
The synchronization circuit 311 sends a status of synchronization such as establishment or loss of synchronization to the status processing circuit 317 via the signal line 356 as status information.
[0016]
The PID filter 312 also checks the transport_error_indicator bit and the CC bit of the TS packet when performing filtering based on the PID. Since “1” is set in the transport_error_indicator when an error is detected in the demodulation circuit 300, the PID filter 312 confirms that “1” is set in the transport_error_indicator. The packet is regarded as unusable and discarded, and the fact that the PS packet is discarded is sent to the status processing circuit 317 via the signal line 357 as status information.
[0017]
On the other hand, since CCs are assigned consecutive numbers for each PID, it is possible to know whether or not a packet is missing by checking the continuity of CC values. When confirming the discontinuity of the CC value, the PID filter 312 reports the discontinuity of the packet to the status processing circuit 317 via the signal line 357 as status information.
[0018]
When extracting necessary data, the formatter 314 checks the data length of the section over the packet, the data length of the PES packet over the packet, and the CRC (Cyclic Redundancy Check) bit of the section. Among them, in the data length check, a payload_unit_start_indicator bit, a pointer field (pointer_field) bit at the beginning of the payload of a TS packet having a section, a section data length included in a section header, and a PES included in a PES packet header The data length is checked, and if there is a contradiction, a data length error is detected. In the CRC check, the consistency between the 4-byte CRC added to the end of the section data and the data to provide redundancy is checked, and if an error is found, an error is detected. In any case, if an error occurs, the error is reported to the status processing circuit 317 via the signal line 358 as status information.
[0019]
When a buffer in the circuit overflows, the transfer circuit 316 reports the buffer overflow to the status processing circuit 317 via the signal line 359 as status information.
The status processing circuit 317 that has received the status information generates an interrupt to the CPU 332 via the signal line 363, and displays the cause in the status register 318. The CPU 332 reads the register 318 via the signal line 364 and recognizes an interrupt factor.
[0020]
Next, packet access and error processing by the CPU 332 will be described.
The CPU 332 reads out the packet stored in the memory 331 while being arbitrated by the memory manager 330, and performs packet processing. For example, when the CPU 332 processes a section, it reads a packet in the memory 331 and then analyzes the section header to determine a section type. Although the packet has passed any of the conditions for each section type registered in the section filter 315 and passed through the filter, the CPU 332 does not know which condition was satisfied, that is, the section type. Must be analyzed.
[0021]
Next, the operation of the CPU 332 when an interrupt occurs will be described.
When detecting an interrupt from the status processing circuit 317 of the TDDS 310 during the packet processing, the CPU 332 temporarily suspends the packet processing, reads the status register 318 in the status processing circuit 317 via the signal line 364, and determines the cause of the interrupt. know. When the interrupt factor is out of synchronization detected by the synchronization circuit 311, for example, the TS packet already stored in the memory 331 is not affected by the interrupt factor, so the CPU 332 continues to process the packet in the memory 331. . If the interrupt factor is, for example, a data length error detected by the formatter 314, the packet containing the error may have already been stored in the memory 331, and depending on the contents of the packet processing by the interrupted CPU 332, the interrupted packet Processing must be discarded immediately. Similarly, for other interrupt factors, there are packets that can be used in the memory 331 and packets that need to be immediately discarded.
[0022]
[Problems to be solved by the invention]
When the CPU 332 detects an interrupt from the TDDS 310, the CPU 332 reads the status register 318 to know what interrupt factor has occurred. However, there is a time lag between the occurrence of the interrupt factor and the time when the CPU 332 knows the interrupt factor. Further, depending on the type of the interrupt factor, the TS packet continues to flow in the TDDS 310. There was a problem that it was not possible to determine whether or not the error occurred.
[0023]
Further, when two or more error data are consecutive, only the newest error status of the TS packet remains in the status register 318, so that the CPU 332 may overlook an error preceding the latest error data. there were.
[0024]
Further, when the CPU 332 reads and processes a section, the section stored in the memory 331 cannot determine which condition is satisfied by the section filter 315, and the section header needs to be analyzed again. Had to be applied again.
[0025]
The present invention has been made to solve the above problems, and includes an error detected when processing a TS packet, a condition type in which the TS packet is filtered, and an abnormality in the processing of the TS packet. It is an object of the present invention to provide a data processing apparatus capable of presenting status information to a CPU for each TS packet.
[0026]
[Means for Solving the Problems]
In order to achieve the above object, a data processing apparatus for processing and outputting digital data input in a packet format according to claim 1 includes: a synchronization unit for establishing synchronization of input data; Filtering means for extracting necessary data; detecting means for detecting the state of the input data; generating means for generating status data based on the state of the data detected by the detecting means; , The information obtained by filtering is added in log format Output means for outputting the data together with the data extracted by the filtering means.
[0027]
Further, the data processing device according to claim 2 is characterized in that the status data includes whether synchronization can be established by the synchronization means.
[0028]
The data processing device according to claim 3 is characterized in that the status data includes a filtering condition of a filtering unit.
[0029]
The data processing device according to claim 4 is characterized in that the status data includes a processing abnormality in the data processing device.
[0030]
The data processing device according to claim 5, wherein the state of the data is an error detected by any processing device before the data is input to the data processing device, data continuity, data length, and data status. It is characterized in that at least one of the redundancy check results is included.
[0031]
In the data processing device according to claim 6, the input data includes section data including additional information with respect to the output data, and the filtering unit extracts necessary section data from the section data. The detecting means detects the state of the section data, the generating means generates section status data based on the state of the section data detected by the detecting means, and the output means outputs the section data extracted by the filtering means. It is output together with section status data.
[0032]
Further, in the data processing apparatus according to claim 7, when the section data extends over a plurality of packets, and the filtering unit cannot complete the filtering, the generation unit includes the fact that the filtering is incomplete in the section status data. It is characterized by.
[0033]
Further, in the data processing apparatus according to claim 8, the input data includes actual data in the form of a PES packet, the filtering means extracts a necessary PES packet from the PES packet, and the detection means outputs the PES packet. The data state is detected, the generation means generates PES packet status data based on the data state of the PES packet detected by the detection means, and the output means converts the PES packet extracted by the filtering means into a PES packet. It is output together with status data.
[0034]
Further, the data processing device according to claim 9 further includes a discarding unit for discarding unnecessary data, and the generating unit generates discarded data status data based on information about the data discarded by the discarding unit. , The output means outputs the discarded data status data instead of the discarded data.
[0035]
The data processing apparatus according to claim 10, wherein the unnecessary data is at least one of data for which synchronization was not established by the synchronization unit, data that was not extracted by the filtering unit, and data for which an error was detected by the detection unit. It is characterized by including one.
[0036]
The data processing apparatus according to claim 11, further comprising: a data buffer for temporarily storing data extracted by the filtering means before outputting the data from the output means; and a status data generated by the generating means. And a data buffer address holding means for holding a head or end address of the data held in the data buffer before outputting from the data buffer. Immediately before outputting the data of the first address stored in the data buffer from the data processing device or immediately after outputting the data of the end address stored in the data buffer address holding means from the data processing device. Output status data To.
[0037]
The data processing device according to claim 12 is characterized in that the status data includes an overflow of the data buffer.
[0038]
The data processing device according to claim 13, wherein when the data is discarded due to the overflow of the data buffer, the generating means generates discarded data status data based on information of the discarded data, Output status data for discarded data instead of discarded data.
[0039]
A digital broadcast receiver according to a fourteenth aspect includes the data processing device according to any one of the first to thirteenth aspects.
[0040]
A data processing method for processing and outputting digital data input in a packet format according to claim 15, establishes synchronization of the input data, extracts necessary data from the data after the synchronization is established, Detecting a data state, generating status data indicating the data state, and outputting the status data together with the necessary data.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, a data processing device according to a first embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a description will be given of a TS packet based on MPEG2 as an example. However, the principle is the same even if the packet format is another standard. For the format of the TS packet based on MPEG2, see FIG. 6 described above.
[0042]
FIG. 1 is a block diagram schematically illustrating a configuration related to data reception in a digital broadcast receiver according to the present embodiment. In the digital broadcast receiver, a demodulation circuit 100, a TDDS (transport decoder / descrambler) 110, a memory manager 130, a memory 131, and a CPU 132 are mainly involved in data reception. Arrows 150 to 155 and 165 to 166 indicated by thick solid lines indicate signal lines indicating the flow of packets, and arrows 156 to 160 indicated by thin solid lines indicate the flow of status information (status data) for log generation. Arrows 161 to 164 indicated by dotted lines in the signal lines are signal lines indicating the flow of status information, and other information flows are indicated by dashed lines.
[0043]
The TDDS 110 further includes a synchronization circuit 111, a PID filter 112, a descrambler 113, a formatter 114, a section filter 115, a transfer circuit 116, a log generation circuit 120, and a status processing circuit 117. The status processing circuit 117 further includes a status register 118.
[0044]
The synchronization circuit 111 detects the head data '47h' of the fixed-length TS packet input from the signal line 150, recognizes the head of the packet, and establishes synchronization. After the synchronization is established, the TS packet is output to the signal line 151. Further, the status of synchronization establishment in the synchronization circuit 111, that is, whether or not synchronization has been established, is transmitted to the status processing circuit 117 via the signal line 161 as status information, and a TS packet is output from the signal line 151. At this time, status information is output to the signal line 156.
[0045]
The PID filter 112 extracts a necessary TS packet based on the PID of the TS packet input from the signal line 151, outputs the extracted TS packet to the signal line 152, and discards unnecessary TS packets.
[0046]
Further, the PID filter 112 checks the transport_error_indicator of the TS packet to confirm whether the demodulation circuit 100 has detected no error. When there is an error, the PID filter 112 normally discards the transmitted TS packet as being unusable. Further, the PID filter 112 checks the value of the CC (continuity_counter) of the TS packet to confirm the continuity of the packet.
[0047]
In the above processing, the PID filter 112 reports the discard of the TS packet and the continuity of the packet to the status processing circuit 117 via the signal line 162 as status information. The status information of the currently processed TS packet fetched from the signal line 156 includes information related to the processing in the PID filter 112, such as the PID condition of the TS packet passed through the PID filter 112, the discarded TS packet, and the CC The continuity is added, and the signal is output from the signal line 157. That is, the status information output to the signal line 157 includes the result of the detection by the synchronization circuit 111 and the PID filter 112 and information on the processing performed on the TS packet output to the signal line 152. Will be.
[0048]
The descrambler 113 performs a descrambling process on the TS packet input from the signal line 152 and outputs the TS packet to the signal line 153. Regarding the processing in the descrambler 113, if there is valid information as the status information, the information in the descrambler 113 is added to the status information input from the signal line 157, as in the case where the PID filter 112 adds the status information. The packet is output to the signal line 158 together with the output of the packet.
[0049]
The formatter 114 extracts data (for example, an adaptation field, a section, a PES packet) of the TS packet input from the signal line 153 and outputs the data to the signal line 154. At this time, an abnormal data length and a CRC error are detected. The detection result is transmitted to the status processing circuit 117 via the signal line 163, added to the status information input from the signal line 158, and output to the signal line 159. If there is valid information other than the above detection result, it may be output as status information.
[0050]
The section filter 115 performs section filtering on the section extracted by the formatter 114, acquires a necessary section, and outputs it to the signal line 155. The data other than the section is output without any processing.
[0051]
The section filter 115 includes an entry table having a plurality of entries for registering conditions of a section to be acquired. FIG. 2 is a schematic diagram of the entry table 115-1. The entry table 115-1 includes a plurality of entries 115-10 for registering conditions, and an entry number display unit 115-20 indicating a number assigned to each entry.
[0052]
The section filter 115 compares the header portion of the input section with the condition registered in each entry 115-10, and if at least one condition matches the header portion of the input section, the section is filtered by the filter 115. Pass through. When the section has passed the filter 115, the entry number of the matching condition is added to the status information input from the signal line 159 and output to the signal line 160. In addition, when filtering of a section cannot be completely performed for some reason (for example, when a section spans a plurality of TS packets), that is, when filtering is performed, the filtered data is output to a signal line 155 and Alternatively, the descending of filtering may be output to the signal line 160 as status information. Further, the state of the filtering performed before the descending can be output to the signal line 160 as status information.
[0053]
The log generation circuit 120 assembles a log in a fixed format based on the status information input from the signal line 160. The created log is temporarily stored in a buffer (the log buffer 605 in FIG. 4) in the log generation circuit 120 and then sent to the transfer circuit 116.
The transfer circuit 116 outputs the data extracted from the TS packet input from the signal line 155 to the signal line 165 and transfers the data to the memory 131 via the memory manager 130.
[0054]
Since the memory 131 is also accessed from the CPU 132, the memory manager 130 manages the right to access the memory 131. The transfer circuit 116 temporarily stores the data from the section filter 115 in a data buffer (the data buffer 600 in FIG. 4) in the transfer circuit 116, and receives an access permission from the memory manager 130 to the memory 131. To transfer. The transfer circuit 116 outputs the start log or section start log (described later) generated by the log generation circuit 120 to the signal line 165 prior to the data transfer, and subsequently transfers a series of data. , An end log (to be described later) is output to the signal line 165. That is, the memory 131 stores a series of data transferred from the transfer circuit 116 as one packet, and stores a start log at the beginning of each packet and an end log at the end. When the data buffer in the transfer circuit 116 overflows, the overflow is transmitted to the status processing circuit 117 via the signal line 164.
[0055]
When information is input from the signal lines 161, 162, 163 and 164, the status processing circuit 117 interrupts the CPU 132 via the signal line 168 and reflects the input information on the status register 118. Bits are assigned to the status register 118 for each piece of input information, and the corresponding bit is turned on according to the input information. The CPU 132 checks the bit of the status register 118 via the signal line 169 to specify the cause of the interrupt.
[0056]
FIG. 3 is a schematic diagram illustrating an example of a log format. A start log 1000, a section start log 1001, and an end log 1002 are shown in order from the top. Each log will be represented by 2 bytes. The log type such as the start log 1000, the section start log 1001, and the end log 1002 can be determined by a field indicating the log type in the log.
[0057]
At the beginning of the data other than the section, a start log 1000 is added. The start log 1000 includes, for example, a log format (eg, 3 bits), a log type (eg, 3 bits), a data type of data to which the log is added, and status information (eg, a sequence indicating CC discontinuity). Error indicator (1 bit)).
[0058]
At the beginning of the section, a section start log 1001 having a format different from that of the previous start log 1000 is added, because there are many types of additional information as compared with other data. The section start log 1001 includes, for example, a data length (section filtering length, for example, 5 bits) filtered by the section filter 115, a log type (for example, 3 bits), an indicator indicating that section filtering has surrendered, and the section filter 115. , Information such as an entry number of a condition that matches the section (filter matching entry number), completion of filtering (not shown), and a filtering status (not shown) before the filtering is dropped.
[0059]
The end log 1002 includes information such as a format (for example, 3 bits), a log type (for example, 3 bits), status information of data to which the log is added, for example, a data length error indicator, a CRC error indicator, and a sequence error indicator. Has been recorded.
[0060]
Next, the operation of the CPU 132 according to the first embodiment will be described.
When processing a data packet stored in the memory 131, the CPU 132 first reads a log added before and after each packet stored in the memory 131, and acquires status information of a packet to be processed from now on. .
[0061]
For example, when processing a section, in the related art, after reading the section, it is necessary to analyze the header part of the section and determine the section type. However, in this embodiment, the entry number of the condition that matches in the section filter 115, that is, the section type can be known only by reading the section start log added to the head of the section data, and the load on the CPU 132 is reduced. it can. Further, when the section filtering descending indicator of the section start log indicates that the section filtering has been descended, the CPU 132 can perform the section filtering again to remove unnecessary sections. At this time, if the information performed before the drop-off of the section filtering is included in the log as the filtering progress information, the CPU 132 may start with the filtering that should have been performed after the drop-off. As described above, since the log includes the status information, the load on the CPU 132 for the process of recognizing the status of the data is reduced.
[0062]
If an interrupt occurs during the processing of the packet stored in the memory 131, the CPU 132 temporarily suspends the packet processing. When an interrupt occurs from the TDDS 110, the CPU 132 reads the status register 118 and specifies the cause of the interrupt. As a result, if the processing of the data stored in the memory 131 is not affected, the CPU 132 continues the processing of the packet. If the cause of the interruption is that there is a possibility that the data in the memory 131 may be abnormal (for example, a data length error detected by the formatter 114), when processing a packet in the memory 131, the log is read and there is an abnormality. Check if it is data. Data containing no abnormality is used for normal processing even after an interrupt occurs, and if there is an error, the data is discarded.
[0063]
Further, when reading data in the memory 131 irrespective of whether or not an interrupt has occurred, error information recorded in a log may be constantly checked. In this case, the operation program of the CPU 132 is simplified.
[0064]
As described above, by adding the log including the status information to the packet data in the memory 131, the load on the CPU 132 when processing the packet data can be reduced, and the error of the packet data can be reduced. Presence or absence can be clarified.
[0065]
Next, a logical configuration of the log generation circuit 120 and the transfer circuit 116 according to the first embodiment will be described with reference to FIG. FIG. 4 is a block diagram illustrating a configuration of the log generation circuit 120 and the transfer circuit 116. Arrows 155, 165, 651-664, 680, 685, and 690 are signal lines indicating the flow of information.
[0066]
The log generation circuit 120 includes a data buffer 600, a data buffer write pointer 601, a data buffer read pointer 602, a data transfer control circuit 603, a selector 610, and a data buffer overflow detection unit (not shown). It includes a log mark buffer 604, a log buffer 605, a log generation unit 606, a log buffer write pointer 607, a log buffer read pointer 608, and a log transfer control circuit 609.
[0067]
The data buffer 600 temporarily stores data input from the signal line 155 before transferring it to the memory 131, and is a FIFO (first-in first-out) type buffer. Although the TS packet is sent unilaterally, there is a period during which the TDDS 110 cannot access the memory 131 due to the access from the CPU 132 to the memory 131 and the refresh time of the memory 131. Therefore, a buffer for temporarily storing data before transferring the data to the memory 131 like the data buffer 600 is required.
[0068]
The data buffer write pointer 601 indicates a write address of the data buffer 600 via a signal line 651, and the data buffer read pointer 602 indicates a read address of the data buffer 600 via a signal line 653.
[0069]
When the data buffer overflow detection unit detects an abnormality in the processing of the data buffer 600, that is, an overflow, it notifies the status processing circuit 117 of the overflow via the signal line 164 shown in FIG.
[0070]
The data transfer control circuit 603 checks the value of the data buffer write pointer 601 via the signal line 652 and monitors the current storage status in the data buffer 600. When an arbitrarily set amount of data is stored in the data buffer 600, the address of the data to be read is indicated to the data buffer read pointer 602 via the signal line 655, and the data of the address indicated by the read pointer 602 is stored in the data buffer 600. Is output to the signal line 680. The trigger for starting the data transfer is not limited to this.
[0071]
The selector 610 selects data to be transferred to the memory 131. Normally, the selector 610 selects the data buffer 600, connects the signal line 680 to the signal line 165, and outputs data extracted from the TS packet to the signal line 165. When the log transfer is required, the selector 610 is switched to the log buffer 605 side by the instruction of the log transfer control circuit 609 via the signal line 664, and the signal line 658 and the signal line 165 are connected.
[0072]
The log generation unit 606 generates the log format described above based on the status information transmitted on the signal line 160. The generated log is output to the log buffer 605 via the signal line 657.
The log buffer 605 temporarily stores the log generated by the log generation unit 606 before transferring the log to the memory 131, and is a FIFO type buffer. The log buffer write pointer 607 indicates a write address of the log buffer 605 via a signal line 660-1, and the log buffer read pointer 608 indicates a read address of the log buffer 605 via a signal line 661.
[0073]
On the other hand, the formatter 114 generates a log write strobe signal indicating the beginning and end of the data transmitted to the data buffer 600, and transmits the generated log write strobe signal to the log generation circuit. The data flowing on the signal line 155 when the log write strobe signal is active indicates the beginning or end of a series of data. Accordingly, when the log write strobe signal becomes active, the log write strobe signal is notified to the log buffer write pointer 607 and the log buffer 605 via the signal lines 659-1 and 659-2, and is generated by the log generation unit 606. The log is stored at the address indicated by the log buffer write pointer 607.
[0074]
When the log write strobe signal becomes active, the log write strobe signal is notified to the log mark buffer 604 serving as a data buffer address holding unit via a signal line 659-3. The log mark buffer 604 receiving the log write strobe signal stores the address indicated by the data buffer write pointer 601 fetched via the signal line 685, that is, the head or end of a series of data fetched from the TS packet. The address of the data buffer 600 is stored at the same address as the address indicated by the log buffer write pointer 607 captured via the signal line 660-2. Note that the address data stored in the log mark buffer 604 and the log stored in the log buffer 605 have a one-to-one correspondence.
[0075]
The log transfer control circuit 609 temporarily stops the data transfer and transfers the log when the log transfer needs to be performed during the data transfer. The log transfer control circuit 609 monitors the value of the data buffer read pointer 602 via the signal line 690. The log mark buffer 604 outputs the head or end address of the data stored in the data buffer 600 to the log transfer control circuit 609 via the signal line 654, that is, the address where log transfer is required. If the address indicated by the data buffer read pointer 602 matches the address sent from the signal line 654, the log transfer control circuit 609 determines that log transfer is necessary, and causes the data transfer control circuit 603 to transfer data by the signal line 603. Interrupt at 656. When the head of the data is detected, the transfer of the data at the address indicated by the data buffer read pointer 602 (output from the signal line 165) is temporarily stopped. If the end of the data is detected, the data transfer is interrupted after outputting the data at the address indicated by the data buffer read pointer 602 to the signal line 165. Next, the selector 610 is switched to the log buffer 605 side via the signal line 664, a log transfer instruction is sent to the log buffer read pointer 608 via the signal line 663, and the log from the log buffer 605 is sent to the signal line 658 and the selector 610. Output to the signal line 165 via
[0076]
A signal line 662 is a transfer permission signal from the memory manager 130. The transfer permission signal is sent to the data transfer control circuit 603 and the log transfer control circuit 609. Neither data nor logs can be transferred until the transfer permission is received from the memory manager 130 by the transfer permission signal.
[0077]
In the present embodiment, a log is added before and after a data packet in the TDDS 110, and the data packet is transferred to the memory 131 using the same data bus as the data packet. Therefore, it is not necessary to add new logic to the logic of the memory manager 130. Absent.
[0078]
As described above, in order to clarify which TS packet is the status information including the data status and data error, when storing the data in the memory, the status information is collected in a fixed format and logged. Is added before and after the data. Each component in the TDDS 110 transmits status information detected during data processing to the subsequent stage at the same time as the data, and the log generation circuit 120 creates a log based on the status information and stores the log in the memory. When the CPU 132 processes the packet data in the memory 131, by checking the log added before and after the data, it is possible to know the status information on the data, for example, whether or not there is an error. Since a log is added to each data, the CPU 132 does not need to erroneously treat error data as normal data, and does not need to discard normal data as suspicious data. Therefore, it becomes clear whether or not the data stored in the memory contains an error, the data stored in the memory can be used effectively, and the load on the CPU 132 when processing the packet data can be reduced. Can be.
[0079]
As described above, the status information (status data) for log generation indicates, in each circuit in the TDDS 110 exemplified above, an error in data itself and / or an abnormality in data processing (for example, buffer overflow). This can be obtained by providing means for detecting and means for generating status information (status data) for notifying the CPU 132 of the detected error and / or abnormality. Therefore, in addition to the above-mentioned errors and abnormalities, when there is information that should be known in advance when the CPU 132 processes packet data, a circuit that can obtain the information is provided with the detection means and the generation means. Just fine.
[0080]
Whether the status information is included in the start log or the end log may be determined depending on whether acquisition of the status information is in time for the first output of the packet data output from the signal line 165.
[0081]
Other embodiments.
As described with reference to FIG. 1, the TS packet is filtered by the PID filter 112 and the section filter 115, and unnecessary TS packets and data are discarded. Further, those which are determined to be unusable due to loss of synchronization by the synchronization circuit 111 or detection of a data error by the PID filter 112 or the formatter 114 are also discarded. When a TS packet or data is discarded, the discarded data is invisible to the CPU 132, and therefore, it is determined whether the data has been discarded due to an error in the data, did not meet the filter conditions, or was not input from the beginning. Can not do it.
[0082]
Therefore, a method has been devised in which a log relating to the discarded packet or data is stored in the memory 131 to clarify that the packet or data has been discarded. When the data is discarded, each component in the TDDS 110 outputs status information including a discarding factor to a subsequent processing unit. The log generation circuit 120 generates a data discard log based on status information including a discard factor.
[0083]
Also, when data is discarded due to a device error in the TDDS 110, the data discard log can be used. For example, when the data buffer 600 of the transfer circuit 116 overflows, it is determined that the data has been destroyed, and all data processed / stored in the transfer circuit 116 at that time is discarded.
[0084]
FIG. 5 shows a format example of the data discard log.
The data discard log includes, for example, information such as a format format (for example, 3 bits), a log type (for example, 3 bits), an indicator indicating a data buffer overflow, a loss of synchronization indicator, a transport error indicator, and a sequence error indicator.
[0085]
The generated data discard log is transferred to the memory 131. When the CPU 132 reads the data discard log when processing the data in the memory 131, the data before the data discard log can be identified as the normal data before the cause of the data discard, and the data discarded. You can know why.
[0086]
As described above, instead of the data discarded due to a data error or device error, a data discard log indicating that the discard has been generated is stored in the memory 131, so that the CPU 132 can discard the discarded data. And the reason therefor, it is easy to determine normal data.
[0087]
In all the embodiments described above, the description has been given in relation to the configuration related to the data reception in the digital broadcast receiver. However, the data processing device that processes the digital signal input in the packet format (for example, the transport stream packet format) is used. If this is the case, it goes without saying that this embodiment can be applied.
[0088]
【The invention's effect】
As is apparent from the above description, the data processing device of the present invention includes a synchronization unit for establishing synchronization of input data, a filtering unit for extracting necessary data from the input data, and a state of the input data. Detecting means for detecting the status data, generating means for generating status data based on the state of the data detected by the detecting means, , The information obtained by filtering is added in log format Output means for outputting the data together with the data extracted by the filtering means. Therefore, it is possible to clarify which TS packet is the status information including the data state, the data error, and the abnormality that occurred during the data processing, and the CPU uses the data processing device of the present invention. When processing the data output from, by checking the logs added before and after the data, it is possible to know the status information on the data, for example, whether or not there is an error. Since status data is added to each data, the CPU does not need to erroneously treat error data as normal data, and does not need to discard normal data as suspicious data. Further, the load on the CPU when processing packet data can be reduced.
[0089]
Further, if a data discard log indicating that data has been discarded is generated instead of data discarded due to a data error or device abnormality, the CPU can easily determine whether or not the discarded data exists and the reason for the discarded data. You can know.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a configuration related to data reception in a digital broadcast receiver.
FIG. 2 is a schematic diagram of an entry table 115-1.
FIG. 3 is a schematic diagram illustrating a format example of a log.
FIG. 4 is a block diagram illustrating a detailed configuration of a log generation circuit 117 and a transfer circuit 116.
FIG. 5 is a schematic diagram showing another example of a log format.
FIG. 6 is a schematic diagram showing a general format of a TS packet.
FIG. 7 is a block diagram schematically showing a configuration connected to a TDDS 310 in a digital broadcast receiver and its periphery.
[Explanation of symbols]
100 demodulation circuit
110 Transport decoder / descrambler
111 Synchronous circuit
112 PID filter
113 Descrambler
114 Formatter
115 Section Filter
116 transfer circuit
117 Status processing circuit
118 Status register
120 Log generation circuit
130 Memory Manager
131 memory
132 CPU
600 data buffer
601 Data buffer write pointer
602 Data buffer read pointer
603 Data transfer control circuit
604 log mark buffer
605 log buffer
606 Log generation unit
607 Log buffer write pointer
608 Log buffer read pointer
609 Log transfer control circuit
610 selector

Claims (15)

In a data processing device that processes and outputs digital data input in a packet format,
Synchronization means for establishing synchronization of the input data;
Filtering means for extracting necessary data from the input data;
Detecting means for detecting the state of the input data;
Generating means for generating status data based on a state of the data detected by the detecting means;
An output unit that outputs the status data together with data obtained by the filtering unit by adding information obtained by filtering in a log format ,
A data processing device comprising: The data processing device according to claim 1,
The data processing device according to claim 1, wherein the status data includes information indicating whether synchronization can be established by the synchronization unit. The data processing device according to claim 1 or 2,
The data processing device, wherein the status data includes a filtering condition of the filtering unit. 4. The data processing device according to claim 1, wherein:
The data processing device, wherein the status data includes a processing abnormality in the data processing device. The data processing device according to claim 1, wherein
The state of the data is an error detected by any processing device before the data is input to the data processing device, the continuity of the data, the length of the data, and the redundancy check result of the data, A data processing device comprising at least one. The data processing device according to any one of claims 1 to 5,
The input data includes section data including additional information with respect to the output data,
The filtering means extracts necessary section data from the section data,
The detecting means detects a state of the section data,
The generating means generates section status data based on a state of the section data detected by the detecting means,
The output means outputs the section data extracted by the filtering means together with the section status data.
A data processing device characterized by the above-mentioned. The data processing device according to claim 6,
If the section data spans a plurality of packets and the filtering means cannot complete the filtering,
The data processing device, wherein the generation unit includes information that filtering is not completed and information on the progress of filtering is included in the section status data. The data processing device according to any one of claims 1 to 5,
The input data includes actual data in the form of a PES packet,
The filtering means extracts necessary PES packets from the PES packets,
The detecting means detects a state of data of the PES packet,
The generating means generates PES packet status data based on a data state of the PES packet detected by the detecting means,
The output unit outputs the PES packet extracted by the filtering unit together with the PES packet status data.
A data processing device characterized by the above-mentioned. 9. The data processing device according to claim 1, wherein:
The data processing device further includes a discarding unit that discards unnecessary data,
The generating means generates status data for discarded data based on information on the data discarded by the discarding means,
The data processing device, wherein the output means outputs the discarded data status data instead of the discarded data. The data processing device according to claim 9,
The unnecessary data includes at least one of data for which synchronization was not established by the synchronization unit, data that was not extracted by the filtering unit, and data for which an error was detected by the detection unit. Data processing device. The data processing device according to any one of claims 1 to 10,
further,
Before outputting the data extracted by the filtering means from the output means, a data buffer for temporarily holding,
Before outputting the status data generated by the generating unit from the output unit, temporarily holding a status buffer,
Data buffer address holding means for holding a head or end address of data held in the data buffer;
With
The output means outputs the data of the end address stored in the data buffer address holding means immediately before outputting the data of the head address stored in the data buffer address holding means from the data processing device or the data of the end address stored in the data buffer address holding means. Immediately after outputting from the processing device, output the status data stored in the status buffer,
A data processing device characterized by the above-mentioned. The data processing device according to claim 11,
The data processing device, wherein the status data includes an overflow of the data buffer. The data processing device according to claim 12,
When the data is discarded due to overflow of the data buffer, the generation unit generates status data for discarded data based on information of the discarded data,
The data processing device, wherein the output means outputs the discarded data status data instead of the discarded data. A digital broadcast receiver comprising the data processing device according to claim 1. In a control method of a data processing device for processing and outputting digital data input in a packet format,
Establish synchronization of the data entered above,
Extract the necessary data from the data after synchronization is established,
Detects the state of data after synchronization is established,
Generate status data indicating the status of the data,
Outputting the status data together with the necessary data,
A method for controlling a data processing device, comprising a step.

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