JP3560319B2 - Phase adjustment circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a variable delay circuit and a phase adjustment circuit using the variable delay circuit.
[0002]
[Prior art]
In order to realize high-speed data transmission, data input / output is performed in synchronization with a clock signal. In particular, when the frequency of the clock signal exceeds 100 MHz, an external clock signal supplied from outside the semiconductor integrated circuit and the inside of the semiconductor integrated circuit are output using a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop). It is necessary to synchronize with the internal clock signal used.
[0003]
Digital PLLs and DLLs using digital delay circuits have the advantage of being easier to design than analog PLLs and DLLs, but have a phase resolution of one gate of the digital delay circuit. Has the disadvantage that the delay amount cannot be made smaller than the delay amount.
[0004]
As one method for solving such a drawback, Japanese Patent Laid-Open No. Hei 10-276074 discloses a method for realizing a resolution time smaller than the delay amount of one gate of a digital delay circuit. According to this method, the delay amount t_dDelay gate with delay t_dThe decomposition time α is realized by combining with the delay gate of + α. For example, N₁+ N₂= 10 under the condition that_dN each having₁Delay gates and delay amount 1.1t_dN each having₂By connecting the delay gates in series with each other, the delay time is 10 t_dFrom 11t_dAnd the decomposition time is 0.1t_dCan be realized. For example, N₁= 7, N₂= 3, 10.3t_dDelay time can be realized.
[0005]
[Problems to be solved by the invention]
However, according to the method described in the above-mentioned publication, there is a problem that the lower limit of the settable delay time range increases with the expansion of the settable delay time range.
[0006]
For example, the decomposition time is 0.1t_dAnd the settable delay time range is 2t_dTo achieve a delay of₁+ N₂= 20 under the condition of = 20_dN each having₁Delay gates and delay amount 1.1t_dN each having₂It is necessary to connect these delay gates in series. In this case, the lower limit of the settable delay time range is 20t._dWill be.
[0007]
Further, according to the method described in the above-mentioned publication, there is a problem that the lower limit value of the settable delay time range increases as the resolution time increases.
[0008]
For example, the decomposition time is 0.05t_dTo achieve a delay of₁+ N₂= 20 under the condition of = 20_dN each having₁Delay gates and delay amount 1.05t_dN each having₂It is necessary to connect these delay gates in series. Also in this case, the lower limit of the settable delay time range is 20t._dWill be.
[0009]
The present invention has been made to solve the above problems, and provides a variable delay circuit in which the lower limit of the settable delay time does not fluctuate regardless of the range of the settable delay time and the accuracy of the decomposition time. The purpose is to do. It is another object of the present invention to provide a phase adjustment circuit using the variable delay circuit.
[0010]
[Means for Solving the Problems]
The phase adjustment circuit according to the present invention includes a first variable delay circuit for delaying an input signal, a second variable delay circuit capable of controlling a delay time with higher accuracy than the first variable delay circuit, And a control circuit for variably controlling the delay time of the variable delay circuit and the delay time of the second variable delay circuit, and the output of the first variable delay circuit is delayed by the second variable delay circuit. Thereby, a phase adjustment circuit that outputs an output signal having a predetermined phase relationship with the input signal, wherein the second variable delay circuit includes a plurality of delay circuits that delay the output of the first variable delay circuit. A delay circuit, and a selection circuit that selects one of the outputs of the plurality of delay circuits in accordance with a selection signal and outputs the selected output as the output signal. Output of 1 variable delay circuit A first delay circuit that delays by a first delay time, and a second delay circuit that delays the output of the first variable delay circuit by a second delay time longer than the first delay time, The difference between the first delay time and the second delay time is shorter than the minimum delay time that can be set in the first delay circuit. Thereby, the above object is achieved.
[0012]
It is preferable that the range of the delay time that can be set in the second variable delay circuit is wider than the decomposition time of the first variable delay circuit.
[0013]
When the target delay time exceeds the range of the delay time that can be set in the second variable delay circuit, the control circuit resets the delay time of the first variable delay circuit, and resets the delay time of the second variable delay circuit. Preferably, the delay time of the variable delay circuit is reset to substantially the center of the range of the delay time that can be set in the second variable delay circuit.
[0014]
Hereinafter, the operation will be described.
[0015]
Variable delay circuitAccording to this, one of the outputs of the plurality of delay circuits for delaying the input signal is selected by the selection circuit, and the selected output is output as an output signal. The plurality of delay circuits include a first delay circuit for delaying an input signal by a first delay time, a second delay circuit for delaying the input signal by a second delay time longer than the first delay time. It is included. The difference between the first delay time and the second delay time is shorter than the minimum delay time that can be set in the first delay circuit. As a result, the range of the delay time that can be set in the variable delay circuit can be increased as much as possible without limiting to a predetermined range. The lower limit of the delay time that can be set in the variable delay circuit is a fixed value regardless of the range of the delay time that can be set in the variable delay circuit.
[0016]
Claim1According to the invention, a phase adjustment circuit using the above-described variable delay circuit as a second variable delay circuit is provided. Thus, an output signal having a predetermined phase relationship with the input signal can be output.
[0017]
Claim2According to the invention, the range of the delay time that can be set in the second variable delay circuit is wider than the decomposition time of the first variable delay circuit. This increases the chance that the phase of the input signal can be adjusted by adjusting the delay time of the second variable delay circuit without resetting the delay time of the first variable delay circuit. Thus, the number of times of resetting the delay time of the first variable delay circuit can be reduced.
[0018]
Claim3According to the invention, when the second variable delay circuit is reset, the delay time of the second variable delay circuit is substantially at the center of the delay time range that can be set in the second variable delay circuit. Is reset to This makes it possible to quickly adjust the phase relationship between the input signal and the output signal.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(Embodiment 1)
FIG. 1 shows a configuration of the variable delay circuit 101 according to the first embodiment of the present invention.
[0021]
The variable delay circuit 101 receives the input signal F_inAnd one of the outputs of the delay circuits 102-1 to 102-n is selected according to the selection signal SEL, and the selected output is output to the output signal F._outAnd a selection circuit 103 that outputs the data as Here, n is an arbitrary integer of 2 or more.
[0022]
Each of the delay circuits 102-1 to 102-n has a fixed delay amount. Such a fixed delay amount can be obtained, for example, by connecting one or more delay gates in series. The delay gate can be, for example, an inverter.
[0023]
For example, when each of the delay circuits 102-1 to 102-n includes one or more MOS transistor gates (for example, inverters) connected in series, each of the delay circuits 102-1 to 102-n can be set. There is a minimum value of the delay time. The minimum value of the delay time is determined depending on the process of the MOS transistor.
[0024]
For example, the minimum value of the delay time that can be set in the delay circuit 102-1 (that is, the minimum delay time) is t._dSuppose that In this case, t is added to the delay circuit 102-2._dIt is impossible to set a smaller delay time, but t_dA larger delay time (eg, 1.1t_d) Is possible. For example, by adjusting the size and load condition of the MOS transistor included in the delay circuit 102-2, the delay_dA larger delay time can be set.
[0025]
For example, the delay time of the delay circuit 102-k is {1+ (k−1) × 0.1} · t._dCan be set to Here, k = 1, 2,. . . , N. In this case, the difference between the delay time of the delay circuit 102- (k + 1) and the delay time of the delay circuit 102-k is 0.1t_dAnd the minimum delay time t_dShorter than. One of the outputs of the delay circuits 102-1 to 102-n in which the delay time is set as described above is selected, and the selected output is output to the output signal F._outAs the input signal F_inOutput signal F for_outCan be variably adjusted. That is, in the variable delay circuit 101, the delay time is t_d+ T_sFrom 0.1t_dIt becomes possible to set digitally in steps. Where t_sIndicates a delay time generated in the selection circuit 103.
[0026]
Note that the purpose of using the variable delay circuit 101 is to set the decomposition time of the delay amount to t as in the case where the precision of the decomposition time of the delay is to be improved._dIn the case where the delay time is set as follows, the difference between the delay time of the delay circuit 102- (k + 1) and the delay time of the delay circuit 102-k is exactly 0.1t._dNeed not be_dYou only have to make it smaller. Also, the settable delay time steps are not necessarily required to be equal, and the delay time steps may be set to 0.1 t_dMay be included.
[0027]
FIG. 2 shows a configuration of a phase adjustment circuit 100 using the variable delay circuit 101 shown in FIG. In the phase adjustment circuit 100 shown in FIG. 2, the variable delay circuit 101 shown in FIG. 1 is used as a fine delay adjustment circuit.
[0028]
The phase adjusting circuit 100 includes a coarse delay adjusting circuit 111 for delaying the input clock signal eCLK, and a fine delay adjusting circuit 101 capable of controlling the delay time with higher accuracy than the coarse delay adjusting circuit 111. Is delayed by delay fine adjustment circuit 101 to output output clock signal iCLK having a predetermined phase relationship with input clock signal eCLK.
[0029]
The delay fine adjustment circuit 101 includes delay circuits 102-1 to 102-n and a selection circuit 103 for selecting one of the outputs of the delay circuits 102-1 to 102-n according to the selection signal SEL. The selection signal SEL is generated by the control circuit 105 according to an output signal from the phase comparator 104. The output signal from phase comparator 104 is obtained by comparing the phase of input clock signal eCLK with the phase of output clock signal iCLK.
[0030]
The coarse delay adjustment circuit 111 includes a delay circuit 112 and a delay control circuit 113 that controls the delay circuit 112. The delay control circuit 113 is controlled by the control circuit 115 according to an output signal from the monitor circuit 300. The monitor circuit 300 is used to monitor the state of the delay fine adjustment circuit 101. The output signal from the monitor circuit 300 is generated based on the output signal from the phase comparator 104 and the output signal from the phase comparator 114. The output signal from phase comparator 114 is obtained by comparing the phase of input clock signal eCLK with the phase of clock signal dCLK. The clock signal dCLK is obtained by delaying the clock signal eCLK using the coarse delay adjustment circuit 111, the dummy delay circuit 200, and the dummy driver circuit 116.
[0031]
A dummy driver circuit 116 is connected to an output of the coarse delay adjustment circuit 111 via a dummy delay circuit 200. The delay amount of dummy driver circuit 116 is set in advance so as to be substantially equal to the delay amount of driver circuit 106 driving output clock signal iCLK.
[0032]
The settable delay time step in the coarse delay adjustment circuit 111 is represented by t_dThe range of the delay time that can be set in the delay fine adjustment circuit 101 is t_dFrom 1.9t_dAssume that In this case, the delay time of the coarse delay adjustment circuit 111 is (N-1) t_dAnd the delay time of the delay fine adjustment circuit 101 is set to 1.9t._d, The delay time of the phase adjustment circuit 100 is set to (N + 0.9) t_dCan be set to Thus, the delay time of the phase adjustment circuit 100 is set to (N + 0.9) t_dIs set to state A.
[0033]
Further, the delay time of the coarse delay adjustment circuit 111 is set to Nt._dAnd the delay time of the delay fine adjustment circuit 101 is set to t_d, The delay time of the phase adjustment circuit 100 is set to (N + 1) t_dCan be set to Thus, the delay time of the phase adjustment circuit 100 is set to (N + 1) t_dIs set to state B.
[0034]
If the delay characteristics of the coarse delay adjustment circuit 111 and the delay characteristics of the fine delay adjustment circuit 101 are different due to process variation or the like, the delay time (N + 0.9) t set in the state A_dAnd delay time (N + 1) t set in state B_dIs 0.1t_dIt is also assumed that it becomes larger. In this case, since the state of the phase adjustment circuit 100 is not locked to the state A or the state B, an oscillation state in which the oscillation occurs between the state A and the state B may occur. Then, in the delay fine adjustment circuit 101, delay setting is started in order from the maximum value or the minimum value due to the configuration, so that the phase greatly changes.
[0035]
Thus, fine adjustment of the delay amount cannot be realized by simply connecting the coarse delay adjustment circuit 111 and the fine delay adjustment circuit 101. In the phase adjustment circuit 100, the phase comparator 104 and the phase comparator 114 perform phase comparison independently of each other, so that the delay time of the delay coarse adjustment circuit 111 and the delay time of the delay fine adjustment circuit 101 are set independently of each other. Is done. Only when the delay fine adjustment circuit 111 overflows, the delay time of the coarse delay adjustment circuit 111 is reset. Thus, the above-described oscillation operation is prevented.
[0036]
Hereinafter, the operation of the phase adjustment circuit 100 will be described.
[0037]
First, the delay control circuit 113 adjusts the number of stages of the delay circuit 112 so that the phase of the input signal eCLK matches the phase of the clock signal dCLK that has passed through the delay coarse adjustment circuit 111, the dummy delay circuit 200, and the dummy driver circuit 116. Controlled.
[0038]
Here, as shown in FIG. 3, consider the case where the phase of clock signal dCLK is delayed by 0.3 ns from the phase of input clock signal eCLK. It is assumed that the resolution time of the coarse delay adjustment circuit 111 is 1 ns, the delay time of the dummy delay circuit 200 is 2 ns, and the delay time range that can be set in the fine delay adjustment circuit 101 is 1.0 ns to 3.0 ns. .
[0039]
The clock signal dCLK is a signal independent of the output clock signal iCLK. Therefore, even when the delay circuit selected in the delay fine adjustment circuit 101 changes, such a change does not affect the phase relationship between the input clock signal eCLK and the clock signal dCLK in the coarse delay adjustment circuit 111. The phase of the clock signal dCLK remains 0.3 ns behind the phase of the input clock signal eCLK.
[0040]
The output of the coarse delay adjustment circuit 111 is supplied to the fine delay adjustment circuit 101 as a clock signal fCLK. The output of the delay fine adjustment circuit 101 is output as an output clock signal iCLK via the driver circuit 106.
[0041]
As shown in FIG. 3, the phase of the clock signal fCLK leads the phase of the clock signal dCLK by 2 ns. This is because the delay time of the dummy delay circuit 200 is set to 2 ns.
[0042]
It can be seen that in order to make the phase of the output clock signal iCLK coincide with the phase of the input clock signal eCLK, as shown in FIG. 3, the clock signal fCLK should be delayed by 1.7 ns.
[0043]
The delay fine adjustment circuit 101 has a delay time range that can be set from 1.0 ns to 3.0 ns in increments of 0.1 ns. Therefore, by setting the delay time of the delay fine adjustment circuit 101 to 1.7 ns, it becomes possible to make the phase of the output clock signal iCLK coincide with the phase of the input clock signal eCLK.
[0044]
As described above, the state of the delay fine adjustment circuit 101 is monitored by the monitor circuit 300. If the range of the delay time that can be set in the fine delay adjustment circuit 101 is wider than the decomposition time of the coarse delay adjustment circuit 111, the delay fine adjustment circuit can be set without resetting the delay time of the coarse delay adjustment circuit 111. By adjusting the delay time of 101, the chance of performing the phase adjustment increases. This is because, even when the phase difference between the input clock signal eCLK and the clock signal dCLK is detected, the phase difference may be able to be adjusted by the delay fine adjustment circuit 101. As described above, by adjusting the delay time of the delay fine adjustment circuit 101 without resetting the delay time of the coarse delay adjustment circuit 111, it is possible to prevent an oscillation operation in which the phase greatly fluctuates. Further, the number of times of resetting the delay time of the coarse delay adjustment circuit 111 can be reduced.
[0045]
FIG. 4A shows the state of the delay coarse adjustment circuit 111 and the state of the delay fine adjustment circuit 101 when the range of the delay time that can be set in the delay fine adjustment circuit 101 is wider than the decomposition time of the coarse delay adjustment circuit 111. Indicates the status.
[0046]
The decomposition time of the coarse delay adjustment circuit 111 is t_dAnd The delay time of the coarse delay adjustment circuit 111 is Nt_dAnd the delay time of the delay fine adjustment circuit 101 is set to the lower limit value of the variable region (for example, t_d) Is defined as a first state. If it is necessary to reduce the delay time of the phase adjustment circuit 100 from the first state, the range of the delay time that can be adjusted by the delay fine adjustment circuit 101 is exceeded. In this case, the delay time of the coarse delay adjustment circuit 111 is (N-1) t_d, And accordingly, the delay time of the delay fine adjustment circuit 101 is also reset. At this time, the delay time set in the delay fine adjustment circuit 101 gradually increases from the lower limit value of the variable region and stabilizes when the predetermined delay time is reached. A stable state after resetting the delay time of the coarse delay adjustment circuit 111 and the delay time of the fine delay adjustment circuit 101 is defined as a second state.
[0047]
Once the transition from the first state to the second state occurs, even if the delay time of the phase adjustment circuit 100 needs to be changed, if the amount of the change is small, the state changes from the second state to the first state. Without returning, by adjusting the delay time of the delay fine adjustment circuit 101, the variation can be compensated. In this case, there is no need to reset the delay time of the coarse delay adjustment circuit 111. Thus, an unstable operation such as a transition from the second state to the first state immediately after the transition from the first state to the second state does not occur.
[0048]
Note that, when a transition from the first state to the second state or a transition from the second state to the first state occurs, the delay fine adjustment circuit 101 is reset, whereby the phase comparator 104 is reset. Can reduce the number of phase comparisons. For example, when the transition from the first state to the second state occurs, the delay time of the delay fine adjustment circuit 101 can be set in the delay fine adjustment circuit 101 as shown in FIG. The delay time (variable area) is reset substantially at the center. By resetting the delay time of the delay fine adjustment circuit 101 in this way, the delay time of the phase adjustment circuit 100 at the time of transition from the first state to the second state hardly fluctuates. This makes it possible for the output clock signal iCLK to quickly follow the input clock signal eCLK. As a result, the phase relationship between the input clock signal eCLK and the output clock signal is adjusted at high speed.
[0049]
Further, by setting the variable range of the delay time of the delay fine adjustment circuit 101 wide, it is possible to make the delay fine adjustment circuit 101 less likely to overflow. As a result, resetting of the delay time of the coarse delay adjustment circuit 111 can be made more difficult. As a result, the number of times of resetting the delay time of the coarse delay adjustment circuit 111 can be reduced.
[0050]
In the first embodiment, the case where the phase of the input clock signal eCLK matches the phase of the output clock signal iCLK is described as an example. However, the target of the phase adjustment by the phase adjustment circuit 100 of the present invention is limited to the clock signal. It is not done. The phase adjustment circuit 100 of the present invention can operate to output an output signal having a predetermined phase relationship with an arbitrary input signal.
[0051]
(Embodiment 2)
FIG. 5 shows a configuration of a phase adjustment circuit 400 according to the second embodiment of the present invention. 5, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.
[0052]
The reference signal Ref is input to the phase adjustment circuit 400. The phase comparator 104 compares the phase of the reference signal Ref with the phase of the output signal OUT, and outputs an output signal indicating the result of the comparison. The phase comparator 114 compares the phase of the reference signal Ref with the phase of the signal dD, and outputs an output signal indicating the result of the comparison.
[0053]
FIG. 6 shows a configuration of a semiconductor integrated circuit 600 including a phase adjustment circuit 400a and a phase adjustment circuit 400b. The phase adjustment circuit 400a and the phase adjustment circuit 400b have the same configuration as the phase adjustment circuit 400 shown in FIG.
[0054]
Input data eD0 supplied from outside the semiconductor integrated circuit 600 is input to the phase adjustment circuit 400a. Input data eD1 supplied from outside the semiconductor integrated circuit 600 is input to the phase adjustment circuit 400b.
[0055]
A skew due to a shape may occur between input data eD0 and input data eD1 supplied from outside the semiconductor integrated circuit 600. The skew due to the shape is caused by, for example, a difference in line length of a transmission line such as a cable or a connector, a difference in line load, or the like. When the data transmission speed is low, such skew can be ignored. However, as the data transmission speed increases, such skew needs to be corrected. The phase adjustment circuits 400a and 400b shown in FIG. 6 are used to correct a skew generated between the input data eD0 and the input data eD1.
[0056]
Changes in the potentials of the input data eD0 and eD1 do not occur at a constant rate. Therefore, a calibration cycle in which the potentials of the input data eD0 and eD1 change periodically is provided before the actual data is transmitted. In the calibration cycle, the delay time of the delay coarse adjustment circuit 111 and the delay time of the delay fine adjustment circuit 101 in the phase adjustment circuit 400a are set with respect to the input data eD0, and the delay in the phase adjustment circuit 400b with respect to the input data eD1. The delay time of the coarse adjustment circuit 111 and the delay time of the fine delay adjustment circuit 101 are set. Thereby, it is possible to correct a skew caused by a shape that does not change with time.
[0057]
By using the phase adjustment circuits 400a and 400b, the latency required to correct the skew can be reduced as compared with the method described in JP-A-10-276074.
[0058]
FIG. 7 illustrates how the latency required to correct the skew is reduced by the phase adjustment circuit 400a.
[0059]
According to the phase adjustment circuit 400a, the minimum value of the delay time that can be set in the delay fine adjustment circuit 101 is (t_d+ T_s). Where t_dRepresents the minimum value of the delay time that can be set in the delay circuit 102, and t_sIndicates a delay time generated in the selection circuit 103. The minimum value of the delay time that can be set in the coarse delay adjustment circuit 111 is 0 s, and the delay time of the driver circuit 106 is t._tThen, the time difference between the input data eD0 and the output data iD0 is (t_d+ T_s+ T_t). t_d= 200ps, t_s= T_tAssuming that = 100 ps, when the data rate is 2.5 Gbps or less, the latency generated for performing the skew correction is one cycle.
[0060]
On the other hand, according to the delay fine-adjustment circuit described in Japanese Patent Application Laid-Open No._d, The minimum delay time that can be set in the delay fine adjustment circuit is 10 t_dBecome. As a result, the time difference between the input data eD0 and the output data iD0 is (10t)_d+ T_s+ T_t). For data transmission at a data rate of 2.5 Mbps, the latency caused by performing skew correction is considerably large at 6 cycles. The upper limit of the data rate at which the skew correction can be performed within a latency of one cycle is 450 Mbps. As described above, the delay fine adjustment circuit described in the above publication cannot cope with ultra-high-speed and low-latency data transmission.
[0061]
【The invention's effect】
According to the present invention, it is possible to provide a variable delay circuit in which the lower limit of the settable delay time does not change regardless of the range of the settable delay time and the accuracy of the decomposition time.
[0062]
Further, according to the present invention, it is possible to provide a phase adjustment circuit capable of matching phases with low latency and high accuracy.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a variable delay circuit 101 according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a phase adjustment circuit 100 using the variable delay circuit 101 shown in FIG.
FIG. 3 is a diagram illustrating a phase relationship between clock signals.
FIGS. 4A and 4B are diagrams illustrating a state of a coarse delay adjustment circuit 111 and a state of a fine delay adjustment circuit 101. FIGS.
FIG. 5 is a diagram showing a configuration of a phase adjustment circuit 400 according to Embodiment 2 of the present invention.
FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit 600 including a phase adjustment circuit 400a and a phase adjustment circuit 400b.
FIG. 7 is a diagram illustrating a manner in which a latency required for correcting a skew is reduced by a phase adjustment circuit 400a.
[Explanation of symbols]
100 Phase adjustment circuit
101 Variable adjustment circuit (fine delay adjustment circuit)
102-1 to 102-n delay circuit
103 selection circuit
104 phase comparator
105 control circuit
106 Driver circuit
111 coarse delay adjustment circuit
112 delay circuit
113 Delay control circuit
114 Phase comparator
115 control circuit
116 Dummy driver circuit
200 Dummy delay circuit
300 monitor circuit
400, 400a, 400b phase adjustment circuit
600 Semiconductor Integrated Circuit

Claims (3)

A first variable delay circuit for delaying an input signal;
A second variable delay circuit capable of controlling a delay time with higher accuracy than the first variable delay circuit;
A control circuit that variably controls a delay time of the first variable delay circuit and a delay time of the second variable delay circuit,
A phase adjustment circuit that outputs an output signal having a predetermined phase relationship with respect to the input signal by delaying an output of the first variable delay circuit by the second variable delay circuit,
The second variable delay circuit includes:
A plurality of delay circuits for delaying the output of the first variable delay circuit;
A selection circuit that selects one of the outputs of the plurality of delay circuits according to a selection signal and outputs the selected output as the output signal;
The plurality of delay circuits are a first delay circuit that delays an output of the first variable delay circuit by a first delay time, and an output of the first variable delay circuit is longer than the first delay time. A second delay circuit that delays by a second delay time,
A phase adjustment circuit, wherein a difference between the first delay time and the second delay time is shorter than a minimum delay time that can be set in the first delay circuit. Wherein the decomposition time of the first variable delay circuit, the wider of the second variable delay of the delay time can be set in the circuit range, the phase adjustment circuit of claim 1. When the target delay time exceeds the range of the delay time that can be set in the second variable delay circuit, the control circuit resets the delay time of the first variable delay circuit, and resets the delay time of the second variable delay circuit. 2. The phase adjustment circuit according to claim 1 , wherein the delay time of the variable delay circuit is reset to substantially the center of the range of the delay time that can be set in the second variable delay circuit.

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