JP3558316B2 - Nonvolatile semiconductor memory device and erroneous write prevention method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and is particularly used for its write verification.
[0002]
[Prior art]
The write / verify operation of the conventional nonvolatile semiconductor memory device will be described in detail with reference to the drawings.
First, FIG. 8 shows a schematic diagram of a nonvolatile semiconductor memory device. However, this figure shows only the configuration necessary for the description. As shown in FIG. 8, the nonvolatile semiconductor memory device includes a memory cell block 992, a memory cell array, bit lines BL1 to BLn, word lines WL1 to WLm, a sense latch circuit 995, verify signal lines LSEN1 and LSEN2, and verify. It comprises a detection circuit and a logic circuit 996.
[0003]
A large number of memory cell blocks 992 included in the memory cell array are connected to word lines Wlj (j is 1 to n) and bit lines BLk (k is 1 to m). Each bit line BLk is connected to a verify signal line LSEN1 or LSEN2 via a sense / latch circuit 995, and the verify signal lines LSEN1 and LSEN2 are connected to a logic circuit 996.
[0004]
FIG. 9 shows a detailed view of the bit lines BL2 and BL3 in the schematic diagram of the nonvolatile semiconductor memory device shown in FIG. As shown in the figure, the sense and latch circuit 995 includes two inverters connected in anti-parallel and transistors ML1 to ML8.
[0005]
The node N1 is connected to the gate terminal of the transistor ML1, to the input / output line I / O line via the transistor ML7, and to the power supply voltage VDD via the transistors ML3 and ML4. The node N2 is connected to the bit line BL2 via the transistor ML6, and to the input / output line I / O via the transistor ML8. The bit line BL2 is connected to one end of a current path of a transistor ML9 for precharging the bit line BL2 to a precharge potential of about 3V. The gate terminal of the transistor ML3 is connected to the bit line BL2, and senses a change in the potential of the bit line BL2 during the verify operation. The transistors ML7 and ML8 are for outputting data read from the memory cell to the input / output line I / O, or for taking in data to be written to the memory cell from the input / output line I / O. Controlled by CSL. The bit line BL2 is connected to the transistor ML6, and connects and separates the bit line BL2 from the latch portion 997 including two inverters. The configuration of the other sense / latch circuits 995 is exactly the same as the above configuration.
[0006]
Next, a detailed view of the memory cell block 992 shown in FIG. 10 is shown. Also, here, a description will be given by taking a NAND type memory cell having eight memory cells as an example.
[0007]
As shown in the figure, the memory cell block 992 is configured by connecting current paths of eight memory cells MC11 to MC18 in series, and one end of each of them is connected to the bit line 1 via the selection transistor SGD1 and the other end thereof. Are connected to the power supply voltage VS via the selection transistor SGS1. The memory cells MC11 to MC18 and the select transistors SGD1, SGS1 are connected to word lines WL11 to WL18, WL1D, WL1S, respectively. Further, the other memory cell block 992 has exactly the same configuration, and the word line WLi1 is commonly connected to the memory cells MCi1 (i is 1 to 8) and the select transistors SGDi and SGSi (i is 1 to 8). Are provided with a common word line WLiD and a common word line WLiS.
[0008]
FIG. 11 is a sectional view of the NAND type memory cell 992 shown in FIG. 10 on a wafer.
As shown in the figure, a P-Well provided on an N-type substrate is provided, and memory cells MC11 to MC18 and select transistors SGS1, SGD1 are provided in the P-Well. Further, the diffusion layer n + used as a source or a drain is shared with an adjacent element.
[0009]
Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 9 will be described. First, the write operation will be described in detail.
First, the control signal CSL is set to a high level potential (hereinafter, referred to as H, for example, VDD) to turn on the transistors ML7 and KL8, so that data to be written to the memory cells in the memory cell block 992 is input / output lines I / I / O is latched by the latch circuit 997. For example, when writing data to a memory cell, a low-level potential (hereinafter, referred to as L, for example, 0 V) is applied to the node N2 of the latch circuit 997, and when not writing data to the memory cell, H is applied to the node N2 of the latch circuit 997. Latch.
[0010]
Next, the transistor ML6 is turned on by the signal PROG1, and the bit line BL2 is electrically connected to the node N2. The bit line BL2 is set to 0 V or a write inhibit potential (for example, 8 V) according to the potential (H or L) of the node N2. ) Is charged. Further, one word line is selected from a number of word lines by an address signal (not shown) (hereinafter, the selected word line is referred to as a selected word line), and the word line is set to a write voltage ( For example, charge to 20V).
[0011]
In addition, according to the potential of the node N2, it is determined whether data is written to a memory cell (hereinafter, referred to as a selected memory cell) in a memory block 992 located at an intersection of the selected word line and the bit line 2. You. That is, when the node N2 is at L, the potential of the control gate and the channel portion of the selected memory cell becomes 20V (20V-0V), so that data is written in the selected memory cell and the threshold voltage of the selected memory cell rises. I do. Further, when the node N2 is at H, the potential of the control gate and the channel portion of the selected memory cell becomes 10 V (20 V-10 V), so that no data is written in the selected memory cell, and the threshold voltage of the selected memory cell is It remains low and does not change. Next, the transistor ML6 is turned off to separate the node N2 from the bit line BL2.
[0012]
Next, a verify operation for determining whether data written in a memory cell is normal will be described.
With the high integration of the memory cell array, erroneous reading occurs due to capacitive coupling between adjacent bit lines. Therefore, it is necessary to shield every other bit line.
[0013]
BL2 is precharged to the precharge level (up to 3 V) by the signal PRE1, and at the same time, BL3 is dropped to the ground by the signal SHIELD2.
Also, the selected word line is applied to a verify potential (for example, 0.5 V). Further, the verify signal line LSEN1 is precharged to H (for example, VDD).
[0014]
If the selected memory cell is in a sufficient write state (normal write state), the threshold voltage of the selected memory cell is sufficiently increased, so that the selected memory cell does not turn on and the bit line BL2 remains H It is. In this case, since the potential of the bit line remains H, the transistor ML3 is turned on, and when the transistor ML4 is further turned on by the signal BLSEN1, the potential of the node N1 is forcibly inverted to the power supply voltage GND (L).
[0015]
Since the potential of the node N1 becomes L, the transistor ML1 is turned off. Therefore, the potential of the verify signal line LSEN1 remains at H, which is the precharge potential, and does not change.
[0016]
On the other hand, if the selected memory cell is in an insufficient write state (abnormal write state), the threshold voltage of the selected memory cell has not risen sufficiently, so that the selected memory cell turns on and the bit line BL2 goes from H level. Discharge to L. Therefore, the transistor ML3 is turned off, so that the potential of the node N1 remains at H.
[0017]
Since the potential of the node N1 remains at H, the transistor ML1 turns on. Further, since the transistor ML2 is turned on by the signal VERIFY1, the verify signal line LSEN1 is electrically connected to GND. As a result, the potential of the verify signal line LSEN1 is discharged from H, which is the precharge potential, to L.
[0018]
Also, the verify operation is not performed on the bit line connected to the memory cell in the write-protected state.
As described above, whether the memory cell in the written state is normal is detected by the verify detection circuit as a change in the potential of the verify signal line LSEN1 or LSEN2.
[0019]
That is, if all the memory cells are in the normal write state, the verify signal lines LSEN1 and LSEN2 are not discharged and remain at the precharge voltage of H.
[0020]
On the other hand, if there is at least one memory cell in which writing is insufficient, the verify signal line LSEN1 or LSEN2 is discharged, and its potential becomes L.
This result is detected by the verify detection circuit, and if it is determined that all the cells in the write state are in the normal write state, a series of the write / verify operation ends.
[0021]
On the other hand, if at least one of the memory cells has an abnormal write state, the write operation is performed again, and the process is repeated until all the memory cells are in the normal write state.
Next, the verify detection circuit will be described in more detail with reference to FIG.
[0022]
As shown, the verify detection circuit includes inverters I1 to I5 and transistors Tr1 to Tr4.
The signal input from the verify signal line LSENn (n is 1 or 2) is connected to the gate terminal of the transistor Tr2 via the inverter I1. The current paths of the transistors Tr2 to Tr4 are connected in series between the power supply voltage VDD and GND, and one end of a latch circuit composed of the anti-parallel connected inverters I2 and I3 is connected to the node N3. . A node N4 at the other end of the latch circuit is connected to the logic circuit 996 via inverters I4 and I5 connected in two stages.
[0023]
Next, the operation of the verify detection circuit will be described.
As described above, the potential of the verify signal line LSEN1 or LSEN2 is precharged to H, and thereafter the verify operation is performed.
[0024]
If all the cells in the write state are in a normal state, the verify signal line LSENn remains at H. At this time, when the transistor Tr2 is turned on and the transistor Tr3 is also turned on by the signal VRSEN, the node N3 is electrically connected to the power supply voltage VDD (H). Therefore, the potential of the node N3 changes from L to H. However, the node 3 is precharged to GND (L) by turning on Tr4 in advance.
[0025]
On the other hand, when one of the cells in the written state is insufficient, the verify signal line LSENn changes from H to L. At this time, since the transistor Tr2 is turned off, the potential of the node N3 remains at L. However, the node N3 is precharged to GND (L) by turning on Tr4 in advance.
[0026]
The potential of the node N3 is transmitted to the logic circuit 996 via the latch circuit and the inverters I4 and I5.
As described above, all the verification results for one page can be collectively detected by one operation.
[0027]
The normal verify operation is performed to detect whether or not the data of the memory cell in the written state is normal. Therefore, as described above, the verify operation is not performed on the memory cells in the write-inhibited state.
[0028]
In practice, for a write-inhibited cell, the potential difference between the control gate and the channel of the memory cell is reduced to reduce the write speed and prevent data from being written. However, actually, only the writing speed is reduced, so that data may be erroneously written to the write-inhibited cell.
[0029]
Conventionally, a circuit for detecting erroneous writing is provided outside or inside the nonvolatile semiconductor memory device, and erroneous writing is corrected by using an error correcting code ECC (Error Correcting Code) or the like.
[0030]
[Problems to be solved by the invention]
As described above, in the conventional nonvolatile semiconductor memory device, when data is erroneously written in the write-inhibited cell, it cannot be detected by the conventional verify operation. Therefore, a circuit for detecting this write error is required.
[0031]
The present invention has been made in view of the above problems, and has as its object to provide a nonvolatile semiconductor memory device capable of verifying not only a write bit but also erroneous write of a write inhibit bit.
[0032]
[Means for Solving the Problems]
In order to achieve the above object, the present invention relates to a method in which a sense latch circuit connected to one end of a predetermined bit line (this bit line is referred to as a bit line a) has a predetermined memory cell connected to the bit line. When latching data to be written to a bit line, a sense / latch circuit connected to one end of a bit line which is different from the bit line and which does not participate in writing (this bit line is referred to as a bit line b) is detected. Latch the data for
[0033]
The nonvolatile semiconductor memory device according to the present invention has an erroneous write verify operation different from the write verify operation, and senses and latches one end of a bit line a used for writing and a bit line b not used for writing. The circuit is connected via data changing means. Therefore, the non-volatile semiconductor memory device according to the present invention changes the data latched on the bit line b at the time of the above-mentioned erroneous write verify operation to the data changing means, and senses this change to determine whether there is an erroneous write. Can be detected.
Since the present invention is configured as described above, it is possible to detect an erroneous write of a write-inhibited cell.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic view of a nonvolatile semiconductor memory device according to the present invention.
As shown in FIG. 1, the nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cell blocks 992, sense and latch circuits 1 and 2, data changing means 1 and 2, bit lines m and n, verify circuits 1 and 2, logic gates 3 and 4, and verify signal lines LSEN1 and LSEN2.
[0035]
The sense / latch circuit 1 connected to one end of the bit line m holds data to be written or read in a predetermined memory cell in a predetermined memory cell block 992 connected to the bit line m. belongs to. Also, a sense / latch circuit is connected to one end of the bit line n arranged next to the bit line.
[0036]
Data conversion means 2 and 1 are connected to the other ends of the bit lines m and n, respectively, and these data conversion means 2 and 1 are connected to the sense and latch circuits 2 and 1, respectively.
[0037]
The sense / latch circuits 1 and 2 are connected to verify detection circuits 1 and 2 via verify signal lines LSEN1 and LSEN2, respectively, and the verify detection circuits 1 and 2 are connected to logic gates 3 and 4, respectively.
[0038]
Next, FIG. 2 shows a detailed circuit diagram of the nonvolatile semiconductor memory device shown in FIG. As shown in FIG. 2, the sense and latch circuit 1 includes transistors ML1 to ML4, ML6 to ML8, and a latch portion 10 in which two inverters are connected in anti-parallel. The same applies to the sense latch 2.
[0039]
The latch portion 10 is connected to the bit line m via the transistor ML6 and to the input / output line I / O via the transistors ML7 and ML8. The node NL1 of the latch portion 10 is connected to the power supply voltage GND via the transistors ML3 and ML4, and is connected to the gate terminal of the transistor ML1. One end of the current path of the transistor ML2 limited by the signal VERIFY1 is connected to the verify signal line LSEN1, and the other end is connected to the power supply voltage GND via the transistor ML1.
[0040]
The data conversion means 1 includes two transistors ML9 and ML10 whose current paths are connected in series.
FIG. 9 shows a detailed diagram of the verify detection circuit, and FIGS. 10 and 11 show detailed diagrams of the memory cell block 992.
[0041]
Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 2 will be described.
First, a write operation for writing data to a memory cell included in a predetermined memory cell block 992 connected to the bit line m will be described.
[0042]
First, the transistors ML7 and ML8 are turned on by the signal CSL, and predetermined data to be written to the memory cell is taken in from the input / output line I / O to the latch portion 10.
[0043]
For example, when data is to be written to a target memory cell, the high voltage level H (hereinafter simply referred to as H) is applied to the node NL1 of the latch portion 10, and the low voltage level L (hereinafter simply referred to as L) is applied to the node NL2. Is held.
[0044]
If data is not to be written to the target memory cell, L is held at the node NL1 and H is held at the node NL2 of the latch portion 10.
At this time, the latch portion 20 connected to one end of the bit line n holds inverted data of the data latched by the latch portion 10. For example, as follows.
When the node NL1 = L and the node NL2 = H, the node NR1 = H, the node NR = L, the node NL1 = H, and the node NL2 = L, the node NR1 = L and the node NR = H. By doing so, the bit line m is connected to the node NL2. As described above, whether data is written to a predetermined memory cell is determined in accordance with the data held in node NL2.
[0045]
That is, when the potential held at the node NL2 is L, data is written to a predetermined memory cell, and the memory cell enters a write state. When the potential held at the node N2 is H, data is not written in a predetermined memory cell. This is called a write-protected state.
[0046]
Thereafter, when a predetermined memory cell is in a write state, a write verify operation is performed to check whether the written data is normal. If it is determined by this write verify operation that writing is normal, a series of write and write verify operations ends.
[0047]
When it is determined that the writing is abnormal, the writing operation is performed again. Thereafter, a write verify operation is performed, and the operation is repeated until the write operation becomes normal.
After the normal write verify passes, an erroneous write verify operation is performed.
[0048]
When data is not written to a memory cell, this memory cell must be in a write-protected state. However, as described above, data may be erroneously written. Here, the erroneous write verify operation refers to an operation for determining whether a memory cell in a write-inhibited state is normally in a write-inhibited state. Therefore, the erroneous write verify operation has a different characteristic from the normal write verify operation for determining whether the data written in the memory cell is normal.
[0049]
Next, an erroneous write verify operation will be described.
First, the bit line m is precharged to H and then brought into a floating state, and a verify potential of 0 V for erroneous write verification is applied to a word line (selected word line) connected to a predetermined memory cell.
[0050]
When a predetermined memory cell is in a normal write-inhibited state, the threshold voltage of the memory cell is low because the memory cell is kept in the erased state. Therefore, since this memory cell is turned on even at 0 V, the potential of the bit line m precharged to H is discharged to L.
[0051]
When a predetermined memory cell is in an abnormal writing state, that is, in a state where data is erroneously written, the threshold voltage of this memory cell is high. Therefore, since this memory cell does not turn ON, the potential of the bit line m precharged to H remains at H.
[0052]
The change in the potential of the bit line m described above is received by the transistor MR1 in the data conversion means 2. That is, when a predetermined memory cell is in a normal write state, the potential of the bit line m is discharged to L, and the transistor MR1 is turned on.
[0053]
On the other hand, when a predetermined memory cell is in an abnormal write state, that is, in an erroneous write state, the potential of the bit line m remains H, so that the transistor MR1 does not turn on.
[0054]
As described above, when it is not desired to write data into a predetermined memory cell, that is, when it is desired to set a predetermined memory cell in a write-protected state, in the latch portion 10, the nodes NL1 = L and NL2 = H are held. The latch section 20 holds the inverted data. That is, it should be noted that the nodes NR1 = H and NR2 = L are held in the latch section 20.
[0055]
At this time, the transistor MR2 is turned on by the signal DSENSE1. When the predetermined memory cell is in the normal write-inhibited state, the transistor MR1 is ON, so that the potential of the node NR1 in the latch portion 20 is inverted from H to L, and the potential of the node NR2 is inverted from L to H.
[0056]
When a predetermined memory cell is in an erroneous write state (abnormal write inhibit state), the transistor MR1 is OFF, so that the potential of the node NR2 in the latch portion 20 remains L.
[0057]
Next, when a predetermined memory cell is in a normal write-protected state, the potential of the node NR1 is L, so that the transistor MR3 is turned off.
Further, when a predetermined memory cell is in an erroneous write state (abnormal write inhibit state), the potential of the node NR1 is H, so that the transistor MR3 is turned on. At this time, when the transistor MR4 is turned on by the signal VERIFY2, the verify signal line LSEN2 is connected to GND, and the verify signal line LSEN2 precharged to H is discharged to L.
[0058]
The above is summarized as follows. In the erroneous write verify operation, the potential of the bit line is changed depending on whether the write state of a predetermined memory cell is normal. This change in the potential of the bit line is sensed by the data conversion means 2, and whether or not to discharge the verify signal line LSEN2 is determined according to the result.
[0059]
For example, when a predetermined memory cell is in a normal write-inhibited state, the nodes NR1 = L and NR2 = H, the potential of the verify signal line LSEN2 remains at H, and there is no change.
[0060]
When a predetermined memory cell is in an erroneous write state, the potential of the verify signal line LSEN2 decreases from H to L while the nodes NR1 = H and NR2 = L.
That is, if at least one of the memory cells in the write-inhibited state is in the erroneous write state, the potential of the verify signal line LSEN2 is discharged to L. The change in the potential makes it possible to detect whether or not a predetermined memory cell is in an erroneous write state.
[0061]
The result of the erroneous write verify is collectively detected by the verify signal line LSEN2, and is latched by the verify detecting circuit 2 in this case.
The erroneous write verify described above is performed on the memory cells in the write-inhibited state, and normal write verify is performed on all the memory cells in the write state.
[0062]
The results of the write verify operation and the erroneous write verify operation are sensed collectively by the verify signal line LSEN1 or LSEN2 and latched by the verify detection circuit 1 or 2.
[0063]
Then, the data latched in the verify detection circuits 1 and 2 are logically ANDed by the logic gates 3 and 4, and if both pass, a verify pass is output, and the erroneous write verify operation ends.
[0064]
Next, a second embodiment of the present invention is shown in FIG.
As shown in FIG. 3, different from the above embodiment, the data change means, the latch sense circuit, and the input / output line I / O are arranged between the memory cells on both sides.
[0065]
Next, FIG. 4 shows an inverted data generation circuit for generating inverted data when the data to be latched in the latch portion 10 and the inverted data are latched in the latch portion 20. As shown in FIG. 4, the inversion data generation circuit includes transfer gates TG1 to TG4 and inverters 1 to 3, and DataL is connected to A in FIG. 2 and DataR is connected to B in FIG.
[0066]
Next, the operation of the inverted data generation circuit will be described. When the signal Left is set to H, the signal Right is set to L, and the signal Data is set to H, the transfer gates TG1 and 3 are turned on, and the transfer gates TG2 and 4 are turned off. Therefore, DataL becomes H and DataR becomes L. Conversely, when the signal Left is L, the signal Right is H, and the signal Data is H,
DataL becomes L and DataR becomes H.
[0067]
Further, when erroneous write verification is performed on a memory cell connected to the bit line m, a bit line n different from the bit line m may be used, so that the bit line m and the bit line n are adjacent to each other. unnecessary.
[0068]
Further, in the above embodiment, the memory cell array has been described as a NAND type memory cell. However, the memory cell array may be a NOR type memory cell shown in FIG. 5, an AND type shown in FIG. 6, and a DINOR type memory cell shown in FIG. good.
[0069]
According to the present invention, by providing data conversion means in a memory cell, a memory cell in an erroneous write state can be detected.
In addition, the erroneous write verify operation described above only adds a data conversion means composed of two transistors, compared to the conventional circuit, and thus does not greatly increase the occupied area.
[0070]
In addition, although the power supply voltage VDD is required for the data conversion means, no through current flows, so that even if the data conversion means is added to the nonvolatile semiconductor memory device, there is no increase in power consumption.
Further, since the added data conversion means is constituted by the same MOS transistor as the memory cell, the manufacturing process does not become complicated.
[0071]
【The invention's effect】
Since the present invention is configured as described above, erroneous write verification can be performed, and power consumption is not increased, the manufacturing process is not complicated, and the occupied area is not significantly increased.
[Brief description of the drawings]
FIG. 1 is a schematic circuit diagram of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a detailed circuit diagram of the first embodiment according to the present invention.
FIG. 3 is a detailed circuit diagram of the first embodiment according to the present invention.
FIG. 4 is a detailed circuit diagram of an inverted data generation circuit.
FIG. 5 is a diagram showing a NOR type memory cell array.
FIG. 6 is a diagram showing an AND type memory cell array.
FIG. 7 is a diagram showing a DINOR type memory cell array.
FIG. 8 is a schematic circuit diagram of a conventional nonvolatile semiconductor memory device.
FIG. 9 is a detailed circuit diagram of a conventional nonvolatile semiconductor memory device.
FIG. 10 is a diagram showing a NAND type memory cell array.
FIG. 11 is a sectional view of a NAND memory cell array.
FIG. 12 is a detailed diagram of a verify detection circuit.
[Explanation of symbols]
992 memory cell block
ML1 to ML10, MR1 to MR4 transistors
10, 20 Latch part
3, 4 logic gate
LSEN1, LSEN2 verify signal line
I / O input / output line

Claims (10)

In a nonvolatile semiconductor memory device,
A memory cell array having a plurality of memory cells having a floating gate,
A first bit line connected to a first memory cell in the memory cell array;
A second bit line connected to a second memory cell in the memory cell array;
First latch means connected to one end of the first bit line, for latching data to be written to the first memory cell or data read from the first memory cell;
Data changing means connected between the first latch means and one end of the second bit line, for changing data latched by the first latch means,
A non-volatile semiconductor memory device that has the function of detecting and preventing erroneous writing. A memory cell array having a plurality of memory cells, a first bit line connected to a first memory cell in the memory cell array, and a second bit line connected to a second memory cell in the memory cell array And a first latch connected to one end of the first bit line for latching data for writing to the first memory cell or data read from the first memory cell. And a non-volatile semiconductor storage device having
Data changing means connected between the first latch means and one end of the second bit line, for changing data latched by the first latch means,
A non-volatile semiconductor memory device that has the function of detecting and preventing erroneous writing. A memory cell array having a plurality of memory cells having a charge storage layer;
A plurality of word lines connected to the memory cells for selecting the predetermined memory cells;
A first bit line connected to a first memory cell in the memory cell array and transferring data for writing to the memory cell or data read from the memory cell;
Connected to a second memory cell in the memory cell array, and adjacent to the first bit line, for transferring data for writing to the memory cell or transferring data read from the memory cell; A second bit line,
First latch means connected to one end of the first bit line, for latching data to be written to the first memory cell or data read from the first memory cell;
A second latch unit connected to one end of the second bit line, for latching data to be written to the second memory cell or data read from the second memory cell;
The data latched by the first latch means is connected between the first latch means and the other end of the second bit line, and changes the data latched by the first latch means according to the written data of the second memory cell. Data change means for causing
First verify detection means connected to the first latch means for detecting whether data written to the first memory cell is normal or abnormal;
And second verify detecting means connected to the second latch means for detecting whether data written to the second memory cell is normal or abnormal. Non-volatile semiconductor storage device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said data changing means comprises two MOS transistors whose current paths are connected in series. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said latch means is configured by connecting two inverters in anti-parallel. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell array constitutes a NAND memory cell in which current paths of a plurality of memory cell arrays are connected in series. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell array forms an AND type memory cell. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell array forms a DINOR type memory cell. A first data latch operation for holding data as to whether or not to write to a memory cell connected to the first bit line, in first latch means connected to one end of the first bit line;
A second data latch operation for holding data corresponding to the data latched by the first latch means in a second latch means connected to one end of a second bit line;
A data write operation for writing data to the memory cell according to the data held in the first latch means;
When the data held in the first latch unit is write-inhibited data for inhibiting data writing to the memory cell, the memory cell is stored in the second latch unit in accordance with the data held in the second latch unit. An incorrect write verify operation for detecting whether the is in a normal write-inhibited state or an erroneous write state in which writing has been performed erroneously;
A method for preventing erroneous writing in a nonvolatile semiconductor memory device, comprising: A first data latch operation for holding data as to whether or not to write to a memory cell connected to the first bit line, in first latch means connected to one end of the first bit line;
A second data latch operation for holding inverted data of the data latched by the first latch means in a second latch means connected to one end of a second bit line;
A data write operation for writing to the memory cell according to the data held in the first latch means;
In the case where the data held in the first latch unit is write-inhibited data for inhibiting writing to the memory cell, but the data is written to the memory cell, the second latch unit Erroneous write verify operation for detecting that the memory cell is in an erroneous write state by inverting the data held in
A method for preventing erroneous writing in a nonvolatile semiconductor memory device, comprising:

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