JP3547585B2 - Microprocessor having conditional execution instruction - Google Patents

Description

【００５２】

【００５３】

【００５４】

reserved
【００５５】

【００５６】

【００５７】

【００５８】

【００５９】

【００６０】

【００６１】

【００６２】

【００６３】
図８は、図１に示したこの発明における条件実行命令を有するマイクロプロセッサ１の並列２命令実行時のパイプライン動作を示す説明図である。
この動作は、命令のフォーマットフィールドの値ＦＭ＝００のときに実行される。パイプライン１９０、１９５は、ＩＦステージ１９１、Ｄ／Ａステージ１９２、Ｅ／Ｍステージ１９３、Ｗステージ１９４で構成される。並列２命令実行時には、メモリアクセスユニット３での実行１９０と整数演算ユニット４での実行１９５が並列に行われる。
【００６４】
図９は、図１に示したこの発明における条件実行命令を有するマイクロプロセッサのパイプライン動作を示す説明図であり、図において、各ステージはクロックに同期しており、クロックのＨｉｇｈの期間とＬｏｗの期間により、２つの期間に分割される。
【００６５】
ＩＦステージのクロックがＨｉｇｈのときがＩ１期間、ＬｏｗのときがＩ２期間、Ｄ／ＡステージのクロックがＨｉｇｈのときがＤ１期間、ＬｏｗのときがＤ２期間、Ｅ／ＭステージのクロックがＨｉｇｈのときがＥ１期間、ＬｏｗのときがＥ２期間、ＩＦステージのクロックがＨｉｇｈのときがＷ１期間、ＬｏｗのときがＷ２期間である。
【００６６】
ＩＦステージでは命令のフェッチを行い、Ｄ／ＡステージではＤ１期間内に命令のデコード及び汎用レジスタのリードを行い、Ｄ２期間内にメモリのアドレス計算を行う。Ｅ／ＭステージとＷステージのＷ１期間では演算の実行及びメモリのアクセスを行い、ＷステージのＷ２期間にて汎用レジスタへの書き込みを行う。
【００６７】
図１０は、マイクロプロセッサ１においてデータ干渉が起こる場合のプログラム例である。データ干渉については後述する。
【００６８】
図において、ＡＤＤ命令は、第２オペランド及び第３オペランドで指定される汎用レジスタの値を加算し、演算結果を第１オペランドで指定される汎用レジスタに書き込む命令である。ＡＤＤ命令２００では、汎用レジスタＲ２の値及び汎用レジスタＲ３の値が加算され、その加算結果が、汎用レジスタＲ４に書き込まれる。
【００６９】
ＡＤＤ命令２１０では、汎用レジスタＲ１０の値及び汎用レジスタＲ４の値が加算され、その加算結果が、汎用レジスタＲ１１内に書き込まれる。ＡＤＤ命令２１０において、汎用レジスタＲ４の値は、ＡＤＤ命令２００の加算結果と等しい。
【００７０】
ＡＤＤ命令２００において、汎用レジスタＲ４への加算結果の書き込みは、Ｗ２期間内に行われるために、ＡＤＤ命令２１０のＤ２期間では、この汎用レジスタＲ４への加算結果の書き込みはまだ終っていないため、ＡＤＤ命令２１０のＤ１期間で読み出した汎用レジスタＲ４の値は、演算に使用することができない。このような状況をデータ干渉と呼ぶ。データ干渉が起こる状況では、ＡＤＤ命令２００の加算結果を、汎用レジスタＲ４を経由せずに専用のデータ転送経路（バイパス経路）を介してＡＤＤ命令２１０のＤ２期間に渡す制御を行う。
【００７１】
図１１は、図１０のプログラムを実行したときのパイプラインの動作を示した説明図であり、図において、２２０は命令２００に対応したパイプライン、２３０は命令２１０に対応したパイプラインである。パイプライン２２０とパイプライン２３０で同じ列にあるステージがそれぞれ同時に実行されることを示している。図１１内の矢印が示すように、パイプライン２２０のＥ２期間からパイプライン２３０のＤ２期間に加算結果をバイパス経路を介して渡すことにより、パイプラインを乱さずに命令の実行を行う。
【００７２】
図１２は、図１０に示すプログラムを実行するときのマイクロプロセッサ１の動作を説明するためのブロック図であり、図１に示すマイクロプロセッサ１のブロック図と同一の参照番号を用いている。即ち、ＡＬＵ１５、汎用レジスタ５、メモリアクセスユニット３、ＭＵデコーダ８は、図１に示したものと同一構成要素である。
【００７３】
メモリアクセスユニット３において、２４０はＤ２バスに出力されたデータをＥ１期間内に取り込み、取り込んだデータをＡＬＵ１５に出力するＥ１レジスタ、２４１は、ＡＬＵ１５からの出力データをＥ１バスを介してＥ２期間内に取り込み、取り込んだデータをＥ２バスに出力するとともに、レジスタ出力制御部２５２から出力される制御信号に従って取り込んだデータをバイパス経路Ｂ０を経由してＤ２バスへ出力するＥ２レジスタ、２４２は汎用レジスタ５の出力をＳ２バスを介してＤ２期間内に取り込み、レジスタ出力制御部２５２の出力に従って取り込んだデータをデータ経路Ｄ０を経由してＤ２バスへ出力するＤ２レジスタ、２４３はＥ２レジスタ２４１の出力をＥ２バスを介してＷ１期間内に取り込み、取り込んだデータをＷ１バスに出力するＷ１レジスタである。
【００７４】
ＭＵデコーダ８において、２５０はバイパス制御を行うバイパス制御部、２６０は条件実行命令における制御を行う条件実行制御部である。
【００７５】
バイパス制御部２５０において、２５１はデータ干渉が起こっているか否かを判定するバイパス判定部、２５２はバイパス判定部の判定結果および条件実行判定部２６１の判定結果に従って、Ｅ２レジスタ２４１およびＤ２レジスタ２４２にＤ２バスへの出力を制御する信号を出力するレジスタ出力制御部である。
【００７６】
条件実行制御部２６０において、２６１は条件実行命令が有効であるか無効であるかを判定する条件実行判定部、２６２は条件実行判定部２６１の判定結果に従って、汎用レジスタ５への書き込みを制御する信号を出力する汎用レジスタ書き込み制御部である。
【００７７】
図１３は、条件実行判定部２６１を示すブロック図であり、図において、２７０は図２における実行条件フィールド１０５と同じものである。２７１は図７におけるＦ０フラグ１８１およびＦ１フラグ１８２と同じものである。２７２は実行条件フィールド２７０に設定されている条件をデコードし実行コントロールフラグ２７１に設定されている条件と合致しているか否かを判断するデコーダである。
【００７８】
次に動作について説明する。
先ず、図１０に示すプログラムを実施の形態１の条件実行命令を有するマイクロプロセッサ１が実行したときの動作について説明する。
【００７９】
図１０に示すプログラム内の命令２００が実行され得られる加算結果は、ＡＬＵ１５から出力され、Ｅ１バスを介して、命令２００のＥ２期間内にＥ２レジスタ２４１に格納される。Ｅ２レジスタ２４１からの出力は、Ｅ２バスを介して命令２００のＷ１期間内にＷ１レジスタ２４３に格納される。
【００８０】
命令２００の実行の場合には、実行条件フィールド２７０はＣＣ＝０００の値を持ち、前に述べたように実行コントロールフラグ２７１の値によらずいつでも当該命令は有効である。従って、条件実行判定部２６１は、当該命令が有効であると判定し判定結果を汎用レジスタ書き込み制御部２６２およびレジスタ出力制御部２５２に出力する。汎用レジスタ書き込み制御部２６２は、条件実行判定部２６１の判定結果に従って書き込むことを許可する制御信号を汎用レジスタへ出力する。
【００８１】
Ｗ１レジスタ２４３に格納されたデータは、汎用レジスタ書き込み制御部２６２の制御信号に従って、Ｗ１バスを介して汎用レジスタ内に、命令２００のＷ２期間内に書き込まれる。命令２１０においてＲ４のデータは、汎用レジスタ５からＳ２バスを介して命令２１０のＤ２期間内にＤ２レジスタ２４２に取り込まれる。
【００８２】
バイパス判定部２５１は、命令２１０がデータ干渉を起こしていると判定し、判定結果をレジスタ出力制御部２５２へ出力する。レジスタ出力制御部２５２は、バイパス判定部２５１の判定結果に従って、命令２００の加算結果を保持しているＥ２レジスタ２４１に、Ｄ２バスへの出力を許可することを意味する制御信号を出力し、汎用レジスタ５のデータを保持するＤ２レジスタ２４２にＤ２バスへの出力を許可しないことを意味する制御信号を出力する。
【００８３】
Ｅ２レジスタ２４１は、レジスタ出力制御部２５２の制御信号に従って保持したデータのＤ２バスへの出力を行う。一方、Ｄ２レジスタ２４２は、レジスタ出力制御部２５２の制御信号に従って保持したデータのＤ２バスへの出力を行わない。Ｅ１レジスタ２４０は、Ｅ２レジスタ２４１からの出力データをＤ２バスを介して命令２１０のＥ１期間内に取り込み、取り込まれたデータをＡＬＵ１５へ出力する。ＡＬＵ１５は、Ｅ１レジスタ２４０からの出力データをもとに命令２１０の加算演算を行う。
【００８４】
次に、図１０に示すプログラム内の命令２００が条件実行命令であった場合の実施の形態１の条件実行命令を有するマイクロプロセッサ１の動作について説明する。
【００８５】
図１４は、図１０に示すプログラム内の命令２００が、条件実行命令である場合のデータ干渉の発生を示す説明図である。図において、命令２８０は条件実行命令であり、命令に／ＴＸが記述されているため、前述したように実行コントロールフラグＦ０が１のとき命令２８０は有効になり、実行コントロールフラグＦ０が０のとき命令２８０は無効となる。実行コントロールフラグＦ１の値は考慮されない。
【００８６】
命令２８０が有効のときには、命令２９１の汎用レジスタＲ４の値は、命令２８０の加算結果と一致し、命令２８０が無効のときは、命令２９１の汎用レジスタＲ４の値は、命令２８０を実行する以前の値と一致する。図１４に示す命令２８０の加算結果は、ＡＬＵ１５から出力され、Ｅ１バスを介して命令２００のＥ２期間内にＥ２レジスタ２４１内に格納される。Ｅ２レジスタ２４１からの出力は、Ｅ２バスを介して命令２８０のＷ１期間内にＷ１レジスタ２４３内に格納される。
【００８７】
命令２８０の場合には、実行条件フィールド２７０はＣＣ＝００１の値を持ち、条件実行判定部２６１は、実行コントロールフラグ２７１のＦ０フラグが１のとき命令２８０は有効であると判定し、Ｆ０フラグが０のとき命令２８０は無効であると判定し、判定結果を汎用レジスタ書き込み制御部２６２に出力するとともに、レジスタ出力制御部２５２に出力する。
【００８８】
まず、命令２８０が有効であった場合、マイクロプロセッサ１が図１０に示すプログラムを実行したときと同じ動作を行う。
次に、命令２８０が無効であったときの動作を説明する。
汎用レジスタ書き込み制御部２６２は、条件実行判定部２６１の判定結果に従って、書き込むことを許可しないことを指示する制御信号を汎用レジスタ５に対して出力する。Ｗ１レジスタ２４３内に格納されたデータは、汎用レジスタ書き込み制御部２６２の制御信号に従い、汎用レジスタ５への書き込みは行われない。命令２９０においてＲ４のデータは、汎用レジスタ５からＳ２バスを介して命令２９０のＤ２期間内にＤ２レジスタ２４２内に取り込まれる。
【００８９】
バイパス判定部２５１は、命令２１０がデータ干渉を起こしていると判定し、判定結果をレジスタ出力制御部２５２へ出力する。レジスタ出力制御部２５２は、条件実行判定部２６１の判定結果に従って、バイパス判定部２５１の判定結果によらず、Ｅ２レジスタ２４１に対してバイパス経路Ｂ０を経由して行われるＤ２バスへの出力を許可しないことを意味する制御信号を出力する。さらに、レジスタ出力制御部２５２は、汎用レジスタ５のデータを保持するＤ２レジスタ２４２に、データ経路Ｄ０を経由したＤ２バスへのデータ出力を許可することを指示する制御信号を出力する。Ｅ２レジスタ２４１は、レジスタ出力制御部２５２から送信される制御信号に従って、保持したデータのバイパス経路Ｂ０を経由して行われるＤ２バスへの出力を実行しない。
【００９０】
一方、Ｄ２レジスタ２４２は、レジスタ出力制御部２５２の制御信号に従って保持したデータのＤ２バスへの出力を行う。Ｅ１レジスタ２４０は、Ｅ２レジスタからの出力データをＤ２バスを介して命令２１０のＥ１期間内に取り込み、取り込まれたデータをＡＬＵ１５へ出力する。ＡＬＵ１５は、Ｅ１レジスタからの出力データをもとに命令２８０の加算演算を行う。
【００９１】
以上のように、この実施の形態１によれば、条件実行命令を含む命令のパイプライン間でデータ干渉が発生しているか否かを判定し、バイパス判定部２５１での判定結果に基づいて行われるレジスタ出力制御部２５２の出力を、実行条件制御部２６０内の条件実行判定部２６１での判定結果に従って制御し、バイパス経路Ｂ０やデータ経路Ｄ０を介したデータ転送を制御するようにしたので、条件実行命令を実行するパイプラインにおいてデータ干渉が発生した場合でも、命令を効率良く実行し、データ干渉による誤動作を回避できる。
【００９２】
実施の形態２．
図１５は、この発明の実施の形態２におけるマイクロプロセッサで実行されるプログラム例を示す説明図である。実施の形態１のマイクロプロセッサの構成要素以外のこの実施の形態２のマイクロプロセッサの構成要素は、図１７に示す説明図を用いて後述する。なお、図１および図１２に示した実施の形態１のマイクロプロセッサの構成要素と同様のものについては、同一符号を用い、またそれらの説明を省略する。
【００９３】
図１５におけるＬＤ２Ｗ命令３００は、第２オペランド及び第３オペランドで指定された汎用レジスタに設定されている値の和で示されるメモリアドレスから８ｂｙｔｅのデータを読み出し、第１オペランドで指定された汎用レジスタおよび、その汎用レジスタ内のレジスタ番号に１を加えた汎用レジスタ内に読み出したデータを書き込む命令である。また、図１５において、第２オペランドのプラス（＋）記号は、アドレッシングモードがポストインクリメントであることを示しており、メモリからデータを読み出した後、第２オペランドで指定されている汎用レジスタの値に８が加算される。
【００９４】
図１５に示すプログラムにおいて、命令３００はレジスタＲ２およびＲ３の値の和で示されるメモリ内のメモリアドレスから８ｂｙｔｅのデータを読み出し、読み出したデータをレジスタＲ１０、Ｒ１１へ書き込む命令である。また、レジスタＲ２へは、メモリからデータが読み出された後、８が加算される。
【００９５】
命令３１０は条件実行命令である。命令３１０において記号／ＴＸは、実行コントロールフラグＦ０が１のとき命令３１０は有効になり、実行コントロールフラグＦ０が０のとき命令３１０は無効となることを示している。実行コントロールフラグＦ１の値は考慮されない。命令３１０が有効のときは、命令３００で更新されたレジスタＲ２の値およびＲ３の値の和で示されるメモリアドレスからデータが読み出され、読み出されたデータは、レジスタＲ１２、Ｒ１３内に書き込まれる。
【００９６】
また、レジスタＲ２はメモリからデータが読み出された後、８が加算される。命令３１０が無効のときには、レジスタＲ１２、Ｒ１３および、Ｒ２の値は変化しない。
【００９７】
命令３２０は、命令３１０が有効のときには、命令３１０で更新されたレジスタＲ２の値およびＲ３の値の和で示されるメモリ内のメモリアドレスからデータが読み出され、読み出されたデータはレジスタＲ１４、Ｒ１５へ書き込まれる。命令３１０が無効のときには、命令３００で更新されたレジスタＲ２の値およびＲ３の値の加算で示されるメモリアドレスのデータが読み出され、読み出されたデータは、レジスタＲ１４、Ｒ１５内に書き込まれる。また、レジスタＲ２へは、メモリからデータが読み出された後、８が加算される。
【００９８】
図１６は、実施の形態２のマイクロプロセッサ１が、図１５に示すプログラムを実行したときのパイプラインの動作を示した説明図であり、図において、命令３００に対応したパイプラインが３３０であり、命令３１０に対応したパイプラインが３４０であり、命令３２０に対応したパイプラインが３５０である。
【００９９】
図１６において、パイプライン３３０、３４０および３５０で同じ列にあるステージがそれぞれ同時に実行されることを示している。命令３００において、汎用レジスタＲ２に８が加算された値が書き戻されるのはＷ２期間であるため、命令３１０においてレジスタＲ２の値が読み出されるＤ１期間ではまだ更新されておらず、データ干渉が起こっている。そのため、矢印３３１に示すように命令３００のＤ１期間で更新されたＲ２の値を、命令３００のＥ１期間から命令３１０のＤ１期間に渡す。
【０１００】
命令３１０において、命令が有効であるとき、レジスタＲ２の値に８が加算された値が書き戻されるのは、Ｗ２期間であるため、命令３２０においてレジスタＲ２の値が汎用レジスタ５から読み出されるＤ１期間では、レジスタＲ２の値はまだ更新されておらず、データ干渉が起こっている。そのため、矢印３４１に示すように、命令３２０のＤ１期間で更新されたレジスタＲ２の値を命令３１０のＥ１期間から命令３２０のＤ１期間に渡す。
【０１０１】
命令３１０が無効であるとき、命令３００においてレジスタＲ２の値に８が加算された値が書き戻されるのはＷ２期間であるため、命令３２０においてレジスタＲ２が汎用レジスタ５から読み出されるＤ１期間ではまだ更新されておらず、データ干渉が起こっている。そのため、矢印３３２に示すように、命令３００のＤ１期間で更新されたＲ２の値を命令３００のＷ１期間から命令３２０のＤ１期間に渡す。
【０１０２】
図１７は、図１５に示すプログラムを実行するときの実施の形態２のマイクロプロセッサの動作を説明するためのブロック図である。図において、汎用レジスタ５、メモリアクセスユニット３、ＭＵデコーダ８、データＲＡＭ７は、図１に示したものと同一の構成要素からなる。また、条件実行制御部２６０は、図１２に示したものと同じ構成要素からなる。
【０１０３】
図１７に示す命令実行ユニットとしてのメモリアクセスユニット３において、３６０はインクリメンタ３７０から得られる出力をＤ２期間内に取り込み、取り込んだデータをＥ１レジスタ３６１へ出力するＤ２レジスタである。３６１はＤ２レジスタ３６０から出力されたデータをＥ１期間内に取り込み、取り込んだデータをＥ２レジスタ３６２に出力するとともに、レジスタ出力制御部３８２から出力される制御信号に従って、バイパス経路Ｂ１を介してＳ１バスへ出力するＥ１レジスタである。
【０１０４】
３６３は加算器３７１からの出力データをＤ２期間内に取り込み、取り込んだデータをＭ１レジスタ３６４へ出力するＤ２レジスタである。３６４はＤ２レジスタ３６３の出力をＥ１期間内に取り込み、取り込んだデータをＯＡバスに出力するＭ１レジスタである。３６５はＥ２バスに出力されたデータをＷ１期間内に取り込み、取り込んだデータをＷ１バスに出力するとともに、レジスタ出力制御部３８２から出力される制御信号に従って、バイパス経路Ｓ２を介してＳ１バスへ出力するＷ１レジスタである。
【０１０５】
３７０はＳ１バスに出力されたデータに８を加算した値を出力するインクリメンタである。３７１はＳ１バスおよび、Ｓ２バスに出力されたデータを入力し、それらの加算結果をＤ２レジスタ３６３に出力する加算器である。ＭＵデコーダ８において、３８０はバイパス制御を行うバイパス制御部である。
【０１０６】
バイパス制御部３８０において、３８１は命令を実行するパイプライン間でデータ干渉が発生しているか否かを判定し、さらにデータ干渉が発生している場合はどのように起こっているかを判定し、判定結果をレジスタ出力制御部３８２へ出力するバイパス判定部である。３８２はバイパス判定部３８１の判定結果および条件実行判定部２６１の判定結果に従って、バイパス経路Ｂ１を介したＥ１レジスタ３６１のデータ転送、バイパス経路Ｂ２を介したＷ１レジスタ３６５のデータ転送、およびデータ経路Ｄ１を介した汎用レジスタ５によるＳ１バスへのデータ転送を制御する制御信号を、これらのＥ１レジスタ３６１、Ｗ１レジスタ３６５および汎用レジスタ５へ出力するレジスタ出力制御部である。
【０１０７】
次に動作について説明する。
先ず、図１５に示すプログラムを実施の形態２のマイクロプロセッサが実行したときの動作について説明する。
命令３００において、汎用レジスタ５内のレジスタＲ２、Ｒ３のデータは、それぞれＳ１バス、Ｓ２バスを介して加算器３７１に出力されるとともに、レジスタＲ２のデータは、Ｓ１バスを介してインクリメンタ３７０にも出力される。加算器３７１から出力される加算結果は、Ｄ２レジスタ３６３、Ｍ１レジスタ３６４を経てＯＡバスへ出力され、データＲＡＭ７のメモリアドレスとして出力される。
【０１０８】
一方、インクリメンタ３７０では、汎用レジスタ５内のレジスタＲ２の値に８が加算され、その加算結果がＤ２レジスタ３６０を経てＥ１レジスタ３６１に出力される。Ｅ１レジスタ３６１に取り込まれたデータは、Ｅ２レジスタ３６２に取り込まれ、Ｅ２バスを介してＷ１レジスタに出力される。Ｗ１レジスタに取り込まれたデータは、Ｗ１バスを介して汎用レジスタ５内へ出力されレジスタＲ２の値が更新される。
【０１０９】
図１５に示す命令３１０では、バイパス判定部３８１は、命令３１０のレジスタＲ２が命令３００とデータ干渉を起こしていると判定し、判定結果をレジスタ出力制御部３８２に出力する。レジスタ出力制御部３８２では、バイパス判定部３８１の判定結果に従って、命令３００のレジスタＲ２の加算結果を保持しているＥ１レジスタにＳ１バスへの出力を許可することを意味する制御信号を出力し、Ｗ１レジスタ３６５および汎用レジスタ５に対してＳ１バスへの出力を許可しないことを意味する制御信号を出力する。
【０１１０】
バイパス経路Ｂ１を介してＳ１バスへ出力されたＥ１レジスタ３６１からのデータは、加算器３７１へ入力されると同時に、インクリメンタ３７０内へ入力される。加算器３７１の加算結果は、Ｄ２レジスタ３６３、Ｍ１レジスタ３６４を経てＯＡバスに出力され、データＲＡＭ７に対するメモリアドレスとして出力される。また、インクリメンタ３７０での加算結果は、Ｄ２レジスタ３６０を経てＥ１レジスタ３６１に取り込まれる。Ｅ１レジスタ３６１に取り込まれたデータは、Ｅ２レジスタ３６２内へ取り込まれ、Ｅ２バスを介してＷ１レジスタ３６５へ出力される。Ｗ１レジスタ３６５に取り込まれたデータは、Ｗ１バスを介して汎用レジスタ５へ出力される。
【０１１１】
実行条件フィールド２７０はＣＣ＝００１の値を持ち、条件実行判定部２６１は、実行コントロールフラグ２７１のＦ０フラグが１のとき命令３１０は有効であると判定し、Ｆ０フラグが０のとき命令３１０は無効であると判定し、判定結果を汎用レジスタ書き込み制御部２６２へ出力する同時に、レジスタ出力制御部３８２へ出力する。命令３１０が有効のときは、汎用レジスタ書き込み制御部２６２は、書き込みを許可することを指示する制御信号を汎用レジスタ５へ出力し、これにより汎用レジスタ５は、Ｗ１バスに出力されたＲ２の更新結果を書き込む。
【０１１２】
命令３１０が無効のときは、汎用レジスタ書き込み制御部２６２は、書き込みを許可しないことを指示する制御信号を汎用レジスタ５に対して出力し、これにより汎用レジスタ５は、Ｗ１バスに出力されたレジスタＲ２の更新結果の書き込みを実行しない。
【０１１３】
命令３２０では、バイパス判定部３８１は、命令３２０のレジスタＲ２が命令３００および命令３１０とデータ干渉を起こしていると判定し、判定結果をレジスタ出力制御部３８２へ出力する。レジスタ出力制御部３８２は、条件実行判定部２６１から出力された命令３１０に対する判定結果に従って、命令３１０が有効のときには、命令３１０のレジスタＲ２の加算結果を保持しているＥ１レジスタ３６１に対し、バイパス経路Ｂ１を介したＳ１バスへのデータ転送を許可することを指示する制御信号を出力し、命令３００のレジスタＲ２の加算結果を保持しているＷ１レジスタ３６５および、汎用レジスタ５に対しては、それぞれバイパス経路Ｂ２、データ経路Ｄ１を介したＳ１バスへの出力を許可しないことを指示する制御信号を出力する。
【０１１４】
命令３１０が無効のときには、レジスタ出力制御部３８２は、命令３１０のレジスタＲ２の加算結果を保持しているＥ１レジスタ３６１および汎用レジスタ５に対し、それぞれバイパス経路Ｂ１、データ経路Ｄ１を介したＳ１バスへのデータ転送を許可しないことを指示する制御信号を出力し、さらに命令３００のレジスタＲ２への加算結果を保持しているＷ１レジスタ３６５に対し、バイパス経路Ｂ２を介したＳ１バスへデータ転送を許可することを指示する制御信号を出力する。
【０１１５】
インクリメンタ３７０および加算器３７１は、命令３１０が有効のとき、Ｅ１レジスタ３６１から出力されたデータをＳ１バスを介して入力する。一方、命令３１０が無効のときには、Ｗ１レジスタ３６５から出力されたデータをＳ１バスを介して入力する。加算器３７１の加算結果は、Ｄ２レジスタ３６３、Ｍ１レジスタ３６４を経てＯＡバスへ出力され、データＲＡＭ７のメモリアドレスとしてデータＲＡＭ７に出力される。
【０１１６】
インクリメンタ３７０の加算結果は、Ｄ２レジスタ３６０を経てＥ１レジスタ３６１へ出力される。Ｅ１レジスタ３６１に取り込まれたデータは、Ｅ２レジスタ３６２へ取り込まれ、Ｅ２バスを介してＷ１レジスタに出力される。Ｗ１レジスタに取り込まれたデータは、Ｗ１バスを介して汎用レジスタ５へ出力される。
【０１１７】
以上のように、この実施の形態２によれば、命令デコードユニット２内に設けられた条件実行制御部２６０内の条件実行判定部２６１が、データ干渉がどのように発生しているかを判定するバイパス制御部３８０内のバイパス判定部３８１の出力を制御し、レジスタ出力制御部３８２から出力される制御信号を制御して、バイパス経路Ｂ１、Ｂ２やデータ経路Ｄ１を選択してデータ転送を実行するように構成したので、条件実行命令を含む複数の命令のパイプラインにおいてデータ干渉が発生した場合でも、命令を効率良く実行でき、データ干渉による誤動作を回避できる。
【０１１８】
【発明の効果】
以上のように、請求項１記載の発明によれば、命令デコーダ内の条件実行判定部が、汎用フラグ内に設定された条件データと実行条件フィールド内に設定された条件とが合致しているか否かを判定し、バイパス制御部が条件実行判定部の判定結果に従って、バイパス経路を使用するか否かを制御するように構成したので、条件実行命令の後にバイパス経路を用いる命令が続いた場合でも、パイプラインのペナルティを課することなく効率良く、また誤動作なく命令を実行できる効果がある。
【０１１９】
請求項２記載の発明によれば、バイパス制御部内のバイパス判定部が、命令実行部で実行される命令のパイプラインでデータ干渉が発生しているか否かを判定し、レジスタ出力制御部が、バイパス判定部の判定結果に基づいて、バイパス経路を介した制御レジスタのデータ転送動作を制御し、また、条件実行制御部内の条件実行判定部が、実行しようとする条件実行命令が有効であるか無効であるかを判定し、汎用レジスタ書き込み制御部が条件実行判定部の判定結果に基づいて汎用レジスタへのデータの書き込みを制御し、バイパス判定部がデータ干渉の発生を判定した場合であっても、レジスタ出力制御部は、条件実行判定部から送信される判定結果に従ってレジスタの動作を停止し、また汎用レジスタ内のデータを使用するようにレジスタおよび汎用レジスタを制御するように構成したので、条件実行命令の後にバイパス経路を用いる命令が続いた場合でも、パイプラインのペナルティを課することなく効率良く、また誤動作なく命令を実行できる効果がある。
【０１２０】
請求項３記載の発明によれば、命令デコーダ内の条件実行制御部が、汎用フラグ内に設定された条件と実行条件フィールド内に設定された条件が合致しているか否かを判定し、バイパス制御部が条件実行判定部の判定に従って、複数のバイパス経路および汎用レジスタを経由するデータ経路のうちいずれかを介したデータ転送を制御するように構成したので、条件実行命令の後にバイパス経路を用いる命令が続いた場合でも、パイプラインのペナルティを課することなく効率良く、また誤動作なく命令を実行できる効果がある。
【０１２１】
請求項４記載の発明によれば、バイパス制御部内のバイパス判定部が、命令実行部で実行される命令のパイプラインでデータ干渉が発生しているか否かを判定し、レジスタ出力制御部がバイパス判定部の判定結果に基づいて、バイパス経路を介した制御レジスタのデータ転送動作を制御し、条件実行制御部内の条件実行判定部が、実行しようとする条件実行命令が有効であるか無効であるかを判定し、汎用レジスタ書き込み制御部が、条件実行判定部の判定結果に基づいて汎用レジスタへのデータの書き込みを制御し、バイパス判定部がデータ干渉の発生を判定した場合であっても、レジスタ出力制御部が条件実行判定部から送信される判定結果に従って、複数のバイパス経路およびデータ経路のいずれかを選択して複数のレジスタあるいは複数の汎用レジスタのいずれかを介したデータ転送を制御するように構成したので、条件実行命令の後にバイパス経路を用いる命令が続いた場合でも、パイプラインのペナルティを課することなく効率良く、また誤動作なく命令を実行できる効果がある。
【図面の簡単な説明】
【図１】この発明の実施の形態１における条件実行命令を有するマイクロプロセッサの基本構成を示すブロック図である。
【図２】図１に示したこの発明における条件実行命令を有するマイクロプロセッサで用いられる命令フォーマットを示す説明図である。
【図３】図１に示したこの発明における条件実行命令を有するマイクロプロセッサで用いられる命令フォーマットフィールドを示す説明図である。
【図４】図１に示したこの発明における条件実行命令を有するマイクロプロセッサで用いられる命令フォーマット内の実行条件フィールドの詳細な内容を示す説明図である。
【図５】図１に示したこの発明における条件実行命令を有するマイクロプロセッサで用いられる命令フォーマット内の演算フィールドを示す説明図である。
【図６】図１に示したこの発明における条件実行命令を有するマイクロプロセッサのレジスタの構成を示す説明図である。
【図７】図１に示したこの発明における条件実行命令を有するマイクロプロセッサのレジスタ内のＰＳＷを示す説明図である。
【図８】図１に示したこの発明における条件実行命令を有するマイクロプロセッサのパイプライン動作を示す説明図である。
【図９】図１に示したこの発明における条件実行命令を有するマイクロプロセッサのパイプライン動作を示す説明図である。
【図１０】この発明の一実施の形態におけるマイクロプロセッサのデータ干渉が起こる場合のプログラム例である。
【図１１】図１０に示すプログラムを実行したときのパイプラインの動作を示した説明図である。
【図１２】図１０に示すプログラムを実行するときのマイクロプロセッサの動作を説明するためのブロック図である。
【図１３】条件実行判定部を示すブロック図である。
【図１４】図１０に示すプログラム内の命令が、条件実行命令である場合のデータ干渉の発生を示す説明図である。
【図１５】この発明の実施の形態２におけるマイクロプロセッサで実行されるプログラム例を示す説明図である。
【図１６】図１５に示すプログラムを実行したときのパイプラインの動作を示す図である。
【図１７】図１５に示すプログラムを実行するときの実施の形態２のマイクロプロセッサの動作を説明するためのブロック図である。
【符号の説明】
２ 命令デコードユニット（命令デコーダ）、３ メモリアクセスユニット（命令実行部）、５ 汎用レジスタ（複数の汎用レジスタ）、２４１，２４２，３６１，３６５ 複数のレジスタ、２５０，３８０ バイパス制御部、２５１，３８１ バイパス判定部、２５２，３８２ レジスタ出力制御部、２６０ 条件実行制御部、２６１ 条件実行判定部、２６２ 汎用レジスタ書き込み制御部、Ｂ０，Ｂ１，Ｂ２ バイパス経路、Ｄ０，Ｄ１ データ経路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microprocessor having a conditional execution instruction that controls execution of an instruction using an execution condition field included in a part of the instruction.
[0002]
[Prior art]
Conventionally, techniques such as conditional execution have been studied as techniques for reducing the penalty of branching and improving the performance of a microprocessor. In a conventional ARM microprocessor, as a flag to be used for determination of conditional execution, a dedicated flag set only by specific instructions such as a negative flag (N), a zero flag (Z), a carry flag (C), and an overflow flag (V) Using flags.
[0003]
As another conventional technique for improving the performance of a microprocessor, there is a technique using a bypass process of an operation result when the number of pipeline stages is increased for the purpose of increasing the operating frequency. In this method, for example, when an instruction for writing an operation result to a general-purpose register is executed, and then an instruction for referencing the register is executed, when the register is referred to by the latter instruction, the operation result of the former instruction is general-purpose. Since the instruction is not written in the register, the instruction is efficiently executed by directly referring to the operation result of the former instruction via a dedicated bypass path without passing through a general-purpose register.
[0004]
[Problems to be solved by the invention]
However, when a bypass path is used in a conventional microprocessor having a conditional execution instruction, for example, a conditional execution instruction for writing an operation result in a general-purpose register is executed, and then the general-purpose register in which the operation result is written is referred to. However, if an instruction using a bypass path is executed and the execution condition of the former instruction is not satisfied and the instruction becomes invalid, the latter instruction will bypass wrong data and cause a malfunction. There were challenges.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In a microprocessor having a conditional execution instruction provided with a bypass path for directly transferring data, an instruction using a bypass path follows the conditional execution instruction. Even in such a case, it is an object of the present invention to obtain a microprocessor having a conditional execution instruction capable of executing an instruction efficiently without imposing a penalty on a pipeline and without malfunction.
[0006]
[Means for Solving the Problems]
A microprocessor having a conditional execution instruction according to the first aspect of the present invention includes an instruction decoder for decoding various instructions such as a conditional execution instruction including an execution condition field and an operation field. , An instruction execution unit that executes an instruction according to an output of the instruction decoder; Stores the operation result of the instruction executed by the instruction execution unit, conditions data Is included. Just Control register and instruction execution unit Of instructions executed in Store the result General Register and an instruction execution unit. , General registers Use the operation result stored in Without storing the operation result of the instruction executed immediately before control A bypass path for bypassing an operation result in the register. In particular, the condition execution determination unit in the instruction decoder determines whether the condition data set in the general-purpose flag and the condition set in the execution condition field match, and the bypass control unit determines whether the condition execution has been performed. Whether to use a bypass route according to the judgment result of the section Or use the operation result stored in the general-purpose register Is controlled, and even if an instruction using the bypass path follows the conditional execution instruction, the instruction is executed efficiently without imposing a penalty on the pipeline and without malfunction.
[0007]
In the microprocessor having the conditional execution instruction according to the second aspect of the present invention, the bypass determination unit in the bypass control unit determines whether data interference occurs in the pipeline of the instruction executed by the instruction execution unit. The register output control unit controls the data transfer operation of the control register via the bypass path based on the determination result of the bypass determination unit, and the condition execution determination unit in the condition execution control unit executes It is determined whether the execution instruction is valid or invalid, and the general-purpose register write control unit controls the writing of data to the general-purpose register based on the determination result of the condition execution determination unit. further, The control register obtains and stores the operation result of the instruction executed by the instruction execution unit, and obtains and stores the operation result from the general-purpose register, and transfers the operation result obtained via the general-purpose register to other than the bypass path. A register connected to a data transfer path for transferring data through the path of Even when the bypass determination unit determines the occurrence of data interference, the register output control unit stops the operation of the register according to the determination result transmitted from the condition execution determination unit, Of the operation result stored in Use data Control via a data transfer path other than the bypass path register Data transfer Is controlled, and even if an instruction using the bypass path follows the conditional execution instruction, the instruction is executed efficiently without imposing a penalty on the pipeline and without malfunction.
[0008]
A microprocessor having a conditional execution instruction according to the third aspect of the present invention is an instruction decoder for decoding various instructions such as a conditional execution instruction including an execution condition field and an operation field, and a control register including a general-purpose flag for setting a condition. An instruction execution unit that executes an instruction according to the output of the instruction decoder; a plurality of general-purpose registers that store the execution results of the instruction execution unit; and an instruction execution unit that is provided immediately before execution without passing through the general-purpose register. A plurality of bypass paths for bypassing the operation results in the plurality of registers storing the operation results of the instruction, and a data path for data transfer via general-purpose registers. In particular, the condition execution control unit in the instruction decoder determines whether the condition set in the general-purpose flag and the condition set in the execution condition field match, and the bypass control unit determines , The data transfer via one of the plurality of bypass paths and the data path passing through the general-purpose register is controlled. Therefore, even if an instruction using the bypass path follows the instruction that executes the condition, the penalty of the pipeline , And execute instructions efficiently and without malfunction.
[0009]
In the microprocessor having the conditional execution instruction according to the fourth aspect of the present invention, the bypass determination unit in the bypass control unit determines whether data interference occurs in the pipeline of the instruction executed by the instruction execution unit. The register output control unit controls the data transfer operation of the control register via the bypass path based on the determination result of the bypass determination unit, and the condition execution determination unit in the condition execution control unit executes a condition execution instruction to be executed. The general-purpose register write control unit controls whether data is written to the general-purpose register based on the determination result of the condition execution determination unit, and the bypass determination unit determines whether data interference occurs. Even in the case where the determination is made, the register output control unit determines the plurality of bypass paths and the data paths according to the determination result transmitted from the condition execution determination unit. Select one to control data transfer through either the plurality of registers or the plurality of general-purpose registers, so penalize the pipeline even if a condition execution instruction is followed by an instruction using a bypass path. The instruction is executed efficiently and without malfunction.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described.
Embodiment 1 FIG.
First, a basic configuration of a microprocessor having a conditional execution instruction according to the present invention will be described.
[0011]
Microprocessor hardware configuration
FIG. 1 is a block diagram showing the overall configuration of a microprocessor having a conditional execution instruction according to the present invention, which is a 32-bit microprocessor having a 32-bit internal data bus. In the figure, 1 is a microprocessor core having a condition execution instruction, 2 is an instruction decode unit (instruction decoder) for decoding an instruction code inputted from the instruction RAM 6 via a 64-bit ID bus, and 3 is an address calculator. Memory access unit (instruction execution unit) that performs an arithmetic operation, 4 is an integer operation unit that performs arithmetic logic operation or shift operation, 5 is a general-purpose register (a plurality of general-purpose registers) of 32 bits × 64 words, 7 is data in which data is stored RAM.
[0012]
In the instruction decoding unit 2, 8 and 9 are decoders for decoding instruction codes, respectively, and 10 is a processor status word (Processor Status Word, hereinafter referred to as PSW) indicating the status of the processor. Instruction decode unit 2 further creates control signal 11 and provides it to memory access unit 3. The instruction decode unit 2 creates a control signal 12 based on the result of decoding by the decoder 9 and the contents of the PSW 10 and supplies the control signal 12 to the integer operation unit 4.
[0013]
In the memory access unit 3, when an instruction not including a jump or a branch is executed, the PC 13 adds 8 to a PC (program counter) value to calculate a PC value for an instruction to be executed next, and executes an instruction including a jump or a branch. A PC control unit that sometimes adds a branch displacement to a PC value or calculates a PC value for an instruction at a jump destination by performing a calculation according to an addressing mode specified by an operation. Reference numeral 14 denotes a memory control unit that sends the PC value calculated by the PC control unit 13 to the instruction RAM 6 via the 32-bit IA bus and outputs an instruction code from the instruction RAM 6.
[0014]
The memory control unit 14 transfers address data to the data RAM 7 via a 32-bit OA bus, and accesses data necessary for executing an instruction via a 64-bit OD bus. Numeral 15 performs an arithmetic and logic operation using data of up to three words transferred from the general-purpose register 5 via the 32-bit wide S1, S2, and S6 buses, and outputs the calculation result via the 32-bit wide W1 bus. ALU that transfers the data to the general-purpose register 5. A shifter 16 performs a shift operation using data transferred from the general-purpose register 5 via the S1, S2, and S6 buses, and transfers the operation result to the general-purpose register 5 via the W1 bus.
[0015]
It is possible to transfer 32-bit data four words at a time to the memory access unit 3 via the S1, S2, S5, and S6 buses. Therefore, for example, the contents of the third register are stored in an area of the memory addressed by the sum of the contents of the first register and the contents of the second register, and the content of the third register is stored in the address where the contents of the third register are stored. A two-word store instruction for storing the contents of the fourth register in a memory area addressed by a value obtained by adding a predetermined value can be realized.
[0016]
The memory access unit 3 transfers the two-word operation result in the memory access unit 3 or the two-word data transferred from the data RAM 7 to the general-purpose register 5 via the W1 bus, the W3E bus, and the W3O bus. can do.
[0017]
In the integer operation unit 4, 17 multiplies using data of up to three words transferred from the general-purpose register 5 via the 32-bit width S3 bus, S4 bus, and S5 bus, and converts the operation result into a 32-bit width W2. This is a multiplier that transfers the data to the general-purpose register 5 via the bus, the W3E bus, and the W3O bus. Reference numeral 18 denotes an accumulator that holds the result of the multiplication by accumulative addition or subtraction. Two 64-bit accumulators are incorporated. 19 performs an arithmetic and logic operation using data of up to three words transferred from the general-purpose register 5 via the S3 bus, the S4 bus, and the S5 bus, and performs a general-purpose operation on the W2 bus, the W3E bus, and the W3O bus. ALU to be transferred to the register 5. Reference numeral 20 performs a shift operation using the data transferred from the general-purpose register 5 via the S3, S4, and S5 buses, and transfers the operation result to the general-purpose register 5 via the W2, W3E, and W3O buses. It is a shifter.
[0018]
In the microprocessor 1, up to six types of register values can be read from the general-purpose register 5, and the read data is S1 bus, S2 bus, S3 bus, S4 bus, S5 bus, S6 bus, respectively. Output to the bus. Further, up to four types of register values can be simultaneously written into the general-purpose register 5 via the W1 bus, the W2 bus, the W3E bus, and the W3O bus.
[0019]
FIG. 2 is an explanatory diagram showing an instruction format used in the microprocessor 1 having the conditional execution instruction according to the present invention shown in FIG.
As instruction formats, there are a two-operation instruction format 101 that specifies two operations with one instruction code, and a one-operation instruction format 102 that specifies one operation with one instruction code.
[0020]
The format 101 of the two-operation instruction includes a format field including a field 103 and a field 104, and execution condition fields 105 attached to the two operation fields 106 and 107. The format 102 of one operation instruction includes a format field including a field 108 and a field 104, an operation field including fields 108, 109, and 110, and an execution condition field 105 attached to the operation field.
[0021]
FIG. 3 is an explanatory diagram showing an instruction format field used in the microprocessor 1 having a conditional execution instruction according to the present invention shown in FIG. 1, where FM is a 2-bit value consisting of a field 103 and a field 104. It is.
[0022]
When the value of the format field is FM = 00, this instruction is a two-operation instruction. Then, the operation of operation_0 indicated by the operation field 106 and the operation of operation_1 indicated by the operation field 107 are executed in parallel in the clock cycle immediately after decoding. The operation of operation_0 is executed by the memory access unit 3, and the operation of operation_1 is executed by the integer operation unit 4.
[0023]
When the value of the format field is FM = 01, it indicates that this instruction is a two-operation instruction. Then, the operation of operation_0 is executed in the clock cycle immediately after decoding, and the operation of operation_1 is executed one clock cycle later than the operation of operation_0.
[0024]
When the value of the format field is FM = 10, it indicates that this instruction is a two-operation instruction. Then, the operation of operation_1 is executed in the clock cycle immediately after decoding, and the operation of operation_0 is executed one clock cycle later than the operation_1.
[0025]
If the value of the format field is FM = 11, it indicates that this instruction is a one-operation instruction. Then, one operation specified in the operation field including the fields 108, 109, and 110 is executed in the clock cycle immediately after decoding.
[0026]
FIG. 4 is an explanatory diagram showing the detailed contents of the execution condition field 105 in the instruction format used in the microprocessor having the conditional execution instruction according to the present invention shown in FIG.
In the execution condition field 105, the operation of the operation_0 and the operation of the operation_1 in the operation fields 106 and 107 and the operation of the operation fields 108, 109 and 110 are effective according to the values of the execution control flags F0 and F1 of the microprocessor 1. Or invalid. The contents of the execution control flags F0 and F1 will be described later.
[0027]
That the operation is valid means that the operation result is reflected in the register, the memory, and the flag, and the result of the operation by the operation remains. An invalid operation means that the operation result is not reflected in the register, the memory, and the flag, and an operation result as if an invalid operation (NOP) was executed remains.
[0028]
When the value of the execution condition field 105 is CC = 000, the operation is always valid regardless of the values of the execution control flags F0 and F1. When / TX is described in the instruction, it means that CC = 000.
[0029]
When the value of the execution condition field 105 is CC = 001, the operation is valid only when the execution control flag F0 = true. The state of the execution control flag F1 may be any. When / FX is described in the instruction, it means that CC = 001.
[0030]
When the value of the execution condition field 105 is CC = 010, the operation is valid only when the execution control flag F0 = false. The state of the execution control flag F1 may be any. When / FX is described in the instruction, it means that CC = 010.
[0031]
When the value of the execution condition field 105 is CC = 011, the operation is valid only when the execution control flag F1 = true. The state of the execution control flag F0 may be any state. When / XT is described in the instruction, it means that CC = 011. When CC = 100, the operation is valid only when the execution control flag F1 = false. The state of the execution control flag F0 may be any state. When / XF is described in the instruction, it means that CC = 100.
[0032]
When the value of the execution condition field 105 is CC = 101, the operation is valid only when the execution control flag F0 = true and F1 = true. When / TT is described in the instruction, it means that CC = 101. When CC = 110, the operation is valid only when the execution control flag F0 = true and F1 = false. When / TF is described in the instruction, it means that CC = 110.
[0033]
The operation when the value of the execution condition field 105 is CC = 111 is undefined, and the user cannot use an instruction with CC = 111.
[0034]
FIG. 5 is an explanatory diagram showing operation fields in the instruction format used in the microprocessor having the conditional execution instruction according to the present invention shown in FIG. In the figure, formats 111 to 117 are based on a short type operation field 106 or an operation field 107 represented by 28 bits. The formats 118 and 119 are based on long operation fields composed of fields 108, 109 and 110. The format 111 (Short_M) includes a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, a field 123 for specifying the register number or immediate value of 6-bit length, and whether the field 123 indicates the register number. Is indicated by a field 124 for designating whether or not the data is displayed.
[0035]
As shown in the explanatory diagram of FIG. 5, when the value X of the field 124 is “00”, “01” or “11”, it indicates that the field 123 indicates a register number, and when the value X is “10”, the immediate value is Is shown. This format 111 is used for a memory access operation of register indirect addressing.
[0036]
The format 112 (Short_A) includes a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, a field 123 for specifying the register number or the immediate value of 6-bit length, and whether the field 123 indicates the register number. It comprises a field 125 for specifying whether to indicate an immediate value.
[0037]
As shown in the explanatory diagram of FIG. 5, when the value X of the field 125 in the format 112 is “0”, it indicates that the field 123 indicates a register number, and when it is “1”, it indicates an immediate value. It indicates that. This format 112 is used for arithmetic operations, logical operations, shift operations, and bit operations.
[0038]
The format 113 (Short_B1) includes a field 120 for specifying the operation content and a field 126 for specifying the register number. This format 113 is used for jump instructions and branch instructions by register designation.
[0039]
The format 114 (Short_B2) includes a field 120 for specifying the operation content and a displacement 127 field having a length of 18 bits. This format 114 is used for jump instructions and branch instructions.
[0040]
The format 115 (Short_B3) includes a field 120 for specifying the operation content, a field 121 for specifying the register number, a field 128 for specifying the register number or the immediate value of 12-bit length, and whether the field 128 indicates the register number or the immediate value. It comprises a field 129 to specify and a field 130 to specify whether to perform a conditional jump or a conditional branch based on the field 121 based on the zero judgment. This format 115 is used for conditional jump instructions and conditional branch instructions.
[0041]
The format 116 (Short_D1) includes a field 120 for specifying the operation content, a field 121 for specifying the register number, a field 128 for specifying the register number or the immediate value of 12-bit length, and whether the field 128 indicates the register number or the immediate value. It consists of a field 129 to be specified. This format 116 is used for conditional jump instructions, conditional branch instructions, and repeat instructions.
[0042]
The format 117 (Short_D2) includes a field 120 for specifying an operation content, a field 128 for specifying a register number or a 12-bit immediate value, a field 129 for specifying whether the field 128 indicates a register number or an immediate value, a delay instruction ( Field 131 relating to a delayed instruction). This format 117 is used for a delayed jump instruction, a delayed branch instruction, and a repeat instruction.
[0043]
The format 118 (Long1) is composed of a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, and a field 132 for specifying a 32-bit immediate value. The format 118 is used for a complex arithmetic operation, an arithmetic operation using a large immediate value, a memory access operation of large register indirect addressing with displacement, a branch operation with a large displacement, and a jump instruction to an absolute number value.
[0044]
The format 119 (Long2) is a conditional jump based on a field 120 for specifying the operation content, two fields 121 and 122 for specifying the register number, a field 132 for specifying a 32-bit immediate value, and a field 132 based on the zero judgment. Alternatively, it is constituted by a field 133 for designating whether or not to perform a conditional branch.
[0045]
This format 119 is used for a conditional jump or conditional branch instruction having a large branch displacement.
[0046]
FIG. 6 is an explanatory diagram showing a configuration of a register of a microprocessor having a conditional execution instruction according to the present invention shown in FIG.
The microprocessor 1 includes 64 32-bit general-purpose registers 5, 12 control registers 150, and two accumulators 18. The content of the general register 140 of R0 is always 0, and writing to it is ignored. The general-purpose register of R62 is a link register in which a return address from the subroutine is set. The general-purpose register of R63 is a stack pointer, and operates as a user stack pointer (SPU) or an interrupt stutter pointer (SPI) according to the value of the SM field of the PSW 10. The control register 150 includes a program counter 151, a PSW 10, and various dedicated registers.
[0047]
In the calculation using the format 112 shown in FIG. 5, each of the 64 general-purpose registers 5 can be accessed by being divided into upper 16 bits and lower 16 bits. Further, the two accumulators 18 can be separately accessed by dividing them into upper 32 bits and lower 32 bits.
[0048]
FIG. 7 is an explanatory diagram showing the PSW in the register of the microprocessor having the conditional execution instruction according to the present invention shown in FIG.
The upper 16 bits of the PSW 10 include an SM field 171 for switching a stack pointer, an EA field 172 indicating detection of a software debugger trap (SDBT), a DB field 173 specifying permission of SDBT, an IE field 174 specifying permission of interrupt, There is an RP field 178 for designating permission of a repeat operation, and an MD field 176 for designating permission of modulo addressing.
[0049]
The lower 16 bits are a flag field 180. The flag field 180 has eight flags, of which the F0 flag 181 and the F1 flag 182 specify the validity / invalidity of the operation. The value of each flag changes according to the result of the comparison operation or the arithmetic operation. In addition, it is changed by initializing by a flag initialization operation or by writing an arbitrary value to the flag field 180 in a flag value writing operation. The contents of the flag field 180 are read by a flag value read operation.
[0050]
Hereinafter, a list of instructions of the microprocessor 1 having the conditional execution instruction of the present invention is shown.
[0051]

[0052]

[0053]

[0054]

reserved
[0055]

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]
FIG. 8 is an explanatory diagram showing a pipeline operation when the microprocessor 1 having the conditional execution instruction according to the present invention shown in FIG. 1 executes two parallel instructions.
This operation is executed when the value of the format field of the instruction is FM = 00. Each of the pipelines 190 and 195 includes an IF stage 191, a D / A stage 192, an E / M stage 193, and a W stage 194. When executing two parallel instructions, execution 190 in the memory access unit 3 and execution 195 in the integer operation unit 4 are performed in parallel.
[0064]
FIG. 9 is an explanatory diagram showing the pipeline operation of the microprocessor having the conditional execution instruction according to the present invention shown in FIG. 1. In the figure, each stage is synchronized with the clock, and the high period of the clock and the low period are shown. Is divided into two periods.
[0065]
When the clock of the IF stage is High for the I1 period, when it is Low, the I2 period, when the clock of the D / A stage is High, the D1 period, when it is Low, it is the D2 period, and when the clock of the E / M stage is High. Is the E1 period, when it is low, it is the E2 period, when the clock of the IF stage is high, it is the W1 period, and when it is low, it is the W2 period.
[0066]
At the IF stage, an instruction is fetched. At the D / A stage, the instruction is decoded and the general-purpose register is read within the period D1, and the memory address is calculated within the period D2. In the W1 period of the E / M stage and the W stage, execution of operations and access to the memory are performed, and writing to the general-purpose register is performed in the W2 period of the W stage.
[0067]
FIG. 10 is an example of a program when data interference occurs in the microprocessor 1. Data interference will be described later.
[0068]
In the figure, the ADD instruction is an instruction for adding the values of the general-purpose registers specified by the second operand and the third operand, and writing the operation result to the general-purpose register specified by the first operand. In the ADD instruction 200, the value of the general-purpose register R2 and the value of the general-purpose register R3 are added, and the addition result is written to the general-purpose register R4.
[0069]
In the ADD instruction 210, the value of the general-purpose register R10 and the value of the general-purpose register R4 are added, and the addition result is written into the general-purpose register R11. In the ADD instruction 210, the value of the general-purpose register R4 is equal to the addition result of the ADD instruction 200.
[0070]
In the ADD instruction 200, the writing of the addition result to the general-purpose register R4 is performed within the W2 period. Therefore, during the D2 period of the ADD instruction 210, the writing of the addition result to the general-purpose register R4 is not completed. The value of the general-purpose register R4 read in the period D1 of the ADD instruction 210 cannot be used for the operation. Such a situation is called data interference. In a situation where data interference occurs, control is performed to pass the addition result of the ADD instruction 200 to the D2 period of the ADD instruction 210 via a dedicated data transfer path (bypass path) without passing through the general-purpose register R4.
[0071]
FIG. 11 is an explanatory diagram showing the operation of the pipeline when the program of FIG. 10 is executed. In FIG. 11, reference numeral 220 denotes a pipeline corresponding to the instruction 200, and reference numeral 230 denotes a pipeline corresponding to the instruction 210. This shows that the stages in the same column in the pipeline 220 and the pipeline 230 are respectively executed simultaneously. As indicated by the arrow in FIG. 11, by passing the addition result from the E2 period of the pipeline 220 to the D2 period of the pipeline 230 via the bypass path, the instruction is executed without disturbing the pipeline.
[0072]
FIG. 12 is a block diagram for explaining the operation of the microprocessor 1 when executing the program shown in FIG. 10, and the same reference numerals as those in the block diagram of the microprocessor 1 shown in FIG. 1 are used. That is, the ALU 15, the general-purpose register 5, the memory access unit 3, and the MU decoder 8 are the same components as those shown in FIG.
[0073]
In the memory access unit 3, reference numeral 240 denotes an E1 register for fetching the data output to the D2 bus within the E1 period and outputting the fetched data to the ALU 15; 241 denotes output data from the ALU 15 for the E2 period via the E1 bus. The E2 register 242 outputs the fetched data to the D2 bus via the bypass path B0 while outputting the fetched data to the E2 bus, and outputs the fetched data in accordance with the control signal output from the register output control unit 252. Register 243 via the S2 bus and outputs the fetched data to the D2 bus via the data path D0 according to the output of the register output control unit 252. The D2 register 243 outputs the output of the E2 register 241 to the E2 Takes in the W1 period via the bus and Is W1 register for outputting the first bus.
[0074]
In the MU decoder 8, reference numeral 250 denotes a bypass control unit for performing bypass control, and reference numeral 260 denotes a condition execution control unit for controlling a condition execution instruction.
[0075]
In the bypass control unit 250, reference numeral 251 denotes a bypass determination unit that determines whether or not data interference has occurred. 252 denotes an E2 register 241 and a D2 register 242 according to the determination result of the bypass determination unit and the determination result of the condition execution determination unit 261. A register output control unit that outputs a signal for controlling output to the D2 bus.
[0076]
In the condition execution control unit 260, 261 is a condition execution determination unit that determines whether a condition execution instruction is valid or invalid, and 262 controls writing to the general-purpose register 5 according to the determination result of the condition execution determination unit 261. This is a general-purpose register write control unit that outputs a signal.
[0077]
FIG. 13 is a block diagram showing the condition execution determination unit 261. In the figure, 270 is the same as the execution condition field 105 in FIG. 271 is the same as the F0 flag 181 and the F1 flag 182 in FIG. A decoder 272 decodes the condition set in the execution condition field 270 and determines whether the condition matches the condition set in the execution control flag 271.
[0078]
Next, the operation will be described.
First, the operation when the microprocessor 1 having the conditional execution instruction according to the first embodiment executes the program shown in FIG. 10 will be described.
[0079]
The addition result obtained by executing the instruction 200 in the program shown in FIG. 10 is output from the ALU 15 and stored in the E2 register 241 via the E1 bus within the E2 period of the instruction 200. The output from the E2 register 241 is stored in the W1 register 243 via the E2 bus within the W1 period of the instruction 200.
[0080]
When the instruction 200 is executed, the execution condition field 270 has a value of CC = 000, and the instruction is always valid regardless of the value of the execution control flag 271 as described above. Therefore, the condition execution determination unit 261 determines that the instruction is valid, and outputs the determination result to the general-purpose register write control unit 262 and the register output control unit 252. The general-purpose register write control unit 262 outputs a control signal that permits writing according to the determination result of the condition execution determination unit 261 to the general-purpose register.
[0081]
The data stored in the W1 register 243 is written into the general-purpose register via the W1 bus during the W2 period of the instruction 200 according to the control signal of the general-purpose register write control unit 262. In the instruction 210, the data of R4 is taken into the D2 register 242 from the general-purpose register 5 via the S2 bus within the D2 period of the instruction 210.
[0082]
The bypass determination unit 251 determines that the instruction 210 causes data interference, and outputs a result of the determination to the register output control unit 252. The register output control unit 252 outputs a control signal indicating that output to the D2 bus is permitted to the E2 register 241 holding the addition result of the instruction 200 according to the determination result of the bypass determination unit 251. A control signal indicating that output to the D2 bus is not permitted is output to the D2 register 242 holding the data of the register 5.
[0083]
The E2 register 241 outputs the held data to the D2 bus according to the control signal of the register output control unit 252. On the other hand, the D2 register 242 does not output the held data to the D2 bus according to the control signal of the register output control unit 252. The E1 register 240 captures the output data from the E2 register 241 via the D2 bus within the E1 period of the instruction 210, and outputs the captured data to the ALU 15. The ALU 15 performs an addition operation on the instruction 210 based on the output data from the E1 register 240.
[0084]
Next, the operation of the microprocessor 1 having the conditional execution instruction according to the first embodiment when the instruction 200 in the program shown in FIG. 10 is a conditional execution instruction will be described.
[0085]
FIG. 14 is an explanatory diagram showing the occurrence of data interference when the instruction 200 in the program shown in FIG. 10 is a conditional execution instruction. In the figure, an instruction 280 is a conditional execution instruction and / TX is described in the instruction. Therefore, when the execution control flag F0 is 1, the instruction 280 is valid, and when the execution control flag F0 is 0, as described above. Instruction 280 is invalid. The value of the execution control flag F1 is not considered.
[0086]
When the instruction 280 is valid, the value of the general-purpose register R4 of the instruction 291 matches the addition result of the instruction 280, and when the instruction 280 is invalid, the value of the general-purpose register R4 of the instruction 291 becomes the value before executing the instruction 280. Matches the value of. The addition result of the instruction 280 shown in FIG. 14 is output from the ALU 15 and stored in the E2 register 241 via the E1 bus within the E2 period of the instruction 200. The output from the E2 register 241 is stored in the W1 register 243 via the E2 bus within the W1 period of the instruction 280.
[0087]
In the case of the instruction 280, the execution condition field 270 has a value of CC = 001, and the condition execution determination unit 261 determines that the instruction 280 is valid when the F0 flag of the execution control flag 271 is 1, and the F0 flag Is 0, the instruction 280 is determined to be invalid, and the determination result is output to the general-purpose register write control unit 262 and to the register output control unit 252.
[0088]
First, when the instruction 280 is valid, the same operation as when the microprocessor 1 executes the program shown in FIG. 10 is performed.
Next, the operation when the instruction 280 is invalid will be described.
The general-purpose register write control unit 262 outputs to the general-purpose register 5 a control signal indicating that writing is not permitted according to the determination result of the condition execution determination unit 261. The data stored in the W1 register 243 is not written to the general-purpose register 5 according to the control signal of the general-purpose register write control unit 262. In the instruction 290, the data of R4 is taken into the D2 register 242 from the general-purpose register 5 via the S2 bus within the D2 period of the instruction 290.
[0089]
The bypass determination unit 251 determines that the instruction 210 causes data interference, and outputs a result of the determination to the register output control unit 252. The register output control unit 252 permits the E2 register 241 to output to the D2 bus via the bypass path B0 regardless of the determination result of the bypass determination unit 251 according to the determination result of the condition execution determination unit 261. It outputs a control signal that means not to do so. Further, the register output control unit 252 outputs a control signal for instructing the D2 register 242 holding the data of the general-purpose register 5 to permit data output to the D2 bus via the data path D0. The E2 register 241 does not output the held data to the D2 bus via the bypass path B0 according to the control signal transmitted from the register output control unit 252.
[0090]
On the other hand, the D2 register 242 outputs the held data to the D2 bus according to the control signal of the register output control unit 252. The E1 register 240 captures the output data from the E2 register via the D2 bus within the E1 period of the instruction 210, and outputs the captured data to the ALU 15. The ALU 15 performs the addition operation of the instruction 280 based on the output data from the E1 register.
[0091]
As described above, according to the first embodiment, it is determined whether or not data interference has occurred between the pipelines of the instructions including the conditional execution instructions, and the execution is performed based on the determination result of the bypass determination unit 251. The output of the register output control unit 252 is controlled in accordance with the result of the determination by the condition execution determination unit 261 in the execution condition control unit 260, and the data transfer via the bypass path B0 and the data path D0 is controlled. Even when data interference occurs in a pipeline that executes a conditional execution instruction, the instruction can be executed efficiently and a malfunction due to the data interference can be avoided.
[0092]
Embodiment 2 FIG.
FIG. 15 is an explanatory diagram showing an example of a program executed by the microprocessor according to the second embodiment of the present invention. Components of the microprocessor according to the second embodiment other than the components of the microprocessor according to the first embodiment will be described later with reference to an explanatory diagram shown in FIG. Note that the same components as those of the microprocessor of the first embodiment shown in FIGS. 1 and 12 are denoted by the same reference numerals, and description thereof is omitted.
[0093]
The LD2W instruction 300 in FIG. 15 reads 8-byte data from the memory address indicated by the sum of the values set in the general-purpose registers specified by the second operand and the third operand, and reads the general-purpose register specified by the first operand. And an instruction to write the read data in the general-purpose register obtained by adding 1 to the register number in the general-purpose register. In FIG. 15, the plus (+) sign of the second operand indicates that the addressing mode is post-increment, and after reading data from the memory, the value of the general-purpose register specified by the second operand Is added to.
[0094]
In the program shown in FIG. 15, an instruction 300 is an instruction for reading 8-byte data from a memory address in the memory indicated by the sum of the values of the registers R2 and R3, and writing the read data to the registers R10 and R11. After data is read from the memory, 8 is added to the register R2.
[0095]
Instruction 310 is a conditional execution instruction. The symbol / TX in the instruction 310 indicates that when the execution control flag F0 is 1, the instruction 310 is valid, and when the execution control flag F0 is 0, the instruction 310 is invalid. The value of the execution control flag F1 is not considered. When the instruction 310 is valid, data is read from the memory address indicated by the sum of the value of the register R2 and the value of R3 updated by the instruction 300, and the read data is written into the registers R12 and R13. It is.
[0096]
In addition, 8 is added to the register R2 after the data is read from the memory. When the instruction 310 is invalid, the values of the registers R12, R13, and R2 do not change.
[0097]
When the instruction 310 is valid, the instruction 320 reads data from a memory address in the memory indicated by the sum of the value of the register R2 and the value of the register R3 updated by the instruction 310, and stores the read data in the register R14. , R15. When the instruction 310 is invalid, the data at the memory address indicated by the addition of the value of the register R2 and the value of the register R3 updated by the instruction 300 is read, and the read data is written into the registers R14 and R15. . After data is read from the memory, 8 is added to the register R2.
[0098]
FIG. 16 is an explanatory diagram showing the operation of the pipeline when the microprocessor 1 according to the second embodiment executes the program shown in FIG. 15. In FIG. 16, the pipeline corresponding to the instruction 300 is 330. , The pipeline corresponding to the instruction 310 is 340, and the pipeline corresponding to the instruction 320 is 350.
[0099]
FIG. 16 shows that the stages in the same column in the pipelines 330, 340 and 350 are each executed simultaneously. In the instruction 300, since the value obtained by adding 8 to the general-purpose register R2 is written back during the W2 period, the value has not been updated in the D1 period during which the value of the register R2 is read out in the instruction 310, and data interference may occur. ing. Therefore, the value of R2 updated in the period D1 of the instruction 300 is transferred from the period E1 of the instruction 300 to the period D1 of the instruction 310 as indicated by an arrow 331.
[0100]
In the instruction 310, when the instruction is valid, the value obtained by adding 8 to the value of the register R2 is written back during the W2 period. During the period, the value of the register R2 has not been updated yet, and data interference has occurred. Therefore, as indicated by an arrow 341, the value of the register R2 updated in the period D1 of the instruction 320 is transferred from the period E1 of the instruction 310 to the period D1 of the instruction 320.
[0101]
When the instruction 310 is invalid, the value obtained by adding 8 to the value of the register R2 in the instruction 300 is written back in the W2 period. Therefore, in the instruction 320, the register R2 is still read in the D1 period in which the register R2 is read from the general-purpose register 5. Not updated, causing data interference. Therefore, as indicated by the arrow 332, the value of R2 updated in the period D1 of the instruction 300 is transferred from the period W1 of the instruction 300 to the period D1 of the instruction 320.
[0102]
FIG. 17 is a block diagram for explaining an operation of the microprocessor according to the second embodiment when executing the program shown in FIG. In the figure, a general-purpose register 5, a memory access unit 3, an MU decoder 8, and a data RAM 7 are composed of the same components as those shown in FIG. Further, the condition execution control unit 260 includes the same components as those shown in FIG.
[0103]
In the memory access unit 3 as the instruction execution unit shown in FIG. 17, reference numeral 360 denotes a D2 register which captures the output obtained from the incrementer 370 within the D2 period and outputs the captured data to the E1 register 361. Numeral 361 captures the data output from the D2 register 360 during the E1 period, outputs the captured data to the E2 register 362, and, according to a control signal output from the register output control unit 382, connects the S1 bus via the bypass path B1. Is an E1 register output to
[0104]
A D2 register 363 captures output data from the adder 371 during the D2 period and outputs the captured data to the M1 register 364. An M1 register 364 captures the output of the D2 register 363 during the E1 period and outputs the captured data to the OA bus. 365 fetches the data output to the E2 bus within the W1 period, outputs the fetched data to the W1 bus, and outputs the data to the S1 bus via the bypass path S2 according to the control signal output from the register output control unit 382. W1 register.
[0105]
An incrementer 370 outputs a value obtained by adding 8 to the data output to the S1 bus. Reference numeral 371 denotes an adder that inputs data output to the S1 bus and the S2 bus, and outputs the result of addition to the D2 register 363. In the MU decoder 8, reference numeral 380 denotes a bypass control unit that performs bypass control.
[0106]
In the bypass control unit 380, 381 determines whether or not data interference has occurred between the pipelines executing instructions, and further determines how the data interference has occurred if data interference has occurred. A bypass determination unit that outputs a result to the register output control unit 382. 382 is a data transfer of the E1 register 361 via the bypass path B1, a data transfer of the W1 register 365 via the bypass path B2, and a data path D1 according to the determination result of the bypass determination unit 381 and the determination result of the condition execution determination unit 261. A register output control unit that outputs a control signal for controlling data transfer to the S1 bus by the general-purpose register 5 via the E1 register 361, the W1 register 365, and the general-purpose register 5.
[0107]
Next, the operation will be described.
First, the operation when the microprocessor of the second embodiment executes the program shown in FIG. 15 will be described.
In the instruction 300, the data of the registers R2 and R3 in the general-purpose register 5 are output to the adder 371 via the S1 bus and the S2 bus, respectively, and the data of the register R2 is transmitted to the incrementer 370 via the S1 bus. Is also output. The addition result output from the adder 371 is output to the OA bus via the D2 register 363 and the M1 register 364, and is output as a memory address of the data RAM 7.
[0108]
On the other hand, in the incrementer 370, 8 is added to the value of the register R2 in the general-purpose register 5, and the addition result is output to the E1 register 361 via the D2 register 360. The data captured by the E1 register 361 is captured by the E2 register 362 and output to the W1 register via the E2 bus. The data taken into the W1 register is output to the general-purpose register 5 via the W1 bus, and the value of the register R2 is updated.
[0109]
In the instruction 310 illustrated in FIG. 15, the bypass determination unit 381 determines that the register R2 of the instruction 310 is causing data interference with the instruction 300, and outputs a determination result to the register output control unit 382. The register output control unit 382 outputs a control signal indicating that output to the S1 bus is permitted to the E1 register holding the addition result of the register R2 of the instruction 300 according to the determination result of the bypass determination unit 381. It outputs a control signal to the W1 register 365 and the general-purpose register 5 indicating that output to the S1 bus is not permitted.
[0110]
The data from the E1 register 361 output to the S1 bus via the bypass path B1 is input to the adder 371 and at the same time to the incrementer 370. The addition result of the adder 371 is output to the OA bus via the D2 register 363 and the M1 register 364, and is output as a memory address for the data RAM 7. Further, the addition result at the incrementer 370 is taken into the E1 register 361 via the D2 register 360. The data captured by the E1 register 361 is captured by the E2 register 362 and output to the W1 register 365 via the E2 bus. The data taken into the W1 register 365 is output to the general-purpose register 5 via the W1 bus.
[0111]
The execution condition field 270 has a value of CC = 001, and the condition execution determination unit 261 determines that the instruction 310 is valid when the F0 flag of the execution control flag 271 is 1, and when the F0 flag is 0, the instruction 310 It determines that it is invalid, and outputs the determination result to the general-purpose register write control unit 262 and at the same time, to the register output control unit 382. When the instruction 310 is valid, the general-purpose register write control unit 262 outputs a control signal instructing permission of writing to the general-purpose register 5, so that the general-purpose register 5 updates the R2 output to the W1 bus. Write the result.
[0112]
When the instruction 310 is invalid, the general-purpose register write control unit 262 outputs a control signal indicating that writing is not permitted to the general-purpose register 5, whereby the general-purpose register 5 outputs the register output to the W1 bus. The writing of the update result of R2 is not executed.
[0113]
In the instruction 320, the bypass determination unit 381 determines that the register R2 of the instruction 320 causes data interference with the instruction 300 and the instruction 310, and outputs a determination result to the register output control unit 382. When the instruction 310 is valid, the register output control unit 382 bypasses the E1 register 361 holding the addition result of the register R2 of the instruction 310 according to the determination result for the instruction 310 output from the condition execution determination unit 261. A control signal indicating that data transfer to the S1 bus via the path B1 is permitted is output, and the W1 register 365 holding the addition result of the register R2 of the instruction 300 and the general-purpose register 5 are: Control signals are output to instruct that output to the S1 bus via the bypass path B2 and the data path D1 is not permitted.
[0114]
When the instruction 310 is invalid, the register output control unit 382 sends the E1 register 361 and the general-purpose register 5 holding the addition result of the register R2 of the instruction 310 to the S1 bus via the bypass path B1 and the data path D1, respectively. To the W1 register 365 which holds the result of adding the instruction 300 to the register R2 to the S1 bus via the bypass path B2. A control signal indicating permission is output.
[0115]
When the instruction 310 is valid, the incrementer 370 and the adder 371 input the data output from the E1 register 361 via the S1 bus. On the other hand, when the instruction 310 is invalid, the data output from the W1 register 365 is input via the S1 bus. The addition result of the adder 371 is output to the OA bus via the D2 register 363 and the M1 register 364, and is output to the data RAM 7 as a memory address of the data RAM 7.
[0116]
The addition result of the incrementer 370 is output to the E1 register 361 via the D2 register 360. The data captured by the E1 register 361 is captured by the E2 register 362 and output to the W1 register via the E2 bus. The data taken into the W1 register is output to the general-purpose register 5 via the W1 bus.
[0117]
As described above, according to the second embodiment, condition execution determination unit 261 in condition execution control unit 260 provided in instruction decode unit 2 determines how data interference has occurred. The output of the bypass determination unit 381 in the bypass control unit 380 is controlled, the control signal output from the register output control unit 382 is controlled, and the data transfer is executed by selecting the bypass paths B1 and B2 and the data path D1. With such a configuration, even when data interference occurs in a pipeline of a plurality of instructions including a conditional execution instruction, the instructions can be executed efficiently and a malfunction due to the data interference can be avoided.
[0118]
【The invention's effect】
As described above, according to the first aspect of the present invention, the condition execution determination unit in the instruction decoder determines whether the condition data set in the general-purpose flag matches the condition set in the execution condition field. The bypass control unit is configured to determine whether or not to use the bypass route according to the determination result of the condition execution determination unit. However, there is an effect that instructions can be executed efficiently without imposing a penalty on the pipeline and without malfunction.
[0119]
According to the second aspect of the present invention, the bypass determination unit in the bypass control unit determines whether data interference occurs in the pipeline of the instruction executed by the instruction execution unit, and the register output control unit The data transfer operation of the control register via the bypass path is controlled based on the determination result of the bypass determination unit, and the condition execution instruction to be executed by the condition execution determination unit in the condition execution control unit is valid. In this case, the general-purpose register write control unit controls data writing to the general-purpose register based on the determination result of the condition execution determination unit, and the bypass determination unit determines that data interference has occurred. Also, the register output control unit stops the operation of the register according to the judgment result transmitted from the condition execution judgment unit, and sets the register to use the data in the general-purpose register. And the general-purpose registers are controlled, so that even if a condition execution instruction is followed by an instruction using a bypass path, the effect is that the instruction can be executed efficiently without imposing a penalty on the pipeline and without malfunction. is there.
[0120]
According to the third aspect of the present invention, the condition execution control unit in the instruction decoder determines whether the condition set in the general-purpose flag and the condition set in the execution condition field match, and The control unit is configured to control the data transfer via one of the plurality of bypass paths and the data path passing through the general-purpose register according to the determination of the condition execution determination unit, so that the bypass path is used after the condition execution instruction. Even if the instruction continues, there is an effect that the instruction can be executed efficiently without imposing a penalty on the pipeline and without malfunction.
[0121]
According to the fourth aspect of the present invention, the bypass determination unit in the bypass control unit determines whether data interference has occurred in the pipeline of the instruction executed by the instruction execution unit, and the register output control unit determines The data transfer operation of the control register via the bypass path is controlled based on the determination result of the determination unit, and the condition execution determination unit in the condition execution control unit determines whether the condition execution instruction to be executed is valid or invalid. Whether the general-purpose register write control unit controls the writing of data to the general-purpose register based on the determination result of the condition execution determination unit, even if the bypass determination unit determines the occurrence of data interference, The register output control unit selects one of a plurality of bypass paths and a data path according to the determination result transmitted from the condition execution determination unit, and selects a plurality of registers or Is configured to control data transfer via any of the general-purpose registers, so that even when a condition execution instruction is followed by an instruction using a bypass path, it is efficient without imposing a pipeline penalty, and There is an effect that the instruction can be executed without malfunction.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of a microprocessor having a conditional execution instruction according to Embodiment 1 of the present invention.
FIG. 2 is an explanatory diagram showing an instruction format used in a microprocessor having a conditional execution instruction according to the present invention shown in FIG. 1;
FIG. 3 is an explanatory diagram showing an instruction format field used in a microprocessor having a conditional execution instruction according to the present invention shown in FIG. 1;
FIG. 4 is an explanatory diagram showing detailed contents of an execution condition field in an instruction format used in a microprocessor having a conditional execution instruction in the present invention shown in FIG. 1;
FIG. 5 is an explanatory diagram showing an operation field in an instruction format used in a microprocessor having a conditional execution instruction according to the present invention shown in FIG. 1;
FIG. 6 is an explanatory diagram showing a configuration of a register of a microprocessor having a conditional execution instruction in the present invention shown in FIG. 1;
7 is an explanatory diagram showing a PSW in a register of the microprocessor having the conditional execution instruction according to the present invention shown in FIG. 1;
FIG. 8 is an explanatory diagram showing a pipeline operation of a microprocessor having a conditional execution instruction according to the present invention shown in FIG. 1;
FIG. 9 is an explanatory diagram showing a pipeline operation of a microprocessor having a conditional execution instruction in the present invention shown in FIG. 1;
FIG. 10 is an example of a program when data interference of a microprocessor occurs in one embodiment of the present invention.
FIG. 11 is an explanatory diagram showing an operation of the pipeline when the program shown in FIG. 10 is executed.
FIG. 12 is a block diagram for explaining the operation of the microprocessor when executing the program shown in FIG. 10;
FIG. 13 is a block diagram illustrating a condition execution determination unit.
FIG. 14 is an explanatory diagram showing occurrence of data interference when an instruction in the program shown in FIG. 10 is a condition execution instruction.
FIG. 15 is an explanatory diagram illustrating an example of a program executed by a microprocessor according to Embodiment 2 of the present invention;
FIG. 16 is a diagram showing an operation of the pipeline when the program shown in FIG. 15 is executed.
17 is a block diagram for explaining an operation of the microprocessor according to the second embodiment when executing the program shown in FIG.
[Explanation of symbols]
2 instruction decode unit (instruction decoder), 3 memory access unit (instruction execution unit), 5 general registers (plural general registers), 241, 242, 361, 365 plural registers, 250, 380 bypass control unit, 251, 381 Bypass determination section, 252, 382 register output control section, 260 condition execution control section, 261 condition execution determination section, 262 general-purpose register write control section, B0, B1, B2 bypass path, D0, D1 data path.

Claims (4)

An instruction decoder for decoding various instructions such as a conditional execution instruction including an execution condition field and an operation field;
An instruction execution unit that executes an instruction according to an output of the instruction decoder;
Stores the operation result of the instruction executed by the instruction execution unit, and a control register comprising Nde contains generic flag condition data is set,
A general register that stores the operation result of the instruction executed by the instruction execution unit,
Provided in the instruction execution unit, wherein without using the operation result stored in general registers, a bypass for bypassing the calculation result of the control register that stores the operation result of the instruction executed immediately before With a route,
The instruction decoder comprises:
A condition execution determination unit that determines whether the condition data set in the general-purpose flag and the condition set in the execution condition field match each other ,
A bypass control unit for controlling whether to use the bypass path or to use the operation result stored in the general-purpose register according to a determination result of the condition execution determination unit. A microprocessor having: The bypass control unit
A bypass determination unit that determines whether or not data interference has occurred in a pipeline of instructions executed by the instruction execution unit;
A register output control unit that controls a data transfer operation of a control register via a bypass path based on a determination result of the bypass determination unit,
The conditional execution control unit
A condition execution determination unit that determines whether a condition execution instruction to be executed is valid or invalid;
A general-purpose register write control unit that controls writing of data to a general-purpose register based on a determination result of the condition execution determination unit,
The control register includes:
A register for acquiring and storing the operation result of the instruction executed by the instruction execution unit, and obtaining and storing the operation result from the general-purpose register; and bypassing the operation result obtained via the general-purpose register. A register connected to a data transfer path for transferring data through a path other than the path,
The register output control unit includes:
Also the bypass determination unit is a case where it is determined the occurrence of data interference, in accordance with the determination result transmitted from said condition execution determination unit, to stop the data transfer via the control register and the bypass path, the general purpose register 2. The microcontroller having a conditional execution instruction according to claim 1 , wherein data transfer of the control register via a data transfer path other than the bypass path is controlled so as to use the stored data of the operation result. Processor. An instruction decoder for decoding various instructions such as a conditional execution instruction including an execution condition field and an operation field;
A control register including a general purpose flag for which a condition is set;
An instruction execution unit that executes an instruction according to an output of the instruction decoder;
A plurality of general-purpose registers for storing execution results of the instruction execution unit;
A plurality of bypass paths provided in the instruction execution unit, for bypassing the operation result in a plurality of registers storing the operation result of the instruction executed immediately before, without passing through the general-purpose register ;
A data path for data transfer via the general-purpose register,
The instruction decoder comprises:
Wherein the determining whether or not conditional execution control unit sets conditions to the conditions set in the general purpose flags said execution condition field is matched, according to the determination of the condition execution determination unit, the plurality of bypass paths And a bypass control unit for controlling data transfer via any of the data paths passing through the general-purpose register. The bypass control unit
A bypass determination unit that determines whether or not data interference has occurred in a pipeline of instructions executed by the instruction execution unit;
A register output control unit that controls a data transfer operation of a control register via a bypass path based on a determination result of the bypass determination unit,
The conditional execution control unit
A condition execution determination unit that determines whether a condition execution instruction to be executed is valid or invalid;
A general-purpose register write control unit that controls writing of data to a general-purpose register based on a determination result of the condition execution determination unit,
Even when the bypass determination unit determines the occurrence of data interference, the register output control unit is configured to output one of the plurality of bypass paths and the data path according to a determination result transmitted from the condition execution determination unit. 4. The microprocessor having a conditional execution instruction according to claim 3, wherein the microprocessor controls the data transfer via one of the plurality of registers or the plurality of general-purpose registers.

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